add sysbus/pci/sdbus separator comments to keep it clearer
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/sd/sdhci.c | 21 ++++++++++-----------
1 file changed, 10 insertions(+), 11 deletions(-)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index a56c0c273e..c8b7b1ca4c 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -1256,13 +1256,17 @@ const VMStateDescription sdhci_vmstate = {
/* Capabilities registers provide information on supported features of this
* specific host controller implementation */
-static Property sdhci_pci_properties[] = {
+static Property sdhci_properties[] = {
DEFINE_PROP_UINT32("capareg", SDHCIState, capareg,
SDHC_CAPAB_REG_DEFAULT),
DEFINE_PROP_UINT32("maxcurr", SDHCIState, maxcurr, 0),
+ DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk,
+ false),
DEFINE_PROP_END_OF_LIST(),
};
+/* --- qdev PCI --- */
+
static void sdhci_pci_realize(PCIDevice *dev, Error **errp)
{
SDHCIState *s = PCI_SDHCI(dev);
@@ -1295,7 +1299,7 @@ static void sdhci_pci_class_init(ObjectClass *klass, void *data)
k->class_id = PCI_CLASS_SYSTEM_SDHCI;
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
dc->vmsd = &sdhci_vmstate;
- dc->props = sdhci_pci_properties;
+ dc->props = sdhci_properties;
dc->reset = sdhci_poweron_reset;
}
@@ -1310,14 +1314,7 @@ static const TypeInfo sdhci_pci_info = {
},
};
-static Property sdhci_sysbus_properties[] = {
- DEFINE_PROP_UINT32("capareg", SDHCIState, capareg,
- SDHC_CAPAB_REG_DEFAULT),
- DEFINE_PROP_UINT32("maxcurr", SDHCIState, maxcurr, 0),
- DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk,
- false),
- DEFINE_PROP_END_OF_LIST(),
-};
+/* --- qdev SysBus --- */
static void sdhci_sysbus_init(Object *obj)
{
@@ -1350,7 +1347,7 @@ static void sdhci_sysbus_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
dc->vmsd = &sdhci_vmstate;
- dc->props = sdhci_sysbus_properties;
+ dc->props = sdhci_properties;
dc->realize = sdhci_sysbus_realize;
dc->reset = sdhci_poweron_reset;
}
@@ -1364,6 +1361,8 @@ static const TypeInfo sdhci_sysbus_info = {
.class_init = sdhci_sysbus_class_init,
};
+/* --- qdev bus master --- */
+
static void sdhci_bus_class_init(ObjectClass *klass, void *data)
{
SDBusClass *sbc = SD_BUS_CLASS(klass);
--
2.15.1
On Wed, Dec 13, 2017 at 11:58 AM, Philippe Mathieu-Daudé
<f4bug@amsat.org> wrote:
> add sysbus/pci/sdbus separator comments to keep it clearer
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> hw/sd/sdhci.c | 21 ++++++++++-----------
> 1 file changed, 10 insertions(+), 11 deletions(-)
>
> diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
> index a56c0c273e..c8b7b1ca4c 100644
> --- a/hw/sd/sdhci.c
> +++ b/hw/sd/sdhci.c
> @@ -1256,13 +1256,17 @@ const VMStateDescription sdhci_vmstate = {
>
> /* Capabilities registers provide information on supported features of this
> * specific host controller implementation */
> -static Property sdhci_pci_properties[] = {
> +static Property sdhci_properties[] = {
> DEFINE_PROP_UINT32("capareg", SDHCIState, capareg,
> SDHC_CAPAB_REG_DEFAULT),
> DEFINE_PROP_UINT32("maxcurr", SDHCIState, maxcurr, 0),
> + DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk,
> + false),
I like the reduction of code in this patch, but aren't we now going to
have device properties that aren't actually connected to anything?
Alistair
> DEFINE_PROP_END_OF_LIST(),
> };
>
> +/* --- qdev PCI --- */
> +
> static void sdhci_pci_realize(PCIDevice *dev, Error **errp)
> {
> SDHCIState *s = PCI_SDHCI(dev);
> @@ -1295,7 +1299,7 @@ static void sdhci_pci_class_init(ObjectClass *klass, void *data)
> k->class_id = PCI_CLASS_SYSTEM_SDHCI;
> set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
> dc->vmsd = &sdhci_vmstate;
> - dc->props = sdhci_pci_properties;
> + dc->props = sdhci_properties;
> dc->reset = sdhci_poweron_reset;
> }
>
> @@ -1310,14 +1314,7 @@ static const TypeInfo sdhci_pci_info = {
> },
> };
>
> -static Property sdhci_sysbus_properties[] = {
> - DEFINE_PROP_UINT32("capareg", SDHCIState, capareg,
> - SDHC_CAPAB_REG_DEFAULT),
> - DEFINE_PROP_UINT32("maxcurr", SDHCIState, maxcurr, 0),
> - DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk,
> - false),
> - DEFINE_PROP_END_OF_LIST(),
> -};
> +/* --- qdev SysBus --- */
>
> static void sdhci_sysbus_init(Object *obj)
> {
> @@ -1350,7 +1347,7 @@ static void sdhci_sysbus_class_init(ObjectClass *klass, void *data)
> DeviceClass *dc = DEVICE_CLASS(klass);
>
> dc->vmsd = &sdhci_vmstate;
> - dc->props = sdhci_sysbus_properties;
> + dc->props = sdhci_properties;
> dc->realize = sdhci_sysbus_realize;
> dc->reset = sdhci_poweron_reset;
> }
> @@ -1364,6 +1361,8 @@ static const TypeInfo sdhci_sysbus_info = {
> .class_init = sdhci_sysbus_class_init,
> };
>
> +/* --- qdev bus master --- */
> +
> static void sdhci_bus_class_init(ObjectClass *klass, void *data)
> {
> SDBusClass *sbc = SD_BUS_CLASS(klass);
> --
> 2.15.1
>
>
>> /* Capabilities registers provide information on supported features of this
>> * specific host controller implementation */
>> -static Property sdhci_pci_properties[] = {
>> +static Property sdhci_properties[] = {
>> DEFINE_PROP_UINT32("capareg", SDHCIState, capareg,
>> SDHC_CAPAB_REG_DEFAULT),
>> DEFINE_PROP_UINT32("maxcurr", SDHCIState, maxcurr, 0),
>> + DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk,
>> + false),
>
> I like the reduction of code in this patch, but aren't we now going to
> have device properties that aren't actually connected to anything?
I'm not sure I understand, ar you worried about the PCI_SDHCI will now
have this property but not use it?
I couldn't find any machine using SDHCI via PCI and was tempted to
just remove this code,
the only references to it is the REDHAT_SDHCI from commits ece5e5bfa13
and 224d10ff5ae.
Maybe an attempt to write SDHCI qtests via PCI?
>> DEFINE_PROP_END_OF_LIST(),
>> };
>>
>> +/* --- qdev PCI --- */
>> +
>> static void sdhci_pci_realize(PCIDevice *dev, Error **errp)
>> {
>> SDHCIState *s = PCI_SDHCI(dev);
>> @@ -1295,7 +1299,7 @@ static void sdhci_pci_class_init(ObjectClass *klass, void *data)
>> k->class_id = PCI_CLASS_SYSTEM_SDHCI;
>> set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
>> dc->vmsd = &sdhci_vmstate;
>> - dc->props = sdhci_pci_properties;
>> + dc->props = sdhci_properties;
>> dc->reset = sdhci_poweron_reset;
>> }
>>
>> @@ -1310,14 +1314,7 @@ static const TypeInfo sdhci_pci_info = {
>> },
>> };
>>
>> -static Property sdhci_sysbus_properties[] = {
>> - DEFINE_PROP_UINT32("capareg", SDHCIState, capareg,
>> - SDHC_CAPAB_REG_DEFAULT),
>> - DEFINE_PROP_UINT32("maxcurr", SDHCIState, maxcurr, 0),
>> - DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk,
>> - false),
>> - DEFINE_PROP_END_OF_LIST(),
>> -};
>> +/* --- qdev SysBus --- */
On Thu, Dec 14, 2017 at 10:40 AM, Philippe Mathieu-Daudé
<f4bug@amsat.org> wrote:
>>> /* Capabilities registers provide information on supported features of this
>>> * specific host controller implementation */
>>> -static Property sdhci_pci_properties[] = {
>>> +static Property sdhci_properties[] = {
>>> DEFINE_PROP_UINT32("capareg", SDHCIState, capareg,
>>> SDHC_CAPAB_REG_DEFAULT),
>>> DEFINE_PROP_UINT32("maxcurr", SDHCIState, maxcurr, 0),
>>> + DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk,
>>> + false),
>>
>> I like the reduction of code in this patch, but aren't we now going to
>> have device properties that aren't actually connected to anything?
>
> I'm not sure I understand, ar you worried about the PCI_SDHCI will now
> have this property but not use it?
>
> I couldn't find any machine using SDHCI via PCI and was tempted to
> just remove this code,
> the only references to it is the REDHAT_SDHCI from commits ece5e5bfa13
> and 224d10ff5ae.
So it is also possible to set these properties from the command line.
If I'm a user and I see that my device has a property "foo" I expect
that setting that property will have an affect on that device. So
there shouldn't be properties that aren't actually connected to the
device.
Alistair
>
> Maybe an attempt to write SDHCI qtests via PCI?
>
>>> DEFINE_PROP_END_OF_LIST(),
>>> };
>>>
>>> +/* --- qdev PCI --- */
>>> +
>>> static void sdhci_pci_realize(PCIDevice *dev, Error **errp)
>>> {
>>> SDHCIState *s = PCI_SDHCI(dev);
>>> @@ -1295,7 +1299,7 @@ static void sdhci_pci_class_init(ObjectClass *klass, void *data)
>>> k->class_id = PCI_CLASS_SYSTEM_SDHCI;
>>> set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
>>> dc->vmsd = &sdhci_vmstate;
>>> - dc->props = sdhci_pci_properties;
>>> + dc->props = sdhci_properties;
>>> dc->reset = sdhci_poweron_reset;
>>> }
>>>
>>> @@ -1310,14 +1314,7 @@ static const TypeInfo sdhci_pci_info = {
>>> },
>>> };
>>>
>>> -static Property sdhci_sysbus_properties[] = {
>>> - DEFINE_PROP_UINT32("capareg", SDHCIState, capareg,
>>> - SDHC_CAPAB_REG_DEFAULT),
>>> - DEFINE_PROP_UINT32("maxcurr", SDHCIState, maxcurr, 0),
>>> - DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk,
>>> - false),
>>> - DEFINE_PROP_END_OF_LIST(),
>>> -};
>>> +/* --- qdev SysBus --- */
>
On Thu, Dec 14, 2017 at 03:40:17PM -0300, Philippe Mathieu-Daudé wrote:
> >> /* Capabilities registers provide information on supported features of this
> >> * specific host controller implementation */
> >> -static Property sdhci_pci_properties[] = {
> >> +static Property sdhci_properties[] = {
> >> DEFINE_PROP_UINT32("capareg", SDHCIState, capareg,
> >> SDHC_CAPAB_REG_DEFAULT),
> >> DEFINE_PROP_UINT32("maxcurr", SDHCIState, maxcurr, 0),
> >> + DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk,
> >> + false),
> >
> > I like the reduction of code in this patch, but aren't we now going to
> > have device properties that aren't actually connected to anything?
>
> I'm not sure I understand, ar you worried about the PCI_SDHCI will now
> have this property but not use it?
>
> I couldn't find any machine using SDHCI via PCI and was tempted to
> just remove this code,
I'm not sure if you are suggesting the removal of PCI SDHCI support or
removal of some of the properties.
I do find qemu's PCI SDHCI support useful for testing. SeaBIOS can
launch an OS from PCI SDHCI (qemu-system-x86_64 -device sdhci-pci
-device sd-card,drive=drive0 -drive id=drive0,if=none,file=dos-drivec)
and linux has drivers for it as well. A number of the Chromebooks
ship with PCI SDHCI devices on them, so it's not an unheard of
configuration.
I've never manually set any of the PCI properites, however.
-Kevin
On 14/12/2017 19:40, Philippe Mathieu-Daudé wrote:
>>> + DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk,
>>> + false),
>> I like the reduction of code in this patch, but aren't we now going to
>> have device properties that aren't actually connected to anything?
> I'm not sure I understand, ar you worried about the PCI_SDHCI will now
> have this property but not use it?
>
> I couldn't find any machine using SDHCI via PCI and was tempted to
> just remove this code,
PCI devices can be created with -device, they don't have to be added by
boards.
Paolo
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