In reviewing my previous patch, Peter pointed out that it is
CONSTRAINED UNPREDICTABLE what happens when you mix the number
of registers in a LDX[PR] + STX[RP] pair.  So most of the bug
that I thought that I was fixing isn't a bug at all.

That said, the patch does still fix a real bug wrt single-copy
semantics, so patch 2 is largely unchanged; the commit message
is re-worded.

I also un-squashed Alistair's original patches and dropped the
tcg/tcg-op.c change, to be revisited for 2.11.


r~


Alistair Francis (2):
  target/arm: Correct exclusive store cmpxchg memop mask
  target/arm: Require alignment for load exclusive

Richard Henderson (1):
  target/arm: Correct load exclusive pair atomicity

 target/arm/translate-a64.c | 63 ++++++++++++++++++++++++++++------------------
 1 file changed, 39 insertions(+), 24 deletions(-)

-- 
2.13.4

On 15 August 2017 at 15:57, Richard Henderson
<richard.henderson@linaro.org> wrote:
> In reviewing my previous patch, Peter pointed out that it is
> CONSTRAINED UNPREDICTABLE what happens when you mix the number
> of registers in a LDX[PR] + STX[RP] pair.  So most of the bug
> that I thought that I was fixing isn't a bug at all.
>
> That said, the patch does still fix a real bug wrt single-copy
> semantics, so patch 2 is largely unchanged; the commit message
> is re-worded.
>
> I also un-squashed Alistair's original patches and dropped the
> tcg/tcg-op.c change, to be revisited for 2.11.

Applied to master (with various reviewed-by etc tags, and
the typos in the commit message for 3/3 fixed).

thanks
-- PMM