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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id n11sm20626318pfg.15.2017.08.15.07.57.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 15 Aug 2017 07:57:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1yklcVDekvLBXIP3CEvj2/bNmxst4wAEfOaesd04J40=; b=hiPydfhP7gaxMwnvpE/flWktVYjI/EUkVtVK93OpgUnkAgZM4jCX6/h49XQcT8pC4f N5/ryWAVoBue+0w5mUHni8tjrnniP9OPQoo61EfP1dPXdCRh7u1PhjMstRPe1p6MHCX6 qOjfCmsVayOh2MT88n0Bss0OxmcR1IBHxsqsk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1yklcVDekvLBXIP3CEvj2/bNmxst4wAEfOaesd04J40=; b=IcyKpbnjXuDcaO/Af9/+pJvn4IE+/T20keZr7B4f5eE86vtxST9SJX9CTZEu/HC2A2 HkHDbcKoVUhVKZMZhAFGHRy6T4dl7HwBUtgSpkpWfp4zlInQa8MvY1vUgfkV2pM+gTba icJCOh7NinL1dOt8Y3V1FUPA8BLbaVHUI9O8JmbXYeUZViDiSlebSUK+sQdzY52Pnpt7 jKZ2tRLI84dg4yj4iZ7aWfYd2JMs5F/h1+6gstZLiLWkkVpovNvl6mil9w9hJ3af08RK MVSoz9aceYC3qyuWClbGg/ZiO0Lj2oPxtjJJLIGFDj4vN8W8X9yT0l6VH/wXVtkHi1ca KFnw== X-Gm-Message-State: AHYfb5hv8gnn6AaO7mvZ6MG7m5pq264hx0mq5qKCgzM/mjXomRkdm/pk Ro0rq2RyhQnJssj4OVoLeg== X-Received: by 10.84.169.67 with SMTP id g61mr31527247plb.109.1502809038303; Tue, 15 Aug 2017 07:57:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 15 Aug 2017 07:57:12 -0700 Message-Id: <20170815145714.17635-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.4 In-Reply-To: <20170815145714.17635-1-richard.henderson@linaro.org> References: <20170815145714.17635-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::235 Subject: [Qemu-devel] [PATCH v2 for-2.10 1/3] target/arm: Correct exclusive store cmpxchg memop mask X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, alistair.francis@xilinx.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Alistair Francis When we perform the atomic_cmpxchg operation we want to perform the operation on a pair of 32-bit registers. Previously we were just passing the register size in which was set to MO_32. This would result in the high register to be ignored. To fix this issue we hardcode the size to be 64-bits long when operating on 32-bit pairs. Reviewed-by: Edgar E. Iglesias Signed-off-by: Alistair Francis Message-Id: Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Portia Stephens --- target/arm/translate-a64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 58ed4c6d05..113e2e172b 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1913,7 +1913,7 @@ static void gen_store_exclusive(DisasContext *s, int = rd, int rt, int rt2, tcg_gen_concat32_i64(val, cpu_exclusive_val, cpu_exclusive_hig= h); tcg_gen_atomic_cmpxchg_i64(tmp, addr, val, tmp, get_mem_index(s), - size | MO_ALIGN | s->be_data); + MO_64 | MO_ALIGN | s->be_data); tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, val); tcg_temp_free_i64(val); } else if (s->be_data =3D=3D MO_LE) { --=20 2.13.4 From nobody Sun May 5 00:37:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1502809148734507.7447423336964; Tue, 15 Aug 2017 07:59:08 -0700 (PDT) Received: from localhost ([::1]:39221 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dhdJD-0006Yv-9o for importer@patchew.org; Tue, 15 Aug 2017 10:59:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34183) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dhdHX-0005Ip-TF for qemu-devel@nongnu.org; Tue, 15 Aug 2017 10:57:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dhdHV-0004J1-84 for qemu-devel@nongnu.org; Tue, 15 Aug 2017 10:57:23 -0400 Received: from mail-pg0-x22d.google.com ([2607:f8b0:400e:c05::22d]:33136) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dhdHV-0004IL-06 for qemu-devel@nongnu.org; Tue, 15 Aug 2017 10:57:21 -0400 Received: by mail-pg0-x22d.google.com with SMTP id u5so7130791pgn.0 for ; Tue, 15 Aug 2017 07:57:20 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id n11sm20626318pfg.15.2017.08.15.07.57.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 15 Aug 2017 07:57:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aKSHdHsWCeTS98zZ+zVKyMBhPWkI6YZN9ENm/xYAoRs=; b=VTsDvDUo+NY93nq/DIadQbJnH9szLCJnAuq+OmmPkd1nbSJbzoyoPZtg29HCQXhZG0 6igN30Lv70wyXKGlI84UyPQSQ9Vcpg5woKOjUgCdN53kBgB/EkDZ9PYnOMhvWDKfzMm+ tvUQXaNZm394aGllsD0GtprO23CCdbQeDmmpQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aKSHdHsWCeTS98zZ+zVKyMBhPWkI6YZN9ENm/xYAoRs=; b=mTpm1x0uyIw6ixBMDIRtouNTM+hMXgGbA4mZhJiJjwncfd8t4q32ipTkDH44VFWuRH k5TevQ/rOZZ/NUOFRU4E5zY8i3LV1sVdLaFgE2q5KLVidM4sh926cxXdAL8hloFj6qiN VyGs1TFBFHW3e8W0fLZF4HzkRno025ELRrtuQgfivJ05IdWV9rn79Uc6/XIaBCMM9knk /ZubHB3i2B99GgGNqrQTmDQzU5+N1uWkQnrRl9X/cX4mTTfM1JuBwBxBTXsNZfCpNEyt Sb94lAIkG5/HmOdAxhgXYauUICDpUwAmZUq1HT4sZN8q03o0R4QksTTtLALh30I7aXLT wnzg== X-Gm-Message-State: AHYfb5jmPkO+faN2QxPQNFf/PBYntOlL/eiL4p4xsZ2TbzMxyWihBB6s 6jVpHIDIiefh598iXE9Mqw== X-Received: by 10.84.194.129 with SMTP id h1mr31529268pld.237.1502809039570; Tue, 15 Aug 2017 07:57:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 15 Aug 2017 07:57:13 -0700 Message-Id: <20170815145714.17635-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.4 In-Reply-To: <20170815145714.17635-1-richard.henderson@linaro.org> References: <20170815145714.17635-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22d Subject: [Qemu-devel] [PATCH v2 for-2.10 2/3] target/arm: Correct load exclusive pair atomicity X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, alistair.francis@xilinx.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We are not providing the required single-copy atomic semantics for the 64-bit operation that is the 32-bit paired load. At the same time, leave the entire 64-bit value in cpu_exclusive_val and stop writing to cpu_exclusive_high. This means that we do not have to re-assemble the 64-bit quantity when it comes time to store. At the same time, drop a redundant temporary and perform all loads directly into the cpu_exclusive_* globals. Tested-by: Alistair Francis Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 60 ++++++++++++++++++++++++++++--------------= ---- 1 file changed, 37 insertions(+), 23 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 113e2e172b..eac545e4f2 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1853,29 +1853,42 @@ static void disas_b_exc_sys(DisasContext *s, uint32= _t insn) static void gen_load_exclusive(DisasContext *s, int rt, int rt2, TCGv_i64 addr, int size, bool is_pair) { - TCGv_i64 tmp =3D tcg_temp_new_i64(); - TCGMemOp memop =3D s->be_data + size; + int idx =3D get_mem_index(s); + TCGMemOp memop =3D s->be_data; =20 g_assert(size <=3D 3); - tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s), memop); - if (is_pair) { - TCGv_i64 addr2 =3D tcg_temp_new_i64(); - TCGv_i64 hitmp =3D tcg_temp_new_i64(); - g_assert(size >=3D 2); - tcg_gen_addi_i64(addr2, addr, 1 << size); - tcg_gen_qemu_ld_i64(hitmp, addr2, get_mem_index(s), memop); - tcg_temp_free_i64(addr2); - tcg_gen_mov_i64(cpu_exclusive_high, hitmp); - tcg_gen_mov_i64(cpu_reg(s, rt2), hitmp); - tcg_temp_free_i64(hitmp); - } + if (size =3D=3D 2) { + /* The pair must be single-copy atomic for the doubleword. */ + memop |=3D MO_64; + tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop); + if (s->be_data =3D=3D MO_LE) { + tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 0, = 32); + tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 32= , 32); + } else { + tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 32,= 32); + tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 0,= 32); + } + } else { + /* The pair must be single-copy atomic for *each* doubleword, + but not the entire quadword. */ + memop |=3D MO_64; + tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop); =20 - tcg_gen_mov_i64(cpu_exclusive_val, tmp); - tcg_gen_mov_i64(cpu_reg(s, rt), tmp); + TCGv_i64 addr2 =3D tcg_temp_new_i64(); + tcg_gen_addi_i64(addr2, addr, 8); + tcg_gen_qemu_ld_i64(cpu_exclusive_high, addr2, idx, memop); + tcg_temp_free_i64(addr2); =20 - tcg_temp_free_i64(tmp); + tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val); + tcg_gen_mov_i64(cpu_reg(s, rt2), cpu_exclusive_high); + } + } else { + memop |=3D size; + tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop); + tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val); + } tcg_gen_mov_i64(cpu_exclusive_addr, addr); } =20 @@ -1908,14 +1921,15 @@ static void gen_store_exclusive(DisasContext *s, in= t rd, int rt, int rt2, tmp =3D tcg_temp_new_i64(); if (is_pair) { if (size =3D=3D 2) { - TCGv_i64 val =3D tcg_temp_new_i64(); - tcg_gen_concat32_i64(tmp, cpu_reg(s, rt), cpu_reg(s, rt2)); - tcg_gen_concat32_i64(val, cpu_exclusive_val, cpu_exclusive_hig= h); - tcg_gen_atomic_cmpxchg_i64(tmp, addr, val, tmp, + if (s->be_data =3D=3D MO_LE) { + tcg_gen_concat32_i64(tmp, cpu_reg(s, rt), cpu_reg(s, rt2)); + } else { + tcg_gen_concat32_i64(tmp, cpu_reg(s, rt2), cpu_reg(s, rt)); + } + tcg_gen_atomic_cmpxchg_i64(tmp, addr, cpu_exclusive_val, tmp, get_mem_index(s), MO_64 | MO_ALIGN | s->be_data); - tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, val); - tcg_temp_free_i64(val); + tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val); } else if (s->be_data =3D=3D MO_LE) { gen_helper_paired_cmpxchg64_le(tmp, cpu_env, addr, cpu_reg(s, = rt), cpu_reg(s, rt2)); --=20 2.13.4 From nobody Sun May 5 00:37:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1502809270409537.5181543185869; Tue, 15 Aug 2017 08:01:10 -0700 (PDT) Received: from localhost ([::1]:39398 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dhdLB-00009d-Ac for importer@patchew.org; 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id n11sm20626318pfg.15.2017.08.15.07.57.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 15 Aug 2017 07:57:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SgAaEYM18OE+mUpjVkYzlZyVnbr8ndjZmIY5W1zNvyI=; b=ZoFcqDuet/QGi2nRgJNNHLha7S3eqMac5sj5ziUv5J3cp6pdhpxQPweKEV5STN4jV5 OEQf8PD4f/mfeUG/3ceWg7a9L7DhNzIa7t10rp+gmUPR6NW0q9fC6b9fGx9xu2J7bWKs 4W1OPJMDNKW/IRXczKvGirPC7gTpCwoDWZP0I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SgAaEYM18OE+mUpjVkYzlZyVnbr8ndjZmIY5W1zNvyI=; b=fbh4fcQ0jY9MvZ+H0QoghBPSl3PIryIi+jJfdhgSULHSlkBp7JsgmWnQvEEUGcTSrd y1C06xp9Dvka6NGaOzDbfttY8MX8a/Ds0BoA6UsYRgRIbHb0tnB2S20a2LdWpBJzPl+L cNJBcJFWL68bBzQ8zEM8IqBEf3o6DOSP9Ebna5t6KlTxcImszxmsGzIzFj4TUa5H90YF n+PF5w0YzNT1s2ubV6P41nb6IXkoBlyEq070FrOc/SnbeByxXXyr2QYc1vMD64S+98PJ Es5vlqlKhpLkRTRCAtWHRx+l1vD3GnPwnPLb3rrMGTl2lJjR1YmcmREJ4boMtP4Uy7ok 3RRw== X-Gm-Message-State: AHYfb5hc9DSjNJwDRyzFyxG13LOE9bsKvgY47XGSwHoJdum0RU3Y6D1/ F+ZZ4hnRCX+XtGi+iDJFlw== X-Received: by 10.84.167.230 with SMTP id i35mr31743455plg.181.1502809041202; Tue, 15 Aug 2017 07:57:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 15 Aug 2017 07:57:14 -0700 Message-Id: <20170815145714.17635-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.4 In-Reply-To: <20170815145714.17635-1-richard.henderson@linaro.org> References: <20170815145714.17635-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::236 Subject: [Qemu-devel] [PATCH v2 for-2.10 3/3] target/arm: Require alignment for load exclusive X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, alistair.francis@xilinx.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Alistair Francis Acording to the ARM ARM exclusive loads require the same allignment as exclusive stores. Let's update the memops used for the load to match that of the store. This adds the alignment requirement to the memops. Reviewed-by: Edgar E. Iglesias Signed-off-by: Alistair Francis [rth: Require 16-byte alignment for 64-bit LDXP.] Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index eac545e4f2..2200e25be0 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1861,7 +1861,7 @@ static void gen_load_exclusive(DisasContext *s, int r= t, int rt2, g_assert(size >=3D 2); if (size =3D=3D 2) { /* The pair must be single-copy atomic for the doubleword. */ - memop |=3D MO_64; + memop |=3D MO_64 | MO_ALIGN; tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop); if (s->be_data =3D=3D MO_LE) { tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 0, = 32); @@ -1871,10 +1871,11 @@ static void gen_load_exclusive(DisasContext *s, int= rt, int rt2, tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 0,= 32); } } else { - /* The pair must be single-copy atomic for *each* doubleword, - but not the entire quadword. */ + /* The pair must be single-copy atomic for *each* doubleword, = not + the entire quadword, however it must be quadword aligned. = */ memop |=3D MO_64; - tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop); + tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, + memop | MO_ALIGN_16); =20 TCGv_i64 addr2 =3D tcg_temp_new_i64(); tcg_gen_addi_i64(addr2, addr, 8); @@ -1885,7 +1886,7 @@ static void gen_load_exclusive(DisasContext *s, int r= t, int rt2, tcg_gen_mov_i64(cpu_reg(s, rt2), cpu_exclusive_high); } } else { - memop |=3D size; + memop |=3D size | MO_ALIGN; tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop); tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val); } --=20 2.13.4