[Qemu-devel] [PATCH v2 21/27] target/sh4: Tidy misc illegal insn checks

Richard Henderson posted 27 patches 8 years, 4 months ago
There is a newer version of this series
[Qemu-devel] [PATCH v2 21/27] target/sh4: Tidy misc illegal insn checks
Posted by Richard Henderson 8 years, 4 months ago
Now that we have a do_illegal label, use goto in order
to self-document the forcing of the exception.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target/sh4/translate.c | 22 +++++++++++++---------
 1 file changed, 13 insertions(+), 9 deletions(-)

diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index a4370c6..06cf649 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -1079,8 +1079,9 @@ static void _decode_opc(DisasContext * ctx)
             if (ctx->tbflags & FPSCR_PR) {
                 TCGv_i64 fp0, fp1;
 
-		if (ctx->opcode & 0x0110)
-		    break; /* illegal instruction */
+                if (ctx->opcode & 0x0110) {
+                    goto do_illegal;
+                }
 		fp0 = tcg_temp_new_i64();
 		fp1 = tcg_temp_new_i64();
 		gen_load_fpr64(ctx, fp0, B11_8);
@@ -1142,7 +1143,7 @@ static void _decode_opc(DisasContext * ctx)
         {
             CHECK_FPU_ENABLED
             if (ctx->tbflags & FPSCR_PR) {
-                break; /* illegal instruction */
+                goto do_illegal;
             } else {
                 gen_helper_fmac_FT(FREG(B11_8), cpu_env,
                                    FREG(0), FREG(B7_4), FREG(B11_8));
@@ -1693,8 +1694,9 @@ static void _decode_opc(DisasContext * ctx)
 	CHECK_FPU_ENABLED
         if (ctx->tbflags & FPSCR_PR) {
 	    TCGv_i64 fp;
-	    if (ctx->opcode & 0x0100)
-		break; /* illegal instruction */
+            if (ctx->opcode & 0x0100) {
+                goto do_illegal;
+            }
 	    fp = tcg_temp_new_i64();
             gen_helper_float_DT(fp, cpu_env, cpu_fpul);
 	    gen_store_fpr64(ctx, fp, B11_8);
@@ -1708,8 +1710,9 @@ static void _decode_opc(DisasContext * ctx)
 	CHECK_FPU_ENABLED
         if (ctx->tbflags & FPSCR_PR) {
 	    TCGv_i64 fp;
-	    if (ctx->opcode & 0x0100)
-		break; /* illegal instruction */
+            if (ctx->opcode & 0x0100) {
+		goto do_illegal;
+            }
 	    fp = tcg_temp_new_i64();
 	    gen_load_fpr64(ctx, fp, B11_8);
             gen_helper_ftrc_DT(cpu_fpul, cpu_env, fp);
@@ -1730,8 +1733,9 @@ static void _decode_opc(DisasContext * ctx)
     case 0xf06d: /* fsqrt FRn */
 	CHECK_FPU_ENABLED
         if (ctx->tbflags & FPSCR_PR) {
-	    if (ctx->opcode & 0x0100)
-		break; /* illegal instruction */
+            if (ctx->opcode & 0x0100) {
+		goto do_illegal;
+            }
 	    TCGv_i64 fp = tcg_temp_new_i64();
 	    gen_load_fpr64(ctx, fp, B11_8);
             gen_helper_fsqrt_DT(fp, cpu_env, fp);
-- 
2.9.4


Re: [Qemu-devel] [PATCH v2 21/27] target/sh4: Tidy misc illegal insn checks
Posted by Aurelien Jarno 8 years, 4 months ago
On 2017-07-06 16:21, Richard Henderson wrote:
> Now that we have a do_illegal label, use goto in order
> to self-document the forcing of the exception.
> 
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
>  target/sh4/translate.c | 22 +++++++++++++---------
>  1 file changed, 13 insertions(+), 9 deletions(-)

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>

-- 
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
aurelien@aurel32.net                 http://www.aurel32.net

Re: [Qemu-devel] [PATCH v2 21/27] target/sh4: Tidy misc illegal insn checks
Posted by Philippe Mathieu-Daudé 8 years, 3 months ago
On 07/06/2017 11:21 PM, Richard Henderson wrote:
> Now that we have a do_illegal label, use goto in order
> to self-document the forcing of the exception.
> 
> Signed-off-by: Richard Henderson <rth@twiddle.net>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

> ---
>   target/sh4/translate.c | 22 +++++++++++++---------
>   1 file changed, 13 insertions(+), 9 deletions(-)
> 
> diff --git a/target/sh4/translate.c b/target/sh4/translate.c
> index a4370c6..06cf649 100644
> --- a/target/sh4/translate.c
> +++ b/target/sh4/translate.c
> @@ -1079,8 +1079,9 @@ static void _decode_opc(DisasContext * ctx)
>               if (ctx->tbflags & FPSCR_PR) {
>                   TCGv_i64 fp0, fp1;
>   
> -		if (ctx->opcode & 0x0110)
> -		    break; /* illegal instruction */
> +                if (ctx->opcode & 0x0110) {
> +                    goto do_illegal;
> +                }
>   		fp0 = tcg_temp_new_i64();
>   		fp1 = tcg_temp_new_i64();
>   		gen_load_fpr64(ctx, fp0, B11_8);
> @@ -1142,7 +1143,7 @@ static void _decode_opc(DisasContext * ctx)
>           {
>               CHECK_FPU_ENABLED
>               if (ctx->tbflags & FPSCR_PR) {
> -                break; /* illegal instruction */
> +                goto do_illegal;
>               } else {
>                   gen_helper_fmac_FT(FREG(B11_8), cpu_env,
>                                      FREG(0), FREG(B7_4), FREG(B11_8));
> @@ -1693,8 +1694,9 @@ static void _decode_opc(DisasContext * ctx)
>   	CHECK_FPU_ENABLED
>           if (ctx->tbflags & FPSCR_PR) {
>   	    TCGv_i64 fp;
> -	    if (ctx->opcode & 0x0100)
> -		break; /* illegal instruction */
> +            if (ctx->opcode & 0x0100) {
> +                goto do_illegal;
> +            }
>   	    fp = tcg_temp_new_i64();
>               gen_helper_float_DT(fp, cpu_env, cpu_fpul);
>   	    gen_store_fpr64(ctx, fp, B11_8);
> @@ -1708,8 +1710,9 @@ static void _decode_opc(DisasContext * ctx)
>   	CHECK_FPU_ENABLED
>           if (ctx->tbflags & FPSCR_PR) {
>   	    TCGv_i64 fp;
> -	    if (ctx->opcode & 0x0100)
> -		break; /* illegal instruction */
> +            if (ctx->opcode & 0x0100) {
> +		goto do_illegal;
> +            }
>   	    fp = tcg_temp_new_i64();
>   	    gen_load_fpr64(ctx, fp, B11_8);
>               gen_helper_ftrc_DT(cpu_fpul, cpu_env, fp);
> @@ -1730,8 +1733,9 @@ static void _decode_opc(DisasContext * ctx)
>       case 0xf06d: /* fsqrt FRn */
>   	CHECK_FPU_ENABLED
>           if (ctx->tbflags & FPSCR_PR) {
> -	    if (ctx->opcode & 0x0100)
> -		break; /* illegal instruction */
> +            if (ctx->opcode & 0x0100) {
> +		goto do_illegal;
> +            }
>   	    TCGv_i64 fp = tcg_temp_new_i64();
>   	    gen_load_fpr64(ctx, fp, B11_8);
>               gen_helper_fsqrt_DT(fp, cpu_env, fp);
>