The following series includes emulation of the platform-specific MIPS extension
for Cavium Octeon CPUS:
- basic Octeon vCPU model
- custom instruction decoder for Octeon
- implementation of arithmetic and logic instructions

v3 changes:
 - separated vCPU model definition and decodetree for Octeon
   (suggested by Philippe Mathieu-Daudé)
 - fixed length field for EXTS/CINS (bug found by Richard Henderson)

v2 changes:
 - simplified instruction decoding and translation (suggested by Richard Henderson)

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Pavel Dovgalyuk (2):
      target/mips: introduce Cavium Octeon CPU model
      target/mips: implement Octeon-specific arithmetic instructions


 target/mips/cpu-defs.c.inc | 28 ----------------------------
 1 file changed, 28 deletions(-)

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Pavel Dovgalyuk