The following series includes emulation of the platform-specific MIPS extension
for Cavium Octeon CPUS:
- basic Octeon vCPU model
- custom instruction decoder for Octeon
- implementation of arithmetic and logic instructions

v2 changes:
 - simplified instruction decoding and translation (suggested by Richard Henderson)

---

Pavel Dovgalyuk (3):
      target/mips: introduce Cavium Octeon CPU model
      target/mips: implement Octeon-specific BBIT instructions
      target/mips: implement Octeon-specific arithmetic instructions


 target/mips/tcg/meson.build        |   2 +
 target/mips/tcg/octeon.decode      |  41 ++++++
 target/mips/tcg/octeon_translate.c | 201 +++++++++++++++++++++++++++++
 target/mips/tcg/translate.c        |   5 +
 target/mips/tcg/translate.h        |   1 +
 5 files changed, 250 insertions(+)
 create mode 100644 target/mips/tcg/octeon.decode
 create mode 100644 target/mips/tcg/octeon_translate.c

--
Pavel Dovgalyuk