Add new features for intel processor

[PATCH 0/2] Add new features for intel processor

Cathy Zhang posted 2 patches 3 years, 9 months ago

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git fetch https://github.com/patchew-project/qemu tags/patchew/1593991036-12183-1-git-send-email-cathy.zhang@intel.com

Maintainers: Richard Henderson <rth@twiddle.net>, Paolo Bonzini <pbonzini@redhat.com>, Eduardo Habkost <ehabkost@redhat.com>

target/i386/cpu.c | 4 ++--
target/i386/cpu.h | 4 ++++
2 files changed, 6 insertions(+), 2 deletions(-)

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[PATCH 0/2] Add new features for intel processor

Posted by Cathy Zhang 3 years, 9 months ago

This patchset is to add two new features for intel processors
which support them, like Sapphire Rapids. SERIALIZE is a faster
serializing instruction which does not modify registers,
arithmetic flags or memory, will not cause VM exit. TSX suspend
load tracking instruction aims to give a way to choose which
memory accesses do not need to be tracked in the TSX read set.

Cathy Zhang (2):
  target/i386: Add SERIALIZE cpu feature
  target/i386: Enable TSX Suspend Load Address Tracking feature

 target/i386/cpu.c | 4 ++--
 target/i386/cpu.h | 4 ++++
 2 files changed, 6 insertions(+), 2 deletions(-)

--
1.8.3.1

Re: [PATCH 0/2] Add new features for intel processor

Posted by Paolo Bonzini 3 years, 9 months ago

On 06/07/20 01:17, Cathy Zhang wrote:
> This patchset is to add two new features for intel processors
> which support them, like Sapphire Rapids. SERIALIZE is a faster
> serializing instruction which does not modify registers,
> arithmetic flags or memory, will not cause VM exit. TSX suspend
> load tracking instruction aims to give a way to choose which
> memory accesses do not need to be tracked in the TSX read set.
> 
> Cathy Zhang (2):
>   target/i386: Add SERIALIZE cpu feature
>   target/i386: Enable TSX Suspend Load Address Tracking feature
> 
>  target/i386/cpu.c | 4 ++--
>  target/i386/cpu.h | 4 ++++
>  2 files changed, 6 insertions(+), 2 deletions(-)
> 
> --
> 1.8.3.1
> 

Queued, thanks.

Paolo