[Qemu-devel] [PATCH 18/52] hw/riscv/Makefile.objs: Create CONFIG_* for riscv boards

Paolo Bonzini posted 52 patches 7 years ago
Maintainers: Eduardo Habkost <ehabkost@redhat.com>, "Marc-André Lureau" <marcandre.lureau@redhat.com>, Palmer Dabbelt <palmer@sifive.com>, Max Filippov <jcmvbkbc@gmail.com>, Alistair Francis <alistair@alistair23.me>, Guan Xuetao <gxt@mprc.pku.edu.cn>, Max Reitz <mreitz@redhat.com>, Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>, Igor Mammedov <imammedo@redhat.com>, Aleksandar Markovic <amarkovic@wavecomp.com>, Fam Zheng <fam@euphon.net>, Cornelia Huck <cohuck@redhat.com>, Peter Crosthwaite <crosthwaite.peter@gmail.com>, Gerd Hoffmann <kraxel@redhat.com>, Aleksandar Rikalo <arikalo@wavecomp.com>, Corey Minyard <minyard@acm.org>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Alex Williamson <alex.williamson@redhat.com>, Alberto Garcia <berto@igalia.com>, Anthony Green <green@moxielogic.com>, Jason Wang <jasowang@redhat.com>, Aurelien Jarno <aurelien@aurel32.net>, Richard Henderson <rth@twiddle.net>, Greg Kurz <groug@kaod.org>, "Daniel P. Berrangé" <berrange@redhat.com>, Alistair Francis <Alistair.Francis@wdc.com>, Marcel Apfelbaum <marcel.apfelbaum@gmail.com>, Michael Clark <mjc@sifive.com>, Kevin Wolf <kwolf@redhat.com>, Chris Wulff <crwulff@gmail.com>, "Michael S. Tsirkin" <mst@redhat.com>, Stafford Horne <shorne@gmail.com>, Michael Walle <michael@walle.cc>, "Edgar E. Iglesias" <edgar.iglesias@gmail.com>, David Hildenbrand <david@redhat.com>, Marek Vasut <marex@denx.de>, Paolo Bonzini <pbonzini@redhat.com>, David Gibson <david@gibson.dropbear.id.au>, Peter Maydell <peter.maydell@linaro.org>, Halil Pasic <pasic@linux.ibm.com>, Stefan Berger <stefanb@linux.ibm.com>, John Snow <jsnow@redhat.com>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Christian Borntraeger <borntraeger@de.ibm.com>, Artyom Tarasenko <atar4qemu@gmail.com>, Cleber Rosa <crosa@redhat.com>
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[Qemu-devel] [PATCH 18/52] hw/riscv/Makefile.objs: Create CONFIG_* for riscv boards
Posted by Paolo Bonzini 7 years ago
From: Yang Zhong <yang.zhong@intel.com>

Add the new configs to default-configs/riscv*-sofmmu.mak.

Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20190123065618.3520-15-yang.zhong@intel.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 default-configs/riscv32-softmmu.mak |  7 +++++++
 default-configs/riscv64-softmmu.mak |  7 +++++++
 hw/riscv/Makefile.objs              | 22 +++++++++++-----------
 3 files changed, 25 insertions(+), 11 deletions(-)

diff --git a/default-configs/riscv32-softmmu.mak b/default-configs/riscv32-softmmu.mak
index fbfd1d4..6533716 100644
--- a/default-configs/riscv32-softmmu.mak
+++ b/default-configs/riscv32-softmmu.mak
@@ -12,3 +12,10 @@ CONFIG_PCI_EXPRESS_GENERIC_BRIDGE=y
 
 CONFIG_VGA=y
 CONFIG_VGA_PCI=y
+
+CONFIG_SPIKE=y
+CONFIG_HART=y
+CONFIG_SIFIVE_E=y
+CONFIG_SIFIVE=y
+CONFIG_SIFIVE_U=y
+CONFIG_RISCV_VIRT=y
diff --git a/default-configs/riscv64-softmmu.mak b/default-configs/riscv64-softmmu.mak
index fbfd1d4..6533716 100644
--- a/default-configs/riscv64-softmmu.mak
+++ b/default-configs/riscv64-softmmu.mak
@@ -12,3 +12,10 @@ CONFIG_PCI_EXPRESS_GENERIC_BRIDGE=y
 
 CONFIG_VGA=y
 CONFIG_VGA_PCI=y
+
+CONFIG_SPIKE=y
+CONFIG_HART=y
+CONFIG_SIFIVE_E=y
+CONFIG_SIFIVE=y
+CONFIG_SIFIVE_U=y
+CONFIG_RISCV_VIRT=y
diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs
index 1dde01d..79bfb3a 100644
--- a/hw/riscv/Makefile.objs
+++ b/hw/riscv/Makefile.objs
@@ -1,11 +1,11 @@
-obj-y += riscv_htif.o
-obj-y += riscv_hart.o
-obj-y += sifive_e.o
-obj-y += sifive_clint.o
-obj-y += sifive_prci.o
-obj-y += sifive_plic.o
-obj-y += sifive_test.o
-obj-y += sifive_u.o
-obj-y += sifive_uart.o
-obj-y += spike.o
-obj-y += virt.o
+obj-$(CONFIG_SPIKE) += riscv_htif.o
+obj-$(CONFIG_HART) += riscv_hart.o
+obj-$(CONFIG_SIFIVE_E) += sifive_e.o
+obj-$(CONFIG_SIFIVE) += sifive_clint.o
+obj-$(CONFIG_SIFIVE) += sifive_prci.o
+obj-$(CONFIG_SIFIVE) += sifive_plic.o
+obj-$(CONFIG_SIFIVE) += sifive_test.o
+obj-$(CONFIG_SIFIVE_U) += sifive_u.o
+obj-$(CONFIG_SIFIVE) += sifive_uart.o
+obj-$(CONFIG_SPIKE) += spike.o
+obj-$(CONFIG_RISCV_VIRT) += virt.o
-- 
1.8.3.1