| 1 | target-arm queue: | 1 | Two small bugfixes, plus most of RTH's refactoring of cpregs |
|---|---|---|---|
| 2 | * mostly my latest v8M stuff, plus a couple of minor patches | 2 | handling. |
| 3 | 3 | ||
| 4 | The following changes since commit a0b261db8c030813e30a39eae47359ac2a37f7e2: | 4 | -- PMM |
| 5 | 5 | ||
| 6 | Merge remote-tracking branch 'remotes/ehabkost/tags/python-next-pull-request' into staging (2017-10-12 10:02:09 +0100) | 6 | The following changes since commit 1fba9dc71a170b3a05b9d3272dd8ecfe7f26e215: |
| 7 | 7 | ||
| 8 | are available in the git repository at: | 8 | Merge tag 'pull-request-2022-05-04' of https://gitlab.com/thuth/qemu into staging (2022-05-04 08:07:02 -0700) |
| 9 | 9 | ||
| 10 | git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20171012 | 10 | are available in the Git repository at: |
| 11 | 11 | ||
| 12 | for you to fetch changes up to cf5f7937b05c84d5565134f058c00cd48304a117: | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220505 |
| 13 | 13 | ||
| 14 | nvic: Fix miscalculation of offsets into ITNS array (2017-10-12 16:33:16 +0100) | 14 | for you to fetch changes up to 99a50d1a67c602126fc2b3a4812d3000eba9bf34: |
| 15 | |||
| 16 | target/arm: read access to performance counters from EL0 (2022-05-05 09:36:22 +0100) | ||
| 15 | 17 | ||
| 16 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
| 17 | target-arm queue: | 19 | target-arm queue: |
| 18 | * v8M: SG, BLXNS, secure-return | 20 | * Enable read access to performance counters from EL0 |
| 19 | * v8M: fixes for coverity issues in previous patches | 21 | * Enable SCTLR_EL1.BT0 for aarch64-linux-user |
| 20 | * arm: fix armv7m_init() declaration to match definition | 22 | * Refactoring of cpreg handling |
| 21 | * watchdog/aspeed: fix variable type to store reload value | ||
| 22 | 23 | ||
| 23 | ---------------------------------------------------------------- | 24 | ---------------------------------------------------------------- |
| 24 | Cédric Le Goater (1): | 25 | Alex Zuepke (1): |
| 25 | watchdog/aspeed: fix variable type to store reload value | 26 | target/arm: read access to performance counters from EL0 |
| 26 | 27 | ||
| 27 | Igor Mammedov (1): | 28 | Richard Henderson (22): |
| 28 | arm: fix armv7m_init() declaration to match definition | 29 | target/arm: Enable SCTLR_EL1.BT0 for aarch64-linux-user |
| 30 | target/arm: Split out cpregs.h | ||
| 31 | target/arm: Reorg CPAccessResult and access_check_cp_reg | ||
| 32 | target/arm: Replace sentinels with ARRAY_SIZE in cpregs.h | ||
| 33 | target/arm: Make some more cpreg data static const | ||
| 34 | target/arm: Reorg ARMCPRegInfo type field bits | ||
| 35 | target/arm: Avoid bare abort() or assert(0) | ||
| 36 | target/arm: Change cpreg access permissions to enum | ||
| 37 | target/arm: Name CPState type | ||
| 38 | target/arm: Name CPSecureState type | ||
| 39 | target/arm: Drop always-true test in define_arm_vh_e2h_redirects_aliases | ||
| 40 | target/arm: Store cpregs key in the hash table directly | ||
| 41 | target/arm: Merge allocation of the cpreg and its name | ||
| 42 | target/arm: Hoist computation of key in add_cpreg_to_hashtable | ||
| 43 | target/arm: Consolidate cpreg updates in add_cpreg_to_hashtable | ||
| 44 | target/arm: Use bool for is64 and ns in add_cpreg_to_hashtable | ||
| 45 | target/arm: Hoist isbanked computation in add_cpreg_to_hashtable | ||
| 46 | target/arm: Perform override check early in add_cpreg_to_hashtable | ||
| 47 | target/arm: Reformat comments in add_cpreg_to_hashtable | ||
| 48 | target/arm: Remove HOST_BIG_ENDIAN ifdef in add_cpreg_to_hashtable | ||
| 49 | target/arm: Add isar predicates for FEAT_Debugv8p2 | ||
| 50 | target/arm: Add isar_feature_{aa64,any}_ras | ||
| 29 | 51 | ||
| 30 | Peter Maydell (11): | 52 | target/arm/cpregs.h | 453 ++++++++++++++++++++++++++++++++++++++ |
| 31 | target/arm: Add M profile secure MMU index values to get_a32_user_mem_index() | 53 | target/arm/cpu.h | 393 +++------------------------------ |
| 32 | target/arm: Implement SG instruction | 54 | hw/arm/pxa2xx.c | 2 +- |
| 33 | target/arm: Implement BLXNS | 55 | hw/arm/pxa2xx_pic.c | 2 +- |
| 34 | target/arm: Implement secure function return | 56 | hw/intc/arm_gicv3_cpuif.c | 6 +- |
| 35 | target-arm: Don't check for "Thumb2 or M profile" for not-Thumb1 | 57 | hw/intc/arm_gicv3_kvm.c | 3 +- |
| 36 | target/arm: Pull Thumb insn word loads up to top level | 58 | target/arm/cpu.c | 25 +-- |
| 37 | target-arm: Simplify insn_crosses_page() | 59 | target/arm/cpu64.c | 2 +- |
| 38 | target/arm: Support some Thumb insns being always unconditional | 60 | target/arm/cpu_tcg.c | 5 +- |
| 39 | target/arm: Implement SG instruction corner cases | 61 | target/arm/gdbstub.c | 5 +- |
| 40 | nvic: Add missing 'break' | 62 | target/arm/helper.c | 358 +++++++++++++----------------- |
| 41 | nvic: Fix miscalculation of offsets into ITNS array | 63 | target/arm/hvf/hvf.c | 2 +- |
| 42 | 64 | target/arm/kvm-stub.c | 4 +- | |
| 43 | include/hw/arm/arm.h | 2 +- | 65 | target/arm/kvm.c | 4 +- |
| 44 | target/arm/helper.h | 1 + | 66 | target/arm/machine.c | 4 +- |
| 45 | target/arm/internals.h | 8 ++ | 67 | target/arm/op_helper.c | 57 ++--- |
| 46 | hw/intc/armv7m_nvic.c | 5 +- | 68 | target/arm/translate-a64.c | 14 +- |
| 47 | hw/watchdog/wdt_aspeed.c | 4 +- | 69 | target/arm/translate-neon.c | 2 +- |
| 48 | target/arm/helper.c | 306 ++++++++++++++++++++++++++++++++++++++++++++-- | 70 | target/arm/translate.c | 13 +- |
| 49 | target/arm/translate.c | 310 ++++++++++++++++++++++++++++++++--------------- | 71 | tests/tcg/aarch64/bti-3.c | 42 ++++ |
| 50 | 7 files changed, 521 insertions(+), 115 deletions(-) | 72 | tests/tcg/aarch64/Makefile.target | 6 +- |
| 51 | 73 | 21 files changed, 738 insertions(+), 664 deletions(-) | |
| 74 | create mode 100644 target/arm/cpregs.h | ||
| 75 | create mode 100644 tests/tcg/aarch64/bti-3.c | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 1 | 2 | ||
| 3 | This controls whether the PACI{A,B}SP instructions trap with BTYPE=3 | ||
| 4 | (indirect branch from register other than x16/x17). The linux kernel | ||
| 5 | sets this in bti_enable(). | ||
| 6 | |||
| 7 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/998 | ||
| 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | Message-id: 20220427042312.294300-1-richard.henderson@linaro.org | ||
| 11 | [PMM: remove stray change to makefile comment] | ||
| 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 13 | --- | ||
| 14 | target/arm/cpu.c | 2 ++ | ||
| 15 | tests/tcg/aarch64/bti-3.c | 42 +++++++++++++++++++++++++++++++ | ||
| 16 | tests/tcg/aarch64/Makefile.target | 6 ++--- | ||
| 17 | 3 files changed, 47 insertions(+), 3 deletions(-) | ||
| 18 | create mode 100644 tests/tcg/aarch64/bti-3.c | ||
| 19 | |||
| 20 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
| 21 | index XXXXXXX..XXXXXXX 100644 | ||
| 22 | --- a/target/arm/cpu.c | ||
| 23 | +++ b/target/arm/cpu.c | ||
| 24 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev) | ||
| 25 | /* Enable all PAC keys. */ | ||
| 26 | env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | | ||
| 27 | SCTLR_EnDA | SCTLR_EnDB); | ||
| 28 | + /* Trap on btype=3 for PACIxSP. */ | ||
| 29 | + env->cp15.sctlr_el[1] |= SCTLR_BT0; | ||
| 30 | /* and to the FP/Neon instructions */ | ||
| 31 | env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); | ||
| 32 | /* and to the SVE instructions */ | ||
| 33 | diff --git a/tests/tcg/aarch64/bti-3.c b/tests/tcg/aarch64/bti-3.c | ||
| 34 | new file mode 100644 | ||
| 35 | index XXXXXXX..XXXXXXX | ||
| 36 | --- /dev/null | ||
| 37 | +++ b/tests/tcg/aarch64/bti-3.c | ||
| 38 | @@ -XXX,XX +XXX,XX @@ | ||
| 39 | +/* | ||
| 40 | + * BTI vs PACIASP | ||
| 41 | + */ | ||
| 42 | + | ||
| 43 | +#include "bti-crt.inc.c" | ||
| 44 | + | ||
| 45 | +static void skip2_sigill(int sig, siginfo_t *info, ucontext_t *uc) | ||
| 46 | +{ | ||
| 47 | + uc->uc_mcontext.pc += 8; | ||
| 48 | + uc->uc_mcontext.pstate = 1; | ||
| 49 | +} | ||
| 50 | + | ||
| 51 | +#define BTYPE_1() \ | ||
| 52 | + asm("mov %0,#1; adr x16, 1f; br x16; 1: hint #25; mov %0,#0" \ | ||
| 53 | + : "=r"(skipped) : : "x16", "x30") | ||
| 54 | + | ||
| 55 | +#define BTYPE_2() \ | ||
| 56 | + asm("mov %0,#1; adr x16, 1f; blr x16; 1: hint #25; mov %0,#0" \ | ||
| 57 | + : "=r"(skipped) : : "x16", "x30") | ||
| 58 | + | ||
| 59 | +#define BTYPE_3() \ | ||
| 60 | + asm("mov %0,#1; adr x15, 1f; br x15; 1: hint #25; mov %0,#0" \ | ||
| 61 | + : "=r"(skipped) : : "x15", "x30") | ||
| 62 | + | ||
| 63 | +#define TEST(WHICH, EXPECT) \ | ||
| 64 | + do { WHICH(); fail += skipped ^ EXPECT; } while (0) | ||
| 65 | + | ||
| 66 | +int main() | ||
| 67 | +{ | ||
| 68 | + int fail = 0; | ||
| 69 | + int skipped; | ||
| 70 | + | ||
| 71 | + /* Signal-like with SA_SIGINFO. */ | ||
| 72 | + signal_info(SIGILL, skip2_sigill); | ||
| 73 | + | ||
| 74 | + /* With SCTLR_EL1.BT0 set, PACIASP is not compatible with type=3. */ | ||
| 75 | + TEST(BTYPE_1, 0); | ||
| 76 | + TEST(BTYPE_2, 0); | ||
| 77 | + TEST(BTYPE_3, 1); | ||
| 78 | + | ||
| 79 | + return fail; | ||
| 80 | +} | ||
| 81 | diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target | ||
| 82 | index XXXXXXX..XXXXXXX 100644 | ||
| 83 | --- a/tests/tcg/aarch64/Makefile.target | ||
| 84 | +++ b/tests/tcg/aarch64/Makefile.target | ||
| 85 | @@ -XXX,XX +XXX,XX @@ endif | ||
| 86 | # BTI Tests | ||
| 87 | # bti-1 tests the elf notes, so we require special compiler support. | ||
| 88 | ifneq ($(CROSS_CC_HAS_ARMV8_BTI),) | ||
| 89 | -AARCH64_TESTS += bti-1 | ||
| 90 | -bti-1: CFLAGS += -mbranch-protection=standard | ||
| 91 | -bti-1: LDFLAGS += -nostdlib | ||
| 92 | +AARCH64_TESTS += bti-1 bti-3 | ||
| 93 | +bti-1 bti-3: CFLAGS += -mbranch-protection=standard | ||
| 94 | +bti-1 bti-3: LDFLAGS += -nostdlib | ||
| 95 | endif | ||
| 96 | # bti-2 tests PROT_BTI, so no special compiler support required. | ||
| 97 | AARCH64_TESTS += bti-2 | ||
| 98 | -- | ||
| 99 | 2.25.1 | diff view generated by jsdifflib |
| 1 | Recent changes have left insn_crosses_page() more complicated | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | than it needed to be: | ||
| 3 | * it's only called from thumb_tr_translate_insn() so we know | ||
| 4 | for certain that we're looking at a Thumb insn | ||
| 5 | * the caller's check for dc->pc >= dc->next_page_start - 3 | ||
| 6 | means that dc->pc can't possibly be 4 aligned, so there's | ||
| 7 | no need to check that (the check was partly there to ensure | ||
| 8 | that we didn't treat an ARM insn as Thumb, I think) | ||
| 9 | * we now have thumb_insn_is_16bit() which lets us do a precise | ||
| 10 | check of the length of the next insn, rather than opencoding | ||
| 11 | an inaccurate check | ||
| 12 | 2 | ||
| 13 | Simplify it down to just loading the first half of the insn | 3 | Move ARMCPRegInfo and all related declarations to a new |
| 14 | and calling thumb_insn_is_16bit() on it. | 4 | internal header, out of the public cpu.h. |
| 15 | 5 | ||
| 6 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
| 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 9 | Message-id: 20220501055028.646596-2-richard.henderson@linaro.org | ||
| 16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 17 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 18 | Message-id: 1507556919-24992-8-git-send-email-peter.maydell@linaro.org | ||
| 19 | --- | 11 | --- |
| 20 | target/arm/translate.c | 27 ++++++--------------------- | 12 | target/arm/cpregs.h | 413 +++++++++++++++++++++++++++++++++++++ |
| 21 | 1 file changed, 6 insertions(+), 21 deletions(-) | 13 | target/arm/cpu.h | 368 --------------------------------- |
| 14 | hw/arm/pxa2xx.c | 1 + | ||
| 15 | hw/arm/pxa2xx_pic.c | 1 + | ||
| 16 | hw/intc/arm_gicv3_cpuif.c | 1 + | ||
| 17 | hw/intc/arm_gicv3_kvm.c | 2 + | ||
| 18 | target/arm/cpu.c | 1 + | ||
| 19 | target/arm/cpu64.c | 1 + | ||
| 20 | target/arm/cpu_tcg.c | 1 + | ||
| 21 | target/arm/gdbstub.c | 3 +- | ||
| 22 | target/arm/helper.c | 1 + | ||
| 23 | target/arm/op_helper.c | 1 + | ||
| 24 | target/arm/translate-a64.c | 4 +- | ||
| 25 | target/arm/translate.c | 3 +- | ||
| 26 | 14 files changed, 427 insertions(+), 374 deletions(-) | ||
| 27 | create mode 100644 target/arm/cpregs.h | ||
| 22 | 28 | ||
| 29 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h | ||
| 30 | new file mode 100644 | ||
| 31 | index XXXXXXX..XXXXXXX | ||
| 32 | --- /dev/null | ||
| 33 | +++ b/target/arm/cpregs.h | ||
| 34 | @@ -XXX,XX +XXX,XX @@ | ||
| 35 | +/* | ||
| 36 | + * QEMU ARM CP Register access and descriptions | ||
| 37 | + * | ||
| 38 | + * Copyright (c) 2022 Linaro Ltd | ||
| 39 | + * | ||
| 40 | + * This program is free software; you can redistribute it and/or | ||
| 41 | + * modify it under the terms of the GNU General Public License | ||
| 42 | + * as published by the Free Software Foundation; either version 2 | ||
| 43 | + * of the License, or (at your option) any later version. | ||
| 44 | + * | ||
| 45 | + * This program is distributed in the hope that it will be useful, | ||
| 46 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 47 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 48 | + * GNU General Public License for more details. | ||
| 49 | + * | ||
| 50 | + * You should have received a copy of the GNU General Public License | ||
| 51 | + * along with this program; if not, see | ||
| 52 | + * <http://www.gnu.org/licenses/gpl-2.0.html> | ||
| 53 | + */ | ||
| 54 | + | ||
| 55 | +#ifndef TARGET_ARM_CPREGS_H | ||
| 56 | +#define TARGET_ARM_CPREGS_H | ||
| 57 | + | ||
| 58 | +/* | ||
| 59 | + * ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a | ||
| 60 | + * special-behaviour cp reg and bits [11..8] indicate what behaviour | ||
| 61 | + * it has. Otherwise it is a simple cp reg, where CONST indicates that | ||
| 62 | + * TCG can assume the value to be constant (ie load at translate time) | ||
| 63 | + * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END | ||
| 64 | + * indicates that the TB should not be ended after a write to this register | ||
| 65 | + * (the default is that the TB ends after cp writes). OVERRIDE permits | ||
| 66 | + * a register definition to override a previous definition for the | ||
| 67 | + * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the | ||
| 68 | + * old must have the OVERRIDE bit set. | ||
| 69 | + * ALIAS indicates that this register is an alias view of some underlying | ||
| 70 | + * state which is also visible via another register, and that the other | ||
| 71 | + * register is handling migration and reset; registers marked ALIAS will not be | ||
| 72 | + * migrated but may have their state set by syncing of register state from KVM. | ||
| 73 | + * NO_RAW indicates that this register has no underlying state and does not | ||
| 74 | + * support raw access for state saving/loading; it will not be used for either | ||
| 75 | + * migration or KVM state synchronization. (Typically this is for "registers" | ||
| 76 | + * which are actually used as instructions for cache maintenance and so on.) | ||
| 77 | + * IO indicates that this register does I/O and therefore its accesses | ||
| 78 | + * need to be marked with gen_io_start() and also end the TB. In particular, | ||
| 79 | + * registers which implement clocks or timers require this. | ||
| 80 | + * RAISES_EXC is for when the read or write hook might raise an exception; | ||
| 81 | + * the generated code will synchronize the CPU state before calling the hook | ||
| 82 | + * so that it is safe for the hook to call raise_exception(). | ||
| 83 | + * NEWEL is for writes to registers that might change the exception | ||
| 84 | + * level - typically on older ARM chips. For those cases we need to | ||
| 85 | + * re-read the new el when recomputing the translation flags. | ||
| 86 | + */ | ||
| 87 | +#define ARM_CP_SPECIAL 0x0001 | ||
| 88 | +#define ARM_CP_CONST 0x0002 | ||
| 89 | +#define ARM_CP_64BIT 0x0004 | ||
| 90 | +#define ARM_CP_SUPPRESS_TB_END 0x0008 | ||
| 91 | +#define ARM_CP_OVERRIDE 0x0010 | ||
| 92 | +#define ARM_CP_ALIAS 0x0020 | ||
| 93 | +#define ARM_CP_IO 0x0040 | ||
| 94 | +#define ARM_CP_NO_RAW 0x0080 | ||
| 95 | +#define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) | ||
| 96 | +#define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) | ||
| 97 | +#define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) | ||
| 98 | +#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) | ||
| 99 | +#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) | ||
| 100 | +#define ARM_CP_DC_GVA (ARM_CP_SPECIAL | 0x0600) | ||
| 101 | +#define ARM_CP_DC_GZVA (ARM_CP_SPECIAL | 0x0700) | ||
| 102 | +#define ARM_LAST_SPECIAL ARM_CP_DC_GZVA | ||
| 103 | +#define ARM_CP_FPU 0x1000 | ||
| 104 | +#define ARM_CP_SVE 0x2000 | ||
| 105 | +#define ARM_CP_NO_GDB 0x4000 | ||
| 106 | +#define ARM_CP_RAISES_EXC 0x8000 | ||
| 107 | +#define ARM_CP_NEWEL 0x10000 | ||
| 108 | +/* Used only as a terminator for ARMCPRegInfo lists */ | ||
| 109 | +#define ARM_CP_SENTINEL 0xfffff | ||
| 110 | +/* Mask of only the flag bits in a type field */ | ||
| 111 | +#define ARM_CP_FLAG_MASK 0x1f0ff | ||
| 112 | + | ||
| 113 | +/* | ||
| 114 | + * Valid values for ARMCPRegInfo state field, indicating which of | ||
| 115 | + * the AArch32 and AArch64 execution states this register is visible in. | ||
| 116 | + * If the reginfo doesn't explicitly specify then it is AArch32 only. | ||
| 117 | + * If the reginfo is declared to be visible in both states then a second | ||
| 118 | + * reginfo is synthesised for the AArch32 view of the AArch64 register, | ||
| 119 | + * such that the AArch32 view is the lower 32 bits of the AArch64 one. | ||
| 120 | + * Note that we rely on the values of these enums as we iterate through | ||
| 121 | + * the various states in some places. | ||
| 122 | + */ | ||
| 123 | +enum { | ||
| 124 | + ARM_CP_STATE_AA32 = 0, | ||
| 125 | + ARM_CP_STATE_AA64 = 1, | ||
| 126 | + ARM_CP_STATE_BOTH = 2, | ||
| 127 | +}; | ||
| 128 | + | ||
| 129 | +/* | ||
| 130 | + * ARM CP register secure state flags. These flags identify security state | ||
| 131 | + * attributes for a given CP register entry. | ||
| 132 | + * The existence of both or neither secure and non-secure flags indicates that | ||
| 133 | + * the register has both a secure and non-secure hash entry. A single one of | ||
| 134 | + * these flags causes the register to only be hashed for the specified | ||
| 135 | + * security state. | ||
| 136 | + * Although definitions may have any combination of the S/NS bits, each | ||
| 137 | + * registered entry will only have one to identify whether the entry is secure | ||
| 138 | + * or non-secure. | ||
| 139 | + */ | ||
| 140 | +enum { | ||
| 141 | + ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ | ||
| 142 | + ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ | ||
| 143 | +}; | ||
| 144 | + | ||
| 145 | +/* | ||
| 146 | + * Return true if cptype is a valid type field. This is used to try to | ||
| 147 | + * catch errors where the sentinel has been accidentally left off the end | ||
| 148 | + * of a list of registers. | ||
| 149 | + */ | ||
| 150 | +static inline bool cptype_valid(int cptype) | ||
| 151 | +{ | ||
| 152 | + return ((cptype & ~ARM_CP_FLAG_MASK) == 0) | ||
| 153 | + || ((cptype & ARM_CP_SPECIAL) && | ||
| 154 | + ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); | ||
| 155 | +} | ||
| 156 | + | ||
| 157 | +/* | ||
| 158 | + * Access rights: | ||
| 159 | + * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM | ||
| 160 | + * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and | ||
| 161 | + * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 | ||
| 162 | + * (ie any of the privileged modes in Secure state, or Monitor mode). | ||
| 163 | + * If a register is accessible in one privilege level it's always accessible | ||
| 164 | + * in higher privilege levels too. Since "Secure PL1" also follows this rule | ||
| 165 | + * (ie anything visible in PL2 is visible in S-PL1, some things are only | ||
| 166 | + * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the | ||
| 167 | + * terminology a little and call this PL3. | ||
| 168 | + * In AArch64 things are somewhat simpler as the PLx bits line up exactly | ||
| 169 | + * with the ELx exception levels. | ||
| 170 | + * | ||
| 171 | + * If access permissions for a register are more complex than can be | ||
| 172 | + * described with these bits, then use a laxer set of restrictions, and | ||
| 173 | + * do the more restrictive/complex check inside a helper function. | ||
| 174 | + */ | ||
| 175 | +#define PL3_R 0x80 | ||
| 176 | +#define PL3_W 0x40 | ||
| 177 | +#define PL2_R (0x20 | PL3_R) | ||
| 178 | +#define PL2_W (0x10 | PL3_W) | ||
| 179 | +#define PL1_R (0x08 | PL2_R) | ||
| 180 | +#define PL1_W (0x04 | PL2_W) | ||
| 181 | +#define PL0_R (0x02 | PL1_R) | ||
| 182 | +#define PL0_W (0x01 | PL1_W) | ||
| 183 | + | ||
| 184 | +/* | ||
| 185 | + * For user-mode some registers are accessible to EL0 via a kernel | ||
| 186 | + * trap-and-emulate ABI. In this case we define the read permissions | ||
| 187 | + * as actually being PL0_R. However some bits of any given register | ||
| 188 | + * may still be masked. | ||
| 189 | + */ | ||
| 190 | +#ifdef CONFIG_USER_ONLY | ||
| 191 | +#define PL0U_R PL0_R | ||
| 192 | +#else | ||
| 193 | +#define PL0U_R PL1_R | ||
| 194 | +#endif | ||
| 195 | + | ||
| 196 | +#define PL3_RW (PL3_R | PL3_W) | ||
| 197 | +#define PL2_RW (PL2_R | PL2_W) | ||
| 198 | +#define PL1_RW (PL1_R | PL1_W) | ||
| 199 | +#define PL0_RW (PL0_R | PL0_W) | ||
| 200 | + | ||
| 201 | +typedef enum CPAccessResult { | ||
| 202 | + /* Access is permitted */ | ||
| 203 | + CP_ACCESS_OK = 0, | ||
| 204 | + /* | ||
| 205 | + * Access fails due to a configurable trap or enable which would | ||
| 206 | + * result in a categorized exception syndrome giving information about | ||
| 207 | + * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, | ||
| 208 | + * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or | ||
| 209 | + * PL1 if in EL0, otherwise to the current EL). | ||
| 210 | + */ | ||
| 211 | + CP_ACCESS_TRAP = 1, | ||
| 212 | + /* | ||
| 213 | + * Access fails and results in an exception syndrome 0x0 ("uncategorized"). | ||
| 214 | + * Note that this is not a catch-all case -- the set of cases which may | ||
| 215 | + * result in this failure is specifically defined by the architecture. | ||
| 216 | + */ | ||
| 217 | + CP_ACCESS_TRAP_UNCATEGORIZED = 2, | ||
| 218 | + /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ | ||
| 219 | + CP_ACCESS_TRAP_EL2 = 3, | ||
| 220 | + CP_ACCESS_TRAP_EL3 = 4, | ||
| 221 | + /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ | ||
| 222 | + CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, | ||
| 223 | + CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, | ||
| 224 | +} CPAccessResult; | ||
| 225 | + | ||
| 226 | +typedef struct ARMCPRegInfo ARMCPRegInfo; | ||
| 227 | + | ||
| 228 | +/* | ||
| 229 | + * Access functions for coprocessor registers. These cannot fail and | ||
| 230 | + * may not raise exceptions. | ||
| 231 | + */ | ||
| 232 | +typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); | ||
| 233 | +typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, | ||
| 234 | + uint64_t value); | ||
| 235 | +/* Access permission check functions for coprocessor registers. */ | ||
| 236 | +typedef CPAccessResult CPAccessFn(CPUARMState *env, | ||
| 237 | + const ARMCPRegInfo *opaque, | ||
| 238 | + bool isread); | ||
| 239 | +/* Hook function for register reset */ | ||
| 240 | +typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); | ||
| 241 | + | ||
| 242 | +#define CP_ANY 0xff | ||
| 243 | + | ||
| 244 | +/* Definition of an ARM coprocessor register */ | ||
| 245 | +struct ARMCPRegInfo { | ||
| 246 | + /* Name of register (useful mainly for debugging, need not be unique) */ | ||
| 247 | + const char *name; | ||
| 248 | + /* | ||
| 249 | + * Location of register: coprocessor number and (crn,crm,opc1,opc2) | ||
| 250 | + * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a | ||
| 251 | + * 'wildcard' field -- any value of that field in the MRC/MCR insn | ||
| 252 | + * will be decoded to this register. The register read and write | ||
| 253 | + * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 | ||
| 254 | + * used by the program, so it is possible to register a wildcard and | ||
| 255 | + * then behave differently on read/write if necessary. | ||
| 256 | + * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 | ||
| 257 | + * must both be zero. | ||
| 258 | + * For AArch64-visible registers, opc0 is also used. | ||
| 259 | + * Since there are no "coprocessors" in AArch64, cp is purely used as a | ||
| 260 | + * way to distinguish (for KVM's benefit) guest-visible system registers | ||
| 261 | + * from demuxed ones provided to preserve the "no side effects on | ||
| 262 | + * KVM register read/write from QEMU" semantics. cp==0x13 is guest | ||
| 263 | + * visible (to match KVM's encoding); cp==0 will be converted to | ||
| 264 | + * cp==0x13 when the ARMCPRegInfo is registered, for convenience. | ||
| 265 | + */ | ||
| 266 | + uint8_t cp; | ||
| 267 | + uint8_t crn; | ||
| 268 | + uint8_t crm; | ||
| 269 | + uint8_t opc0; | ||
| 270 | + uint8_t opc1; | ||
| 271 | + uint8_t opc2; | ||
| 272 | + /* Execution state in which this register is visible: ARM_CP_STATE_* */ | ||
| 273 | + int state; | ||
| 274 | + /* Register type: ARM_CP_* bits/values */ | ||
| 275 | + int type; | ||
| 276 | + /* Access rights: PL*_[RW] */ | ||
| 277 | + int access; | ||
| 278 | + /* Security state: ARM_CP_SECSTATE_* bits/values */ | ||
| 279 | + int secure; | ||
| 280 | + /* | ||
| 281 | + * The opaque pointer passed to define_arm_cp_regs_with_opaque() when | ||
| 282 | + * this register was defined: can be used to hand data through to the | ||
| 283 | + * register read/write functions, since they are passed the ARMCPRegInfo*. | ||
| 284 | + */ | ||
| 285 | + void *opaque; | ||
| 286 | + /* | ||
| 287 | + * Value of this register, if it is ARM_CP_CONST. Otherwise, if | ||
| 288 | + * fieldoffset is non-zero, the reset value of the register. | ||
| 289 | + */ | ||
| 290 | + uint64_t resetvalue; | ||
| 291 | + /* | ||
| 292 | + * Offset of the field in CPUARMState for this register. | ||
| 293 | + * This is not needed if either: | ||
| 294 | + * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs | ||
| 295 | + * 2. both readfn and writefn are specified | ||
| 296 | + */ | ||
| 297 | + ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ | ||
| 298 | + | ||
| 299 | + /* | ||
| 300 | + * Offsets of the secure and non-secure fields in CPUARMState for the | ||
| 301 | + * register if it is banked. These fields are only used during the static | ||
| 302 | + * registration of a register. During hashing the bank associated | ||
| 303 | + * with a given security state is copied to fieldoffset which is used from | ||
| 304 | + * there on out. | ||
| 305 | + * | ||
| 306 | + * It is expected that register definitions use either fieldoffset or | ||
| 307 | + * bank_fieldoffsets in the definition but not both. It is also expected | ||
| 308 | + * that both bank offsets are set when defining a banked register. This | ||
| 309 | + * use indicates that a register is banked. | ||
| 310 | + */ | ||
| 311 | + ptrdiff_t bank_fieldoffsets[2]; | ||
| 312 | + | ||
| 313 | + /* | ||
| 314 | + * Function for making any access checks for this register in addition to | ||
| 315 | + * those specified by the 'access' permissions bits. If NULL, no extra | ||
| 316 | + * checks required. The access check is performed at runtime, not at | ||
| 317 | + * translate time. | ||
| 318 | + */ | ||
| 319 | + CPAccessFn *accessfn; | ||
| 320 | + /* | ||
| 321 | + * Function for handling reads of this register. If NULL, then reads | ||
| 322 | + * will be done by loading from the offset into CPUARMState specified | ||
| 323 | + * by fieldoffset. | ||
| 324 | + */ | ||
| 325 | + CPReadFn *readfn; | ||
| 326 | + /* | ||
| 327 | + * Function for handling writes of this register. If NULL, then writes | ||
| 328 | + * will be done by writing to the offset into CPUARMState specified | ||
| 329 | + * by fieldoffset. | ||
| 330 | + */ | ||
| 331 | + CPWriteFn *writefn; | ||
| 332 | + /* | ||
| 333 | + * Function for doing a "raw" read; used when we need to copy | ||
| 334 | + * coprocessor state to the kernel for KVM or out for | ||
| 335 | + * migration. This only needs to be provided if there is also a | ||
| 336 | + * readfn and it has side effects (for instance clear-on-read bits). | ||
| 337 | + */ | ||
| 338 | + CPReadFn *raw_readfn; | ||
| 339 | + /* | ||
| 340 | + * Function for doing a "raw" write; used when we need to copy KVM | ||
| 341 | + * kernel coprocessor state into userspace, or for inbound | ||
| 342 | + * migration. This only needs to be provided if there is also a | ||
| 343 | + * writefn and it masks out "unwritable" bits or has write-one-to-clear | ||
| 344 | + * or similar behaviour. | ||
| 345 | + */ | ||
| 346 | + CPWriteFn *raw_writefn; | ||
| 347 | + /* | ||
| 348 | + * Function for resetting the register. If NULL, then reset will be done | ||
| 349 | + * by writing resetvalue to the field specified in fieldoffset. If | ||
| 350 | + * fieldoffset is 0 then no reset will be done. | ||
| 351 | + */ | ||
| 352 | + CPResetFn *resetfn; | ||
| 353 | + | ||
| 354 | + /* | ||
| 355 | + * "Original" writefn and readfn. | ||
| 356 | + * For ARMv8.1-VHE register aliases, we overwrite the read/write | ||
| 357 | + * accessor functions of various EL1/EL0 to perform the runtime | ||
| 358 | + * check for which sysreg should actually be modified, and then | ||
| 359 | + * forwards the operation. Before overwriting the accessors, | ||
| 360 | + * the original function is copied here, so that accesses that | ||
| 361 | + * really do go to the EL1/EL0 version proceed normally. | ||
| 362 | + * (The corresponding EL2 register is linked via opaque.) | ||
| 363 | + */ | ||
| 364 | + CPReadFn *orig_readfn; | ||
| 365 | + CPWriteFn *orig_writefn; | ||
| 366 | +}; | ||
| 367 | + | ||
| 368 | +/* | ||
| 369 | + * Macros which are lvalues for the field in CPUARMState for the | ||
| 370 | + * ARMCPRegInfo *ri. | ||
| 371 | + */ | ||
| 372 | +#define CPREG_FIELD32(env, ri) \ | ||
| 373 | + (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) | ||
| 374 | +#define CPREG_FIELD64(env, ri) \ | ||
| 375 | + (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) | ||
| 376 | + | ||
| 377 | +#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } | ||
| 378 | + | ||
| 379 | +void define_arm_cp_regs_with_opaque(ARMCPU *cpu, | ||
| 380 | + const ARMCPRegInfo *regs, void *opaque); | ||
| 381 | +void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, | ||
| 382 | + const ARMCPRegInfo *regs, void *opaque); | ||
| 383 | +static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) | ||
| 384 | +{ | ||
| 385 | + define_arm_cp_regs_with_opaque(cpu, regs, 0); | ||
| 386 | +} | ||
| 387 | +static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) | ||
| 388 | +{ | ||
| 389 | + define_one_arm_cp_reg_with_opaque(cpu, regs, 0); | ||
| 390 | +} | ||
| 391 | +const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); | ||
| 392 | + | ||
| 393 | +/* | ||
| 394 | + * Definition of an ARM co-processor register as viewed from | ||
| 395 | + * userspace. This is used for presenting sanitised versions of | ||
| 396 | + * registers to userspace when emulating the Linux AArch64 CPU | ||
| 397 | + * ID/feature ABI (advertised as HWCAP_CPUID). | ||
| 398 | + */ | ||
| 399 | +typedef struct ARMCPRegUserSpaceInfo { | ||
| 400 | + /* Name of register */ | ||
| 401 | + const char *name; | ||
| 402 | + | ||
| 403 | + /* Is the name actually a glob pattern */ | ||
| 404 | + bool is_glob; | ||
| 405 | + | ||
| 406 | + /* Only some bits are exported to user space */ | ||
| 407 | + uint64_t exported_bits; | ||
| 408 | + | ||
| 409 | + /* Fixed bits are applied after the mask */ | ||
| 410 | + uint64_t fixed_bits; | ||
| 411 | +} ARMCPRegUserSpaceInfo; | ||
| 412 | + | ||
| 413 | +#define REGUSERINFO_SENTINEL { .name = NULL } | ||
| 414 | + | ||
| 415 | +void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods); | ||
| 416 | + | ||
| 417 | +/* CPWriteFn that can be used to implement writes-ignored behaviour */ | ||
| 418 | +void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 419 | + uint64_t value); | ||
| 420 | +/* CPReadFn that can be used for read-as-zero behaviour */ | ||
| 421 | +uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); | ||
| 422 | + | ||
| 423 | +/* | ||
| 424 | + * CPResetFn that does nothing, for use if no reset is required even | ||
| 425 | + * if fieldoffset is non zero. | ||
| 426 | + */ | ||
| 427 | +void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); | ||
| 428 | + | ||
| 429 | +/* | ||
| 430 | + * Return true if this reginfo struct's field in the cpu state struct | ||
| 431 | + * is 64 bits wide. | ||
| 432 | + */ | ||
| 433 | +static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) | ||
| 434 | +{ | ||
| 435 | + return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); | ||
| 436 | +} | ||
| 437 | + | ||
| 438 | +static inline bool cp_access_ok(int current_el, | ||
| 439 | + const ARMCPRegInfo *ri, int isread) | ||
| 440 | +{ | ||
| 441 | + return (ri->access >> ((current_el * 2) + isread)) & 1; | ||
| 442 | +} | ||
| 443 | + | ||
| 444 | +/* Raw read of a coprocessor register (as needed for migration, etc) */ | ||
| 445 | +uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); | ||
| 446 | + | ||
| 447 | +#endif /* TARGET_ARM_CPREGS_H */ | ||
| 448 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
| 449 | index XXXXXXX..XXXXXXX 100644 | ||
| 450 | --- a/target/arm/cpu.h | ||
| 451 | +++ b/target/arm/cpu.h | ||
| 452 | @@ -XXX,XX +XXX,XX @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) | ||
| 453 | return kvmid; | ||
| 454 | } | ||
| 455 | |||
| 456 | -/* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a | ||
| 457 | - * special-behaviour cp reg and bits [11..8] indicate what behaviour | ||
| 458 | - * it has. Otherwise it is a simple cp reg, where CONST indicates that | ||
| 459 | - * TCG can assume the value to be constant (ie load at translate time) | ||
| 460 | - * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END | ||
| 461 | - * indicates that the TB should not be ended after a write to this register | ||
| 462 | - * (the default is that the TB ends after cp writes). OVERRIDE permits | ||
| 463 | - * a register definition to override a previous definition for the | ||
| 464 | - * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the | ||
| 465 | - * old must have the OVERRIDE bit set. | ||
| 466 | - * ALIAS indicates that this register is an alias view of some underlying | ||
| 467 | - * state which is also visible via another register, and that the other | ||
| 468 | - * register is handling migration and reset; registers marked ALIAS will not be | ||
| 469 | - * migrated but may have their state set by syncing of register state from KVM. | ||
| 470 | - * NO_RAW indicates that this register has no underlying state and does not | ||
| 471 | - * support raw access for state saving/loading; it will not be used for either | ||
| 472 | - * migration or KVM state synchronization. (Typically this is for "registers" | ||
| 473 | - * which are actually used as instructions for cache maintenance and so on.) | ||
| 474 | - * IO indicates that this register does I/O and therefore its accesses | ||
| 475 | - * need to be marked with gen_io_start() and also end the TB. In particular, | ||
| 476 | - * registers which implement clocks or timers require this. | ||
| 477 | - * RAISES_EXC is for when the read or write hook might raise an exception; | ||
| 478 | - * the generated code will synchronize the CPU state before calling the hook | ||
| 479 | - * so that it is safe for the hook to call raise_exception(). | ||
| 480 | - * NEWEL is for writes to registers that might change the exception | ||
| 481 | - * level - typically on older ARM chips. For those cases we need to | ||
| 482 | - * re-read the new el when recomputing the translation flags. | ||
| 483 | - */ | ||
| 484 | -#define ARM_CP_SPECIAL 0x0001 | ||
| 485 | -#define ARM_CP_CONST 0x0002 | ||
| 486 | -#define ARM_CP_64BIT 0x0004 | ||
| 487 | -#define ARM_CP_SUPPRESS_TB_END 0x0008 | ||
| 488 | -#define ARM_CP_OVERRIDE 0x0010 | ||
| 489 | -#define ARM_CP_ALIAS 0x0020 | ||
| 490 | -#define ARM_CP_IO 0x0040 | ||
| 491 | -#define ARM_CP_NO_RAW 0x0080 | ||
| 492 | -#define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) | ||
| 493 | -#define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) | ||
| 494 | -#define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) | ||
| 495 | -#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) | ||
| 496 | -#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) | ||
| 497 | -#define ARM_CP_DC_GVA (ARM_CP_SPECIAL | 0x0600) | ||
| 498 | -#define ARM_CP_DC_GZVA (ARM_CP_SPECIAL | 0x0700) | ||
| 499 | -#define ARM_LAST_SPECIAL ARM_CP_DC_GZVA | ||
| 500 | -#define ARM_CP_FPU 0x1000 | ||
| 501 | -#define ARM_CP_SVE 0x2000 | ||
| 502 | -#define ARM_CP_NO_GDB 0x4000 | ||
| 503 | -#define ARM_CP_RAISES_EXC 0x8000 | ||
| 504 | -#define ARM_CP_NEWEL 0x10000 | ||
| 505 | -/* Used only as a terminator for ARMCPRegInfo lists */ | ||
| 506 | -#define ARM_CP_SENTINEL 0xfffff | ||
| 507 | -/* Mask of only the flag bits in a type field */ | ||
| 508 | -#define ARM_CP_FLAG_MASK 0x1f0ff | ||
| 509 | - | ||
| 510 | -/* Valid values for ARMCPRegInfo state field, indicating which of | ||
| 511 | - * the AArch32 and AArch64 execution states this register is visible in. | ||
| 512 | - * If the reginfo doesn't explicitly specify then it is AArch32 only. | ||
| 513 | - * If the reginfo is declared to be visible in both states then a second | ||
| 514 | - * reginfo is synthesised for the AArch32 view of the AArch64 register, | ||
| 515 | - * such that the AArch32 view is the lower 32 bits of the AArch64 one. | ||
| 516 | - * Note that we rely on the values of these enums as we iterate through | ||
| 517 | - * the various states in some places. | ||
| 518 | - */ | ||
| 519 | -enum { | ||
| 520 | - ARM_CP_STATE_AA32 = 0, | ||
| 521 | - ARM_CP_STATE_AA64 = 1, | ||
| 522 | - ARM_CP_STATE_BOTH = 2, | ||
| 523 | -}; | ||
| 524 | - | ||
| 525 | -/* ARM CP register secure state flags. These flags identify security state | ||
| 526 | - * attributes for a given CP register entry. | ||
| 527 | - * The existence of both or neither secure and non-secure flags indicates that | ||
| 528 | - * the register has both a secure and non-secure hash entry. A single one of | ||
| 529 | - * these flags causes the register to only be hashed for the specified | ||
| 530 | - * security state. | ||
| 531 | - * Although definitions may have any combination of the S/NS bits, each | ||
| 532 | - * registered entry will only have one to identify whether the entry is secure | ||
| 533 | - * or non-secure. | ||
| 534 | - */ | ||
| 535 | -enum { | ||
| 536 | - ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ | ||
| 537 | - ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ | ||
| 538 | -}; | ||
| 539 | - | ||
| 540 | -/* Return true if cptype is a valid type field. This is used to try to | ||
| 541 | - * catch errors where the sentinel has been accidentally left off the end | ||
| 542 | - * of a list of registers. | ||
| 543 | - */ | ||
| 544 | -static inline bool cptype_valid(int cptype) | ||
| 545 | -{ | ||
| 546 | - return ((cptype & ~ARM_CP_FLAG_MASK) == 0) | ||
| 547 | - || ((cptype & ARM_CP_SPECIAL) && | ||
| 548 | - ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); | ||
| 549 | -} | ||
| 550 | - | ||
| 551 | -/* Access rights: | ||
| 552 | - * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM | ||
| 553 | - * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and | ||
| 554 | - * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 | ||
| 555 | - * (ie any of the privileged modes in Secure state, or Monitor mode). | ||
| 556 | - * If a register is accessible in one privilege level it's always accessible | ||
| 557 | - * in higher privilege levels too. Since "Secure PL1" also follows this rule | ||
| 558 | - * (ie anything visible in PL2 is visible in S-PL1, some things are only | ||
| 559 | - * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the | ||
| 560 | - * terminology a little and call this PL3. | ||
| 561 | - * In AArch64 things are somewhat simpler as the PLx bits line up exactly | ||
| 562 | - * with the ELx exception levels. | ||
| 563 | - * | ||
| 564 | - * If access permissions for a register are more complex than can be | ||
| 565 | - * described with these bits, then use a laxer set of restrictions, and | ||
| 566 | - * do the more restrictive/complex check inside a helper function. | ||
| 567 | - */ | ||
| 568 | -#define PL3_R 0x80 | ||
| 569 | -#define PL3_W 0x40 | ||
| 570 | -#define PL2_R (0x20 | PL3_R) | ||
| 571 | -#define PL2_W (0x10 | PL3_W) | ||
| 572 | -#define PL1_R (0x08 | PL2_R) | ||
| 573 | -#define PL1_W (0x04 | PL2_W) | ||
| 574 | -#define PL0_R (0x02 | PL1_R) | ||
| 575 | -#define PL0_W (0x01 | PL1_W) | ||
| 576 | - | ||
| 577 | -/* | ||
| 578 | - * For user-mode some registers are accessible to EL0 via a kernel | ||
| 579 | - * trap-and-emulate ABI. In this case we define the read permissions | ||
| 580 | - * as actually being PL0_R. However some bits of any given register | ||
| 581 | - * may still be masked. | ||
| 582 | - */ | ||
| 583 | -#ifdef CONFIG_USER_ONLY | ||
| 584 | -#define PL0U_R PL0_R | ||
| 585 | -#else | ||
| 586 | -#define PL0U_R PL1_R | ||
| 587 | -#endif | ||
| 588 | - | ||
| 589 | -#define PL3_RW (PL3_R | PL3_W) | ||
| 590 | -#define PL2_RW (PL2_R | PL2_W) | ||
| 591 | -#define PL1_RW (PL1_R | PL1_W) | ||
| 592 | -#define PL0_RW (PL0_R | PL0_W) | ||
| 593 | - | ||
| 594 | /* Return the highest implemented Exception Level */ | ||
| 595 | static inline int arm_highest_el(CPUARMState *env) | ||
| 596 | { | ||
| 597 | @@ -XXX,XX +XXX,XX @@ static inline int arm_current_el(CPUARMState *env) | ||
| 598 | } | ||
| 599 | } | ||
| 600 | |||
| 601 | -typedef struct ARMCPRegInfo ARMCPRegInfo; | ||
| 602 | - | ||
| 603 | -typedef enum CPAccessResult { | ||
| 604 | - /* Access is permitted */ | ||
| 605 | - CP_ACCESS_OK = 0, | ||
| 606 | - /* Access fails due to a configurable trap or enable which would | ||
| 607 | - * result in a categorized exception syndrome giving information about | ||
| 608 | - * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, | ||
| 609 | - * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or | ||
| 610 | - * PL1 if in EL0, otherwise to the current EL). | ||
| 611 | - */ | ||
| 612 | - CP_ACCESS_TRAP = 1, | ||
| 613 | - /* Access fails and results in an exception syndrome 0x0 ("uncategorized"). | ||
| 614 | - * Note that this is not a catch-all case -- the set of cases which may | ||
| 615 | - * result in this failure is specifically defined by the architecture. | ||
| 616 | - */ | ||
| 617 | - CP_ACCESS_TRAP_UNCATEGORIZED = 2, | ||
| 618 | - /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ | ||
| 619 | - CP_ACCESS_TRAP_EL2 = 3, | ||
| 620 | - CP_ACCESS_TRAP_EL3 = 4, | ||
| 621 | - /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ | ||
| 622 | - CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, | ||
| 623 | - CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, | ||
| 624 | -} CPAccessResult; | ||
| 625 | - | ||
| 626 | -/* Access functions for coprocessor registers. These cannot fail and | ||
| 627 | - * may not raise exceptions. | ||
| 628 | - */ | ||
| 629 | -typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); | ||
| 630 | -typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, | ||
| 631 | - uint64_t value); | ||
| 632 | -/* Access permission check functions for coprocessor registers. */ | ||
| 633 | -typedef CPAccessResult CPAccessFn(CPUARMState *env, | ||
| 634 | - const ARMCPRegInfo *opaque, | ||
| 635 | - bool isread); | ||
| 636 | -/* Hook function for register reset */ | ||
| 637 | -typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); | ||
| 638 | - | ||
| 639 | -#define CP_ANY 0xff | ||
| 640 | - | ||
| 641 | -/* Definition of an ARM coprocessor register */ | ||
| 642 | -struct ARMCPRegInfo { | ||
| 643 | - /* Name of register (useful mainly for debugging, need not be unique) */ | ||
| 644 | - const char *name; | ||
| 645 | - /* Location of register: coprocessor number and (crn,crm,opc1,opc2) | ||
| 646 | - * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a | ||
| 647 | - * 'wildcard' field -- any value of that field in the MRC/MCR insn | ||
| 648 | - * will be decoded to this register. The register read and write | ||
| 649 | - * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 | ||
| 650 | - * used by the program, so it is possible to register a wildcard and | ||
| 651 | - * then behave differently on read/write if necessary. | ||
| 652 | - * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 | ||
| 653 | - * must both be zero. | ||
| 654 | - * For AArch64-visible registers, opc0 is also used. | ||
| 655 | - * Since there are no "coprocessors" in AArch64, cp is purely used as a | ||
| 656 | - * way to distinguish (for KVM's benefit) guest-visible system registers | ||
| 657 | - * from demuxed ones provided to preserve the "no side effects on | ||
| 658 | - * KVM register read/write from QEMU" semantics. cp==0x13 is guest | ||
| 659 | - * visible (to match KVM's encoding); cp==0 will be converted to | ||
| 660 | - * cp==0x13 when the ARMCPRegInfo is registered, for convenience. | ||
| 661 | - */ | ||
| 662 | - uint8_t cp; | ||
| 663 | - uint8_t crn; | ||
| 664 | - uint8_t crm; | ||
| 665 | - uint8_t opc0; | ||
| 666 | - uint8_t opc1; | ||
| 667 | - uint8_t opc2; | ||
| 668 | - /* Execution state in which this register is visible: ARM_CP_STATE_* */ | ||
| 669 | - int state; | ||
| 670 | - /* Register type: ARM_CP_* bits/values */ | ||
| 671 | - int type; | ||
| 672 | - /* Access rights: PL*_[RW] */ | ||
| 673 | - int access; | ||
| 674 | - /* Security state: ARM_CP_SECSTATE_* bits/values */ | ||
| 675 | - int secure; | ||
| 676 | - /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when | ||
| 677 | - * this register was defined: can be used to hand data through to the | ||
| 678 | - * register read/write functions, since they are passed the ARMCPRegInfo*. | ||
| 679 | - */ | ||
| 680 | - void *opaque; | ||
| 681 | - /* Value of this register, if it is ARM_CP_CONST. Otherwise, if | ||
| 682 | - * fieldoffset is non-zero, the reset value of the register. | ||
| 683 | - */ | ||
| 684 | - uint64_t resetvalue; | ||
| 685 | - /* Offset of the field in CPUARMState for this register. | ||
| 686 | - * | ||
| 687 | - * This is not needed if either: | ||
| 688 | - * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs | ||
| 689 | - * 2. both readfn and writefn are specified | ||
| 690 | - */ | ||
| 691 | - ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ | ||
| 692 | - | ||
| 693 | - /* Offsets of the secure and non-secure fields in CPUARMState for the | ||
| 694 | - * register if it is banked. These fields are only used during the static | ||
| 695 | - * registration of a register. During hashing the bank associated | ||
| 696 | - * with a given security state is copied to fieldoffset which is used from | ||
| 697 | - * there on out. | ||
| 698 | - * | ||
| 699 | - * It is expected that register definitions use either fieldoffset or | ||
| 700 | - * bank_fieldoffsets in the definition but not both. It is also expected | ||
| 701 | - * that both bank offsets are set when defining a banked register. This | ||
| 702 | - * use indicates that a register is banked. | ||
| 703 | - */ | ||
| 704 | - ptrdiff_t bank_fieldoffsets[2]; | ||
| 705 | - | ||
| 706 | - /* Function for making any access checks for this register in addition to | ||
| 707 | - * those specified by the 'access' permissions bits. If NULL, no extra | ||
| 708 | - * checks required. The access check is performed at runtime, not at | ||
| 709 | - * translate time. | ||
| 710 | - */ | ||
| 711 | - CPAccessFn *accessfn; | ||
| 712 | - /* Function for handling reads of this register. If NULL, then reads | ||
| 713 | - * will be done by loading from the offset into CPUARMState specified | ||
| 714 | - * by fieldoffset. | ||
| 715 | - */ | ||
| 716 | - CPReadFn *readfn; | ||
| 717 | - /* Function for handling writes of this register. If NULL, then writes | ||
| 718 | - * will be done by writing to the offset into CPUARMState specified | ||
| 719 | - * by fieldoffset. | ||
| 720 | - */ | ||
| 721 | - CPWriteFn *writefn; | ||
| 722 | - /* Function for doing a "raw" read; used when we need to copy | ||
| 723 | - * coprocessor state to the kernel for KVM or out for | ||
| 724 | - * migration. This only needs to be provided if there is also a | ||
| 725 | - * readfn and it has side effects (for instance clear-on-read bits). | ||
| 726 | - */ | ||
| 727 | - CPReadFn *raw_readfn; | ||
| 728 | - /* Function for doing a "raw" write; used when we need to copy KVM | ||
| 729 | - * kernel coprocessor state into userspace, or for inbound | ||
| 730 | - * migration. This only needs to be provided if there is also a | ||
| 731 | - * writefn and it masks out "unwritable" bits or has write-one-to-clear | ||
| 732 | - * or similar behaviour. | ||
| 733 | - */ | ||
| 734 | - CPWriteFn *raw_writefn; | ||
| 735 | - /* Function for resetting the register. If NULL, then reset will be done | ||
| 736 | - * by writing resetvalue to the field specified in fieldoffset. If | ||
| 737 | - * fieldoffset is 0 then no reset will be done. | ||
| 738 | - */ | ||
| 739 | - CPResetFn *resetfn; | ||
| 740 | - | ||
| 741 | - /* | ||
| 742 | - * "Original" writefn and readfn. | ||
| 743 | - * For ARMv8.1-VHE register aliases, we overwrite the read/write | ||
| 744 | - * accessor functions of various EL1/EL0 to perform the runtime | ||
| 745 | - * check for which sysreg should actually be modified, and then | ||
| 746 | - * forwards the operation. Before overwriting the accessors, | ||
| 747 | - * the original function is copied here, so that accesses that | ||
| 748 | - * really do go to the EL1/EL0 version proceed normally. | ||
| 749 | - * (The corresponding EL2 register is linked via opaque.) | ||
| 750 | - */ | ||
| 751 | - CPReadFn *orig_readfn; | ||
| 752 | - CPWriteFn *orig_writefn; | ||
| 753 | -}; | ||
| 754 | - | ||
| 755 | -/* Macros which are lvalues for the field in CPUARMState for the | ||
| 756 | - * ARMCPRegInfo *ri. | ||
| 757 | - */ | ||
| 758 | -#define CPREG_FIELD32(env, ri) \ | ||
| 759 | - (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) | ||
| 760 | -#define CPREG_FIELD64(env, ri) \ | ||
| 761 | - (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) | ||
| 762 | - | ||
| 763 | -#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } | ||
| 764 | - | ||
| 765 | -void define_arm_cp_regs_with_opaque(ARMCPU *cpu, | ||
| 766 | - const ARMCPRegInfo *regs, void *opaque); | ||
| 767 | -void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, | ||
| 768 | - const ARMCPRegInfo *regs, void *opaque); | ||
| 769 | -static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) | ||
| 770 | -{ | ||
| 771 | - define_arm_cp_regs_with_opaque(cpu, regs, 0); | ||
| 772 | -} | ||
| 773 | -static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) | ||
| 774 | -{ | ||
| 775 | - define_one_arm_cp_reg_with_opaque(cpu, regs, 0); | ||
| 776 | -} | ||
| 777 | -const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); | ||
| 778 | - | ||
| 779 | -/* | ||
| 780 | - * Definition of an ARM co-processor register as viewed from | ||
| 781 | - * userspace. This is used for presenting sanitised versions of | ||
| 782 | - * registers to userspace when emulating the Linux AArch64 CPU | ||
| 783 | - * ID/feature ABI (advertised as HWCAP_CPUID). | ||
| 784 | - */ | ||
| 785 | -typedef struct ARMCPRegUserSpaceInfo { | ||
| 786 | - /* Name of register */ | ||
| 787 | - const char *name; | ||
| 788 | - | ||
| 789 | - /* Is the name actually a glob pattern */ | ||
| 790 | - bool is_glob; | ||
| 791 | - | ||
| 792 | - /* Only some bits are exported to user space */ | ||
| 793 | - uint64_t exported_bits; | ||
| 794 | - | ||
| 795 | - /* Fixed bits are applied after the mask */ | ||
| 796 | - uint64_t fixed_bits; | ||
| 797 | -} ARMCPRegUserSpaceInfo; | ||
| 798 | - | ||
| 799 | -#define REGUSERINFO_SENTINEL { .name = NULL } | ||
| 800 | - | ||
| 801 | -void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods); | ||
| 802 | - | ||
| 803 | -/* CPWriteFn that can be used to implement writes-ignored behaviour */ | ||
| 804 | -void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 805 | - uint64_t value); | ||
| 806 | -/* CPReadFn that can be used for read-as-zero behaviour */ | ||
| 807 | -uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); | ||
| 808 | - | ||
| 809 | -/* CPResetFn that does nothing, for use if no reset is required even | ||
| 810 | - * if fieldoffset is non zero. | ||
| 811 | - */ | ||
| 812 | -void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); | ||
| 813 | - | ||
| 814 | -/* Return true if this reginfo struct's field in the cpu state struct | ||
| 815 | - * is 64 bits wide. | ||
| 816 | - */ | ||
| 817 | -static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) | ||
| 818 | -{ | ||
| 819 | - return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); | ||
| 820 | -} | ||
| 821 | - | ||
| 822 | -static inline bool cp_access_ok(int current_el, | ||
| 823 | - const ARMCPRegInfo *ri, int isread) | ||
| 824 | -{ | ||
| 825 | - return (ri->access >> ((current_el * 2) + isread)) & 1; | ||
| 826 | -} | ||
| 827 | - | ||
| 828 | -/* Raw read of a coprocessor register (as needed for migration, etc) */ | ||
| 829 | -uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); | ||
| 830 | - | ||
| 831 | /** | ||
| 832 | * write_list_to_cpustate | ||
| 833 | * @cpu: ARMCPU | ||
| 834 | diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c | ||
| 835 | index XXXXXXX..XXXXXXX 100644 | ||
| 836 | --- a/hw/arm/pxa2xx.c | ||
| 837 | +++ b/hw/arm/pxa2xx.c | ||
| 838 | @@ -XXX,XX +XXX,XX @@ | ||
| 839 | #include "qemu/cutils.h" | ||
| 840 | #include "qemu/log.h" | ||
| 841 | #include "qom/object.h" | ||
| 842 | +#include "target/arm/cpregs.h" | ||
| 843 | |||
| 844 | static struct { | ||
| 845 | hwaddr io_base; | ||
| 846 | diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c | ||
| 847 | index XXXXXXX..XXXXXXX 100644 | ||
| 848 | --- a/hw/arm/pxa2xx_pic.c | ||
| 849 | +++ b/hw/arm/pxa2xx_pic.c | ||
| 850 | @@ -XXX,XX +XXX,XX @@ | ||
| 851 | #include "hw/sysbus.h" | ||
| 852 | #include "migration/vmstate.h" | ||
| 853 | #include "qom/object.h" | ||
| 854 | +#include "target/arm/cpregs.h" | ||
| 855 | |||
| 856 | #define ICIP 0x00 /* Interrupt Controller IRQ Pending register */ | ||
| 857 | #define ICMR 0x04 /* Interrupt Controller Mask register */ | ||
| 858 | diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c | ||
| 859 | index XXXXXXX..XXXXXXX 100644 | ||
| 860 | --- a/hw/intc/arm_gicv3_cpuif.c | ||
| 861 | +++ b/hw/intc/arm_gicv3_cpuif.c | ||
| 862 | @@ -XXX,XX +XXX,XX @@ | ||
| 863 | #include "gicv3_internal.h" | ||
| 864 | #include "hw/irq.h" | ||
| 865 | #include "cpu.h" | ||
| 866 | +#include "target/arm/cpregs.h" | ||
| 867 | |||
| 868 | /* | ||
| 869 | * Special case return value from hppvi_index(); must be larger than | ||
| 870 | diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c | ||
| 871 | index XXXXXXX..XXXXXXX 100644 | ||
| 872 | --- a/hw/intc/arm_gicv3_kvm.c | ||
| 873 | +++ b/hw/intc/arm_gicv3_kvm.c | ||
| 874 | @@ -XXX,XX +XXX,XX @@ | ||
| 875 | #include "vgic_common.h" | ||
| 876 | #include "migration/blocker.h" | ||
| 877 | #include "qom/object.h" | ||
| 878 | +#include "target/arm/cpregs.h" | ||
| 879 | + | ||
| 880 | |||
| 881 | #ifdef DEBUG_GICV3_KVM | ||
| 882 | #define DPRINTF(fmt, ...) \ | ||
| 883 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
| 884 | index XXXXXXX..XXXXXXX 100644 | ||
| 885 | --- a/target/arm/cpu.c | ||
| 886 | +++ b/target/arm/cpu.c | ||
| 887 | @@ -XXX,XX +XXX,XX @@ | ||
| 888 | #include "kvm_arm.h" | ||
| 889 | #include "disas/capstone.h" | ||
| 890 | #include "fpu/softfloat.h" | ||
| 891 | +#include "cpregs.h" | ||
| 892 | |||
| 893 | static void arm_cpu_set_pc(CPUState *cs, vaddr value) | ||
| 894 | { | ||
| 895 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
| 896 | index XXXXXXX..XXXXXXX 100644 | ||
| 897 | --- a/target/arm/cpu64.c | ||
| 898 | +++ b/target/arm/cpu64.c | ||
| 899 | @@ -XXX,XX +XXX,XX @@ | ||
| 900 | #include "hvf_arm.h" | ||
| 901 | #include "qapi/visitor.h" | ||
| 902 | #include "hw/qdev-properties.h" | ||
| 903 | +#include "cpregs.h" | ||
| 904 | |||
| 905 | |||
| 906 | #ifndef CONFIG_USER_ONLY | ||
| 907 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
| 908 | index XXXXXXX..XXXXXXX 100644 | ||
| 909 | --- a/target/arm/cpu_tcg.c | ||
| 910 | +++ b/target/arm/cpu_tcg.c | ||
| 911 | @@ -XXX,XX +XXX,XX @@ | ||
| 912 | #if !defined(CONFIG_USER_ONLY) | ||
| 913 | #include "hw/boards.h" | ||
| 914 | #endif | ||
| 915 | +#include "cpregs.h" | ||
| 916 | |||
| 917 | /* CPU models. These are not needed for the AArch64 linux-user build. */ | ||
| 918 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) | ||
| 919 | diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c | ||
| 920 | index XXXXXXX..XXXXXXX 100644 | ||
| 921 | --- a/target/arm/gdbstub.c | ||
| 922 | +++ b/target/arm/gdbstub.c | ||
| 923 | @@ -XXX,XX +XXX,XX @@ | ||
| 924 | */ | ||
| 925 | #include "qemu/osdep.h" | ||
| 926 | #include "cpu.h" | ||
| 927 | -#include "internals.h" | ||
| 928 | #include "exec/gdbstub.h" | ||
| 929 | +#include "internals.h" | ||
| 930 | +#include "cpregs.h" | ||
| 931 | |||
| 932 | typedef struct RegisterSysregXmlParam { | ||
| 933 | CPUState *cs; | ||
| 934 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
| 935 | index XXXXXXX..XXXXXXX 100644 | ||
| 936 | --- a/target/arm/helper.c | ||
| 937 | +++ b/target/arm/helper.c | ||
| 938 | @@ -XXX,XX +XXX,XX @@ | ||
| 939 | #include "exec/cpu_ldst.h" | ||
| 940 | #include "semihosting/common-semi.h" | ||
| 941 | #endif | ||
| 942 | +#include "cpregs.h" | ||
| 943 | |||
| 944 | #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ | ||
| 945 | #define PMCR_NUM_COUNTERS 4 /* QEMU IMPDEF choice */ | ||
| 946 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c | ||
| 947 | index XXXXXXX..XXXXXXX 100644 | ||
| 948 | --- a/target/arm/op_helper.c | ||
| 949 | +++ b/target/arm/op_helper.c | ||
| 950 | @@ -XXX,XX +XXX,XX @@ | ||
| 951 | #include "internals.h" | ||
| 952 | #include "exec/exec-all.h" | ||
| 953 | #include "exec/cpu_ldst.h" | ||
| 954 | +#include "cpregs.h" | ||
| 955 | |||
| 956 | #define SIGNBIT (uint32_t)0x80000000 | ||
| 957 | #define SIGNBIT64 ((uint64_t)1 << 63) | ||
| 958 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
| 959 | index XXXXXXX..XXXXXXX 100644 | ||
| 960 | --- a/target/arm/translate-a64.c | ||
| 961 | +++ b/target/arm/translate-a64.c | ||
| 962 | @@ -XXX,XX +XXX,XX @@ | ||
| 963 | #include "translate.h" | ||
| 964 | #include "internals.h" | ||
| 965 | #include "qemu/host-utils.h" | ||
| 966 | - | ||
| 967 | #include "semihosting/semihost.h" | ||
| 968 | #include "exec/gen-icount.h" | ||
| 969 | - | ||
| 970 | #include "exec/helper-proto.h" | ||
| 971 | #include "exec/helper-gen.h" | ||
| 972 | #include "exec/log.h" | ||
| 973 | - | ||
| 974 | +#include "cpregs.h" | ||
| 975 | #include "translate-a64.h" | ||
| 976 | #include "qemu/atomic128.h" | ||
| 977 | |||
| 23 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 978 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
| 24 | index XXXXXXX..XXXXXXX 100644 | 979 | index XXXXXXX..XXXXXXX 100644 |
| 25 | --- a/target/arm/translate.c | 980 | --- a/target/arm/translate.c |
| 26 | +++ b/target/arm/translate.c | 981 | +++ b/target/arm/translate.c |
| 27 | @@ -XXX,XX +XXX,XX @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s) | 982 | @@ -XXX,XX +XXX,XX @@ |
| 28 | { | 983 | #include "qemu/bitops.h" |
| 29 | /* Return true if the insn at dc->pc might cross a page boundary. | 984 | #include "arm_ldst.h" |
| 30 | * (False positives are OK, false negatives are not.) | 985 | #include "semihosting/semihost.h" |
| 31 | + * We know this is a Thumb insn, and our caller ensures we are | 986 | - |
| 32 | + * only called if dc->pc is less than 4 bytes from the page | 987 | #include "exec/helper-proto.h" |
| 33 | + * boundary, so we cross the page if the first 16 bits indicate | 988 | #include "exec/helper-gen.h" |
| 34 | + * that this is a 32 bit insn. | 989 | - |
| 35 | */ | 990 | #include "exec/log.h" |
| 36 | - uint16_t insn; | 991 | +#include "cpregs.h" |
| 37 | + uint16_t insn = arm_lduw_code(env, s->pc, s->sctlr_b); | 992 | |
| 38 | 993 | ||
| 39 | - if ((s->pc & 3) == 0) { | 994 | #define ENABLE_ARCH_4T arm_dc_feature(s, ARM_FEATURE_V4T) |
| 40 | - /* At a 4-aligned address we can't be crossing a page */ | ||
| 41 | - return false; | ||
| 42 | - } | ||
| 43 | - | ||
| 44 | - /* This must be a Thumb insn */ | ||
| 45 | - insn = arm_lduw_code(env, s->pc, s->sctlr_b); | ||
| 46 | - | ||
| 47 | - if ((insn >> 11) >= 0x1d) { | ||
| 48 | - /* Top five bits 0b11101 / 0b11110 / 0b11111 : this is the | ||
| 49 | - * First half of a 32-bit Thumb insn. Thumb-1 cores might | ||
| 50 | - * end up actually treating this as two 16-bit insns (see the | ||
| 51 | - * code at the start of disas_thumb2_insn()) but we don't bother | ||
| 52 | - * to check for that as it is unlikely, and false positives here | ||
| 53 | - * are harmless. | ||
| 54 | - */ | ||
| 55 | - return true; | ||
| 56 | - } | ||
| 57 | - /* Definitely a 16-bit insn, can't be crossing a page. */ | ||
| 58 | - return false; | ||
| 59 | + return !thumb_insn_is_16bit(s, insn); | ||
| 60 | } | ||
| 61 | |||
| 62 | static int arm_tr_init_disas_context(DisasContextBase *dcbase, | ||
| 63 | -- | 995 | -- |
| 64 | 2.7.4 | 996 | 2.25.1 |
| 65 | 997 | ||
| 66 | 998 | diff view generated by jsdifflib |
| 1 | Add the M profile secure MMU index values to the switch in | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | get_a32_user_mem_index() so that LDRT/STRT work correctly | ||
| 3 | rather than asserting at translate time. | ||
| 4 | 2 | ||
| 3 | Rearrange the values of the enumerators of CPAccessResult | ||
| 4 | so that we may directly extract the target el. For the two | ||
| 5 | special cases in access_check_cp_reg, use CPAccessResult. | ||
| 6 | |||
| 7 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
| 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 10 | Message-id: 20220501055028.646596-3-richard.henderson@linaro.org | ||
| 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Message-id: 1507556919-24992-2-git-send-email-peter.maydell@linaro.org | ||
| 8 | --- | 12 | --- |
| 9 | target/arm/translate.c | 4 ++++ | 13 | target/arm/cpregs.h | 26 ++++++++++++-------- |
| 10 | 1 file changed, 4 insertions(+) | 14 | target/arm/op_helper.c | 56 +++++++++++++++++++++--------------------- |
| 15 | 2 files changed, 44 insertions(+), 38 deletions(-) | ||
| 11 | 16 | ||
| 12 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 17 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h |
| 13 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
| 14 | --- a/target/arm/translate.c | 19 | --- a/target/arm/cpregs.h |
| 15 | +++ b/target/arm/translate.c | 20 | +++ b/target/arm/cpregs.h |
| 16 | @@ -XXX,XX +XXX,XX @@ static inline int get_a32_user_mem_index(DisasContext *s) | 21 | @@ -XXX,XX +XXX,XX @@ static inline bool cptype_valid(int cptype) |
| 17 | case ARMMMUIdx_MPriv: | 22 | typedef enum CPAccessResult { |
| 18 | case ARMMMUIdx_MNegPri: | 23 | /* Access is permitted */ |
| 19 | return arm_to_core_mmu_idx(ARMMMUIdx_MUser); | 24 | CP_ACCESS_OK = 0, |
| 20 | + case ARMMMUIdx_MSUser: | 25 | + |
| 21 | + case ARMMMUIdx_MSPriv: | 26 | + /* |
| 22 | + case ARMMMUIdx_MSNegPri: | 27 | + * Combined with one of the following, the low 2 bits indicate the |
| 23 | + return arm_to_core_mmu_idx(ARMMMUIdx_MSUser); | 28 | + * target exception level. If 0, the exception is taken to the usual |
| 24 | case ARMMMUIdx_S2NS: | 29 | + * target EL (EL1 or PL1 if in EL0, otherwise to the current EL). |
| 30 | + */ | ||
| 31 | + CP_ACCESS_EL_MASK = 3, | ||
| 32 | + | ||
| 33 | /* | ||
| 34 | * Access fails due to a configurable trap or enable which would | ||
| 35 | * result in a categorized exception syndrome giving information about | ||
| 36 | * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, | ||
| 37 | - * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or | ||
| 38 | - * PL1 if in EL0, otherwise to the current EL). | ||
| 39 | + * 0xc or 0x18). | ||
| 40 | */ | ||
| 41 | - CP_ACCESS_TRAP = 1, | ||
| 42 | + CP_ACCESS_TRAP = (1 << 2), | ||
| 43 | + CP_ACCESS_TRAP_EL2 = CP_ACCESS_TRAP | 2, | ||
| 44 | + CP_ACCESS_TRAP_EL3 = CP_ACCESS_TRAP | 3, | ||
| 45 | + | ||
| 46 | /* | ||
| 47 | * Access fails and results in an exception syndrome 0x0 ("uncategorized"). | ||
| 48 | * Note that this is not a catch-all case -- the set of cases which may | ||
| 49 | * result in this failure is specifically defined by the architecture. | ||
| 50 | */ | ||
| 51 | - CP_ACCESS_TRAP_UNCATEGORIZED = 2, | ||
| 52 | - /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ | ||
| 53 | - CP_ACCESS_TRAP_EL2 = 3, | ||
| 54 | - CP_ACCESS_TRAP_EL3 = 4, | ||
| 55 | - /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ | ||
| 56 | - CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, | ||
| 57 | - CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, | ||
| 58 | + CP_ACCESS_TRAP_UNCATEGORIZED = (2 << 2), | ||
| 59 | + CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = CP_ACCESS_TRAP_UNCATEGORIZED | 2, | ||
| 60 | + CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = CP_ACCESS_TRAP_UNCATEGORIZED | 3, | ||
| 61 | } CPAccessResult; | ||
| 62 | |||
| 63 | typedef struct ARMCPRegInfo ARMCPRegInfo; | ||
| 64 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c | ||
| 65 | index XXXXXXX..XXXXXXX 100644 | ||
| 66 | --- a/target/arm/op_helper.c | ||
| 67 | +++ b/target/arm/op_helper.c | ||
| 68 | @@ -XXX,XX +XXX,XX @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome, | ||
| 69 | uint32_t isread) | ||
| 70 | { | ||
| 71 | const ARMCPRegInfo *ri = rip; | ||
| 72 | + CPAccessResult res = CP_ACCESS_OK; | ||
| 73 | int target_el; | ||
| 74 | |||
| 75 | if (arm_feature(env, ARM_FEATURE_XSCALE) && ri->cp < 14 | ||
| 76 | && extract32(env->cp15.c15_cpar, ri->cp, 1) == 0) { | ||
| 77 | - raise_exception(env, EXCP_UDEF, syndrome, exception_target_el(env)); | ||
| 78 | + res = CP_ACCESS_TRAP; | ||
| 79 | + goto fail; | ||
| 80 | } | ||
| 81 | |||
| 82 | /* | ||
| 83 | @@ -XXX,XX +XXX,XX @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome, | ||
| 84 | mask &= ~((1 << 4) | (1 << 14)); | ||
| 85 | |||
| 86 | if (env->cp15.hstr_el2 & mask) { | ||
| 87 | - target_el = 2; | ||
| 88 | - goto exept; | ||
| 89 | + res = CP_ACCESS_TRAP_EL2; | ||
| 90 | + goto fail; | ||
| 91 | } | ||
| 92 | } | ||
| 93 | |||
| 94 | - if (!ri->accessfn) { | ||
| 95 | + if (ri->accessfn) { | ||
| 96 | + res = ri->accessfn(env, ri, isread); | ||
| 97 | + } | ||
| 98 | + if (likely(res == CP_ACCESS_OK)) { | ||
| 99 | return; | ||
| 100 | } | ||
| 101 | |||
| 102 | - switch (ri->accessfn(env, ri, isread)) { | ||
| 103 | - case CP_ACCESS_OK: | ||
| 104 | - return; | ||
| 105 | + fail: | ||
| 106 | + switch (res & ~CP_ACCESS_EL_MASK) { | ||
| 107 | case CP_ACCESS_TRAP: | ||
| 108 | - target_el = exception_target_el(env); | ||
| 109 | - break; | ||
| 110 | - case CP_ACCESS_TRAP_EL2: | ||
| 111 | - /* Requesting a trap to EL2 when we're in EL3 is | ||
| 112 | - * a bug in the access function. | ||
| 113 | - */ | ||
| 114 | - assert(arm_current_el(env) != 3); | ||
| 115 | - target_el = 2; | ||
| 116 | - break; | ||
| 117 | - case CP_ACCESS_TRAP_EL3: | ||
| 118 | - target_el = 3; | ||
| 119 | break; | ||
| 120 | case CP_ACCESS_TRAP_UNCATEGORIZED: | ||
| 121 | - target_el = exception_target_el(env); | ||
| 122 | - syndrome = syn_uncategorized(); | ||
| 123 | - break; | ||
| 124 | - case CP_ACCESS_TRAP_UNCATEGORIZED_EL2: | ||
| 125 | - target_el = 2; | ||
| 126 | - syndrome = syn_uncategorized(); | ||
| 127 | - break; | ||
| 128 | - case CP_ACCESS_TRAP_UNCATEGORIZED_EL3: | ||
| 129 | - target_el = 3; | ||
| 130 | syndrome = syn_uncategorized(); | ||
| 131 | break; | ||
| 25 | default: | 132 | default: |
| 26 | g_assert_not_reached(); | 133 | g_assert_not_reached(); |
| 134 | } | ||
| 135 | |||
| 136 | -exept: | ||
| 137 | + target_el = res & CP_ACCESS_EL_MASK; | ||
| 138 | + switch (target_el) { | ||
| 139 | + case 0: | ||
| 140 | + target_el = exception_target_el(env); | ||
| 141 | + break; | ||
| 142 | + case 2: | ||
| 143 | + assert(arm_current_el(env) != 3); | ||
| 144 | + assert(arm_is_el2_enabled(env)); | ||
| 145 | + break; | ||
| 146 | + case 3: | ||
| 147 | + assert(arm_feature(env, ARM_FEATURE_EL3)); | ||
| 148 | + break; | ||
| 149 | + default: | ||
| 150 | + /* No "direct" traps to EL1 */ | ||
| 151 | + g_assert_not_reached(); | ||
| 152 | + } | ||
| 153 | + | ||
| 154 | raise_exception(env, EXCP_UDEF, syndrome, target_el); | ||
| 155 | } | ||
| 156 | |||
| 27 | -- | 157 | -- |
| 28 | 2.7.4 | 158 | 2.25.1 |
| 29 | 159 | ||
| 30 | 160 | diff view generated by jsdifflib |
| 1 | Implement the SG instruction, which we emulate 'by hand' in the | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | exception handling code path. | ||
| 3 | 2 | ||
| 3 | Remove a possible source of error by removing REGINFO_SENTINEL | ||
| 4 | and using ARRAY_SIZE (convinently hidden inside a macro) to | ||
| 5 | find the end of the set of regs being registered or modified. | ||
| 6 | |||
| 7 | The space saved by not having the extra array element reduces | ||
| 8 | the executable's .data.rel.ro section by about 9k. | ||
| 9 | |||
| 10 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
| 11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 12 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 13 | Message-id: 20220501055028.646596-4-richard.henderson@linaro.org | ||
| 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Message-id: 1507556919-24992-3-git-send-email-peter.maydell@linaro.org | ||
| 7 | --- | 15 | --- |
| 8 | target/arm/helper.c | 132 ++++++++++++++++++++++++++++++++++++++++++++++++++-- | 16 | target/arm/cpregs.h | 53 +++++++++--------- |
| 9 | 1 file changed, 127 insertions(+), 5 deletions(-) | 17 | hw/arm/pxa2xx.c | 1 - |
| 18 | hw/arm/pxa2xx_pic.c | 1 - | ||
| 19 | hw/intc/arm_gicv3_cpuif.c | 5 -- | ||
| 20 | hw/intc/arm_gicv3_kvm.c | 1 - | ||
| 21 | target/arm/cpu64.c | 1 - | ||
| 22 | target/arm/cpu_tcg.c | 4 -- | ||
| 23 | target/arm/helper.c | 111 ++++++++------------------------------ | ||
| 24 | 8 files changed, 48 insertions(+), 129 deletions(-) | ||
| 10 | 25 | ||
| 26 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h | ||
| 27 | index XXXXXXX..XXXXXXX 100644 | ||
| 28 | --- a/target/arm/cpregs.h | ||
| 29 | +++ b/target/arm/cpregs.h | ||
| 30 | @@ -XXX,XX +XXX,XX @@ | ||
| 31 | #define ARM_CP_NO_GDB 0x4000 | ||
| 32 | #define ARM_CP_RAISES_EXC 0x8000 | ||
| 33 | #define ARM_CP_NEWEL 0x10000 | ||
| 34 | -/* Used only as a terminator for ARMCPRegInfo lists */ | ||
| 35 | -#define ARM_CP_SENTINEL 0xfffff | ||
| 36 | /* Mask of only the flag bits in a type field */ | ||
| 37 | #define ARM_CP_FLAG_MASK 0x1f0ff | ||
| 38 | |||
| 39 | @@ -XXX,XX +XXX,XX @@ enum { | ||
| 40 | ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ | ||
| 41 | }; | ||
| 42 | |||
| 43 | -/* | ||
| 44 | - * Return true if cptype is a valid type field. This is used to try to | ||
| 45 | - * catch errors where the sentinel has been accidentally left off the end | ||
| 46 | - * of a list of registers. | ||
| 47 | - */ | ||
| 48 | -static inline bool cptype_valid(int cptype) | ||
| 49 | -{ | ||
| 50 | - return ((cptype & ~ARM_CP_FLAG_MASK) == 0) | ||
| 51 | - || ((cptype & ARM_CP_SPECIAL) && | ||
| 52 | - ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); | ||
| 53 | -} | ||
| 54 | - | ||
| 55 | /* | ||
| 56 | * Access rights: | ||
| 57 | * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM | ||
| 58 | @@ -XXX,XX +XXX,XX @@ struct ARMCPRegInfo { | ||
| 59 | #define CPREG_FIELD64(env, ri) \ | ||
| 60 | (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) | ||
| 61 | |||
| 62 | -#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } | ||
| 63 | +void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, const ARMCPRegInfo *reg, | ||
| 64 | + void *opaque); | ||
| 65 | |||
| 66 | -void define_arm_cp_regs_with_opaque(ARMCPU *cpu, | ||
| 67 | - const ARMCPRegInfo *regs, void *opaque); | ||
| 68 | -void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, | ||
| 69 | - const ARMCPRegInfo *regs, void *opaque); | ||
| 70 | -static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) | ||
| 71 | -{ | ||
| 72 | - define_arm_cp_regs_with_opaque(cpu, regs, 0); | ||
| 73 | -} | ||
| 74 | static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) | ||
| 75 | { | ||
| 76 | - define_one_arm_cp_reg_with_opaque(cpu, regs, 0); | ||
| 77 | + define_one_arm_cp_reg_with_opaque(cpu, regs, NULL); | ||
| 78 | } | ||
| 79 | + | ||
| 80 | +void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *regs, | ||
| 81 | + void *opaque, size_t len); | ||
| 82 | + | ||
| 83 | +#define define_arm_cp_regs_with_opaque(CPU, REGS, OPAQUE) \ | ||
| 84 | + do { \ | ||
| 85 | + QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) == 0); \ | ||
| 86 | + define_arm_cp_regs_with_opaque_len(CPU, REGS, OPAQUE, \ | ||
| 87 | + ARRAY_SIZE(REGS)); \ | ||
| 88 | + } while (0) | ||
| 89 | + | ||
| 90 | +#define define_arm_cp_regs(CPU, REGS) \ | ||
| 91 | + define_arm_cp_regs_with_opaque(CPU, REGS, NULL) | ||
| 92 | + | ||
| 93 | const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); | ||
| 94 | |||
| 95 | /* | ||
| 96 | @@ -XXX,XX +XXX,XX @@ typedef struct ARMCPRegUserSpaceInfo { | ||
| 97 | uint64_t fixed_bits; | ||
| 98 | } ARMCPRegUserSpaceInfo; | ||
| 99 | |||
| 100 | -#define REGUSERINFO_SENTINEL { .name = NULL } | ||
| 101 | +void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len, | ||
| 102 | + const ARMCPRegUserSpaceInfo *mods, | ||
| 103 | + size_t mods_len); | ||
| 104 | |||
| 105 | -void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods); | ||
| 106 | +#define modify_arm_cp_regs(REGS, MODS) \ | ||
| 107 | + do { \ | ||
| 108 | + QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) == 0); \ | ||
| 109 | + QEMU_BUILD_BUG_ON(ARRAY_SIZE(MODS) == 0); \ | ||
| 110 | + modify_arm_cp_regs_with_len(REGS, ARRAY_SIZE(REGS), \ | ||
| 111 | + MODS, ARRAY_SIZE(MODS)); \ | ||
| 112 | + } while (0) | ||
| 113 | |||
| 114 | /* CPWriteFn that can be used to implement writes-ignored behaviour */ | ||
| 115 | void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 116 | diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c | ||
| 117 | index XXXXXXX..XXXXXXX 100644 | ||
| 118 | --- a/hw/arm/pxa2xx.c | ||
| 119 | +++ b/hw/arm/pxa2xx.c | ||
| 120 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pxa_cp_reginfo[] = { | ||
| 121 | { .name = "PWRMODE", .cp = 14, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 0, | ||
| 122 | .access = PL1_RW, .type = ARM_CP_IO, | ||
| 123 | .readfn = arm_cp_read_zero, .writefn = pxa2xx_pwrmode_write }, | ||
| 124 | - REGINFO_SENTINEL | ||
| 125 | }; | ||
| 126 | |||
| 127 | static void pxa2xx_setup_cp14(PXA2xxState *s) | ||
| 128 | diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c | ||
| 129 | index XXXXXXX..XXXXXXX 100644 | ||
| 130 | --- a/hw/arm/pxa2xx_pic.c | ||
| 131 | +++ b/hw/arm/pxa2xx_pic.c | ||
| 132 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pxa_pic_cp_reginfo[] = { | ||
| 133 | REGINFO_FOR_PIC_CP("ICLR2", 8), | ||
| 134 | REGINFO_FOR_PIC_CP("ICFP2", 9), | ||
| 135 | REGINFO_FOR_PIC_CP("ICPR2", 0xa), | ||
| 136 | - REGINFO_SENTINEL | ||
| 137 | }; | ||
| 138 | |||
| 139 | static const MemoryRegionOps pxa2xx_pic_ops = { | ||
| 140 | diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c | ||
| 141 | index XXXXXXX..XXXXXXX 100644 | ||
| 142 | --- a/hw/intc/arm_gicv3_cpuif.c | ||
| 143 | +++ b/hw/intc/arm_gicv3_cpuif.c | ||
| 144 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = { | ||
| 145 | .readfn = icc_igrpen1_el3_read, | ||
| 146 | .writefn = icc_igrpen1_el3_write, | ||
| 147 | }, | ||
| 148 | - REGINFO_SENTINEL | ||
| 149 | }; | ||
| 150 | |||
| 151 | static uint64_t ich_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
| 152 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_hcr_reginfo[] = { | ||
| 153 | .readfn = ich_vmcr_read, | ||
| 154 | .writefn = ich_vmcr_write, | ||
| 155 | }, | ||
| 156 | - REGINFO_SENTINEL | ||
| 157 | }; | ||
| 158 | |||
| 159 | static const ARMCPRegInfo gicv3_cpuif_ich_apxr1_reginfo[] = { | ||
| 160 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr1_reginfo[] = { | ||
| 161 | .readfn = ich_ap_read, | ||
| 162 | .writefn = ich_ap_write, | ||
| 163 | }, | ||
| 164 | - REGINFO_SENTINEL | ||
| 165 | }; | ||
| 166 | |||
| 167 | static const ARMCPRegInfo gicv3_cpuif_ich_apxr23_reginfo[] = { | ||
| 168 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr23_reginfo[] = { | ||
| 169 | .readfn = ich_ap_read, | ||
| 170 | .writefn = ich_ap_write, | ||
| 171 | }, | ||
| 172 | - REGINFO_SENTINEL | ||
| 173 | }; | ||
| 174 | |||
| 175 | static void gicv3_cpuif_el_change_hook(ARMCPU *cpu, void *opaque) | ||
| 176 | @@ -XXX,XX +XXX,XX @@ void gicv3_init_cpuif(GICv3State *s) | ||
| 177 | .readfn = ich_lr_read, | ||
| 178 | .writefn = ich_lr_write, | ||
| 179 | }, | ||
| 180 | - REGINFO_SENTINEL | ||
| 181 | }; | ||
| 182 | define_arm_cp_regs(cpu, lr_regset); | ||
| 183 | } | ||
| 184 | diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c | ||
| 185 | index XXXXXXX..XXXXXXX 100644 | ||
| 186 | --- a/hw/intc/arm_gicv3_kvm.c | ||
| 187 | +++ b/hw/intc/arm_gicv3_kvm.c | ||
| 188 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = { | ||
| 189 | */ | ||
| 190 | .resetfn = arm_gicv3_icc_reset, | ||
| 191 | }, | ||
| 192 | - REGINFO_SENTINEL | ||
| 193 | }; | ||
| 194 | |||
| 195 | /** | ||
| 196 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
| 197 | index XXXXXXX..XXXXXXX 100644 | ||
| 198 | --- a/target/arm/cpu64.c | ||
| 199 | +++ b/target/arm/cpu64.c | ||
| 200 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = { | ||
| 201 | { .name = "L2MERRSR", | ||
| 202 | .cp = 15, .opc1 = 3, .crm = 15, | ||
| 203 | .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
| 204 | - REGINFO_SENTINEL | ||
| 205 | }; | ||
| 206 | |||
| 207 | static void aarch64_a57_initfn(Object *obj) | ||
| 208 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
| 209 | index XXXXXXX..XXXXXXX 100644 | ||
| 210 | --- a/target/arm/cpu_tcg.c | ||
| 211 | +++ b/target/arm/cpu_tcg.c | ||
| 212 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortexa8_cp_reginfo[] = { | ||
| 213 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 214 | { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, | ||
| 215 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 216 | - REGINFO_SENTINEL | ||
| 217 | }; | ||
| 218 | |||
| 219 | static void cortex_a8_initfn(Object *obj) | ||
| 220 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortexa9_cp_reginfo[] = { | ||
| 221 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | ||
| 222 | { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, | ||
| 223 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | ||
| 224 | - REGINFO_SENTINEL | ||
| 225 | }; | ||
| 226 | |||
| 227 | static void cortex_a9_initfn(Object *obj) | ||
| 228 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortexa15_cp_reginfo[] = { | ||
| 229 | #endif | ||
| 230 | { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, | ||
| 231 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 232 | - REGINFO_SENTINEL | ||
| 233 | }; | ||
| 234 | |||
| 235 | static void cortex_a7_initfn(Object *obj) | ||
| 236 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortexr5_cp_reginfo[] = { | ||
| 237 | .access = PL1_RW, .type = ARM_CP_CONST }, | ||
| 238 | { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, | ||
| 239 | .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, | ||
| 240 | - REGINFO_SENTINEL | ||
| 241 | }; | ||
| 242 | |||
| 243 | static void cortex_r5_initfn(Object *obj) | ||
| 11 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 244 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
| 12 | index XXXXXXX..XXXXXXX 100644 | 245 | index XXXXXXX..XXXXXXX 100644 |
| 13 | --- a/target/arm/helper.c | 246 | --- a/target/arm/helper.c |
| 14 | +++ b/target/arm/helper.c | 247 | +++ b/target/arm/helper.c |
| 15 | @@ -XXX,XX +XXX,XX @@ typedef struct V8M_SAttributes { | 248 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cp_reginfo[] = { |
| 16 | bool irvalid; | 249 | .secure = ARM_CP_SECSTATE_S, |
| 17 | } V8M_SAttributes; | 250 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s), |
| 18 | 251 | .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, | |
| 19 | +static void v8m_security_lookup(CPUARMState *env, uint32_t address, | 252 | - REGINFO_SENTINEL |
| 20 | + MMUAccessType access_type, ARMMMUIdx mmu_idx, | 253 | }; |
| 21 | + V8M_SAttributes *sattrs); | 254 | |
| 255 | static const ARMCPRegInfo not_v8_cp_reginfo[] = { | ||
| 256 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v8_cp_reginfo[] = { | ||
| 257 | { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, | ||
| 258 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, | ||
| 259 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE }, | ||
| 260 | - REGINFO_SENTINEL | ||
| 261 | }; | ||
| 262 | |||
| 263 | static const ARMCPRegInfo not_v6_cp_reginfo[] = { | ||
| 264 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v6_cp_reginfo[] = { | ||
| 265 | */ | ||
| 266 | { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2, | ||
| 267 | .access = PL1_W, .type = ARM_CP_WFI }, | ||
| 268 | - REGINFO_SENTINEL | ||
| 269 | }; | ||
| 270 | |||
| 271 | static const ARMCPRegInfo not_v7_cp_reginfo[] = { | ||
| 272 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v7_cp_reginfo[] = { | ||
| 273 | .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP }, | ||
| 274 | { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2, | ||
| 275 | .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP }, | ||
| 276 | - REGINFO_SENTINEL | ||
| 277 | }; | ||
| 278 | |||
| 279 | static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 280 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = { | ||
| 281 | .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access, | ||
| 282 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1), | ||
| 283 | .resetfn = cpacr_reset, .writefn = cpacr_write, .readfn = cpacr_read }, | ||
| 284 | - REGINFO_SENTINEL | ||
| 285 | }; | ||
| 286 | |||
| 287 | typedef struct pm_event { | ||
| 288 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = { | ||
| 289 | { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, | ||
| 290 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, | ||
| 291 | .writefn = tlbimvaa_write }, | ||
| 292 | - REGINFO_SENTINEL | ||
| 293 | }; | ||
| 294 | |||
| 295 | static const ARMCPRegInfo v7mp_cp_reginfo[] = { | ||
| 296 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7mp_cp_reginfo[] = { | ||
| 297 | { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, | ||
| 298 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, | ||
| 299 | .writefn = tlbimvaa_is_write }, | ||
| 300 | - REGINFO_SENTINEL | ||
| 301 | }; | ||
| 302 | |||
| 303 | static const ARMCPRegInfo pmovsset_cp_reginfo[] = { | ||
| 304 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmovsset_cp_reginfo[] = { | ||
| 305 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), | ||
| 306 | .writefn = pmovsset_write, | ||
| 307 | .raw_writefn = raw_write }, | ||
| 308 | - REGINFO_SENTINEL | ||
| 309 | }; | ||
| 310 | |||
| 311 | static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 312 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo t2ee_cp_reginfo[] = { | ||
| 313 | { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0, | ||
| 314 | .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr), | ||
| 315 | .accessfn = teehbr_access, .resetvalue = 0 }, | ||
| 316 | - REGINFO_SENTINEL | ||
| 317 | }; | ||
| 318 | |||
| 319 | static const ARMCPRegInfo v6k_cp_reginfo[] = { | ||
| 320 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6k_cp_reginfo[] = { | ||
| 321 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s), | ||
| 322 | offsetoflow32(CPUARMState, cp15.tpidrprw_ns) }, | ||
| 323 | .resetvalue = 0 }, | ||
| 324 | - REGINFO_SENTINEL | ||
| 325 | }; | ||
| 326 | |||
| 327 | #ifndef CONFIG_USER_ONLY | ||
| 328 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = { | ||
| 329 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), | ||
| 330 | .writefn = gt_sec_cval_write, .raw_writefn = raw_write, | ||
| 331 | }, | ||
| 332 | - REGINFO_SENTINEL | ||
| 333 | }; | ||
| 334 | |||
| 335 | static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 336 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = { | ||
| 337 | .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, | ||
| 338 | .readfn = gt_virt_cnt_read, | ||
| 339 | }, | ||
| 340 | - REGINFO_SENTINEL | ||
| 341 | }; | ||
| 342 | |||
| 343 | #endif | ||
| 344 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vapa_cp_reginfo[] = { | ||
| 345 | .access = PL1_W, .accessfn = ats_access, | ||
| 346 | .writefn = ats_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, | ||
| 347 | #endif | ||
| 348 | - REGINFO_SENTINEL | ||
| 349 | }; | ||
| 350 | |||
| 351 | /* Return basic MPU access permission bits. */ | ||
| 352 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmsav7_cp_reginfo[] = { | ||
| 353 | .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]), | ||
| 354 | .writefn = pmsav7_rgnr_write, | ||
| 355 | .resetfn = arm_cp_reset_ignore }, | ||
| 356 | - REGINFO_SENTINEL | ||
| 357 | }; | ||
| 358 | |||
| 359 | static const ARMCPRegInfo pmsav5_cp_reginfo[] = { | ||
| 360 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmsav5_cp_reginfo[] = { | ||
| 361 | { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0, | ||
| 362 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | ||
| 363 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) }, | ||
| 364 | - REGINFO_SENTINEL | ||
| 365 | }; | ||
| 366 | |||
| 367 | static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 368 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = { | ||
| 369 | .access = PL1_RW, .accessfn = access_tvm_trvm, | ||
| 370 | .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]), | ||
| 371 | .resetvalue = 0, }, | ||
| 372 | - REGINFO_SENTINEL | ||
| 373 | }; | ||
| 374 | |||
| 375 | static const ARMCPRegInfo vmsa_cp_reginfo[] = { | ||
| 376 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { | ||
| 377 | /* No offsetoflow32 -- pass the entire TCR to writefn/raw_writefn. */ | ||
| 378 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.tcr_el[3]), | ||
| 379 | offsetof(CPUARMState, cp15.tcr_el[1])} }, | ||
| 380 | - REGINFO_SENTINEL | ||
| 381 | }; | ||
| 382 | |||
| 383 | /* Note that unlike TTBCR, writing to TTBCR2 does not require flushing | ||
| 384 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo omap_cp_reginfo[] = { | ||
| 385 | { .name = "C9", .cp = 15, .crn = 9, | ||
| 386 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, | ||
| 387 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 }, | ||
| 388 | - REGINFO_SENTINEL | ||
| 389 | }; | ||
| 390 | |||
| 391 | static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 392 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo xscale_cp_reginfo[] = { | ||
| 393 | { .name = "XSCALE_UNLOCK_DCACHE", | ||
| 394 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1, | ||
| 395 | .access = PL1_W, .type = ARM_CP_NOP }, | ||
| 396 | - REGINFO_SENTINEL | ||
| 397 | }; | ||
| 398 | |||
| 399 | static const ARMCPRegInfo dummy_c15_cp_reginfo[] = { | ||
| 400 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dummy_c15_cp_reginfo[] = { | ||
| 401 | .access = PL1_RW, | ||
| 402 | .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE, | ||
| 403 | .resetvalue = 0 }, | ||
| 404 | - REGINFO_SENTINEL | ||
| 405 | }; | ||
| 406 | |||
| 407 | static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = { | ||
| 408 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = { | ||
| 409 | { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6, | ||
| 410 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, | ||
| 411 | .resetvalue = 0 }, | ||
| 412 | - REGINFO_SENTINEL | ||
| 413 | }; | ||
| 414 | |||
| 415 | static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = { | ||
| 416 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = { | ||
| 417 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | ||
| 418 | { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0, | ||
| 419 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | ||
| 420 | - REGINFO_SENTINEL | ||
| 421 | }; | ||
| 422 | |||
| 423 | static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = { | ||
| 424 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = { | ||
| 425 | { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3, | ||
| 426 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, | ||
| 427 | .resetvalue = (1 << 30) }, | ||
| 428 | - REGINFO_SENTINEL | ||
| 429 | }; | ||
| 430 | |||
| 431 | static const ARMCPRegInfo strongarm_cp_reginfo[] = { | ||
| 432 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo strongarm_cp_reginfo[] = { | ||
| 433 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | ||
| 434 | .access = PL1_RW, .resetvalue = 0, | ||
| 435 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW }, | ||
| 436 | - REGINFO_SENTINEL | ||
| 437 | }; | ||
| 438 | |||
| 439 | static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
| 440 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lpae_cp_reginfo[] = { | ||
| 441 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), | ||
| 442 | offsetof(CPUARMState, cp15.ttbr1_ns) }, | ||
| 443 | .writefn = vmsa_ttbr_write, }, | ||
| 444 | - REGINFO_SENTINEL | ||
| 445 | }; | ||
| 446 | |||
| 447 | static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
| 448 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { | ||
| 449 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, | ||
| 450 | .writefn = sdcr_write, | ||
| 451 | .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) }, | ||
| 452 | - REGINFO_SENTINEL | ||
| 453 | }; | ||
| 454 | |||
| 455 | /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */ | ||
| 456 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { | ||
| 457 | .type = ARM_CP_CONST, | ||
| 458 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2, | ||
| 459 | .access = PL2_RW, .resetvalue = 0 }, | ||
| 460 | - REGINFO_SENTINEL | ||
| 461 | }; | ||
| 462 | |||
| 463 | /* Ditto, but for registers which exist in ARMv8 but not v7 */ | ||
| 464 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = { | ||
| 465 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4, | ||
| 466 | .access = PL2_RW, | ||
| 467 | .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 468 | - REGINFO_SENTINEL | ||
| 469 | }; | ||
| 470 | |||
| 471 | static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) | ||
| 472 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = { | ||
| 473 | .cp = 15, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, | ||
| 474 | .access = PL2_RW, | ||
| 475 | .fieldoffset = offsetof(CPUARMState, cp15.hstr_el2) }, | ||
| 476 | - REGINFO_SENTINEL | ||
| 477 | }; | ||
| 478 | |||
| 479 | static const ARMCPRegInfo el2_v8_cp_reginfo[] = { | ||
| 480 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_v8_cp_reginfo[] = { | ||
| 481 | .access = PL2_RW, | ||
| 482 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.hcr_el2), | ||
| 483 | .writefn = hcr_writehigh }, | ||
| 484 | - REGINFO_SENTINEL | ||
| 485 | }; | ||
| 486 | |||
| 487 | static CPAccessResult sel2_access(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 488 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_sec_cp_reginfo[] = { | ||
| 489 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 6, .opc2 = 2, | ||
| 490 | .access = PL2_RW, .accessfn = sel2_access, | ||
| 491 | .fieldoffset = offsetof(CPUARMState, cp15.vstcr_el2) }, | ||
| 492 | - REGINFO_SENTINEL | ||
| 493 | }; | ||
| 494 | |||
| 495 | static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 496 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_cp_reginfo[] = { | ||
| 497 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5, | ||
| 498 | .access = PL3_W, .type = ARM_CP_NO_RAW, | ||
| 499 | .writefn = tlbi_aa64_vae3_write }, | ||
| 500 | - REGINFO_SENTINEL | ||
| 501 | }; | ||
| 502 | |||
| 503 | #ifndef CONFIG_USER_ONLY | ||
| 504 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = { | ||
| 505 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, | ||
| 506 | .access = PL1_RW, .accessfn = access_tda, | ||
| 507 | .type = ARM_CP_NOP }, | ||
| 508 | - REGINFO_SENTINEL | ||
| 509 | }; | ||
| 510 | |||
| 511 | static const ARMCPRegInfo debug_lpae_cp_reginfo[] = { | ||
| 512 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = { | ||
| 513 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | ||
| 514 | { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0, | ||
| 515 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | ||
| 516 | - REGINFO_SENTINEL | ||
| 517 | }; | ||
| 518 | |||
| 519 | /* Return the exception level to which exceptions should be taken | ||
| 520 | @@ -XXX,XX +XXX,XX @@ static void define_debug_regs(ARMCPU *cpu) | ||
| 521 | .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]), | ||
| 522 | .writefn = dbgbcr_write, .raw_writefn = raw_write | ||
| 523 | }, | ||
| 524 | - REGINFO_SENTINEL | ||
| 525 | }; | ||
| 526 | define_arm_cp_regs(cpu, dbgregs); | ||
| 527 | } | ||
| 528 | @@ -XXX,XX +XXX,XX @@ static void define_debug_regs(ARMCPU *cpu) | ||
| 529 | .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]), | ||
| 530 | .writefn = dbgwcr_write, .raw_writefn = raw_write | ||
| 531 | }, | ||
| 532 | - REGINFO_SENTINEL | ||
| 533 | }; | ||
| 534 | define_arm_cp_regs(cpu, dbgregs); | ||
| 535 | } | ||
| 536 | @@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu) | ||
| 537 | .type = ARM_CP_IO, | ||
| 538 | .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn, | ||
| 539 | .raw_writefn = pmevtyper_rawwrite }, | ||
| 540 | - REGINFO_SENTINEL | ||
| 541 | }; | ||
| 542 | define_arm_cp_regs(cpu, pmev_regs); | ||
| 543 | g_free(pmevcntr_name); | ||
| 544 | @@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu) | ||
| 545 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5, | ||
| 546 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | ||
| 547 | .resetvalue = extract64(cpu->pmceid1, 32, 32) }, | ||
| 548 | - REGINFO_SENTINEL | ||
| 549 | }; | ||
| 550 | define_arm_cp_regs(cpu, v81_pmu_regs); | ||
| 551 | } | ||
| 552 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lor_reginfo[] = { | ||
| 553 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7, | ||
| 554 | .access = PL1_R, .accessfn = access_lor_ns, | ||
| 555 | .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 556 | - REGINFO_SENTINEL | ||
| 557 | }; | ||
| 558 | |||
| 559 | #ifdef TARGET_AARCH64 | ||
| 560 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pauth_reginfo[] = { | ||
| 561 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 3, | ||
| 562 | .access = PL1_RW, .accessfn = access_pauth, | ||
| 563 | .fieldoffset = offsetof(CPUARMState, keys.apib.hi) }, | ||
| 564 | - REGINFO_SENTINEL | ||
| 565 | }; | ||
| 566 | |||
| 567 | static const ARMCPRegInfo tlbirange_reginfo[] = { | ||
| 568 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = { | ||
| 569 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 5, | ||
| 570 | .access = PL3_W, .type = ARM_CP_NO_RAW, | ||
| 571 | .writefn = tlbi_aa64_rvae3_write }, | ||
| 572 | - REGINFO_SENTINEL | ||
| 573 | }; | ||
| 574 | |||
| 575 | static const ARMCPRegInfo tlbios_reginfo[] = { | ||
| 576 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = { | ||
| 577 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 5, | ||
| 578 | .access = PL3_W, .type = ARM_CP_NO_RAW, | ||
| 579 | .writefn = tlbi_aa64_vae3is_write }, | ||
| 580 | - REGINFO_SENTINEL | ||
| 581 | }; | ||
| 582 | |||
| 583 | static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) | ||
| 584 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo rndr_reginfo[] = { | ||
| 585 | .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO, | ||
| 586 | .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 1, | ||
| 587 | .access = PL0_R, .readfn = rndr_readfn }, | ||
| 588 | - REGINFO_SENTINEL | ||
| 589 | }; | ||
| 590 | |||
| 591 | #ifndef CONFIG_USER_ONLY | ||
| 592 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dcpop_reg[] = { | ||
| 593 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 1, | ||
| 594 | .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, | ||
| 595 | .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn }, | ||
| 596 | - REGINFO_SENTINEL | ||
| 597 | }; | ||
| 598 | |||
| 599 | static const ARMCPRegInfo dcpodp_reg[] = { | ||
| 600 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dcpodp_reg[] = { | ||
| 601 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 1, | ||
| 602 | .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, | ||
| 603 | .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn }, | ||
| 604 | - REGINFO_SENTINEL | ||
| 605 | }; | ||
| 606 | #endif /*CONFIG_USER_ONLY*/ | ||
| 607 | |||
| 608 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_reginfo[] = { | ||
| 609 | { .name = "DC_CIGDSW", .state = ARM_CP_STATE_AA64, | ||
| 610 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 6, | ||
| 611 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, | ||
| 612 | - REGINFO_SENTINEL | ||
| 613 | }; | ||
| 614 | |||
| 615 | static const ARMCPRegInfo mte_tco_ro_reginfo[] = { | ||
| 616 | { .name = "TCO", .state = ARM_CP_STATE_AA64, | ||
| 617 | .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7, | ||
| 618 | .type = ARM_CP_CONST, .access = PL0_RW, }, | ||
| 619 | - REGINFO_SENTINEL | ||
| 620 | }; | ||
| 621 | |||
| 622 | static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = { | ||
| 623 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = { | ||
| 624 | .accessfn = aa64_zva_access, | ||
| 625 | #endif | ||
| 626 | }, | ||
| 627 | - REGINFO_SENTINEL | ||
| 628 | }; | ||
| 629 | |||
| 630 | #endif | ||
| 631 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo predinv_reginfo[] = { | ||
| 632 | { .name = "CPPRCTX", .state = ARM_CP_STATE_AA32, | ||
| 633 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 7, | ||
| 634 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | ||
| 635 | - REGINFO_SENTINEL | ||
| 636 | }; | ||
| 637 | |||
| 638 | static uint64_t ccsidr2_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
| 639 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ccsidr2_reginfo[] = { | ||
| 640 | .access = PL1_R, | ||
| 641 | .accessfn = access_aa64_tid2, | ||
| 642 | .readfn = ccsidr2_read, .type = ARM_CP_NO_RAW }, | ||
| 643 | - REGINFO_SENTINEL | ||
| 644 | }; | ||
| 645 | |||
| 646 | static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 647 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo jazelle_regs[] = { | ||
| 648 | .cp = 14, .crn = 2, .crm = 0, .opc1 = 7, .opc2 = 0, | ||
| 649 | .accessfn = access_joscr_jmcr, | ||
| 650 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 651 | - REGINFO_SENTINEL | ||
| 652 | }; | ||
| 653 | |||
| 654 | static const ARMCPRegInfo vhe_reginfo[] = { | ||
| 655 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vhe_reginfo[] = { | ||
| 656 | .access = PL2_RW, .accessfn = e2h_access, | ||
| 657 | .writefn = gt_virt_cval_write, .raw_writefn = raw_write }, | ||
| 658 | #endif | ||
| 659 | - REGINFO_SENTINEL | ||
| 660 | }; | ||
| 661 | |||
| 662 | #ifndef CONFIG_USER_ONLY | ||
| 663 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ats1e1_reginfo[] = { | ||
| 664 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1, | ||
| 665 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, | ||
| 666 | .writefn = ats_write64 }, | ||
| 667 | - REGINFO_SENTINEL | ||
| 668 | }; | ||
| 669 | |||
| 670 | static const ARMCPRegInfo ats1cp_reginfo[] = { | ||
| 671 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ats1cp_reginfo[] = { | ||
| 672 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1, | ||
| 673 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, | ||
| 674 | .writefn = ats_write }, | ||
| 675 | - REGINFO_SENTINEL | ||
| 676 | }; | ||
| 677 | #endif | ||
| 678 | |||
| 679 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo actlr2_hactlr2_reginfo[] = { | ||
| 680 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 3, | ||
| 681 | .access = PL2_RW, .type = ARM_CP_CONST, | ||
| 682 | .resetvalue = 0 }, | ||
| 683 | - REGINFO_SENTINEL | ||
| 684 | }; | ||
| 685 | |||
| 686 | void register_cp_regs_for_features(ARMCPU *cpu) | ||
| 687 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
| 688 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 689 | .accessfn = access_aa32_tid3, | ||
| 690 | .resetvalue = cpu->isar.id_isar6 }, | ||
| 691 | - REGINFO_SENTINEL | ||
| 692 | }; | ||
| 693 | define_arm_cp_regs(cpu, v6_idregs); | ||
| 694 | define_arm_cp_regs(cpu, v6_cp_reginfo); | ||
| 695 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
| 696 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7, | ||
| 697 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | ||
| 698 | .resetvalue = cpu->pmceid1 }, | ||
| 699 | - REGINFO_SENTINEL | ||
| 700 | }; | ||
| 701 | #ifdef CONFIG_USER_ONLY | ||
| 702 | ARMCPRegUserSpaceInfo v8_user_idregs[] = { | ||
| 703 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
| 704 | .exported_bits = 0x000000f0ffffffff }, | ||
| 705 | { .name = "ID_AA64ISAR*_EL1_RESERVED", | ||
| 706 | .is_glob = true }, | ||
| 707 | - REGUSERINFO_SENTINEL | ||
| 708 | }; | ||
| 709 | modify_arm_cp_regs(v8_idregs, v8_user_idregs); | ||
| 710 | #endif | ||
| 711 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
| 712 | .access = PL2_RW, | ||
| 713 | .resetvalue = vmpidr_def, | ||
| 714 | .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) }, | ||
| 715 | - REGINFO_SENTINEL | ||
| 716 | }; | ||
| 717 | define_arm_cp_regs(cpu, vpidr_regs); | ||
| 718 | define_arm_cp_regs(cpu, el2_cp_reginfo); | ||
| 719 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
| 720 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | ||
| 721 | .type = ARM_CP_NO_RAW, | ||
| 722 | .writefn = arm_cp_write_ignore, .readfn = mpidr_read }, | ||
| 723 | - REGINFO_SENTINEL | ||
| 724 | }; | ||
| 725 | define_arm_cp_regs(cpu, vpidr_regs); | ||
| 726 | define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo); | ||
| 727 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
| 728 | .raw_writefn = raw_write, .writefn = sctlr_write, | ||
| 729 | .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]), | ||
| 730 | .resetvalue = cpu->reset_sctlr }, | ||
| 731 | - REGINFO_SENTINEL | ||
| 732 | }; | ||
| 733 | |||
| 734 | define_arm_cp_regs(cpu, el3_regs); | ||
| 735 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
| 736 | { .name = "DUMMY", | ||
| 737 | .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY, | ||
| 738 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 739 | - REGINFO_SENTINEL | ||
| 740 | }; | ||
| 741 | ARMCPRegInfo id_v8_midr_cp_reginfo[] = { | ||
| 742 | { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH, | ||
| 743 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
| 744 | .access = PL1_R, | ||
| 745 | .accessfn = access_aa64_tid1, | ||
| 746 | .type = ARM_CP_CONST, .resetvalue = cpu->revidr }, | ||
| 747 | - REGINFO_SENTINEL | ||
| 748 | }; | ||
| 749 | ARMCPRegInfo id_cp_reginfo[] = { | ||
| 750 | /* These are common to v8 and pre-v8 */ | ||
| 751 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
| 752 | .access = PL1_R, | ||
| 753 | .accessfn = access_aa32_tid1, | ||
| 754 | .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 755 | - REGINFO_SENTINEL | ||
| 756 | }; | ||
| 757 | /* TLBTR is specific to VMSA */ | ||
| 758 | ARMCPRegInfo id_tlbtr_reginfo = { | ||
| 759 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
| 760 | { .name = "MIDR_EL1", | ||
| 761 | .exported_bits = 0x00000000ffffffff }, | ||
| 762 | { .name = "REVIDR_EL1" }, | ||
| 763 | - REGUSERINFO_SENTINEL | ||
| 764 | }; | ||
| 765 | modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_reginfo); | ||
| 766 | #endif | ||
| 767 | if (arm_feature(env, ARM_FEATURE_OMAPCP) || | ||
| 768 | arm_feature(env, ARM_FEATURE_STRONGARM)) { | ||
| 769 | - ARMCPRegInfo *r; | ||
| 770 | + size_t i; | ||
| 771 | /* Register the blanket "writes ignored" value first to cover the | ||
| 772 | * whole space. Then update the specific ID registers to allow write | ||
| 773 | * access, so that they ignore writes rather than causing them to | ||
| 774 | * UNDEF. | ||
| 775 | */ | ||
| 776 | define_one_arm_cp_reg(cpu, &crn0_wi_reginfo); | ||
| 777 | - for (r = id_pre_v8_midr_cp_reginfo; | ||
| 778 | - r->type != ARM_CP_SENTINEL; r++) { | ||
| 779 | - r->access = PL1_RW; | ||
| 780 | + for (i = 0; i < ARRAY_SIZE(id_pre_v8_midr_cp_reginfo); ++i) { | ||
| 781 | + id_pre_v8_midr_cp_reginfo[i].access = PL1_RW; | ||
| 782 | } | ||
| 783 | - for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) { | ||
| 784 | - r->access = PL1_RW; | ||
| 785 | + for (i = 0; i < ARRAY_SIZE(id_cp_reginfo); ++i) { | ||
| 786 | + id_cp_reginfo[i].access = PL1_RW; | ||
| 787 | } | ||
| 788 | id_mpuir_reginfo.access = PL1_RW; | ||
| 789 | id_tlbtr_reginfo.access = PL1_RW; | ||
| 790 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
| 791 | { .name = "MPIDR_EL1", .state = ARM_CP_STATE_BOTH, | ||
| 792 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5, | ||
| 793 | .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW }, | ||
| 794 | - REGINFO_SENTINEL | ||
| 795 | }; | ||
| 796 | #ifdef CONFIG_USER_ONLY | ||
| 797 | ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = { | ||
| 798 | { .name = "MPIDR_EL1", | ||
| 799 | .fixed_bits = 0x0000000080000000 }, | ||
| 800 | - REGUSERINFO_SENTINEL | ||
| 801 | }; | ||
| 802 | modify_arm_cp_regs(mpidr_cp_reginfo, mpidr_user_cp_reginfo); | ||
| 803 | #endif | ||
| 804 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
| 805 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1, | ||
| 806 | .access = PL3_RW, .type = ARM_CP_CONST, | ||
| 807 | .resetvalue = 0 }, | ||
| 808 | - REGINFO_SENTINEL | ||
| 809 | }; | ||
| 810 | define_arm_cp_regs(cpu, auxcr_reginfo); | ||
| 811 | if (cpu_isar_feature(aa32_ac2, cpu)) { | ||
| 812 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
| 813 | .type = ARM_CP_CONST, | ||
| 814 | .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0, | ||
| 815 | .access = PL1_R, .resetvalue = cpu->reset_cbar }, | ||
| 816 | - REGINFO_SENTINEL | ||
| 817 | }; | ||
| 818 | /* We don't implement a r/w 64 bit CBAR currently */ | ||
| 819 | assert(arm_feature(env, ARM_FEATURE_CBAR_RO)); | ||
| 820 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
| 821 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s), | ||
| 822 | offsetof(CPUARMState, cp15.vbar_ns) }, | ||
| 823 | .resetvalue = 0 }, | ||
| 824 | - REGINFO_SENTINEL | ||
| 825 | }; | ||
| 826 | define_arm_cp_regs(cpu, vbar_cp_reginfo); | ||
| 827 | } | ||
| 828 | @@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, | ||
| 829 | r->writefn); | ||
| 830 | } | ||
| 831 | } | ||
| 832 | - /* Bad type field probably means missing sentinel at end of reg list */ | ||
| 833 | - assert(cptype_valid(r->type)); | ||
| 22 | + | 834 | + |
| 23 | /* Definitions for the PMCCNTR and PMCR registers */ | 835 | for (crm = crmmin; crm <= crmmax; crm++) { |
| 24 | #define PMCRD 0x8 | 836 | for (opc1 = opc1min; opc1 <= opc1max; opc1++) { |
| 25 | #define PMCRC 0x4 | 837 | for (opc2 = opc2min; opc2 <= opc2max; opc2++) { |
| 26 | @@ -XXX,XX +XXX,XX @@ static void arm_log_exception(int idx) | 838 | @@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, |
| 27 | } | 839 | } |
| 28 | } | 840 | } |
| 29 | 841 | ||
| 30 | +static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, | 842 | -void define_arm_cp_regs_with_opaque(ARMCPU *cpu, |
| 31 | + uint32_t addr, uint16_t *insn) | 843 | - const ARMCPRegInfo *regs, void *opaque) |
| 32 | +{ | 844 | +/* Define a whole list of registers */ |
| 33 | + /* Load a 16-bit portion of a v7M instruction, returning true on success, | 845 | +void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *regs, |
| 34 | + * or false on failure (in which case we will have pended the appropriate | 846 | + void *opaque, size_t len) |
| 35 | + * exception). | 847 | { |
| 36 | + * We need to do the instruction fetch's MPU and SAU checks | 848 | - /* Define a whole list of registers */ |
| 37 | + * like this because there is no MMU index that would allow | 849 | - const ARMCPRegInfo *r; |
| 38 | + * doing the load with a single function call. Instead we must | 850 | - for (r = regs; r->type != ARM_CP_SENTINEL; r++) { |
| 39 | + * first check that the security attributes permit the load | 851 | - define_one_arm_cp_reg_with_opaque(cpu, r, opaque); |
| 40 | + * and that they don't mismatch on the two halves of the instruction, | 852 | + size_t i; |
| 41 | + * and then we do the load as a secure load (ie using the security | 853 | + for (i = 0; i < len; ++i) { |
| 42 | + * attributes of the address, not the CPU, as architecturally required). | 854 | + define_one_arm_cp_reg_with_opaque(cpu, regs + i, opaque); |
| 43 | + */ | 855 | } |
| 44 | + CPUState *cs = CPU(cpu); | 856 | } |
| 45 | + CPUARMState *env = &cpu->env; | 857 | |
| 46 | + V8M_SAttributes sattrs = {}; | 858 | @@ -XXX,XX +XXX,XX @@ void define_arm_cp_regs_with_opaque(ARMCPU *cpu, |
| 47 | + MemTxAttrs attrs = {}; | 859 | * user-space cannot alter any values and dynamic values pertaining to |
| 48 | + ARMMMUFaultInfo fi = {}; | 860 | * execution state are hidden from user space view anyway. |
| 49 | + MemTxResult txres; | 861 | */ |
| 50 | + target_ulong page_size; | 862 | -void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods) |
| 51 | + hwaddr physaddr; | 863 | +void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len, |
| 52 | + int prot; | 864 | + const ARMCPRegUserSpaceInfo *mods, |
| 53 | + uint32_t fsr; | 865 | + size_t mods_len) |
| 866 | { | ||
| 867 | - const ARMCPRegUserSpaceInfo *m; | ||
| 868 | - ARMCPRegInfo *r; | ||
| 869 | - | ||
| 870 | - for (m = mods; m->name; m++) { | ||
| 871 | + for (size_t mi = 0; mi < mods_len; ++mi) { | ||
| 872 | + const ARMCPRegUserSpaceInfo *m = mods + mi; | ||
| 873 | GPatternSpec *pat = NULL; | ||
| 54 | + | 874 | + |
| 55 | + v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, &sattrs); | 875 | if (m->is_glob) { |
| 56 | + if (!sattrs.nsc || sattrs.ns) { | 876 | pat = g_pattern_spec_new(m->name); |
| 57 | + /* This must be the second half of the insn, and it straddles a | 877 | } |
| 58 | + * region boundary with the second half not being S&NSC. | 878 | - for (r = regs; r->type != ARM_CP_SENTINEL; r++) { |
| 59 | + */ | 879 | + for (size_t ri = 0; ri < regs_len; ++ri) { |
| 60 | + env->v7m.sfsr |= R_V7M_SFSR_INVEP_MASK; | 880 | + ARMCPRegInfo *r = regs + ri; |
| 61 | + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); | ||
| 62 | + qemu_log_mask(CPU_LOG_INT, | ||
| 63 | + "...really SecureFault with SFSR.INVEP\n"); | ||
| 64 | + return false; | ||
| 65 | + } | ||
| 66 | + if (get_phys_addr(env, addr, MMU_INST_FETCH, mmu_idx, | ||
| 67 | + &physaddr, &attrs, &prot, &page_size, &fsr, &fi)) { | ||
| 68 | + /* the MPU lookup failed */ | ||
| 69 | + env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_IACCVIOL_MASK; | ||
| 70 | + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, env->v7m.secure); | ||
| 71 | + qemu_log_mask(CPU_LOG_INT, "...really MemManage with CFSR.IACCVIOL\n"); | ||
| 72 | + return false; | ||
| 73 | + } | ||
| 74 | + *insn = address_space_lduw_le(arm_addressspace(cs, attrs), physaddr, | ||
| 75 | + attrs, &txres); | ||
| 76 | + if (txres != MEMTX_OK) { | ||
| 77 | + env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_IBUSERR_MASK; | ||
| 78 | + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false); | ||
| 79 | + qemu_log_mask(CPU_LOG_INT, "...really BusFault with CFSR.IBUSERR\n"); | ||
| 80 | + return false; | ||
| 81 | + } | ||
| 82 | + return true; | ||
| 83 | +} | ||
| 84 | + | 881 | + |
| 85 | +static bool v7m_handle_execute_nsc(ARMCPU *cpu) | 882 | if (pat && g_pattern_match_string(pat, r->name)) { |
| 86 | +{ | 883 | r->type = ARM_CP_CONST; |
| 87 | + /* Check whether this attempt to execute code in a Secure & NS-Callable | 884 | r->access = PL0U_R; |
| 88 | + * memory region is for an SG instruction; if so, then emulate the | ||
| 89 | + * effect of the SG instruction and return true. Otherwise pend | ||
| 90 | + * the correct kind of exception and return false. | ||
| 91 | + */ | ||
| 92 | + CPUARMState *env = &cpu->env; | ||
| 93 | + ARMMMUIdx mmu_idx; | ||
| 94 | + uint16_t insn; | ||
| 95 | + | ||
| 96 | + /* We should never get here unless get_phys_addr_pmsav8() caused | ||
| 97 | + * an exception for NS executing in S&NSC memory. | ||
| 98 | + */ | ||
| 99 | + assert(!env->v7m.secure); | ||
| 100 | + assert(arm_feature(env, ARM_FEATURE_M_SECURITY)); | ||
| 101 | + | ||
| 102 | + /* We want to do the MPU lookup as secure; work out what mmu_idx that is */ | ||
| 103 | + mmu_idx = arm_v7m_mmu_idx_for_secstate(env, true); | ||
| 104 | + | ||
| 105 | + if (!v7m_read_half_insn(cpu, mmu_idx, env->regs[15], &insn)) { | ||
| 106 | + return false; | ||
| 107 | + } | ||
| 108 | + | ||
| 109 | + if (!env->thumb) { | ||
| 110 | + goto gen_invep; | ||
| 111 | + } | ||
| 112 | + | ||
| 113 | + if (insn != 0xe97f) { | ||
| 114 | + /* Not an SG instruction first half (we choose the IMPDEF | ||
| 115 | + * early-SG-check option). | ||
| 116 | + */ | ||
| 117 | + goto gen_invep; | ||
| 118 | + } | ||
| 119 | + | ||
| 120 | + if (!v7m_read_half_insn(cpu, mmu_idx, env->regs[15] + 2, &insn)) { | ||
| 121 | + return false; | ||
| 122 | + } | ||
| 123 | + | ||
| 124 | + if (insn != 0xe97f) { | ||
| 125 | + /* Not an SG instruction second half (yes, both halves of the SG | ||
| 126 | + * insn have the same hex value) | ||
| 127 | + */ | ||
| 128 | + goto gen_invep; | ||
| 129 | + } | ||
| 130 | + | ||
| 131 | + /* OK, we have confirmed that we really have an SG instruction. | ||
| 132 | + * We know we're NS in S memory so don't need to repeat those checks. | ||
| 133 | + */ | ||
| 134 | + qemu_log_mask(CPU_LOG_INT, "...really an SG instruction at 0x%08" PRIx32 | ||
| 135 | + ", executing it\n", env->regs[15]); | ||
| 136 | + env->regs[14] &= ~1; | ||
| 137 | + switch_v7m_security_state(env, true); | ||
| 138 | + xpsr_write(env, 0, XPSR_IT); | ||
| 139 | + env->regs[15] += 4; | ||
| 140 | + return true; | ||
| 141 | + | ||
| 142 | +gen_invep: | ||
| 143 | + env->v7m.sfsr |= R_V7M_SFSR_INVEP_MASK; | ||
| 144 | + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); | ||
| 145 | + qemu_log_mask(CPU_LOG_INT, | ||
| 146 | + "...really SecureFault with SFSR.INVEP\n"); | ||
| 147 | + return false; | ||
| 148 | +} | ||
| 149 | + | ||
| 150 | void arm_v7m_cpu_do_interrupt(CPUState *cs) | ||
| 151 | { | ||
| 152 | ARMCPU *cpu = ARM_CPU(cs); | ||
| 153 | @@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) | ||
| 154 | * the SG instruction have the same security attributes.) | ||
| 155 | * Everything else must generate an INVEP SecureFault, so we | ||
| 156 | * emulate the SG instruction here. | ||
| 157 | - * TODO: actually emulate SG. | ||
| 158 | */ | ||
| 159 | - env->v7m.sfsr |= R_V7M_SFSR_INVEP_MASK; | ||
| 160 | - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); | ||
| 161 | - qemu_log_mask(CPU_LOG_INT, | ||
| 162 | - "...really SecureFault with SFSR.INVEP\n"); | ||
| 163 | + if (v7m_handle_execute_nsc(cpu)) { | ||
| 164 | + return; | ||
| 165 | + } | ||
| 166 | break; | ||
| 167 | case M_FAKE_FSR_SFAULT: | ||
| 168 | /* Various flavours of SecureFault for attempts to execute or | ||
| 169 | -- | 885 | -- |
| 170 | 2.7.4 | 886 | 2.25.1 |
| 171 | 887 | ||
| 172 | 888 | diff view generated by jsdifflib |
| 1 | From: Cédric Le Goater <clg@kaod.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Initially from Anton D. Kachalov" <mouse@yandex-team.ru> but the SoB was | 3 | These particular data structures are not modified at runtime. |
| 4 | missing. | ||
| 5 | 4 | ||
| 6 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 5 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> |
| 7 | Acked-by: Andrew Jeffery <andrew@aj.id.au> | ||
| 8 | Message-id: 20170920064915.30027-1-clg@kaod.org | ||
| 9 | [clg: change commit log and subject | ||
| 10 | replace UL suffix by ULL ] | ||
| 11 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
| 12 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
| 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 8 | Message-id: 20220501055028.646596-5-richard.henderson@linaro.org | ||
| 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 14 | --- | 10 | --- |
| 15 | hw/watchdog/wdt_aspeed.c | 4 ++-- | 11 | target/arm/helper.c | 16 ++++++++-------- |
| 16 | 1 file changed, 2 insertions(+), 2 deletions(-) | 12 | 1 file changed, 8 insertions(+), 8 deletions(-) |
| 17 | 13 | ||
| 18 | diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c | 14 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
| 19 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
| 20 | --- a/hw/watchdog/wdt_aspeed.c | 16 | --- a/target/arm/helper.c |
| 21 | +++ b/hw/watchdog/wdt_aspeed.c | 17 | +++ b/target/arm/helper.c |
| 22 | @@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size) | 18 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) |
| 23 | 19 | .resetvalue = cpu->pmceid1 }, | |
| 24 | static void aspeed_wdt_reload(AspeedWDTState *s, bool pclk) | 20 | }; |
| 25 | { | 21 | #ifdef CONFIG_USER_ONLY |
| 26 | - uint32_t reload; | 22 | - ARMCPRegUserSpaceInfo v8_user_idregs[] = { |
| 27 | + uint64_t reload; | 23 | + static const ARMCPRegUserSpaceInfo v8_user_idregs[] = { |
| 28 | 24 | { .name = "ID_AA64PFR0_EL1", | |
| 29 | if (pclk) { | 25 | .exported_bits = 0x000f000f00ff0000, |
| 30 | reload = muldiv64(s->regs[WDT_RELOAD_VALUE], NANOSECONDS_PER_SECOND, | 26 | .fixed_bits = 0x0000000000000011 }, |
| 31 | s->pclk_freq); | 27 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) |
| 28 | */ | ||
| 29 | if (arm_feature(env, ARM_FEATURE_EL3)) { | ||
| 30 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { | ||
| 31 | - ARMCPRegInfo nsacr = { | ||
| 32 | + static const ARMCPRegInfo nsacr = { | ||
| 33 | .name = "NSACR", .type = ARM_CP_CONST, | ||
| 34 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | ||
| 35 | .access = PL1_RW, .accessfn = nsacr_access, | ||
| 36 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
| 37 | }; | ||
| 38 | define_one_arm_cp_reg(cpu, &nsacr); | ||
| 39 | } else { | ||
| 40 | - ARMCPRegInfo nsacr = { | ||
| 41 | + static const ARMCPRegInfo nsacr = { | ||
| 42 | .name = "NSACR", | ||
| 43 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | ||
| 44 | .access = PL3_RW | PL1_R, | ||
| 45 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
| 46 | } | ||
| 32 | } else { | 47 | } else { |
| 33 | - reload = s->regs[WDT_RELOAD_VALUE] * 1000; | 48 | if (arm_feature(env, ARM_FEATURE_V8)) { |
| 34 | + reload = s->regs[WDT_RELOAD_VALUE] * 1000ULL; | 49 | - ARMCPRegInfo nsacr = { |
| 50 | + static const ARMCPRegInfo nsacr = { | ||
| 51 | .name = "NSACR", .type = ARM_CP_CONST, | ||
| 52 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | ||
| 53 | .access = PL1_R, | ||
| 54 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
| 55 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 56 | .resetvalue = cpu->pmsav7_dregion << 8 | ||
| 57 | }; | ||
| 58 | - ARMCPRegInfo crn0_wi_reginfo = { | ||
| 59 | + static const ARMCPRegInfo crn0_wi_reginfo = { | ||
| 60 | .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY, | ||
| 61 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W, | ||
| 62 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE | ||
| 63 | }; | ||
| 64 | #ifdef CONFIG_USER_ONLY | ||
| 65 | - ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = { | ||
| 66 | + static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = { | ||
| 67 | { .name = "MIDR_EL1", | ||
| 68 | .exported_bits = 0x00000000ffffffff }, | ||
| 69 | { .name = "REVIDR_EL1" }, | ||
| 70 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
| 71 | .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW }, | ||
| 72 | }; | ||
| 73 | #ifdef CONFIG_USER_ONLY | ||
| 74 | - ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = { | ||
| 75 | + static const ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = { | ||
| 76 | { .name = "MPIDR_EL1", | ||
| 77 | .fixed_bits = 0x0000000080000000 }, | ||
| 78 | }; | ||
| 79 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
| 35 | } | 80 | } |
| 36 | 81 | ||
| 37 | if (aspeed_wdt_is_enabled(s)) { | 82 | if (arm_feature(env, ARM_FEATURE_VBAR)) { |
| 83 | - ARMCPRegInfo vbar_cp_reginfo[] = { | ||
| 84 | + static const ARMCPRegInfo vbar_cp_reginfo[] = { | ||
| 85 | { .name = "VBAR", .state = ARM_CP_STATE_BOTH, | ||
| 86 | .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, | ||
| 87 | .access = PL1_RW, .writefn = vbar_write, | ||
| 38 | -- | 88 | -- |
| 39 | 2.7.4 | 89 | 2.25.1 |
| 40 | 90 | ||
| 41 | 91 | diff view generated by jsdifflib |
| 1 | The common situation of the SG instruction is that it is | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | executed from S&NSC memory by a CPU in NS state. That case | 2 | |
| 3 | is handled by v7m_handle_execute_nsc(). However the instruction | 3 | Instead of defining ARM_CP_FLAG_MASK to remove flags, |
| 4 | also has defined behaviour in a couple of other cases: | 4 | define ARM_CP_SPECIAL_MASK to isolate special cases. |
| 5 | * SG instruction in NS memory (behaves as a NOP) | 5 | Sort the specials to the low bits. Use an enum. |
| 6 | * SG in S memory but CPU already secure (clears IT bits and | 6 | |
| 7 | does nothing else) | 7 | Split the large comment block so as to document each |
| 8 | * SG instruction in v8M without Security Extension (NOP) | 8 | value separately. |
| 9 | 9 | ||
| 10 | These can be implemented in translate.c. | 10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
| 11 | 11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | |
| 12 | Message-id: 20220501055028.646596-6-richard.henderson@linaro.org | ||
| 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 14 | Message-id: 1507556919-24992-10-git-send-email-peter.maydell@linaro.org | ||
| 15 | --- | 14 | --- |
| 16 | target/arm/translate.c | 23 ++++++++++++++++++++++- | 15 | target/arm/cpregs.h | 130 +++++++++++++++++++++++-------------- |
| 17 | 1 file changed, 22 insertions(+), 1 deletion(-) | 16 | target/arm/cpu.c | 4 +- |
| 18 | 17 | target/arm/helper.c | 4 +- | |
| 18 | target/arm/translate-a64.c | 6 +- | ||
| 19 | target/arm/translate.c | 6 +- | ||
| 20 | 5 files changed, 92 insertions(+), 58 deletions(-) | ||
| 21 | |||
| 22 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h | ||
| 23 | index XXXXXXX..XXXXXXX 100644 | ||
| 24 | --- a/target/arm/cpregs.h | ||
| 25 | +++ b/target/arm/cpregs.h | ||
| 26 | @@ -XXX,XX +XXX,XX @@ | ||
| 27 | #define TARGET_ARM_CPREGS_H | ||
| 28 | |||
| 29 | /* | ||
| 30 | - * ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a | ||
| 31 | - * special-behaviour cp reg and bits [11..8] indicate what behaviour | ||
| 32 | - * it has. Otherwise it is a simple cp reg, where CONST indicates that | ||
| 33 | - * TCG can assume the value to be constant (ie load at translate time) | ||
| 34 | - * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END | ||
| 35 | - * indicates that the TB should not be ended after a write to this register | ||
| 36 | - * (the default is that the TB ends after cp writes). OVERRIDE permits | ||
| 37 | - * a register definition to override a previous definition for the | ||
| 38 | - * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the | ||
| 39 | - * old must have the OVERRIDE bit set. | ||
| 40 | - * ALIAS indicates that this register is an alias view of some underlying | ||
| 41 | - * state which is also visible via another register, and that the other | ||
| 42 | - * register is handling migration and reset; registers marked ALIAS will not be | ||
| 43 | - * migrated but may have their state set by syncing of register state from KVM. | ||
| 44 | - * NO_RAW indicates that this register has no underlying state and does not | ||
| 45 | - * support raw access for state saving/loading; it will not be used for either | ||
| 46 | - * migration or KVM state synchronization. (Typically this is for "registers" | ||
| 47 | - * which are actually used as instructions for cache maintenance and so on.) | ||
| 48 | - * IO indicates that this register does I/O and therefore its accesses | ||
| 49 | - * need to be marked with gen_io_start() and also end the TB. In particular, | ||
| 50 | - * registers which implement clocks or timers require this. | ||
| 51 | - * RAISES_EXC is for when the read or write hook might raise an exception; | ||
| 52 | - * the generated code will synchronize the CPU state before calling the hook | ||
| 53 | - * so that it is safe for the hook to call raise_exception(). | ||
| 54 | - * NEWEL is for writes to registers that might change the exception | ||
| 55 | - * level - typically on older ARM chips. For those cases we need to | ||
| 56 | - * re-read the new el when recomputing the translation flags. | ||
| 57 | + * ARMCPRegInfo type field bits: | ||
| 58 | */ | ||
| 59 | -#define ARM_CP_SPECIAL 0x0001 | ||
| 60 | -#define ARM_CP_CONST 0x0002 | ||
| 61 | -#define ARM_CP_64BIT 0x0004 | ||
| 62 | -#define ARM_CP_SUPPRESS_TB_END 0x0008 | ||
| 63 | -#define ARM_CP_OVERRIDE 0x0010 | ||
| 64 | -#define ARM_CP_ALIAS 0x0020 | ||
| 65 | -#define ARM_CP_IO 0x0040 | ||
| 66 | -#define ARM_CP_NO_RAW 0x0080 | ||
| 67 | -#define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) | ||
| 68 | -#define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) | ||
| 69 | -#define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) | ||
| 70 | -#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) | ||
| 71 | -#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) | ||
| 72 | -#define ARM_CP_DC_GVA (ARM_CP_SPECIAL | 0x0600) | ||
| 73 | -#define ARM_CP_DC_GZVA (ARM_CP_SPECIAL | 0x0700) | ||
| 74 | -#define ARM_LAST_SPECIAL ARM_CP_DC_GZVA | ||
| 75 | -#define ARM_CP_FPU 0x1000 | ||
| 76 | -#define ARM_CP_SVE 0x2000 | ||
| 77 | -#define ARM_CP_NO_GDB 0x4000 | ||
| 78 | -#define ARM_CP_RAISES_EXC 0x8000 | ||
| 79 | -#define ARM_CP_NEWEL 0x10000 | ||
| 80 | -/* Mask of only the flag bits in a type field */ | ||
| 81 | -#define ARM_CP_FLAG_MASK 0x1f0ff | ||
| 82 | +enum { | ||
| 83 | + /* | ||
| 84 | + * Register must be handled specially during translation. | ||
| 85 | + * The method is one of the values below: | ||
| 86 | + */ | ||
| 87 | + ARM_CP_SPECIAL_MASK = 0x000f, | ||
| 88 | + /* Special: no change to PE state: writes ignored, reads ignored. */ | ||
| 89 | + ARM_CP_NOP = 0x0001, | ||
| 90 | + /* Special: sysreg is WFI, for v5 and v6. */ | ||
| 91 | + ARM_CP_WFI = 0x0002, | ||
| 92 | + /* Special: sysreg is NZCV. */ | ||
| 93 | + ARM_CP_NZCV = 0x0003, | ||
| 94 | + /* Special: sysreg is CURRENTEL. */ | ||
| 95 | + ARM_CP_CURRENTEL = 0x0004, | ||
| 96 | + /* Special: sysreg is DC ZVA or similar. */ | ||
| 97 | + ARM_CP_DC_ZVA = 0x0005, | ||
| 98 | + ARM_CP_DC_GVA = 0x0006, | ||
| 99 | + ARM_CP_DC_GZVA = 0x0007, | ||
| 100 | + | ||
| 101 | + /* Flag: reads produce resetvalue; writes ignored. */ | ||
| 102 | + ARM_CP_CONST = 1 << 4, | ||
| 103 | + /* Flag: For ARM_CP_STATE_AA32, sysreg is 64-bit. */ | ||
| 104 | + ARM_CP_64BIT = 1 << 5, | ||
| 105 | + /* | ||
| 106 | + * Flag: TB should not be ended after a write to this register | ||
| 107 | + * (the default is that the TB ends after cp writes). | ||
| 108 | + */ | ||
| 109 | + ARM_CP_SUPPRESS_TB_END = 1 << 6, | ||
| 110 | + /* | ||
| 111 | + * Flag: Permit a register definition to override a previous definition | ||
| 112 | + * for the same (cp, is64, crn, crm, opc1, opc2) tuple: either the new | ||
| 113 | + * or the old must have the ARM_CP_OVERRIDE bit set. | ||
| 114 | + */ | ||
| 115 | + ARM_CP_OVERRIDE = 1 << 7, | ||
| 116 | + /* | ||
| 117 | + * Flag: Register is an alias view of some underlying state which is also | ||
| 118 | + * visible via another register, and that the other register is handling | ||
| 119 | + * migration and reset; registers marked ARM_CP_ALIAS will not be migrated | ||
| 120 | + * but may have their state set by syncing of register state from KVM. | ||
| 121 | + */ | ||
| 122 | + ARM_CP_ALIAS = 1 << 8, | ||
| 123 | + /* | ||
| 124 | + * Flag: Register does I/O and therefore its accesses need to be marked | ||
| 125 | + * with gen_io_start() and also end the TB. In particular, registers which | ||
| 126 | + * implement clocks or timers require this. | ||
| 127 | + */ | ||
| 128 | + ARM_CP_IO = 1 << 9, | ||
| 129 | + /* | ||
| 130 | + * Flag: Register has no underlying state and does not support raw access | ||
| 131 | + * for state saving/loading; it will not be used for either migration or | ||
| 132 | + * KVM state synchronization. Typically this is for "registers" which are | ||
| 133 | + * actually used as instructions for cache maintenance and so on. | ||
| 134 | + */ | ||
| 135 | + ARM_CP_NO_RAW = 1 << 10, | ||
| 136 | + /* | ||
| 137 | + * Flag: The read or write hook might raise an exception; the generated | ||
| 138 | + * code will synchronize the CPU state before calling the hook so that it | ||
| 139 | + * is safe for the hook to call raise_exception(). | ||
| 140 | + */ | ||
| 141 | + ARM_CP_RAISES_EXC = 1 << 11, | ||
| 142 | + /* | ||
| 143 | + * Flag: Writes to the sysreg might change the exception level - typically | ||
| 144 | + * on older ARM chips. For those cases we need to re-read the new el when | ||
| 145 | + * recomputing the translation flags. | ||
| 146 | + */ | ||
| 147 | + ARM_CP_NEWEL = 1 << 12, | ||
| 148 | + /* | ||
| 149 | + * Flag: Access check for this sysreg is identical to accessing FPU state | ||
| 150 | + * from an instruction: use translation fp_access_check(). | ||
| 151 | + */ | ||
| 152 | + ARM_CP_FPU = 1 << 13, | ||
| 153 | + /* | ||
| 154 | + * Flag: Access check for this sysreg is identical to accessing SVE state | ||
| 155 | + * from an instruction: use translation sve_access_check(). | ||
| 156 | + */ | ||
| 157 | + ARM_CP_SVE = 1 << 14, | ||
| 158 | + /* Flag: Do not expose in gdb sysreg xml. */ | ||
| 159 | + ARM_CP_NO_GDB = 1 << 15, | ||
| 160 | +}; | ||
| 161 | |||
| 162 | /* | ||
| 163 | * Valid values for ARMCPRegInfo state field, indicating which of | ||
| 164 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
| 165 | index XXXXXXX..XXXXXXX 100644 | ||
| 166 | --- a/target/arm/cpu.c | ||
| 167 | +++ b/target/arm/cpu.c | ||
| 168 | @@ -XXX,XX +XXX,XX @@ static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) | ||
| 169 | ARMCPRegInfo *ri = value; | ||
| 170 | ARMCPU *cpu = opaque; | ||
| 171 | |||
| 172 | - if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { | ||
| 173 | + if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) { | ||
| 174 | return; | ||
| 175 | } | ||
| 176 | |||
| 177 | @@ -XXX,XX +XXX,XX @@ static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) | ||
| 178 | ARMCPU *cpu = opaque; | ||
| 179 | uint64_t oldvalue, newvalue; | ||
| 180 | |||
| 181 | - if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { | ||
| 182 | + if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { | ||
| 183 | return; | ||
| 184 | } | ||
| 185 | |||
| 186 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
| 187 | index XXXXXXX..XXXXXXX 100644 | ||
| 188 | --- a/target/arm/helper.c | ||
| 189 | +++ b/target/arm/helper.c | ||
| 190 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
| 191 | * multiple times. Special registers (ie NOP/WFI) are | ||
| 192 | * never migratable and not even raw-accessible. | ||
| 193 | */ | ||
| 194 | - if ((r->type & ARM_CP_SPECIAL)) { | ||
| 195 | + if (r->type & ARM_CP_SPECIAL_MASK) { | ||
| 196 | r2->type |= ARM_CP_NO_RAW; | ||
| 197 | } | ||
| 198 | if (((r->crm == CP_ANY) && crm != 0) || | ||
| 199 | @@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, | ||
| 200 | /* Check that the register definition has enough info to handle | ||
| 201 | * reads and writes if they are permitted. | ||
| 202 | */ | ||
| 203 | - if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) { | ||
| 204 | + if (!(r->type & (ARM_CP_SPECIAL_MASK | ARM_CP_CONST))) { | ||
| 205 | if (r->access & PL3_R) { | ||
| 206 | assert((r->fieldoffset || | ||
| 207 | (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || | ||
| 208 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
| 209 | index XXXXXXX..XXXXXXX 100644 | ||
| 210 | --- a/target/arm/translate-a64.c | ||
| 211 | +++ b/target/arm/translate-a64.c | ||
| 212 | @@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, | ||
| 213 | } | ||
| 214 | |||
| 215 | /* Handle special cases first */ | ||
| 216 | - switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) { | ||
| 217 | + switch (ri->type & ARM_CP_SPECIAL_MASK) { | ||
| 218 | + case 0: | ||
| 219 | + break; | ||
| 220 | case ARM_CP_NOP: | ||
| 221 | return; | ||
| 222 | case ARM_CP_NZCV: | ||
| 223 | @@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, | ||
| 224 | } | ||
| 225 | return; | ||
| 226 | default: | ||
| 227 | - break; | ||
| 228 | + g_assert_not_reached(); | ||
| 229 | } | ||
| 230 | if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) { | ||
| 231 | return; | ||
| 19 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 232 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
| 20 | index XXXXXXX..XXXXXXX 100644 | 233 | index XXXXXXX..XXXXXXX 100644 |
| 21 | --- a/target/arm/translate.c | 234 | --- a/target/arm/translate.c |
| 22 | +++ b/target/arm/translate.c | 235 | +++ b/target/arm/translate.c |
| 23 | @@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(DisasContext *s, uint32_t insn) | 236 | @@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64, |
| 24 | * - load/store doubleword, load/store exclusive, ldacq/strel, | 237 | } |
| 25 | * table branch. | 238 | |
| 26 | */ | 239 | /* Handle special cases first */ |
| 27 | - if (insn & 0x01200000) { | 240 | - switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) { |
| 28 | + if (insn == 0xe97fe97f && arm_dc_feature(s, ARM_FEATURE_M) && | 241 | + switch (ri->type & ARM_CP_SPECIAL_MASK) { |
| 29 | + arm_dc_feature(s, ARM_FEATURE_V8)) { | 242 | + case 0: |
| 30 | + /* 0b1110_1001_0111_1111_1110_1001_0111_111 | 243 | + break; |
| 31 | + * - SG (v8M only) | 244 | case ARM_CP_NOP: |
| 32 | + * The bulk of the behaviour for this instruction is implemented | 245 | return; |
| 33 | + * in v7m_handle_execute_nsc(), which deals with the insn when | 246 | case ARM_CP_WFI: |
| 34 | + * it is executed by a CPU in non-secure state from memory | 247 | @@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64, |
| 35 | + * which is Secure & NonSecure-Callable. | 248 | s->base.is_jmp = DISAS_WFI; |
| 36 | + * Here we only need to handle the remaining cases: | 249 | return; |
| 37 | + * * in NS memory (including the "security extension not | 250 | default: |
| 38 | + * implemented" case) : NOP | 251 | - break; |
| 39 | + * * in S memory but CPU already secure (clear IT bits) | 252 | + g_assert_not_reached(); |
| 40 | + * We know that the attribute for the memory this insn is | 253 | } |
| 41 | + * in must match the current CPU state, because otherwise | 254 | |
| 42 | + * get_phys_addr_pmsav8 would have generated an exception. | 255 | if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { |
| 43 | + */ | ||
| 44 | + if (s->v8m_secure) { | ||
| 45 | + /* Like the IT insn, we don't need to generate any code */ | ||
| 46 | + s->condexec_cond = 0; | ||
| 47 | + s->condexec_mask = 0; | ||
| 48 | + } | ||
| 49 | + } else if (insn & 0x01200000) { | ||
| 50 | /* 0b1110_1000_x11x_xxxx_xxxx_xxxx_xxxx_xxxx | ||
| 51 | * - load/store dual (post-indexed) | ||
| 52 | * 0b1111_1001_x10x_xxxx_xxxx_xxxx_xxxx_xxxx | ||
| 53 | -- | 256 | -- |
| 54 | 2.7.4 | 257 | 2.25.1 |
| 55 | |||
| 56 | diff view generated by jsdifflib |
| 1 | The code which implements the Thumb1 split BL/BLX instructions | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | is guarded by a check on "not M or THUMB2". All we really need | ||
| 3 | to check here is "not THUMB2" (and we assume that elsewhere too, | ||
| 4 | eg in the ARCH(6T2) test that UNDEFs the Thumb2 insns). | ||
| 5 | 2 | ||
| 6 | This doesn't change behaviour because all M profile cores | 3 | Standardize on g_assert_not_reached() for "should not happen". |
| 7 | have Thumb2 and so ARM_FEATURE_M implies ARM_FEATURE_THUMB2. | 4 | Retain abort() when preceeded by fprintf or error_report. |
| 8 | (v6M implements a very restricted subset of Thumb2, but we | ||
| 9 | can cross that bridge when we get to it with appropriate | ||
| 10 | feature bits.) | ||
| 11 | 5 | ||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Message-id: 20220501055028.646596-7-richard.henderson@linaro.org | ||
| 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 14 | Message-id: 1507556919-24992-6-git-send-email-peter.maydell@linaro.org | ||
| 15 | --- | 10 | --- |
| 16 | target/arm/translate.c | 3 +-- | 11 | target/arm/helper.c | 7 +++---- |
| 17 | 1 file changed, 1 insertion(+), 2 deletions(-) | 12 | target/arm/hvf/hvf.c | 2 +- |
| 13 | target/arm/kvm-stub.c | 4 ++-- | ||
| 14 | target/arm/kvm.c | 4 ++-- | ||
| 15 | target/arm/machine.c | 4 ++-- | ||
| 16 | target/arm/translate-a64.c | 4 ++-- | ||
| 17 | target/arm/translate-neon.c | 2 +- | ||
| 18 | target/arm/translate.c | 4 ++-- | ||
| 19 | 8 files changed, 15 insertions(+), 16 deletions(-) | ||
| 18 | 20 | ||
| 21 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
| 22 | index XXXXXXX..XXXXXXX 100644 | ||
| 23 | --- a/target/arm/helper.c | ||
| 24 | +++ b/target/arm/helper.c | ||
| 25 | @@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, | ||
| 26 | break; | ||
| 27 | default: | ||
| 28 | /* broken reginfo with out-of-range opc1 */ | ||
| 29 | - assert(false); | ||
| 30 | - break; | ||
| 31 | + g_assert_not_reached(); | ||
| 32 | } | ||
| 33 | /* assert our permissions are not too lax (stricter is fine) */ | ||
| 34 | assert((r->access & ~mask) == 0); | ||
| 35 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, | ||
| 36 | break; | ||
| 37 | default: | ||
| 38 | /* Never happens, but compiler isn't smart enough to tell. */ | ||
| 39 | - abort(); | ||
| 40 | + g_assert_not_reached(); | ||
| 41 | } | ||
| 42 | } | ||
| 43 | *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); | ||
| 44 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, | ||
| 45 | break; | ||
| 46 | default: | ||
| 47 | /* Never happens, but compiler isn't smart enough to tell. */ | ||
| 48 | - abort(); | ||
| 49 | + g_assert_not_reached(); | ||
| 50 | } | ||
| 51 | } | ||
| 52 | if (domain_prot == 3) { | ||
| 53 | diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c | ||
| 54 | index XXXXXXX..XXXXXXX 100644 | ||
| 55 | --- a/target/arm/hvf/hvf.c | ||
| 56 | +++ b/target/arm/hvf/hvf.c | ||
| 57 | @@ -XXX,XX +XXX,XX @@ int hvf_vcpu_exec(CPUState *cpu) | ||
| 58 | /* we got kicked, no exit to process */ | ||
| 59 | return 0; | ||
| 60 | default: | ||
| 61 | - assert(0); | ||
| 62 | + g_assert_not_reached(); | ||
| 63 | } | ||
| 64 | |||
| 65 | hvf_sync_vtimer(cpu); | ||
| 66 | diff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c | ||
| 67 | index XXXXXXX..XXXXXXX 100644 | ||
| 68 | --- a/target/arm/kvm-stub.c | ||
| 69 | +++ b/target/arm/kvm-stub.c | ||
| 70 | @@ -XXX,XX +XXX,XX @@ | ||
| 71 | |||
| 72 | bool write_kvmstate_to_list(ARMCPU *cpu) | ||
| 73 | { | ||
| 74 | - abort(); | ||
| 75 | + g_assert_not_reached(); | ||
| 76 | } | ||
| 77 | |||
| 78 | bool write_list_to_kvmstate(ARMCPU *cpu, int level) | ||
| 79 | { | ||
| 80 | - abort(); | ||
| 81 | + g_assert_not_reached(); | ||
| 82 | } | ||
| 83 | diff --git a/target/arm/kvm.c b/target/arm/kvm.c | ||
| 84 | index XXXXXXX..XXXXXXX 100644 | ||
| 85 | --- a/target/arm/kvm.c | ||
| 86 | +++ b/target/arm/kvm.c | ||
| 87 | @@ -XXX,XX +XXX,XX @@ bool write_kvmstate_to_list(ARMCPU *cpu) | ||
| 88 | ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r); | ||
| 89 | break; | ||
| 90 | default: | ||
| 91 | - abort(); | ||
| 92 | + g_assert_not_reached(); | ||
| 93 | } | ||
| 94 | if (ret) { | ||
| 95 | ok = false; | ||
| 96 | @@ -XXX,XX +XXX,XX @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level) | ||
| 97 | r.addr = (uintptr_t)(cpu->cpreg_values + i); | ||
| 98 | break; | ||
| 99 | default: | ||
| 100 | - abort(); | ||
| 101 | + g_assert_not_reached(); | ||
| 102 | } | ||
| 103 | ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r); | ||
| 104 | if (ret) { | ||
| 105 | diff --git a/target/arm/machine.c b/target/arm/machine.c | ||
| 106 | index XXXXXXX..XXXXXXX 100644 | ||
| 107 | --- a/target/arm/machine.c | ||
| 108 | +++ b/target/arm/machine.c | ||
| 109 | @@ -XXX,XX +XXX,XX @@ static int cpu_pre_save(void *opaque) | ||
| 110 | if (kvm_enabled()) { | ||
| 111 | if (!write_kvmstate_to_list(cpu)) { | ||
| 112 | /* This should never fail */ | ||
| 113 | - abort(); | ||
| 114 | + g_assert_not_reached(); | ||
| 115 | } | ||
| 116 | |||
| 117 | /* | ||
| 118 | @@ -XXX,XX +XXX,XX @@ static int cpu_pre_save(void *opaque) | ||
| 119 | } else { | ||
| 120 | if (!write_cpustate_to_list(cpu, false)) { | ||
| 121 | /* This should never fail. */ | ||
| 122 | - abort(); | ||
| 123 | + g_assert_not_reached(); | ||
| 124 | } | ||
| 125 | } | ||
| 126 | |||
| 127 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
| 128 | index XXXXXXX..XXXXXXX 100644 | ||
| 129 | --- a/target/arm/translate-a64.c | ||
| 130 | +++ b/target/arm/translate-a64.c | ||
| 131 | @@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn) | ||
| 132 | gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst); | ||
| 133 | break; | ||
| 134 | default: | ||
| 135 | - abort(); | ||
| 136 | + g_assert_not_reached(); | ||
| 137 | } | ||
| 138 | |||
| 139 | write_fp_sreg(s, rd, tcg_res); | ||
| 140 | @@ -XXX,XX +XXX,XX @@ static void handle_fp_fcvt(DisasContext *s, int opcode, | ||
| 141 | break; | ||
| 142 | } | ||
| 143 | default: | ||
| 144 | - abort(); | ||
| 145 | + g_assert_not_reached(); | ||
| 146 | } | ||
| 147 | } | ||
| 148 | |||
| 149 | diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c | ||
| 150 | index XXXXXXX..XXXXXXX 100644 | ||
| 151 | --- a/target/arm/translate-neon.c | ||
| 152 | +++ b/target/arm/translate-neon.c | ||
| 153 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a) | ||
| 154 | } | ||
| 155 | break; | ||
| 156 | default: | ||
| 157 | - abort(); | ||
| 158 | + g_assert_not_reached(); | ||
| 159 | } | ||
| 160 | if ((vd + a->stride * (nregs - 1)) > 31) { | ||
| 161 | /* | ||
| 19 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 162 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
| 20 | index XXXXXXX..XXXXXXX 100644 | 163 | index XXXXXXX..XXXXXXX 100644 |
| 21 | --- a/target/arm/translate.c | 164 | --- a/target/arm/translate.c |
| 22 | +++ b/target/arm/translate.c | 165 | +++ b/target/arm/translate.c |
| 23 | @@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw | 166 | @@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s, |
| 24 | int conds; | 167 | offset = 4; |
| 25 | int logic_cc; | 168 | break; |
| 26 | 169 | default: | |
| 27 | - if (!(arm_dc_feature(s, ARM_FEATURE_THUMB2) | 170 | - abort(); |
| 28 | - || arm_dc_feature(s, ARM_FEATURE_M))) { | 171 | + g_assert_not_reached(); |
| 29 | + if (!arm_dc_feature(s, ARM_FEATURE_THUMB2)) { | 172 | } |
| 30 | /* Thumb-1 cores may need to treat bl and blx as a pair of | 173 | tcg_gen_addi_i32(addr, addr, offset); |
| 31 | 16-bit instructions to get correct prefetch abort behavior. */ | 174 | tmp = load_reg(s, 14); |
| 32 | insn = insn_hw1; | 175 | @@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s, |
| 176 | offset = 0; | ||
| 177 | break; | ||
| 178 | default: | ||
| 179 | - abort(); | ||
| 180 | + g_assert_not_reached(); | ||
| 181 | } | ||
| 182 | tcg_gen_addi_i32(addr, addr, offset); | ||
| 183 | gen_helper_set_r13_banked(cpu_env, tcg_constant_i32(mode), addr); | ||
| 33 | -- | 184 | -- |
| 34 | 2.7.4 | 185 | 2.25.1 |
| 35 | |||
| 36 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 1 | 2 | ||
| 3 | Create a typedef as well, and use it in ARMCPRegInfo. | ||
| 4 | This won't be perfect for debugging, but it'll nicely | ||
| 5 | display the most common cases. | ||
| 6 | |||
| 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 9 | Message-id: 20220501055028.646596-8-richard.henderson@linaro.org | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 11 | --- | ||
| 12 | target/arm/cpregs.h | 44 +++++++++++++++++++++++--------------------- | ||
| 13 | target/arm/helper.c | 2 +- | ||
| 14 | 2 files changed, 24 insertions(+), 22 deletions(-) | ||
| 15 | |||
| 16 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/target/arm/cpregs.h | ||
| 19 | +++ b/target/arm/cpregs.h | ||
| 20 | @@ -XXX,XX +XXX,XX @@ enum { | ||
| 21 | * described with these bits, then use a laxer set of restrictions, and | ||
| 22 | * do the more restrictive/complex check inside a helper function. | ||
| 23 | */ | ||
| 24 | -#define PL3_R 0x80 | ||
| 25 | -#define PL3_W 0x40 | ||
| 26 | -#define PL2_R (0x20 | PL3_R) | ||
| 27 | -#define PL2_W (0x10 | PL3_W) | ||
| 28 | -#define PL1_R (0x08 | PL2_R) | ||
| 29 | -#define PL1_W (0x04 | PL2_W) | ||
| 30 | -#define PL0_R (0x02 | PL1_R) | ||
| 31 | -#define PL0_W (0x01 | PL1_W) | ||
| 32 | +typedef enum { | ||
| 33 | + PL3_R = 0x80, | ||
| 34 | + PL3_W = 0x40, | ||
| 35 | + PL2_R = 0x20 | PL3_R, | ||
| 36 | + PL2_W = 0x10 | PL3_W, | ||
| 37 | + PL1_R = 0x08 | PL2_R, | ||
| 38 | + PL1_W = 0x04 | PL2_W, | ||
| 39 | + PL0_R = 0x02 | PL1_R, | ||
| 40 | + PL0_W = 0x01 | PL1_W, | ||
| 41 | |||
| 42 | -/* | ||
| 43 | - * For user-mode some registers are accessible to EL0 via a kernel | ||
| 44 | - * trap-and-emulate ABI. In this case we define the read permissions | ||
| 45 | - * as actually being PL0_R. However some bits of any given register | ||
| 46 | - * may still be masked. | ||
| 47 | - */ | ||
| 48 | + /* | ||
| 49 | + * For user-mode some registers are accessible to EL0 via a kernel | ||
| 50 | + * trap-and-emulate ABI. In this case we define the read permissions | ||
| 51 | + * as actually being PL0_R. However some bits of any given register | ||
| 52 | + * may still be masked. | ||
| 53 | + */ | ||
| 54 | #ifdef CONFIG_USER_ONLY | ||
| 55 | -#define PL0U_R PL0_R | ||
| 56 | + PL0U_R = PL0_R, | ||
| 57 | #else | ||
| 58 | -#define PL0U_R PL1_R | ||
| 59 | + PL0U_R = PL1_R, | ||
| 60 | #endif | ||
| 61 | |||
| 62 | -#define PL3_RW (PL3_R | PL3_W) | ||
| 63 | -#define PL2_RW (PL2_R | PL2_W) | ||
| 64 | -#define PL1_RW (PL1_R | PL1_W) | ||
| 65 | -#define PL0_RW (PL0_R | PL0_W) | ||
| 66 | + PL3_RW = PL3_R | PL3_W, | ||
| 67 | + PL2_RW = PL2_R | PL2_W, | ||
| 68 | + PL1_RW = PL1_R | PL1_W, | ||
| 69 | + PL0_RW = PL0_R | PL0_W, | ||
| 70 | +} CPAccessRights; | ||
| 71 | |||
| 72 | typedef enum CPAccessResult { | ||
| 73 | /* Access is permitted */ | ||
| 74 | @@ -XXX,XX +XXX,XX @@ struct ARMCPRegInfo { | ||
| 75 | /* Register type: ARM_CP_* bits/values */ | ||
| 76 | int type; | ||
| 77 | /* Access rights: PL*_[RW] */ | ||
| 78 | - int access; | ||
| 79 | + CPAccessRights access; | ||
| 80 | /* Security state: ARM_CP_SECSTATE_* bits/values */ | ||
| 81 | int secure; | ||
| 82 | /* | ||
| 83 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
| 84 | index XXXXXXX..XXXXXXX 100644 | ||
| 85 | --- a/target/arm/helper.c | ||
| 86 | +++ b/target/arm/helper.c | ||
| 87 | @@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, | ||
| 88 | * to encompass the generic architectural permission check. | ||
| 89 | */ | ||
| 90 | if (r->state != ARM_CP_STATE_AA32) { | ||
| 91 | - int mask = 0; | ||
| 92 | + CPAccessRights mask; | ||
| 93 | switch (r->opc1) { | ||
| 94 | case 0: | ||
| 95 | /* min_EL EL1, but some accessible to EL0 via kernel ABI */ | ||
| 96 | -- | ||
| 97 | 2.25.1 | diff view generated by jsdifflib |
| 1 | Coverity points out that we forgot the 'break' for | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | the SAU_CTRL write case (CID1381683). This has | ||
| 3 | no actual visible consequences because it happens | ||
| 4 | that the following case is effectively a no-op. | ||
| 5 | 2 | ||
| 3 | Give this enum a name and use in ARMCPRegInfo, | ||
| 4 | add_cpreg_to_hashtable and define_one_arm_cp_reg_with_opaque. | ||
| 5 | |||
| 6 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
| 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 9 | Message-id: 20220501055028.646596-9-richard.henderson@linaro.org | ||
| 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 8 | Message-id: 1507742676-9908-1-git-send-email-peter.maydell@linaro.org | ||
| 9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 10 | --- | 11 | --- |
| 11 | hw/intc/armv7m_nvic.c | 1 + | 12 | target/arm/cpregs.h | 6 +++--- |
| 12 | 1 file changed, 1 insertion(+) | 13 | target/arm/helper.c | 6 ++++-- |
| 14 | 2 files changed, 7 insertions(+), 5 deletions(-) | ||
| 13 | 15 | ||
| 14 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | 16 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h |
| 15 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
| 16 | --- a/hw/intc/armv7m_nvic.c | 18 | --- a/target/arm/cpregs.h |
| 17 | +++ b/hw/intc/armv7m_nvic.c | 19 | +++ b/target/arm/cpregs.h |
| 18 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | 20 | @@ -XXX,XX +XXX,XX @@ enum { |
| 19 | return; | 21 | * Note that we rely on the values of these enums as we iterate through |
| 20 | } | 22 | * the various states in some places. |
| 21 | cpu->env.sau.ctrl = value & 3; | 23 | */ |
| 22 | + break; | 24 | -enum { |
| 23 | case 0xdd4: /* SAU_TYPE */ | 25 | +typedef enum { |
| 24 | if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { | 26 | ARM_CP_STATE_AA32 = 0, |
| 25 | goto bad_offset; | 27 | ARM_CP_STATE_AA64 = 1, |
| 28 | ARM_CP_STATE_BOTH = 2, | ||
| 29 | -}; | ||
| 30 | +} CPState; | ||
| 31 | |||
| 32 | /* | ||
| 33 | * ARM CP register secure state flags. These flags identify security state | ||
| 34 | @@ -XXX,XX +XXX,XX @@ struct ARMCPRegInfo { | ||
| 35 | uint8_t opc1; | ||
| 36 | uint8_t opc2; | ||
| 37 | /* Execution state in which this register is visible: ARM_CP_STATE_* */ | ||
| 38 | - int state; | ||
| 39 | + CPState state; | ||
| 40 | /* Register type: ARM_CP_* bits/values */ | ||
| 41 | int type; | ||
| 42 | /* Access rights: PL*_[RW] */ | ||
| 43 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
| 44 | index XXXXXXX..XXXXXXX 100644 | ||
| 45 | --- a/target/arm/helper.c | ||
| 46 | +++ b/target/arm/helper.c | ||
| 47 | @@ -XXX,XX +XXX,XX @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) | ||
| 48 | } | ||
| 49 | |||
| 50 | static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
| 51 | - void *opaque, int state, int secstate, | ||
| 52 | + void *opaque, CPState state, int secstate, | ||
| 53 | int crm, int opc1, int opc2, | ||
| 54 | const char *name) | ||
| 55 | { | ||
| 56 | @@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, | ||
| 57 | * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of | ||
| 58 | * the register, if any. | ||
| 59 | */ | ||
| 60 | - int crm, opc1, opc2, state; | ||
| 61 | + int crm, opc1, opc2; | ||
| 62 | int crmmin = (r->crm == CP_ANY) ? 0 : r->crm; | ||
| 63 | int crmmax = (r->crm == CP_ANY) ? 15 : r->crm; | ||
| 64 | int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1; | ||
| 65 | int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1; | ||
| 66 | int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2; | ||
| 67 | int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2; | ||
| 68 | + CPState state; | ||
| 69 | + | ||
| 70 | /* 64 bit registers have only CRm and Opc1 fields */ | ||
| 71 | assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); | ||
| 72 | /* op0 only exists in the AArch64 encodings */ | ||
| 26 | -- | 73 | -- |
| 27 | 2.7.4 | 74 | 2.25.1 |
| 28 | 75 | ||
| 29 | 76 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 1 | 2 | ||
| 3 | Give this enum a name and use in ARMCPRegInfo and add_cpreg_to_hashtable. | ||
| 4 | Add the enumerator ARM_CP_SECSTATE_BOTH to clarify how 0 | ||
| 5 | is handled in define_one_arm_cp_reg_with_opaque. | ||
| 6 | |||
| 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 9 | Message-id: 20220501055028.646596-10-richard.henderson@linaro.org | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 11 | --- | ||
| 12 | target/arm/cpregs.h | 7 ++++--- | ||
| 13 | target/arm/helper.c | 7 +++++-- | ||
| 14 | 2 files changed, 9 insertions(+), 5 deletions(-) | ||
| 15 | |||
| 16 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/target/arm/cpregs.h | ||
| 19 | +++ b/target/arm/cpregs.h | ||
| 20 | @@ -XXX,XX +XXX,XX @@ typedef enum { | ||
| 21 | * registered entry will only have one to identify whether the entry is secure | ||
| 22 | * or non-secure. | ||
| 23 | */ | ||
| 24 | -enum { | ||
| 25 | +typedef enum { | ||
| 26 | + ARM_CP_SECSTATE_BOTH = 0, /* define one cpreg for each secstate */ | ||
| 27 | ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ | ||
| 28 | ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ | ||
| 29 | -}; | ||
| 30 | +} CPSecureState; | ||
| 31 | |||
| 32 | /* | ||
| 33 | * Access rights: | ||
| 34 | @@ -XXX,XX +XXX,XX @@ struct ARMCPRegInfo { | ||
| 35 | /* Access rights: PL*_[RW] */ | ||
| 36 | CPAccessRights access; | ||
| 37 | /* Security state: ARM_CP_SECSTATE_* bits/values */ | ||
| 38 | - int secure; | ||
| 39 | + CPSecureState secure; | ||
| 40 | /* | ||
| 41 | * The opaque pointer passed to define_arm_cp_regs_with_opaque() when | ||
| 42 | * this register was defined: can be used to hand data through to the | ||
| 43 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
| 44 | index XXXXXXX..XXXXXXX 100644 | ||
| 45 | --- a/target/arm/helper.c | ||
| 46 | +++ b/target/arm/helper.c | ||
| 47 | @@ -XXX,XX +XXX,XX @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) | ||
| 48 | } | ||
| 49 | |||
| 50 | static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
| 51 | - void *opaque, CPState state, int secstate, | ||
| 52 | + void *opaque, CPState state, | ||
| 53 | + CPSecureState secstate, | ||
| 54 | int crm, int opc1, int opc2, | ||
| 55 | const char *name) | ||
| 56 | { | ||
| 57 | @@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, | ||
| 58 | r->secure, crm, opc1, opc2, | ||
| 59 | r->name); | ||
| 60 | break; | ||
| 61 | - default: | ||
| 62 | + case ARM_CP_SECSTATE_BOTH: | ||
| 63 | name = g_strdup_printf("%s_S", r->name); | ||
| 64 | add_cpreg_to_hashtable(cpu, r, opaque, state, | ||
| 65 | ARM_CP_SECSTATE_S, | ||
| 66 | @@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, | ||
| 67 | ARM_CP_SECSTATE_NS, | ||
| 68 | crm, opc1, opc2, r->name); | ||
| 69 | break; | ||
| 70 | + default: | ||
| 71 | + g_assert_not_reached(); | ||
| 72 | } | ||
| 73 | } else { | ||
| 74 | /* AArch64 registers get mapped to non-secure instance | ||
| 75 | -- | ||
| 76 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 1 | 2 | ||
| 3 | The new_key field is always non-zero -- drop the if. | ||
| 4 | |||
| 5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 7 | Message-id: 20220501055028.646596-11-richard.henderson@linaro.org | ||
| 8 | [PMM: reinstated dropped PL3_RW mask] | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/helper.c | 23 +++++++++++------------ | ||
| 12 | 1 file changed, 11 insertions(+), 12 deletions(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/helper.c | ||
| 17 | +++ b/target/arm/helper.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) | ||
| 19 | |||
| 20 | for (i = 0; i < ARRAY_SIZE(aliases); i++) { | ||
| 21 | const struct E2HAlias *a = &aliases[i]; | ||
| 22 | - ARMCPRegInfo *src_reg, *dst_reg; | ||
| 23 | + ARMCPRegInfo *src_reg, *dst_reg, *new_reg; | ||
| 24 | + uint32_t *new_key; | ||
| 25 | + bool ok; | ||
| 26 | |||
| 27 | if (a->feature && !a->feature(&cpu->isar)) { | ||
| 28 | continue; | ||
| 29 | @@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) | ||
| 30 | g_assert(src_reg->opaque == NULL); | ||
| 31 | |||
| 32 | /* Create alias before redirection so we dup the right data. */ | ||
| 33 | - if (a->new_key) { | ||
| 34 | - ARMCPRegInfo *new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo)); | ||
| 35 | - uint32_t *new_key = g_memdup(&a->new_key, sizeof(uint32_t)); | ||
| 36 | - bool ok; | ||
| 37 | + new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo)); | ||
| 38 | + new_key = g_memdup(&a->new_key, sizeof(uint32_t)); | ||
| 39 | |||
| 40 | - new_reg->name = a->new_name; | ||
| 41 | - new_reg->type |= ARM_CP_ALIAS; | ||
| 42 | - /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */ | ||
| 43 | - new_reg->access &= PL2_RW | PL3_RW; | ||
| 44 | + new_reg->name = a->new_name; | ||
| 45 | + new_reg->type |= ARM_CP_ALIAS; | ||
| 46 | + /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */ | ||
| 47 | + new_reg->access &= PL2_RW | PL3_RW; | ||
| 48 | |||
| 49 | - ok = g_hash_table_insert(cpu->cp_regs, new_key, new_reg); | ||
| 50 | - g_assert(ok); | ||
| 51 | - } | ||
| 52 | + ok = g_hash_table_insert(cpu->cp_regs, new_key, new_reg); | ||
| 53 | + g_assert(ok); | ||
| 54 | |||
| 55 | src_reg->opaque = dst_reg; | ||
| 56 | src_reg->orig_readfn = src_reg->readfn ?: raw_read; | ||
| 57 | -- | ||
| 58 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 1 | 2 | ||
| 3 | Cast the uint32_t key into a gpointer directly, which | ||
| 4 | allows us to avoid allocating storage for each key. | ||
| 5 | |||
| 6 | Use g_hash_table_lookup when we already have a gpointer | ||
| 7 | (e.g. for callbacks like count_cpreg), or when using | ||
| 8 | get_arm_cp_reginfo would require casting away const. | ||
| 9 | |||
| 10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 12 | Message-id: 20220501055028.646596-12-richard.henderson@linaro.org | ||
| 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 14 | --- | ||
| 15 | target/arm/cpu.c | 4 ++-- | ||
| 16 | target/arm/gdbstub.c | 2 +- | ||
| 17 | target/arm/helper.c | 41 ++++++++++++++++++----------------------- | ||
| 18 | 3 files changed, 21 insertions(+), 26 deletions(-) | ||
| 19 | |||
| 20 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
| 21 | index XXXXXXX..XXXXXXX 100644 | ||
| 22 | --- a/target/arm/cpu.c | ||
| 23 | +++ b/target/arm/cpu.c | ||
| 24 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_initfn(Object *obj) | ||
| 25 | ARMCPU *cpu = ARM_CPU(obj); | ||
| 26 | |||
| 27 | cpu_set_cpustate_pointers(cpu); | ||
| 28 | - cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, | ||
| 29 | - g_free, cpreg_hashtable_data_destroy); | ||
| 30 | + cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal, | ||
| 31 | + NULL, cpreg_hashtable_data_destroy); | ||
| 32 | |||
| 33 | QLIST_INIT(&cpu->pre_el_change_hooks); | ||
| 34 | QLIST_INIT(&cpu->el_change_hooks); | ||
| 35 | diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c | ||
| 36 | index XXXXXXX..XXXXXXX 100644 | ||
| 37 | --- a/target/arm/gdbstub.c | ||
| 38 | +++ b/target/arm/gdbstub.c | ||
| 39 | @@ -XXX,XX +XXX,XX @@ static void arm_gen_one_xml_sysreg_tag(GString *s, DynamicGDBXMLInfo *dyn_xml, | ||
| 40 | static void arm_register_sysreg_for_xml(gpointer key, gpointer value, | ||
| 41 | gpointer p) | ||
| 42 | { | ||
| 43 | - uint32_t ri_key = *(uint32_t *)key; | ||
| 44 | + uint32_t ri_key = (uintptr_t)key; | ||
| 45 | ARMCPRegInfo *ri = value; | ||
| 46 | RegisterSysregXmlParam *param = (RegisterSysregXmlParam *)p; | ||
| 47 | GString *s = param->s; | ||
| 48 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
| 49 | index XXXXXXX..XXXXXXX 100644 | ||
| 50 | --- a/target/arm/helper.c | ||
| 51 | +++ b/target/arm/helper.c | ||
| 52 | @@ -XXX,XX +XXX,XX @@ bool write_list_to_cpustate(ARMCPU *cpu) | ||
| 53 | static void add_cpreg_to_list(gpointer key, gpointer opaque) | ||
| 54 | { | ||
| 55 | ARMCPU *cpu = opaque; | ||
| 56 | - uint64_t regidx; | ||
| 57 | - const ARMCPRegInfo *ri; | ||
| 58 | - | ||
| 59 | - regidx = *(uint32_t *)key; | ||
| 60 | - ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); | ||
| 61 | + uint32_t regidx = (uintptr_t)key; | ||
| 62 | + const ARMCPRegInfo *ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); | ||
| 63 | |||
| 64 | if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { | ||
| 65 | cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx); | ||
| 66 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_list(gpointer key, gpointer opaque) | ||
| 67 | static void count_cpreg(gpointer key, gpointer opaque) | ||
| 68 | { | ||
| 69 | ARMCPU *cpu = opaque; | ||
| 70 | - uint64_t regidx; | ||
| 71 | const ARMCPRegInfo *ri; | ||
| 72 | |||
| 73 | - regidx = *(uint32_t *)key; | ||
| 74 | - ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); | ||
| 75 | + ri = g_hash_table_lookup(cpu->cp_regs, key); | ||
| 76 | |||
| 77 | if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { | ||
| 78 | cpu->cpreg_array_len++; | ||
| 79 | @@ -XXX,XX +XXX,XX @@ static void count_cpreg(gpointer key, gpointer opaque) | ||
| 80 | |||
| 81 | static gint cpreg_key_compare(gconstpointer a, gconstpointer b) | ||
| 82 | { | ||
| 83 | - uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a); | ||
| 84 | - uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b); | ||
| 85 | + uint64_t aidx = cpreg_to_kvm_id((uintptr_t)a); | ||
| 86 | + uint64_t bidx = cpreg_to_kvm_id((uintptr_t)b); | ||
| 87 | |||
| 88 | if (aidx > bidx) { | ||
| 89 | return 1; | ||
| 90 | @@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) | ||
| 91 | for (i = 0; i < ARRAY_SIZE(aliases); i++) { | ||
| 92 | const struct E2HAlias *a = &aliases[i]; | ||
| 93 | ARMCPRegInfo *src_reg, *dst_reg, *new_reg; | ||
| 94 | - uint32_t *new_key; | ||
| 95 | bool ok; | ||
| 96 | |||
| 97 | if (a->feature && !a->feature(&cpu->isar)) { | ||
| 98 | continue; | ||
| 99 | } | ||
| 100 | |||
| 101 | - src_reg = g_hash_table_lookup(cpu->cp_regs, &a->src_key); | ||
| 102 | - dst_reg = g_hash_table_lookup(cpu->cp_regs, &a->dst_key); | ||
| 103 | + src_reg = g_hash_table_lookup(cpu->cp_regs, | ||
| 104 | + (gpointer)(uintptr_t)a->src_key); | ||
| 105 | + dst_reg = g_hash_table_lookup(cpu->cp_regs, | ||
| 106 | + (gpointer)(uintptr_t)a->dst_key); | ||
| 107 | g_assert(src_reg != NULL); | ||
| 108 | g_assert(dst_reg != NULL); | ||
| 109 | |||
| 110 | @@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) | ||
| 111 | |||
| 112 | /* Create alias before redirection so we dup the right data. */ | ||
| 113 | new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo)); | ||
| 114 | - new_key = g_memdup(&a->new_key, sizeof(uint32_t)); | ||
| 115 | |||
| 116 | new_reg->name = a->new_name; | ||
| 117 | new_reg->type |= ARM_CP_ALIAS; | ||
| 118 | /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */ | ||
| 119 | new_reg->access &= PL2_RW | PL3_RW; | ||
| 120 | |||
| 121 | - ok = g_hash_table_insert(cpu->cp_regs, new_key, new_reg); | ||
| 122 | + ok = g_hash_table_insert(cpu->cp_regs, | ||
| 123 | + (gpointer)(uintptr_t)a->new_key, new_reg); | ||
| 124 | g_assert(ok); | ||
| 125 | |||
| 126 | src_reg->opaque = dst_reg; | ||
| 127 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
| 128 | /* Private utility function for define_one_arm_cp_reg_with_opaque(): | ||
| 129 | * add a single reginfo struct to the hash table. | ||
| 130 | */ | ||
| 131 | - uint32_t *key = g_new(uint32_t, 1); | ||
| 132 | + uint32_t key; | ||
| 133 | ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo)); | ||
| 134 | int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0; | ||
| 135 | int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; | ||
| 136 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
| 137 | if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) { | ||
| 138 | r2->cp = CP_REG_ARM64_SYSREG_CP; | ||
| 139 | } | ||
| 140 | - *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, | ||
| 141 | - r2->opc0, opc1, opc2); | ||
| 142 | + key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, | ||
| 143 | + r2->opc0, opc1, opc2); | ||
| 144 | } else { | ||
| 145 | - *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2); | ||
| 146 | + key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2); | ||
| 147 | } | ||
| 148 | if (opaque) { | ||
| 149 | r2->opaque = opaque; | ||
| 150 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
| 151 | * requested. | ||
| 152 | */ | ||
| 153 | if (!(r->type & ARM_CP_OVERRIDE)) { | ||
| 154 | - ARMCPRegInfo *oldreg; | ||
| 155 | - oldreg = g_hash_table_lookup(cpu->cp_regs, key); | ||
| 156 | + const ARMCPRegInfo *oldreg = get_arm_cp_reginfo(cpu->cp_regs, key); | ||
| 157 | if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) { | ||
| 158 | fprintf(stderr, "Register redefined: cp=%d %d bit " | ||
| 159 | "crn=%d crm=%d opc1=%d opc2=%d, " | ||
| 160 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
| 161 | g_assert_not_reached(); | ||
| 162 | } | ||
| 163 | } | ||
| 164 | - g_hash_table_insert(cpu->cp_regs, key, r2); | ||
| 165 | + g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r2); | ||
| 166 | } | ||
| 167 | |||
| 168 | |||
| 169 | @@ -XXX,XX +XXX,XX @@ void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len, | ||
| 170 | |||
| 171 | const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp) | ||
| 172 | { | ||
| 173 | - return g_hash_table_lookup(cpregs, &encoded_cp); | ||
| 174 | + return g_hash_table_lookup(cpregs, (gpointer)(uintptr_t)encoded_cp); | ||
| 175 | } | ||
| 176 | |||
| 177 | void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 178 | -- | ||
| 179 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 1 | 2 | ||
| 3 | Simplify freeing cp_regs hash table entries by using a single | ||
| 4 | allocation for the entire value. | ||
| 5 | |||
| 6 | This fixes a theoretical bug if we were to ever free the entire | ||
| 7 | hash table, because we've been installing string literal constants | ||
| 8 | into the cpreg structure in define_arm_vh_e2h_redirects_aliases. | ||
| 9 | However, at present we only free entries created for AArch32 | ||
| 10 | wildcard cpregs which get overwritten by more specific cpregs, | ||
| 11 | so this bug is never exposed. | ||
| 12 | |||
| 13 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 14 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 15 | Message-id: 20220501055028.646596-13-richard.henderson@linaro.org | ||
| 16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 17 | --- | ||
| 18 | target/arm/cpu.c | 16 +--------------- | ||
| 19 | target/arm/helper.c | 10 ++++++++-- | ||
| 20 | 2 files changed, 9 insertions(+), 17 deletions(-) | ||
| 21 | |||
| 22 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
| 23 | index XXXXXXX..XXXXXXX 100644 | ||
| 24 | --- a/target/arm/cpu.c | ||
| 25 | +++ b/target/arm/cpu.c | ||
| 26 | @@ -XXX,XX +XXX,XX @@ uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) | ||
| 27 | return (Aff1 << ARM_AFF1_SHIFT) | Aff0; | ||
| 28 | } | ||
| 29 | |||
| 30 | -static void cpreg_hashtable_data_destroy(gpointer data) | ||
| 31 | -{ | ||
| 32 | - /* | ||
| 33 | - * Destroy function for cpu->cp_regs hashtable data entries. | ||
| 34 | - * We must free the name string because it was g_strdup()ed in | ||
| 35 | - * add_cpreg_to_hashtable(). It's OK to cast away the 'const' | ||
| 36 | - * from r->name because we know we definitely allocated it. | ||
| 37 | - */ | ||
| 38 | - ARMCPRegInfo *r = data; | ||
| 39 | - | ||
| 40 | - g_free((void *)r->name); | ||
| 41 | - g_free(r); | ||
| 42 | -} | ||
| 43 | - | ||
| 44 | static void arm_cpu_initfn(Object *obj) | ||
| 45 | { | ||
| 46 | ARMCPU *cpu = ARM_CPU(obj); | ||
| 47 | |||
| 48 | cpu_set_cpustate_pointers(cpu); | ||
| 49 | cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal, | ||
| 50 | - NULL, cpreg_hashtable_data_destroy); | ||
| 51 | + NULL, g_free); | ||
| 52 | |||
| 53 | QLIST_INIT(&cpu->pre_el_change_hooks); | ||
| 54 | QLIST_INIT(&cpu->el_change_hooks); | ||
| 55 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
| 56 | index XXXXXXX..XXXXXXX 100644 | ||
| 57 | --- a/target/arm/helper.c | ||
| 58 | +++ b/target/arm/helper.c | ||
| 59 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
| 60 | * add a single reginfo struct to the hash table. | ||
| 61 | */ | ||
| 62 | uint32_t key; | ||
| 63 | - ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo)); | ||
| 64 | + ARMCPRegInfo *r2; | ||
| 65 | int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0; | ||
| 66 | int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; | ||
| 67 | + size_t name_len; | ||
| 68 | + | ||
| 69 | + /* Combine cpreg and name into one allocation. */ | ||
| 70 | + name_len = strlen(name) + 1; | ||
| 71 | + r2 = g_malloc(sizeof(*r2) + name_len); | ||
| 72 | + *r2 = *r; | ||
| 73 | + r2->name = memcpy(r2 + 1, name, name_len); | ||
| 74 | |||
| 75 | - r2->name = g_strdup(name); | ||
| 76 | /* Reset the secure state to the specific incoming state. This is | ||
| 77 | * necessary as the register may have been defined with both states. | ||
| 78 | */ | ||
| 79 | -- | ||
| 80 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 1 | 2 | ||
| 3 | Move the computation of key to the top of the function. | ||
| 4 | Hoist the resolution of cp as well, as an input to the | ||
| 5 | computation of key. | ||
| 6 | |||
| 7 | This will be required by a subsequent patch. | ||
| 8 | |||
| 9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 11 | Message-id: 20220501055028.646596-14-richard.henderson@linaro.org | ||
| 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 13 | --- | ||
| 14 | target/arm/helper.c | 49 +++++++++++++++++++++++++-------------------- | ||
| 15 | 1 file changed, 27 insertions(+), 22 deletions(-) | ||
| 16 | |||
| 17 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
| 18 | index XXXXXXX..XXXXXXX 100644 | ||
| 19 | --- a/target/arm/helper.c | ||
| 20 | +++ b/target/arm/helper.c | ||
| 21 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
| 22 | ARMCPRegInfo *r2; | ||
| 23 | int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0; | ||
| 24 | int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; | ||
| 25 | + int cp = r->cp; | ||
| 26 | size_t name_len; | ||
| 27 | |||
| 28 | + switch (state) { | ||
| 29 | + case ARM_CP_STATE_AA32: | ||
| 30 | + /* We assume it is a cp15 register if the .cp field is left unset. */ | ||
| 31 | + if (cp == 0 && r->state == ARM_CP_STATE_BOTH) { | ||
| 32 | + cp = 15; | ||
| 33 | + } | ||
| 34 | + key = ENCODE_CP_REG(cp, is64, ns, r->crn, crm, opc1, opc2); | ||
| 35 | + break; | ||
| 36 | + case ARM_CP_STATE_AA64: | ||
| 37 | + /* | ||
| 38 | + * To allow abbreviation of ARMCPRegInfo definitions, we treat | ||
| 39 | + * cp == 0 as equivalent to the value for "standard guest-visible | ||
| 40 | + * sysreg". STATE_BOTH definitions are also always "standard sysreg" | ||
| 41 | + * in their AArch64 view (the .cp value may be non-zero for the | ||
| 42 | + * benefit of the AArch32 view). | ||
| 43 | + */ | ||
| 44 | + if (cp == 0 || r->state == ARM_CP_STATE_BOTH) { | ||
| 45 | + cp = CP_REG_ARM64_SYSREG_CP; | ||
| 46 | + } | ||
| 47 | + key = ENCODE_AA64_CP_REG(cp, r->crn, crm, r->opc0, opc1, opc2); | ||
| 48 | + break; | ||
| 49 | + default: | ||
| 50 | + g_assert_not_reached(); | ||
| 51 | + } | ||
| 52 | + | ||
| 53 | /* Combine cpreg and name into one allocation. */ | ||
| 54 | name_len = strlen(name) + 1; | ||
| 55 | r2 = g_malloc(sizeof(*r2) + name_len); | ||
| 56 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
| 57 | } | ||
| 58 | |||
| 59 | if (r->state == ARM_CP_STATE_BOTH) { | ||
| 60 | - /* We assume it is a cp15 register if the .cp field is left unset. | ||
| 61 | - */ | ||
| 62 | - if (r2->cp == 0) { | ||
| 63 | - r2->cp = 15; | ||
| 64 | - } | ||
| 65 | - | ||
| 66 | #if HOST_BIG_ENDIAN | ||
| 67 | if (r2->fieldoffset) { | ||
| 68 | r2->fieldoffset += sizeof(uint32_t); | ||
| 69 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
| 70 | #endif | ||
| 71 | } | ||
| 72 | } | ||
| 73 | - if (state == ARM_CP_STATE_AA64) { | ||
| 74 | - /* To allow abbreviation of ARMCPRegInfo | ||
| 75 | - * definitions, we treat cp == 0 as equivalent to | ||
| 76 | - * the value for "standard guest-visible sysreg". | ||
| 77 | - * STATE_BOTH definitions are also always "standard | ||
| 78 | - * sysreg" in their AArch64 view (the .cp value may | ||
| 79 | - * be non-zero for the benefit of the AArch32 view). | ||
| 80 | - */ | ||
| 81 | - if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) { | ||
| 82 | - r2->cp = CP_REG_ARM64_SYSREG_CP; | ||
| 83 | - } | ||
| 84 | - key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, | ||
| 85 | - r2->opc0, opc1, opc2); | ||
| 86 | - } else { | ||
| 87 | - key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2); | ||
| 88 | - } | ||
| 89 | if (opaque) { | ||
| 90 | r2->opaque = opaque; | ||
| 91 | } | ||
| 92 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
| 93 | /* Make sure reginfo passed to helpers for wildcarded regs | ||
| 94 | * has the correct crm/opc1/opc2 for this reg, not CP_ANY: | ||
| 95 | */ | ||
| 96 | + r2->cp = cp; | ||
| 97 | r2->crm = crm; | ||
| 98 | r2->opc1 = opc1; | ||
| 99 | r2->opc2 = opc2; | ||
| 100 | -- | ||
| 101 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 1 | 2 | ||
| 3 | Put most of the value writeback to the same place, | ||
| 4 | and improve the comment that goes with them. | ||
| 5 | |||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Message-id: 20220501055028.646596-15-richard.henderson@linaro.org | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/helper.c | 28 ++++++++++++---------------- | ||
| 12 | 1 file changed, 12 insertions(+), 16 deletions(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/helper.c | ||
| 17 | +++ b/target/arm/helper.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
| 19 | *r2 = *r; | ||
| 20 | r2->name = memcpy(r2 + 1, name, name_len); | ||
| 21 | |||
| 22 | - /* Reset the secure state to the specific incoming state. This is | ||
| 23 | - * necessary as the register may have been defined with both states. | ||
| 24 | + /* | ||
| 25 | + * Update fields to match the instantiation, overwiting wildcards | ||
| 26 | + * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH. | ||
| 27 | */ | ||
| 28 | + r2->cp = cp; | ||
| 29 | + r2->crm = crm; | ||
| 30 | + r2->opc1 = opc1; | ||
| 31 | + r2->opc2 = opc2; | ||
| 32 | + r2->state = state; | ||
| 33 | r2->secure = secstate; | ||
| 34 | + if (opaque) { | ||
| 35 | + r2->opaque = opaque; | ||
| 36 | + } | ||
| 37 | |||
| 38 | if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { | ||
| 39 | /* Register is banked (using both entries in array). | ||
| 40 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
| 41 | #endif | ||
| 42 | } | ||
| 43 | } | ||
| 44 | - if (opaque) { | ||
| 45 | - r2->opaque = opaque; | ||
| 46 | - } | ||
| 47 | - /* reginfo passed to helpers is correct for the actual access, | ||
| 48 | - * and is never ARM_CP_STATE_BOTH: | ||
| 49 | - */ | ||
| 50 | - r2->state = state; | ||
| 51 | - /* Make sure reginfo passed to helpers for wildcarded regs | ||
| 52 | - * has the correct crm/opc1/opc2 for this reg, not CP_ANY: | ||
| 53 | - */ | ||
| 54 | - r2->cp = cp; | ||
| 55 | - r2->crm = crm; | ||
| 56 | - r2->opc1 = opc1; | ||
| 57 | - r2->opc2 = opc2; | ||
| 58 | + | ||
| 59 | /* By convention, for wildcarded registers only the first | ||
| 60 | * entry is used for migration; the others are marked as | ||
| 61 | * ALIAS so we don't try to transfer the register | ||
| 62 | -- | ||
| 63 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 1 | 2 | ||
| 3 | Bool is a more appropriate type for these variables. | ||
| 4 | |||
| 5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 7 | Message-id: 20220501055028.646596-16-richard.henderson@linaro.org | ||
| 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | --- | ||
| 10 | target/arm/helper.c | 4 ++-- | ||
| 11 | 1 file changed, 2 insertions(+), 2 deletions(-) | ||
| 12 | |||
| 13 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
| 14 | index XXXXXXX..XXXXXXX 100644 | ||
| 15 | --- a/target/arm/helper.c | ||
| 16 | +++ b/target/arm/helper.c | ||
| 17 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
| 18 | */ | ||
| 19 | uint32_t key; | ||
| 20 | ARMCPRegInfo *r2; | ||
| 21 | - int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0; | ||
| 22 | - int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; | ||
| 23 | + bool is64 = r->type & ARM_CP_64BIT; | ||
| 24 | + bool ns = secstate & ARM_CP_SECSTATE_NS; | ||
| 25 | int cp = r->cp; | ||
| 26 | size_t name_len; | ||
| 27 | |||
| 28 | -- | ||
| 29 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 1 | 2 | ||
| 3 | Computing isbanked only once makes the code | ||
| 4 | a bit easier to read. | ||
| 5 | |||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Message-id: 20220501055028.646596-17-richard.henderson@linaro.org | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/helper.c | 6 ++++-- | ||
| 12 | 1 file changed, 4 insertions(+), 2 deletions(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/helper.c | ||
| 17 | +++ b/target/arm/helper.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
| 19 | bool is64 = r->type & ARM_CP_64BIT; | ||
| 20 | bool ns = secstate & ARM_CP_SECSTATE_NS; | ||
| 21 | int cp = r->cp; | ||
| 22 | + bool isbanked; | ||
| 23 | size_t name_len; | ||
| 24 | |||
| 25 | switch (state) { | ||
| 26 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
| 27 | r2->opaque = opaque; | ||
| 28 | } | ||
| 29 | |||
| 30 | - if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { | ||
| 31 | + isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]; | ||
| 32 | + if (isbanked) { | ||
| 33 | /* Register is banked (using both entries in array). | ||
| 34 | * Overwriting fieldoffset as the array is only used to define | ||
| 35 | * banked registers but later only fieldoffset is used. | ||
| 36 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
| 37 | } | ||
| 38 | |||
| 39 | if (state == ARM_CP_STATE_AA32) { | ||
| 40 | - if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { | ||
| 41 | + if (isbanked) { | ||
| 42 | /* If the register is banked then we don't need to migrate or | ||
| 43 | * reset the 32-bit instance in certain cases: | ||
| 44 | * | ||
| 45 | -- | ||
| 46 | 2.25.1 | diff view generated by jsdifflib |
| 1 | Secure function return happens when a non-secure function has been | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | called using BLXNS and so has a particular magic LR value (either | ||
| 3 | 0xfefffffe or 0xfeffffff). The function return via BX behaves | ||
| 4 | specially when the new PC value is this magic value, in the same | ||
| 5 | way that exception returns are handled. | ||
| 6 | 2 | ||
| 7 | Adjust our BX excret guards so that they recognize the function | 3 | Perform the override check early, so that it is still done |
| 8 | return magic number as well, and perform the function-return | 4 | even when we decide to discard an unreachable cpreg. |
| 9 | unstacking in do_v7m_exception_exit(). | ||
| 10 | 5 | ||
| 6 | Use assert not printf+abort. | ||
| 7 | |||
| 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | Message-id: 20220501055028.646596-18-richard.henderson@linaro.org | ||
| 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 12 | Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 14 | Message-id: 1507556919-24992-5-git-send-email-peter.maydell@linaro.org | ||
| 15 | --- | 12 | --- |
| 16 | target/arm/internals.h | 7 +++ | 13 | target/arm/helper.c | 22 ++++++++-------------- |
| 17 | target/arm/helper.c | 115 +++++++++++++++++++++++++++++++++++++++++++++---- | 14 | 1 file changed, 8 insertions(+), 14 deletions(-) |
| 18 | target/arm/translate.c | 14 +++++- | ||
| 19 | 3 files changed, 126 insertions(+), 10 deletions(-) | ||
| 20 | 15 | ||
| 21 | diff --git a/target/arm/internals.h b/target/arm/internals.h | ||
| 22 | index XXXXXXX..XXXXXXX 100644 | ||
| 23 | --- a/target/arm/internals.h | ||
| 24 | +++ b/target/arm/internals.h | ||
| 25 | @@ -XXX,XX +XXX,XX @@ FIELD(V7M_EXCRET, DCRS, 5, 1) | ||
| 26 | FIELD(V7M_EXCRET, S, 6, 1) | ||
| 27 | FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */ | ||
| 28 | |||
| 29 | +/* Minimum value which is a magic number for exception return */ | ||
| 30 | +#define EXC_RETURN_MIN_MAGIC 0xff000000 | ||
| 31 | +/* Minimum number which is a magic number for function or exception return | ||
| 32 | + * when using v8M security extension | ||
| 33 | + */ | ||
| 34 | +#define FNC_RETURN_MIN_MAGIC 0xfefffffe | ||
| 35 | + | ||
| 36 | /* We use a few fake FSR values for internal purposes in M profile. | ||
| 37 | * M profile cores don't have A/R format FSRs, but currently our | ||
| 38 | * get_phys_addr() code assumes A/R profile and reports failures via | ||
| 39 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 16 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
| 40 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
| 41 | --- a/target/arm/helper.c | 18 | --- a/target/arm/helper.c |
| 42 | +++ b/target/arm/helper.c | 19 | +++ b/target/arm/helper.c |
| 43 | @@ -XXX,XX +XXX,XX @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) | 20 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, |
| 44 | * - if the return value is a magic value, do exception return (like BX) | 21 | g_assert_not_reached(); |
| 45 | * - otherwise bit 0 of the return value is the target security state | 22 | } |
| 46 | */ | 23 | |
| 47 | - if (dest >= 0xff000000) { | 24 | + /* Overriding of an existing definition must be explicitly requested. */ |
| 48 | + uint32_t min_magic; | 25 | + if (!(r->type & ARM_CP_OVERRIDE)) { |
| 49 | + | 26 | + const ARMCPRegInfo *oldreg = get_arm_cp_reginfo(cpu->cp_regs, key); |
| 50 | + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | 27 | + if (oldreg) { |
| 51 | + /* Covers FNC_RETURN and EXC_RETURN magic */ | 28 | + assert(oldreg->type & ARM_CP_OVERRIDE); |
| 52 | + min_magic = FNC_RETURN_MIN_MAGIC; | 29 | + } |
| 53 | + } else { | ||
| 54 | + /* EXC_RETURN magic only */ | ||
| 55 | + min_magic = EXC_RETURN_MIN_MAGIC; | ||
| 56 | + } | 30 | + } |
| 57 | + | 31 | + |
| 58 | + if (dest >= min_magic) { | 32 | /* Combine cpreg and name into one allocation. */ |
| 59 | /* This is an exception return magic value; put it where | 33 | name_len = strlen(name) + 1; |
| 60 | * do_v7m_exception_exit() expects and raise EXCEPTION_EXIT. | 34 | r2 = g_malloc(sizeof(*r2) + name_len); |
| 61 | * Note that if we ever add gen_ss_advance() singlestep support to | 35 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, |
| 62 | @@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu) | 36 | assert(!raw_accessors_invalid(r2)); |
| 63 | bool exc_secure = false; | 37 | } |
| 64 | bool return_to_secure; | 38 | |
| 65 | 39 | - /* Overriding of an existing definition must be explicitly | |
| 66 | - /* We can only get here from an EXCP_EXCEPTION_EXIT, and | 40 | - * requested. |
| 67 | - * gen_bx_excret() enforces the architectural rule | 41 | - */ |
| 68 | - * that jumps to magic addresses don't have magic behaviour unless | 42 | - if (!(r->type & ARM_CP_OVERRIDE)) { |
| 69 | - * we're in Handler mode (compare pseudocode BXWritePC()). | 43 | - const ARMCPRegInfo *oldreg = get_arm_cp_reginfo(cpu->cp_regs, key); |
| 70 | + /* If we're not in Handler mode then jumps to magic exception-exit | 44 | - if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) { |
| 71 | + * addresses don't have magic behaviour. However for the v8M | 45 | - fprintf(stderr, "Register redefined: cp=%d %d bit " |
| 72 | + * security extensions the magic secure-function-return has to | 46 | - "crn=%d crm=%d opc1=%d opc2=%d, " |
| 73 | + * work in thread mode too, so to avoid doing an extra check in | 47 | - "was %s, now %s\n", r2->cp, 32 + 32 * is64, |
| 74 | + * the generated code we allow exception-exit magic to also cause the | 48 | - r2->crn, r2->crm, r2->opc1, r2->opc2, |
| 75 | + * internal exception and bring us here in thread mode. Correct code | 49 | - oldreg->name, r2->name); |
| 76 | + * will never try to do this (the following insn fetch will always | 50 | - g_assert_not_reached(); |
| 77 | + * fault) so we the overhead of having taken an unnecessary exception | 51 | - } |
| 78 | + * doesn't matter. | 52 | - } |
| 79 | */ | 53 | g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r2); |
| 80 | - assert(arm_v7m_is_handler_mode(env)); | ||
| 81 | + if (!arm_v7m_is_handler_mode(env)) { | ||
| 82 | + return; | ||
| 83 | + } | ||
| 84 | |||
| 85 | /* In the spec pseudocode ExceptionReturn() is called directly | ||
| 86 | * from BXWritePC() and gets the full target PC value including | ||
| 87 | @@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu) | ||
| 88 | qemu_log_mask(CPU_LOG_INT, "...successful exception return\n"); | ||
| 89 | } | 54 | } |
| 90 | 55 | ||
| 91 | +static bool do_v7m_function_return(ARMCPU *cpu) | ||
| 92 | +{ | ||
| 93 | + /* v8M security extensions magic function return. | ||
| 94 | + * We may either: | ||
| 95 | + * (1) throw an exception (longjump) | ||
| 96 | + * (2) return true if we successfully handled the function return | ||
| 97 | + * (3) return false if we failed a consistency check and have | ||
| 98 | + * pended a UsageFault that needs to be taken now | ||
| 99 | + * | ||
| 100 | + * At this point the magic return value is split between env->regs[15] | ||
| 101 | + * and env->thumb. We don't bother to reconstitute it because we don't | ||
| 102 | + * need it (all values are handled the same way). | ||
| 103 | + */ | ||
| 104 | + CPUARMState *env = &cpu->env; | ||
| 105 | + uint32_t newpc, newpsr, newpsr_exc; | ||
| 106 | + | ||
| 107 | + qemu_log_mask(CPU_LOG_INT, "...really v7M secure function return\n"); | ||
| 108 | + | ||
| 109 | + { | ||
| 110 | + bool threadmode, spsel; | ||
| 111 | + TCGMemOpIdx oi; | ||
| 112 | + ARMMMUIdx mmu_idx; | ||
| 113 | + uint32_t *frame_sp_p; | ||
| 114 | + uint32_t frameptr; | ||
| 115 | + | ||
| 116 | + /* Pull the return address and IPSR from the Secure stack */ | ||
| 117 | + threadmode = !arm_v7m_is_handler_mode(env); | ||
| 118 | + spsel = env->v7m.control[M_REG_S] & R_V7M_CONTROL_SPSEL_MASK; | ||
| 119 | + | ||
| 120 | + frame_sp_p = get_v7m_sp_ptr(env, true, threadmode, spsel); | ||
| 121 | + frameptr = *frame_sp_p; | ||
| 122 | + | ||
| 123 | + /* These loads may throw an exception (for MPU faults). We want to | ||
| 124 | + * do them as secure, so work out what MMU index that is. | ||
| 125 | + */ | ||
| 126 | + mmu_idx = arm_v7m_mmu_idx_for_secstate(env, true); | ||
| 127 | + oi = make_memop_idx(MO_LE, arm_to_core_mmu_idx(mmu_idx)); | ||
| 128 | + newpc = helper_le_ldul_mmu(env, frameptr, oi, 0); | ||
| 129 | + newpsr = helper_le_ldul_mmu(env, frameptr + 4, oi, 0); | ||
| 130 | + | ||
| 131 | + /* Consistency checks on new IPSR */ | ||
| 132 | + newpsr_exc = newpsr & XPSR_EXCP; | ||
| 133 | + if (!((env->v7m.exception == 0 && newpsr_exc == 0) || | ||
| 134 | + (env->v7m.exception == 1 && newpsr_exc != 0))) { | ||
| 135 | + /* Pend the fault and tell our caller to take it */ | ||
| 136 | + env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK; | ||
| 137 | + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, | ||
| 138 | + env->v7m.secure); | ||
| 139 | + qemu_log_mask(CPU_LOG_INT, | ||
| 140 | + "...taking INVPC UsageFault: " | ||
| 141 | + "IPSR consistency check failed\n"); | ||
| 142 | + return false; | ||
| 143 | + } | ||
| 144 | + | ||
| 145 | + *frame_sp_p = frameptr + 8; | ||
| 146 | + } | ||
| 147 | + | ||
| 148 | + /* This invalidates frame_sp_p */ | ||
| 149 | + switch_v7m_security_state(env, true); | ||
| 150 | + env->v7m.exception = newpsr_exc; | ||
| 151 | + env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK; | ||
| 152 | + if (newpsr & XPSR_SFPA) { | ||
| 153 | + env->v7m.control[M_REG_S] |= R_V7M_CONTROL_SFPA_MASK; | ||
| 154 | + } | ||
| 155 | + xpsr_write(env, 0, XPSR_IT); | ||
| 156 | + env->thumb = newpc & 1; | ||
| 157 | + env->regs[15] = newpc & ~1; | ||
| 158 | + | ||
| 159 | + qemu_log_mask(CPU_LOG_INT, "...function return successful\n"); | ||
| 160 | + return true; | ||
| 161 | +} | ||
| 162 | + | ||
| 163 | static void arm_log_exception(int idx) | ||
| 164 | { | ||
| 165 | if (qemu_loglevel_mask(CPU_LOG_INT)) { | ||
| 166 | @@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) | ||
| 167 | case EXCP_IRQ: | ||
| 168 | break; | ||
| 169 | case EXCP_EXCEPTION_EXIT: | ||
| 170 | - do_v7m_exception_exit(cpu); | ||
| 171 | - return; | ||
| 172 | + if (env->regs[15] < EXC_RETURN_MIN_MAGIC) { | ||
| 173 | + /* Must be v8M security extension function return */ | ||
| 174 | + assert(env->regs[15] >= FNC_RETURN_MIN_MAGIC); | ||
| 175 | + assert(arm_feature(env, ARM_FEATURE_M_SECURITY)); | ||
| 176 | + if (do_v7m_function_return(cpu)) { | ||
| 177 | + return; | ||
| 178 | + } | ||
| 179 | + } else { | ||
| 180 | + do_v7m_exception_exit(cpu); | ||
| 181 | + return; | ||
| 182 | + } | ||
| 183 | + break; | ||
| 184 | default: | ||
| 185 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); | ||
| 186 | return; /* Never happens. Keep compiler happy. */ | ||
| 187 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
| 188 | index XXXXXXX..XXXXXXX 100644 | ||
| 189 | --- a/target/arm/translate.c | ||
| 190 | +++ b/target/arm/translate.c | ||
| 191 | @@ -XXX,XX +XXX,XX @@ static inline void gen_bx_excret(DisasContext *s, TCGv_i32 var) | ||
| 192 | * s->base.is_jmp that we need to do the rest of the work later. | ||
| 193 | */ | ||
| 194 | gen_bx(s, var); | ||
| 195 | - if (s->v7m_handler_mode && arm_dc_feature(s, ARM_FEATURE_M)) { | ||
| 196 | + if (arm_dc_feature(s, ARM_FEATURE_M_SECURITY) || | ||
| 197 | + (s->v7m_handler_mode && arm_dc_feature(s, ARM_FEATURE_M))) { | ||
| 198 | s->base.is_jmp = DISAS_BX_EXCRET; | ||
| 199 | } | ||
| 200 | } | ||
| 201 | @@ -XXX,XX +XXX,XX @@ static inline void gen_bx_excret_final_code(DisasContext *s) | ||
| 202 | { | ||
| 203 | /* Generate the code to finish possible exception return and end the TB */ | ||
| 204 | TCGLabel *excret_label = gen_new_label(); | ||
| 205 | + uint32_t min_magic; | ||
| 206 | + | ||
| 207 | + if (arm_dc_feature(s, ARM_FEATURE_M_SECURITY)) { | ||
| 208 | + /* Covers FNC_RETURN and EXC_RETURN magic */ | ||
| 209 | + min_magic = FNC_RETURN_MIN_MAGIC; | ||
| 210 | + } else { | ||
| 211 | + /* EXC_RETURN magic only */ | ||
| 212 | + min_magic = EXC_RETURN_MIN_MAGIC; | ||
| 213 | + } | ||
| 214 | |||
| 215 | /* Is the new PC value in the magic range indicating exception return? */ | ||
| 216 | - tcg_gen_brcondi_i32(TCG_COND_GEU, cpu_R[15], 0xff000000, excret_label); | ||
| 217 | + tcg_gen_brcondi_i32(TCG_COND_GEU, cpu_R[15], min_magic, excret_label); | ||
| 218 | /* No: end the TB as we would for a DISAS_JMP */ | ||
| 219 | if (is_singlestepping(s)) { | ||
| 220 | gen_singlestep_exception(s); | ||
| 221 | -- | 56 | -- |
| 222 | 2.7.4 | 57 | 2.25.1 |
| 223 | |||
| 224 | diff view generated by jsdifflib |
| 1 | A few Thumb instructions are always unconditional even inside an | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | IT block (as opposed to being UNPREDICTABLE if used inside an | ||
| 3 | IT block): BKPT, the v8M SG instruction, and the A profile | ||
| 4 | HLT (debug halt) instruction. | ||
| 5 | 2 | ||
| 6 | This means we need to suppress the jump-over-instruction-on-condfail | 3 | Put the block comments into the current coding style. |
| 7 | code generation (though the IT state still advances as usual and | ||
| 8 | subsequent insns in the IT block may be conditional). | ||
| 9 | 4 | ||
| 5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 7 | Message-id: 20220501055028.646596-19-richard.henderson@linaro.org | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 12 | Message-id: 1507556919-24992-9-git-send-email-peter.maydell@linaro.org | ||
| 13 | --- | 9 | --- |
| 14 | target/arm/translate.c | 48 +++++++++++++++++++++++++++++++++++++++++++++++- | 10 | target/arm/helper.c | 24 +++++++++++++++--------- |
| 15 | 1 file changed, 47 insertions(+), 1 deletion(-) | 11 | 1 file changed, 15 insertions(+), 9 deletions(-) |
| 16 | 12 | ||
| 17 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 13 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
| 18 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
| 19 | --- a/target/arm/translate.c | 15 | --- a/target/arm/helper.c |
| 20 | +++ b/target/arm/translate.c | 16 | +++ b/target/arm/helper.c |
| 21 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) | 17 | @@ -XXX,XX +XXX,XX @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) |
| 22 | in init_disas_context by adjusting max_insns. */ | 18 | return cpu_list; |
| 23 | } | 19 | } |
| 24 | 20 | ||
| 25 | +static bool thumb_insn_is_unconditional(DisasContext *s, uint32_t insn) | 21 | +/* |
| 26 | +{ | 22 | + * Private utility function for define_one_arm_cp_reg_with_opaque(): |
| 27 | + /* Return true if this Thumb insn is always unconditional, | 23 | + * add a single reginfo struct to the hash table. |
| 28 | + * even inside an IT block. This is true of only a very few | 24 | + */ |
| 29 | + * instructions: BKPT, HLT, and SG. | 25 | static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, |
| 30 | + * | 26 | void *opaque, CPState state, |
| 31 | + * A larger class of instructions are UNPREDICTABLE if used | 27 | CPSecureState secstate, |
| 32 | + * inside an IT block; we do not need to detect those here, because | 28 | int crm, int opc1, int opc2, |
| 33 | + * what we do by default (perform the cc check and update the IT | 29 | const char *name) |
| 34 | + * bits state machine) is a permitted CONSTRAINED UNPREDICTABLE | ||
| 35 | + * choice for those situations. | ||
| 36 | + * | ||
| 37 | + * insn is either a 16-bit or a 32-bit instruction; the two are | ||
| 38 | + * distinguishable because for the 16-bit case the top 16 bits | ||
| 39 | + * are zeroes, and that isn't a valid 32-bit encoding. | ||
| 40 | + */ | ||
| 41 | + if ((insn & 0xffffff00) == 0xbe00) { | ||
| 42 | + /* BKPT */ | ||
| 43 | + return true; | ||
| 44 | + } | ||
| 45 | + | ||
| 46 | + if ((insn & 0xffffffc0) == 0xba80 && arm_dc_feature(s, ARM_FEATURE_V8) && | ||
| 47 | + !arm_dc_feature(s, ARM_FEATURE_M)) { | ||
| 48 | + /* HLT: v8A only. This is unconditional even when it is going to | ||
| 49 | + * UNDEF; see the v8A ARM ARM DDI0487B.a H3.3. | ||
| 50 | + * For v7 cores this was a plain old undefined encoding and so | ||
| 51 | + * honours its cc check. (We might be using the encoding as | ||
| 52 | + * a semihosting trap, but we don't change the cc check behaviour | ||
| 53 | + * on that account, because a debugger connected to a real v7A | ||
| 54 | + * core and emulating semihosting traps by catching the UNDEF | ||
| 55 | + * exception would also only see cases where the cc check passed. | ||
| 56 | + * No guest code should be trying to do a HLT semihosting trap | ||
| 57 | + * in an IT block anyway. | ||
| 58 | + */ | ||
| 59 | + return true; | ||
| 60 | + } | ||
| 61 | + | ||
| 62 | + if (insn == 0xe97fe97f && arm_dc_feature(s, ARM_FEATURE_V8) && | ||
| 63 | + arm_dc_feature(s, ARM_FEATURE_M)) { | ||
| 64 | + /* SG: v8M only */ | ||
| 65 | + return true; | ||
| 66 | + } | ||
| 67 | + | ||
| 68 | + return false; | ||
| 69 | +} | ||
| 70 | + | ||
| 71 | static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) | ||
| 72 | { | 30 | { |
| 73 | DisasContext *dc = container_of(dcbase, DisasContext, base); | 31 | - /* Private utility function for define_one_arm_cp_reg_with_opaque(): |
| 74 | @@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) | 32 | - * add a single reginfo struct to the hash table. |
| 75 | dc->pc += 2; | 33 | - */ |
| 34 | uint32_t key; | ||
| 35 | ARMCPRegInfo *r2; | ||
| 36 | bool is64 = r->type & ARM_CP_64BIT; | ||
| 37 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
| 38 | |||
| 39 | isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]; | ||
| 40 | if (isbanked) { | ||
| 41 | - /* Register is banked (using both entries in array). | ||
| 42 | + /* | ||
| 43 | + * Register is banked (using both entries in array). | ||
| 44 | * Overwriting fieldoffset as the array is only used to define | ||
| 45 | * banked registers but later only fieldoffset is used. | ||
| 46 | */ | ||
| 47 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
| 48 | |||
| 49 | if (state == ARM_CP_STATE_AA32) { | ||
| 50 | if (isbanked) { | ||
| 51 | - /* If the register is banked then we don't need to migrate or | ||
| 52 | + /* | ||
| 53 | + * If the register is banked then we don't need to migrate or | ||
| 54 | * reset the 32-bit instance in certain cases: | ||
| 55 | * | ||
| 56 | * 1) If the register has both 32-bit and 64-bit instances then we | ||
| 57 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
| 58 | r2->type |= ARM_CP_ALIAS; | ||
| 59 | } | ||
| 60 | } else if ((secstate != r->secure) && !ns) { | ||
| 61 | - /* The register is not banked so we only want to allow migration of | ||
| 62 | - * the non-secure instance. | ||
| 63 | + /* | ||
| 64 | + * The register is not banked so we only want to allow migration | ||
| 65 | + * of the non-secure instance. | ||
| 66 | */ | ||
| 67 | r2->type |= ARM_CP_ALIAS; | ||
| 68 | } | ||
| 69 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
| 70 | } | ||
| 76 | } | 71 | } |
| 77 | 72 | ||
| 78 | - if (dc->condexec_mask) { | 73 | - /* By convention, for wildcarded registers only the first |
| 79 | + if (dc->condexec_mask && !thumb_insn_is_unconditional(dc, insn)) { | 74 | + /* |
| 80 | uint32_t cond = dc->condexec_cond; | 75 | + * By convention, for wildcarded registers only the first |
| 81 | 76 | * entry is used for migration; the others are marked as | |
| 82 | if (cond != 0x0e) { /* Skip conditional when condition is AL. */ | 77 | * ALIAS so we don't try to transfer the register |
| 78 | * multiple times. Special registers (ie NOP/WFI) are | ||
| 79 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
| 80 | r2->type |= ARM_CP_ALIAS | ARM_CP_NO_GDB; | ||
| 81 | } | ||
| 82 | |||
| 83 | - /* Check that raw accesses are either forbidden or handled. Note that | ||
| 84 | + /* | ||
| 85 | + * Check that raw accesses are either forbidden or handled. Note that | ||
| 86 | * we can't assert this earlier because the setup of fieldoffset for | ||
| 87 | * banked registers has to be done first. | ||
| 88 | */ | ||
| 83 | -- | 89 | -- |
| 84 | 2.7.4 | 90 | 2.25.1 |
| 85 | |||
| 86 | diff view generated by jsdifflib |
| 1 | From: Igor Mammedov <imammedo@redhat.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | s/cpu_model/cpu_type/ that has been forgotten during | 3 | Since e03b56863d2bc, our host endian indicator is unconditionally |
| 4 | conversion (ba1ba5cc), while touching the line also | 4 | set, which means that we can use a normal C condition. |
| 5 | fixup alignment. | ||
| 6 | 5 | ||
| 7 | Signed-off-by: Igor Mammedov <imammedo@redhat.com> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
| 8 | Message-id: 1507710805-221721-1-git-send-email-imammedo@redhat.com | ||
| 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
| 8 | Message-id: 20220501055028.646596-20-richard.henderson@linaro.org | ||
| 9 | [PMM: quote correct git hash in commit message] | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 11 | --- | 11 | --- |
| 12 | include/hw/arm/arm.h | 2 +- | 12 | target/arm/helper.c | 9 +++------ |
| 13 | 1 file changed, 1 insertion(+), 1 deletion(-) | 13 | 1 file changed, 3 insertions(+), 6 deletions(-) |
| 14 | 14 | ||
| 15 | diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h | 15 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
| 16 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
| 17 | --- a/include/hw/arm/arm.h | 17 | --- a/target/arm/helper.c |
| 18 | +++ b/include/hw/arm/arm.h | 18 | +++ b/target/arm/helper.c |
| 19 | @@ -XXX,XX +XXX,XX @@ typedef enum { | 19 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, |
| 20 | 20 | r2->type |= ARM_CP_ALIAS; | |
| 21 | /* armv7m.c */ | 21 | } |
| 22 | DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq, | 22 | |
| 23 | - const char *kernel_filename, const char *cpu_model); | 23 | - if (r->state == ARM_CP_STATE_BOTH) { |
| 24 | + const char *kernel_filename, const char *cpu_type); | 24 | -#if HOST_BIG_ENDIAN |
| 25 | /** | 25 | - if (r2->fieldoffset) { |
| 26 | * armv7m_load_kernel: | 26 | - r2->fieldoffset += sizeof(uint32_t); |
| 27 | * @cpu: CPU | 27 | - } |
| 28 | -#endif | ||
| 29 | + if (HOST_BIG_ENDIAN && | ||
| 30 | + r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) { | ||
| 31 | + r2->fieldoffset += sizeof(uint32_t); | ||
| 32 | } | ||
| 33 | } | ||
| 34 | |||
| 28 | -- | 35 | -- |
| 29 | 2.7.4 | 36 | 2.25.1 |
| 30 | |||
| 31 | diff view generated by jsdifflib |
| 1 | Implement the BLXNS instruction, which allows secure code to | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | call non-secure code. | ||
| 3 | 2 | ||
| 3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 5 | Message-id: 20220501055028.646596-24-richard.henderson@linaro.org | ||
| 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Message-id: 1507556919-24992-4-git-send-email-peter.maydell@linaro.org | ||
| 7 | --- | 7 | --- |
| 8 | target/arm/helper.h | 1 + | 8 | target/arm/cpu.h | 15 +++++++++++++++ |
| 9 | target/arm/internals.h | 1 + | 9 | 1 file changed, 15 insertions(+) |
| 10 | target/arm/helper.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++ | ||
| 11 | target/arm/translate.c | 17 +++++++++++++-- | ||
| 12 | 4 files changed, 76 insertions(+), 2 deletions(-) | ||
| 13 | 10 | ||
| 14 | diff --git a/target/arm/helper.h b/target/arm/helper.h | 11 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
| 15 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
| 16 | --- a/target/arm/helper.h | 13 | --- a/target/arm/cpu.h |
| 17 | +++ b/target/arm/helper.h | 14 | +++ b/target/arm/cpu.h |
| 18 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(v7m_msr, void, env, i32, i32) | 15 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id) |
| 19 | DEF_HELPER_2(v7m_mrs, i32, env, i32) | 16 | return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0; |
| 20 | |||
| 21 | DEF_HELPER_2(v7m_bxns, void, env, i32) | ||
| 22 | +DEF_HELPER_2(v7m_blxns, void, env, i32) | ||
| 23 | |||
| 24 | DEF_HELPER_4(access_check_cp_reg, void, env, ptr, i32, i32) | ||
| 25 | DEF_HELPER_3(set_cp_reg, void, env, ptr, i32) | ||
| 26 | diff --git a/target/arm/internals.h b/target/arm/internals.h | ||
| 27 | index XXXXXXX..XXXXXXX 100644 | ||
| 28 | --- a/target/arm/internals.h | ||
| 29 | +++ b/target/arm/internals.h | ||
| 30 | @@ -XXX,XX +XXX,XX @@ static inline bool excp_is_internal(int excp) | ||
| 31 | FIELD(V7M_CONTROL, NPRIV, 0, 1) | ||
| 32 | FIELD(V7M_CONTROL, SPSEL, 1, 1) | ||
| 33 | FIELD(V7M_CONTROL, FPCA, 2, 1) | ||
| 34 | +FIELD(V7M_CONTROL, SFPA, 3, 1) | ||
| 35 | |||
| 36 | /* Bit definitions for v7M exception return payload */ | ||
| 37 | FIELD(V7M_EXCRET, ES, 0, 1) | ||
| 38 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
| 39 | index XXXXXXX..XXXXXXX 100644 | ||
| 40 | --- a/target/arm/helper.c | ||
| 41 | +++ b/target/arm/helper.c | ||
| 42 | @@ -XXX,XX +XXX,XX @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) | ||
| 43 | g_assert_not_reached(); | ||
| 44 | } | 17 | } |
| 45 | 18 | ||
| 46 | +void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) | 19 | +static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id) |
| 47 | +{ | 20 | +{ |
| 48 | + /* translate.c should never generate calls here in user-only mode */ | 21 | + return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 8; |
| 49 | + g_assert_not_reached(); | ||
| 50 | +} | 22 | +} |
| 51 | + | 23 | + |
| 52 | void switch_mode(CPUARMState *env, int mode) | 24 | /* |
| 53 | { | 25 | * 64-bit feature tests via id registers. |
| 54 | ARMCPU *cpu = arm_env_get_cpu(env); | 26 | */ |
| 55 | @@ -XXX,XX +XXX,XX @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) | 27 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) |
| 56 | env->regs[15] = dest & ~1; | 28 | return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0; |
| 57 | } | 29 | } |
| 58 | 30 | ||
| 59 | +void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) | 31 | +static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id) |
| 60 | +{ | 32 | +{ |
| 61 | + /* Handle v7M BLXNS: | 33 | + return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8; |
| 62 | + * - bit 0 of the destination address is the target security state | ||
| 63 | + */ | ||
| 64 | + | ||
| 65 | + /* At this point regs[15] is the address just after the BLXNS */ | ||
| 66 | + uint32_t nextinst = env->regs[15] | 1; | ||
| 67 | + uint32_t sp = env->regs[13] - 8; | ||
| 68 | + uint32_t saved_psr; | ||
| 69 | + | ||
| 70 | + /* translate.c will have made BLXNS UNDEF unless we're secure */ | ||
| 71 | + assert(env->v7m.secure); | ||
| 72 | + | ||
| 73 | + if (dest & 1) { | ||
| 74 | + /* target is Secure, so this is just a normal BLX, | ||
| 75 | + * except that the low bit doesn't indicate Thumb/not. | ||
| 76 | + */ | ||
| 77 | + env->regs[14] = nextinst; | ||
| 78 | + env->thumb = 1; | ||
| 79 | + env->regs[15] = dest & ~1; | ||
| 80 | + return; | ||
| 81 | + } | ||
| 82 | + | ||
| 83 | + /* Target is non-secure: first push a stack frame */ | ||
| 84 | + if (!QEMU_IS_ALIGNED(sp, 8)) { | ||
| 85 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
| 86 | + "BLXNS with misaligned SP is UNPREDICTABLE\n"); | ||
| 87 | + } | ||
| 88 | + | ||
| 89 | + saved_psr = env->v7m.exception; | ||
| 90 | + if (env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK) { | ||
| 91 | + saved_psr |= XPSR_SFPA; | ||
| 92 | + } | ||
| 93 | + | ||
| 94 | + /* Note that these stores can throw exceptions on MPU faults */ | ||
| 95 | + cpu_stl_data(env, sp, nextinst); | ||
| 96 | + cpu_stl_data(env, sp + 4, saved_psr); | ||
| 97 | + | ||
| 98 | + env->regs[13] = sp; | ||
| 99 | + env->regs[14] = 0xfeffffff; | ||
| 100 | + if (arm_v7m_is_handler_mode(env)) { | ||
| 101 | + /* Write a dummy value to IPSR, to avoid leaking the current secure | ||
| 102 | + * exception number to non-secure code. This is guaranteed not | ||
| 103 | + * to cause write_v7m_exception() to actually change stacks. | ||
| 104 | + */ | ||
| 105 | + write_v7m_exception(env, 1); | ||
| 106 | + } | ||
| 107 | + switch_v7m_security_state(env, 0); | ||
| 108 | + env->thumb = 1; | ||
| 109 | + env->regs[15] = dest; | ||
| 110 | +} | 34 | +} |
| 111 | + | 35 | + |
| 112 | static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode, | 36 | static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id) |
| 113 | bool spsel) | ||
| 114 | { | 37 | { |
| 115 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 38 | return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0; |
| 116 | index XXXXXXX..XXXXXXX 100644 | 39 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id) |
| 117 | --- a/target/arm/translate.c | 40 | return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id); |
| 118 | +++ b/target/arm/translate.c | ||
| 119 | @@ -XXX,XX +XXX,XX @@ static inline void gen_bxns(DisasContext *s, int rm) | ||
| 120 | s->base.is_jmp = DISAS_EXIT; | ||
| 121 | } | 41 | } |
| 122 | 42 | ||
| 123 | +static inline void gen_blxns(DisasContext *s, int rm) | 43 | +static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id) |
| 124 | +{ | 44 | +{ |
| 125 | + TCGv_i32 var = load_reg(s, rm); | 45 | + return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id); |
| 126 | + | ||
| 127 | + /* We don't need to sync condexec state, for the same reason as bxns. | ||
| 128 | + * We do however need to set the PC, because the blxns helper reads it. | ||
| 129 | + * The blxns helper may throw an exception. | ||
| 130 | + */ | ||
| 131 | + gen_set_pc_im(s, s->pc); | ||
| 132 | + gen_helper_v7m_blxns(cpu_env, var); | ||
| 133 | + tcg_temp_free_i32(var); | ||
| 134 | + s->base.is_jmp = DISAS_EXIT; | ||
| 135 | +} | 46 | +} |
| 136 | + | 47 | + |
| 137 | /* Variant of store_reg which uses branch&exchange logic when storing | 48 | /* |
| 138 | to r15 in ARM architecture v7 and above. The source must be a temporary | 49 | * Forward to the above feature tests given an ARMCPU pointer. |
| 139 | and will be marked as dead. */ | 50 | */ |
| 140 | @@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) | ||
| 141 | goto undef; | ||
| 142 | } | ||
| 143 | if (link) { | ||
| 144 | - /* BLXNS: not yet implemented */ | ||
| 145 | - goto undef; | ||
| 146 | + gen_blxns(s, rm); | ||
| 147 | } else { | ||
| 148 | gen_bxns(s, rm); | ||
| 149 | } | ||
| 150 | -- | 51 | -- |
| 151 | 2.7.4 | 52 | 2.25.1 |
| 152 | |||
| 153 | diff view generated by jsdifflib |
| 1 | Refactor the Thumb decode to do the loads of the instruction words at | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | the top level rather than only loading the second half of a 32-bit | ||
| 3 | Thumb insn in the middle of the decode. | ||
| 4 | 2 | ||
| 5 | This is simple apart from the awkward case of Thumb1, where the | 3 | Add the aa64 predicate for detecting RAS support from id registers. |
| 6 | BL/BLX prefix and suffix instructions live in what in Thumb2 is the | 4 | We already have the aa32 version from the M-profile work. |
| 7 | 32-bit insn space. To handle these we decode enough to identify | 5 | Add the 'any' predicate for testing both aa64 and aa32. |
| 8 | whether we're looking at a prefix/suffix that we handle as a 16 bit | ||
| 9 | insn, or a prefix that we're going to merge with the following suffix | ||
| 10 | to consider as a 32 bit insn. The translation of the 16 bit cases | ||
| 11 | then moves from disas_thumb2_insn() to disas_thumb_insn(). | ||
| 12 | 6 | ||
| 13 | The refactoring has the benefit that we don't need to pass the | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
| 14 | CPUARMState* down into the decoder code any more, but the major | 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
| 15 | reason for doing this is that some Thumb instructions must be always | 9 | Message-id: 20220501055028.646596-34-richard.henderson@linaro.org |
| 16 | unconditional regardless of the IT state bits, so we need to know the | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 17 | whole insn before we emit the "skip this insn if the IT bits and cond | 11 | --- |
| 18 | state tell us to" code. (The always unconditional insns are BKPT, | 12 | target/arm/cpu.h | 10 ++++++++++ |
| 19 | HLT and SG; the last of these is 32 bits.) | 13 | 1 file changed, 10 insertions(+) |
| 20 | 14 | ||
| 21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
| 22 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 23 | Message-id: 1507556919-24992-7-git-send-email-peter.maydell@linaro.org | ||
| 24 | --- | ||
| 25 | target/arm/translate.c | 178 ++++++++++++++++++++++++++++++------------------- | ||
| 26 | 1 file changed, 108 insertions(+), 70 deletions(-) | ||
| 27 | |||
| 28 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
| 29 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
| 30 | --- a/target/arm/translate.c | 17 | --- a/target/arm/cpu.h |
| 31 | +++ b/target/arm/translate.c | 18 | +++ b/target/arm/cpu.h |
| 32 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | 19 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id) |
| 33 | } | 20 | return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2; |
| 34 | } | 21 | } |
| 35 | 22 | ||
| 36 | +static bool thumb_insn_is_16bit(DisasContext *s, uint32_t insn) | 23 | +static inline bool isar_feature_aa64_ras(const ARMISARegisters *id) |
| 37 | +{ | 24 | +{ |
| 38 | + /* Return true if this is a 16 bit instruction. We must be precise | 25 | + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0; |
| 39 | + * about this (matching the decode). We assume that s->pc still | ||
| 40 | + * points to the first 16 bits of the insn. | ||
| 41 | + */ | ||
| 42 | + if ((insn >> 11) < 0x1d) { | ||
| 43 | + /* Definitely a 16-bit instruction */ | ||
| 44 | + return true; | ||
| 45 | + } | ||
| 46 | + | ||
| 47 | + /* Top five bits 0b11101 / 0b11110 / 0b11111 : this is the | ||
| 48 | + * first half of a 32-bit Thumb insn. Thumb-1 cores might | ||
| 49 | + * end up actually treating this as two 16-bit insns, though, | ||
| 50 | + * if it's half of a bl/blx pair that might span a page boundary. | ||
| 51 | + */ | ||
| 52 | + if (arm_dc_feature(s, ARM_FEATURE_THUMB2)) { | ||
| 53 | + /* Thumb2 cores (including all M profile ones) always treat | ||
| 54 | + * 32-bit insns as 32-bit. | ||
| 55 | + */ | ||
| 56 | + return false; | ||
| 57 | + } | ||
| 58 | + | ||
| 59 | + if ((insn >> 11) == 0x1e && (s->pc < s->next_page_start - 3)) { | ||
| 60 | + /* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix, and the suffix | ||
| 61 | + * is not on the next page; we merge this into a 32-bit | ||
| 62 | + * insn. | ||
| 63 | + */ | ||
| 64 | + return false; | ||
| 65 | + } | ||
| 66 | + /* 0b1110_1xxx_xxxx_xxxx : BLX suffix (or UNDEF); | ||
| 67 | + * 0b1111_1xxx_xxxx_xxxx : BL suffix; | ||
| 68 | + * 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix on the end of a page | ||
| 69 | + * -- handle as single 16 bit insn | ||
| 70 | + */ | ||
| 71 | + return true; | ||
| 72 | +} | 26 | +} |
| 73 | + | 27 | + |
| 74 | /* Return true if this is a Thumb-2 logical op. */ | 28 | static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) |
| 75 | static int | ||
| 76 | thumb2_logic_op(int op) | ||
| 77 | @@ -XXX,XX +XXX,XX @@ gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out, | ||
| 78 | |||
| 79 | /* Translate a 32-bit thumb instruction. Returns nonzero if the instruction | ||
| 80 | is not legal. */ | ||
| 81 | -static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw1) | ||
| 82 | +static int disas_thumb2_insn(DisasContext *s, uint32_t insn) | ||
| 83 | { | 29 | { |
| 84 | - uint32_t insn, imm, shift, offset; | 30 | return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; |
| 85 | + uint32_t imm, shift, offset; | 31 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id) |
| 86 | uint32_t rd, rn, rm, rs; | 32 | return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id); |
| 87 | TCGv_i32 tmp; | ||
| 88 | TCGv_i32 tmp2; | ||
| 89 | @@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw | ||
| 90 | int conds; | ||
| 91 | int logic_cc; | ||
| 92 | |||
| 93 | - if (!arm_dc_feature(s, ARM_FEATURE_THUMB2)) { | ||
| 94 | - /* Thumb-1 cores may need to treat bl and blx as a pair of | ||
| 95 | - 16-bit instructions to get correct prefetch abort behavior. */ | ||
| 96 | - insn = insn_hw1; | ||
| 97 | - if ((insn & (1 << 12)) == 0) { | ||
| 98 | - ARCH(5); | ||
| 99 | - /* Second half of blx. */ | ||
| 100 | - offset = ((insn & 0x7ff) << 1); | ||
| 101 | - tmp = load_reg(s, 14); | ||
| 102 | - tcg_gen_addi_i32(tmp, tmp, offset); | ||
| 103 | - tcg_gen_andi_i32(tmp, tmp, 0xfffffffc); | ||
| 104 | - | ||
| 105 | - tmp2 = tcg_temp_new_i32(); | ||
| 106 | - tcg_gen_movi_i32(tmp2, s->pc | 1); | ||
| 107 | - store_reg(s, 14, tmp2); | ||
| 108 | - gen_bx(s, tmp); | ||
| 109 | - return 0; | ||
| 110 | - } | ||
| 111 | - if (insn & (1 << 11)) { | ||
| 112 | - /* Second half of bl. */ | ||
| 113 | - offset = ((insn & 0x7ff) << 1) | 1; | ||
| 114 | - tmp = load_reg(s, 14); | ||
| 115 | - tcg_gen_addi_i32(tmp, tmp, offset); | ||
| 116 | - | ||
| 117 | - tmp2 = tcg_temp_new_i32(); | ||
| 118 | - tcg_gen_movi_i32(tmp2, s->pc | 1); | ||
| 119 | - store_reg(s, 14, tmp2); | ||
| 120 | - gen_bx(s, tmp); | ||
| 121 | - return 0; | ||
| 122 | - } | ||
| 123 | - if ((s->pc & ~TARGET_PAGE_MASK) == 0) { | ||
| 124 | - /* Instruction spans a page boundary. Implement it as two | ||
| 125 | - 16-bit instructions in case the second half causes an | ||
| 126 | - prefetch abort. */ | ||
| 127 | - offset = ((int32_t)insn << 21) >> 9; | ||
| 128 | - tcg_gen_movi_i32(cpu_R[14], s->pc + 2 + offset); | ||
| 129 | - return 0; | ||
| 130 | - } | ||
| 131 | - /* Fall through to 32-bit decode. */ | ||
| 132 | - } | ||
| 133 | - | ||
| 134 | - insn = arm_lduw_code(env, s->pc, s->sctlr_b); | ||
| 135 | - s->pc += 2; | ||
| 136 | - insn |= (uint32_t)insn_hw1 << 16; | ||
| 137 | - | ||
| 138 | + /* The only 32 bit insn that's allowed for Thumb1 is the combined | ||
| 139 | + * BL/BLX prefix and suffix. | ||
| 140 | + */ | ||
| 141 | if ((insn & 0xf800e800) != 0xf000e800) { | ||
| 142 | ARCH(6T2); | ||
| 143 | } | ||
| 144 | @@ -XXX,XX +XXX,XX @@ illegal_op: | ||
| 145 | return 1; | ||
| 146 | } | 33 | } |
| 147 | 34 | ||
| 148 | -static void disas_thumb_insn(CPUARMState *env, DisasContext *s) | 35 | +static inline bool isar_feature_any_ras(const ARMISARegisters *id) |
| 149 | +static void disas_thumb_insn(DisasContext *s, uint32_t insn) | 36 | +{ |
| 150 | { | 37 | + return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id); |
| 151 | - uint32_t val, insn, op, rm, rn, rd, shift, cond; | 38 | +} |
| 152 | + uint32_t val, op, rm, rn, rd, shift, cond; | ||
| 153 | int32_t offset; | ||
| 154 | int i; | ||
| 155 | TCGv_i32 tmp; | ||
| 156 | TCGv_i32 tmp2; | ||
| 157 | TCGv_i32 addr; | ||
| 158 | |||
| 159 | - if (s->condexec_mask) { | ||
| 160 | - cond = s->condexec_cond; | ||
| 161 | - if (cond != 0x0e) { /* Skip conditional when condition is AL. */ | ||
| 162 | - s->condlabel = gen_new_label(); | ||
| 163 | - arm_gen_test_cc(cond ^ 1, s->condlabel); | ||
| 164 | - s->condjmp = 1; | ||
| 165 | - } | ||
| 166 | - } | ||
| 167 | - | ||
| 168 | - insn = arm_lduw_code(env, s->pc, s->sctlr_b); | ||
| 169 | - s->pc += 2; | ||
| 170 | - | ||
| 171 | switch (insn >> 12) { | ||
| 172 | case 0: case 1: | ||
| 173 | |||
| 174 | @@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) | ||
| 175 | |||
| 176 | case 14: | ||
| 177 | if (insn & (1 << 11)) { | ||
| 178 | - if (disas_thumb2_insn(env, s, insn)) | ||
| 179 | - goto undef32; | ||
| 180 | + /* thumb_insn_is_16bit() ensures we can't get here for | ||
| 181 | + * a Thumb2 CPU, so this must be a thumb1 split BL/BLX: | ||
| 182 | + * 0b1110_1xxx_xxxx_xxxx : BLX suffix (or UNDEF) | ||
| 183 | + */ | ||
| 184 | + assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2)); | ||
| 185 | + ARCH(5); | ||
| 186 | + offset = ((insn & 0x7ff) << 1); | ||
| 187 | + tmp = load_reg(s, 14); | ||
| 188 | + tcg_gen_addi_i32(tmp, tmp, offset); | ||
| 189 | + tcg_gen_andi_i32(tmp, tmp, 0xfffffffc); | ||
| 190 | + | 39 | + |
| 191 | + tmp2 = tcg_temp_new_i32(); | 40 | /* |
| 192 | + tcg_gen_movi_i32(tmp2, s->pc | 1); | 41 | * Forward to the above feature tests given an ARMCPU pointer. |
| 193 | + store_reg(s, 14, tmp2); | 42 | */ |
| 194 | + gen_bx(s, tmp); | ||
| 195 | break; | ||
| 196 | } | ||
| 197 | /* unconditional branch */ | ||
| 198 | @@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) | ||
| 199 | break; | ||
| 200 | |||
| 201 | case 15: | ||
| 202 | - if (disas_thumb2_insn(env, s, insn)) | ||
| 203 | - goto undef32; | ||
| 204 | + /* thumb_insn_is_16bit() ensures we can't get here for | ||
| 205 | + * a Thumb2 CPU, so this must be a thumb1 split BL/BLX. | ||
| 206 | + */ | ||
| 207 | + assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2)); | ||
| 208 | + | ||
| 209 | + if (insn & (1 << 11)) { | ||
| 210 | + /* 0b1111_1xxx_xxxx_xxxx : BL suffix */ | ||
| 211 | + offset = ((insn & 0x7ff) << 1) | 1; | ||
| 212 | + tmp = load_reg(s, 14); | ||
| 213 | + tcg_gen_addi_i32(tmp, tmp, offset); | ||
| 214 | + | ||
| 215 | + tmp2 = tcg_temp_new_i32(); | ||
| 216 | + tcg_gen_movi_i32(tmp2, s->pc | 1); | ||
| 217 | + store_reg(s, 14, tmp2); | ||
| 218 | + gen_bx(s, tmp); | ||
| 219 | + } else { | ||
| 220 | + /* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix */ | ||
| 221 | + uint32_t uoffset = ((int32_t)insn << 21) >> 9; | ||
| 222 | + | ||
| 223 | + tcg_gen_movi_i32(cpu_R[14], s->pc + 2 + uoffset); | ||
| 224 | + } | ||
| 225 | break; | ||
| 226 | } | ||
| 227 | return; | ||
| 228 | -undef32: | ||
| 229 | - gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(), | ||
| 230 | - default_exception_el(s)); | ||
| 231 | - return; | ||
| 232 | illegal_op: | ||
| 233 | undef: | ||
| 234 | gen_exception_insn(s, 2, EXCP_UDEF, syn_uncategorized(), | ||
| 235 | @@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) | ||
| 236 | { | ||
| 237 | DisasContext *dc = container_of(dcbase, DisasContext, base); | ||
| 238 | CPUARMState *env = cpu->env_ptr; | ||
| 239 | + uint32_t insn; | ||
| 240 | + bool is_16bit; | ||
| 241 | |||
| 242 | if (arm_pre_translate_insn(dc)) { | ||
| 243 | return; | ||
| 244 | } | ||
| 245 | |||
| 246 | - disas_thumb_insn(env, dc); | ||
| 247 | + insn = arm_lduw_code(env, dc->pc, dc->sctlr_b); | ||
| 248 | + is_16bit = thumb_insn_is_16bit(dc, insn); | ||
| 249 | + dc->pc += 2; | ||
| 250 | + if (!is_16bit) { | ||
| 251 | + uint32_t insn2 = arm_lduw_code(env, dc->pc, dc->sctlr_b); | ||
| 252 | + | ||
| 253 | + insn = insn << 16 | insn2; | ||
| 254 | + dc->pc += 2; | ||
| 255 | + } | ||
| 256 | + | ||
| 257 | + if (dc->condexec_mask) { | ||
| 258 | + uint32_t cond = dc->condexec_cond; | ||
| 259 | + | ||
| 260 | + if (cond != 0x0e) { /* Skip conditional when condition is AL. */ | ||
| 261 | + dc->condlabel = gen_new_label(); | ||
| 262 | + arm_gen_test_cc(cond ^ 1, dc->condlabel); | ||
| 263 | + dc->condjmp = 1; | ||
| 264 | + } | ||
| 265 | + } | ||
| 266 | + | ||
| 267 | + if (is_16bit) { | ||
| 268 | + disas_thumb_insn(dc, insn); | ||
| 269 | + } else { | ||
| 270 | + disas_thumb2_insn(dc, insn); | ||
| 271 | + } | ||
| 272 | |||
| 273 | /* Advance the Thumb condexec condition. */ | ||
| 274 | if (dc->condexec_mask) { | ||
| 275 | -- | 43 | -- |
| 276 | 2.7.4 | 44 | 2.25.1 |
| 277 | |||
| 278 | diff view generated by jsdifflib |
| 1 | This calculation of the first exception vector in | 1 | From: Alex Zuepke <alex.zuepke@tum.de> |
|---|---|---|---|
| 2 | the ITNS<n> register being accessed: | ||
| 3 | int startvec = 32 * (offset - 0x380) + NVIC_FIRST_IRQ; | ||
| 4 | 2 | ||
| 5 | is incorrect, because offset is in bytes, so we only want | 3 | The ARMv8 manual defines that PMUSERENR_EL0.ER enables read-access |
| 6 | to multiply by 8. | 4 | to both PMXEVCNTR_EL0 and PMEVCNTR<n>_EL0 registers, however, |
| 5 | we only use it for PMXEVCNTR_EL0. Extend to PMEVCNTR<n>_EL0 as well. | ||
| 7 | 6 | ||
| 8 | Spotted by Coverity (CID 1381484, CID 1381488), though it is | 7 | Signed-off-by: Alex Zuepke <alex.zuepke@tum.de> |
| 9 | not correct that it actually overflows the buffer, because | 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 10 | we have a 'startvec + i < s->num_irq' guard. | 9 | Message-id: 20220428132717.84190-1-alex.zuepke@tum.de |
| 11 | |||
| 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 14 | Message-id: 1507650856-11718-1-git-send-email-peter.maydell@linaro.org | ||
| 15 | --- | 11 | --- |
| 16 | hw/intc/armv7m_nvic.c | 4 ++-- | 12 | target/arm/helper.c | 4 ++-- |
| 17 | 1 file changed, 2 insertions(+), 2 deletions(-) | 13 | 1 file changed, 2 insertions(+), 2 deletions(-) |
| 18 | 14 | ||
| 19 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | 15 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
| 20 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
| 21 | --- a/hw/intc/armv7m_nvic.c | 17 | --- a/target/arm/helper.c |
| 22 | +++ b/hw/intc/armv7m_nvic.c | 18 | +++ b/target/arm/helper.c |
| 23 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | 19 | @@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu) |
| 24 | return ((s->num_irq - NVIC_FIRST_IRQ) / 32) - 1; | 20 | .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7, |
| 25 | case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */ | 21 | .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS, |
| 26 | { | 22 | .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn, |
| 27 | - int startvec = 32 * (offset - 0x380) + NVIC_FIRST_IRQ; | 23 | - .accessfn = pmreg_access }, |
| 28 | + int startvec = 8 * (offset - 0x380) + NVIC_FIRST_IRQ; | 24 | + .accessfn = pmreg_access_xevcntr }, |
| 29 | int i; | 25 | { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64, |
| 30 | 26 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)), | |
| 31 | if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { | 27 | - .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access, |
| 32 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | 28 | + .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access_xevcntr, |
| 33 | switch (offset) { | 29 | .type = ARM_CP_IO, |
| 34 | case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */ | 30 | .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn, |
| 35 | { | 31 | .raw_readfn = pmevcntr_rawread, |
| 36 | - int startvec = 32 * (offset - 0x380) + NVIC_FIRST_IRQ; | ||
| 37 | + int startvec = 8 * (offset - 0x380) + NVIC_FIRST_IRQ; | ||
| 38 | int i; | ||
| 39 | |||
| 40 | if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { | ||
| 41 | -- | 32 | -- |
| 42 | 2.7.4 | 33 | 2.25.1 |
| 43 | |||
| 44 | diff view generated by jsdifflib |