target-arm queue:
* mostly my latest v8M stuff, plus a couple of minor patches
The following changes since commit a0b261db8c030813e30a39eae47359ac2a37f7e2:
Merge remote-tracking branch 'remotes/ehabkost/tags/python-next-pull-request' into staging (2017-10-12 10:02:09 +0100)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20171012
for you to fetch changes up to cf5f7937b05c84d5565134f058c00cd48304a117:
nvic: Fix miscalculation of offsets into ITNS array (2017-10-12 16:33:16 +0100)
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target-arm queue:
* v8M: SG, BLXNS, secure-return
* v8M: fixes for coverity issues in previous patches
* arm: fix armv7m_init() declaration to match definition
* watchdog/aspeed: fix variable type to store reload value
----------------------------------------------------------------
Cédric Le Goater (1):
watchdog/aspeed: fix variable type to store reload value
Igor Mammedov (1):
arm: fix armv7m_init() declaration to match definition
Peter Maydell (11):
target/arm: Add M profile secure MMU index values to get_a32_user_mem_index()
target/arm: Implement SG instruction
target/arm: Implement BLXNS
target/arm: Implement secure function return
target-arm: Don't check for "Thumb2 or M profile" for not-Thumb1
target/arm: Pull Thumb insn word loads up to top level
target-arm: Simplify insn_crosses_page()
target/arm: Support some Thumb insns being always unconditional
target/arm: Implement SG instruction corner cases
nvic: Add missing 'break'
nvic: Fix miscalculation of offsets into ITNS array
include/hw/arm/arm.h | 2 +-
target/arm/helper.h | 1 +
target/arm/internals.h | 8 ++
hw/intc/armv7m_nvic.c | 5 +-
hw/watchdog/wdt_aspeed.c | 4 +-
target/arm/helper.c | 306 ++++++++++++++++++++++++++++++++++++++++++++--
target/arm/translate.c | 310 ++++++++++++++++++++++++++++++++---------------
7 files changed, 521 insertions(+), 115 deletions(-)