Peter Maydell (18):

target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation

target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH

target/arm: Make asimd_imm_const() public

target/arm: Use asimd_imm_const for A64 decode

target/arm: Use dup_const() instead of bitfield_replicate()

target/arm: Implement MVE logical immediate insns

target/arm: Implement MVE vector shift left by immediate insns

target/arm: Implement MVE vector shift right by immediate insns

target/arm: Implement MVE VSHLL

target/arm: Implement MVE VSRI, VSLI

target/arm: Implement MVE VSHRN, VRSHRN

target/arm: Implement MVE saturating narrowing shifts

target/arm: Implement MVE VSHLC

target/arm: Implement MVE VADDLV

target/arm: Implement MVE long shifts by immediate

target/arm: Implement MVE long shifts by register

target/arm: Implement MVE shifts by immediate

target/arm: Implement MVE shifts by register

Philippe Mathieu-Daudé (1):

tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine

docs/system/arm/aspeed.rst | 1 +

docs/system/arm/nuvoton.rst | 5 +-

include/hw/arm/bcm2835_peripherals.h | 3 +-

include/hw/misc/bcm2835_powermgt.h | 29 ++

target/arm/helper-mve.h | 108 +++++++

target/arm/translate.h | 41 +++

target/arm/mve.decode | 177 ++++++++++-

target/arm/t32.decode | 71 ++++-

hw/arm/bcm2835_peripherals.c | 13 +-

hw/gpio/gpio_pwr.c | 2 +-

hw/misc/bcm2835_powermgt.c | 160 ++++++++++

target/arm/helper-a64.c | 12 +-

target/arm/mve_helper.c | 524 +++++++++++++++++++++++++++++++--

target/arm/translate-a64.c | 86 +-----

target/arm/translate-mve.c | 261 +++++++++++++++-

target/arm/translate-neon.c | 81 -----

target/arm/translate.c | 327 +++++++++++++++++++-

target/arm/vfp_helper.c | 24 +-

hw/misc/meson.build | 1 +

tests/acceptance/boot_linux_console.py | 43 +++

20 files changed, 1760 insertions(+), 209 deletions(-)

create mode 100644 include/hw/misc/bcm2835_powermgt.h

create mode 100644 hw/misc/bcm2835_powermgt.c

From: Patrick Venture <venture@google.com>

Adds a line-item reference to the supported quanta-q71l-bmc aspeed

entry.

Signed-off-by: Patrick Venture <venture@google.com>

Reviewed-by: Cédric Le Goater <clg@kaod.org>

Message-id: 20210615192848.1065297-2-venture@google.com

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

docs/system/arm/aspeed.rst | 1 +

1 file changed, 1 insertion(+)

diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst

index XXXXXXX..XXXXXXX 100644

--- a/docs/system/arm/aspeed.rst

+++ b/docs/system/arm/aspeed.rst

@@ -XXX,XX +XXX,XX @@ etc.

AST2400 SoC based machines :

- ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC

+- ``quanta-q71l-bmc`` OpenBMC Quanta BMC

AST2500 SoC based machines :

--

2.20.1

From: Patrick Venture <venture@google.com>

Add line item reference to quanta-gbs-bmc machine.

Signed-off-by: Patrick Venture <venture@google.com>

Reviewed-by: Cédric Le Goater <clg@kaod.org>

Message-id: 20210615192848.1065297-3-venture@google.com

[PMM: fixed underline Sphinx warning]

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

docs/system/arm/nuvoton.rst | 5 +++--

1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst

index XXXXXXX..XXXXXXX 100644

--- a/docs/system/arm/nuvoton.rst

+++ b/docs/system/arm/nuvoton.rst

@@ -XXX,XX +XXX,XX @@

-Nuvoton iBMC boards (``npcm750-evb``, ``quanta-gsj``)

-=====================================================

+Nuvoton iBMC boards (``*-bmc``, ``npcm750-evb``, ``quanta-gsj``)

+================================================================

The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are

designed to be used as Baseboard Management Controllers (BMCs) in various

@@ -XXX,XX +XXX,XX @@ segment. The following machines are based on this chip :

The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and

Hyperscale applications. The following machines are based on this chip :

+- ``quanta-gbs-bmc`` Quanta GBS server BMC

- ``quanta-gsj`` Quanta GSJ server BMC

There are also two more SoCs, NPCM710 and NPCM705, which are single-core

--

2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Add a test booting and quickly shutdown a raspi2 machine,

to test the power management model:

(1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_raspi2_initrd:

console: [ 0.000000] Booting Linux on physical CPU 0xf00

console: [ 0.000000] Linux version 4.14.98-v7+ (dom@dom-XPS-13-9370) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1200 SMP Tue Feb 12 20:27:48 GMT 2019

console: [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d

console: [ 0.000000] CPU: div instructions available: patching division code

console: [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache

console: [ 0.000000] OF: fdt: Machine model: Raspberry Pi 2 Model B

...

console: Boot successful.

console: cat /proc/cpuinfo

console: / # cat /proc/cpuinfo

...

console: processor : 3

console: model name : ARMv7 Processor rev 5 (v7l)

console: BogoMIPS : 125.00

console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm

console: CPU implementer : 0x41

console: CPU architecture: 7

console: CPU variant : 0x0

console: CPU part : 0xc07

console: CPU revision : 5

console: Hardware : BCM2835

console: Revision : 0000

console: Serial : 0000000000000000

console: cat /proc/iomem

console: / # cat /proc/iomem

console: 00000000-3bffffff : System RAM

console: 00008000-00afffff : Kernel code

console: 00c00000-00d468ef : Kernel data

console: 3f006000-3f006fff : dwc_otg

console: 3f007000-3f007eff : /soc/dma@7e007000

console: 3f00b880-3f00b8bf : /soc/mailbox@7e00b880

console: 3f100000-3f100027 : /soc/watchdog@7e100000

console: 3f101000-3f102fff : /soc/cprman@7e101000

console: 3f200000-3f2000b3 : /soc/gpio@7e200000

PASS (24.59 s)

RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0

JOB TIME : 25.02 s

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>

Message-id: 20210531113837.1689775-1-f4bug@amsat.org

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

tests/acceptance/boot_linux_console.py | 43 ++++++++++++++++++++++++++

1 file changed, 43 insertions(+)

diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py

index XXXXXXX..XXXXXXX 100644

--- a/tests/acceptance/boot_linux_console.py

+++ b/tests/acceptance/boot_linux_console.py

@@ -XXX,XX +XXX,XX @@

from avocado import skip

from avocado import skipUnless

from avocado_qemu import Test

+from avocado_qemu import exec_command

from avocado_qemu import exec_command_and_wait_for_pattern

from avocado_qemu import interrupt_interactive_console_until_pattern

from avocado_qemu import wait_for_console_pattern

@@ -XXX,XX +XXX,XX @@ def test_arm_raspi2_uart0(self):

"""

self.do_test_arm_raspi2(0)

+ def test_arm_raspi2_initrd(self):

+ """

+ :avocado: tags=arch:arm

+ :avocado: tags=machine:raspi2

+ """

+ deb_url = ('http://archive.raspberrypi.org/debian/'

+ 'pool/main/r/raspberrypi-firmware/'

+ 'raspberrypi-kernel_1.20190215-1_armhf.deb')

+ deb_hash = 'cd284220b32128c5084037553db3c482426f3972'

+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)

+ kernel_path = self.extract_from_deb(deb_path, '/boot/kernel7.img')

+ dtb_path = self.extract_from_deb(deb_path, '/boot/bcm2709-rpi-2-b.dtb')

+

+ initrd_url = ('https://github.com/groeck/linux-build-test/raw/'

+ '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'

+ 'arm/rootfs-armv7a.cpio.gz')

+ initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c'

+ initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash)

+ initrd_path = os.path.join(self.workdir, 'rootfs.cpio')

+ archive.gzip_uncompress(initrd_path_gz, initrd_path)

+

+ self.vm.set_console()

+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +

+ 'earlycon=pl011,0x3f201000 console=ttyAMA0 '

+ 'panic=-1 noreboot ' +

+ 'dwc_otg.fiq_fsm_enable=0')

+ self.vm.add_args('-kernel', kernel_path,

+ '-dtb', dtb_path,

+ '-initrd', initrd_path,

+ '-append', kernel_command_line,

+ '-no-reboot')

+ self.vm.launch()

+ self.wait_for_console_pattern('Boot successful.')

+

+ exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',

+ 'BCM2835')

+ exec_command_and_wait_for_pattern(self, 'cat /proc/iomem',

+ '/soc/cprman@7e101000')

+ exec_command(self, 'halt')

+ # Wait for VM to shut down gracefully

+ self.vm.wait()

+

def test_arm_exynos4210_initrd(self):

"""

:avocado: tags=arch:arm

--

2.20.1

Message-id: 20210625111842.3790-3-maxim.uvarov@linaro.org

[PMM: tweaked commit message]

In do_ldst(), the calculation of the offset needs to be based on the

size of the memory access, not the size of the elements in the

vector. This meant we were getting it wrong for the widening and

narrowing variants of the various VLDR and VSTR insns.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20210628135835.6690-2-peter.maydell@linaro.org

---

target/arm/translate-mve.c | 17 +++++++++--------

1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate-mve.c

+++ b/target/arm/translate-mve.c

@@ -XXX,XX +XXX,XX @@ static bool mve_skip_first_beat(DisasContext *s)

}

}

-static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)

+static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn,

+ unsigned msize)

{

TCGv_i32 addr;

uint32_t offset;

@@ -XXX,XX +XXX,XX @@ static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)

return true;

}

- offset = a->imm << a->size;

+ offset = a->imm << msize;

if (!a->a) {

offset = -offset;

}

@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a)

{ gen_helper_mve_vstrw, gen_helper_mve_vldrw },

{ NULL, NULL }

};

- return do_ldst(s, a, ldstfns[a->size][a->l]);

+ return do_ldst(s, a, ldstfns[a->size][a->l], a->size);

}

-#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST) \

+#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST, MSIZE) \

static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a) \

{ \

static MVEGenLdStFn * const ldstfns[2][2] = { \

{ gen_helper_mve_##ST, gen_helper_mve_##SLD }, \

{ NULL, gen_helper_mve_##ULD }, \

}; \

- return do_ldst(s, a, ldstfns[a->u][a->l]); \

+ return do_ldst(s, a, ldstfns[a->u][a->l], MSIZE); \

}

-DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h)

-DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w)

-DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w)

+DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h, MO_8)

+DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w, MO_8)

+DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w, MO_16)

static bool trans_VDUP(DisasContext *s, arg_VDUP *a)

{

--

2.20.1

The initial implementation of the MVE VRMLALDAVH and VRMLSLDAVH

insns had some bugs:

* the 32x32 multiply of elements was being done as 32x32->32,

not 32x32->64

* we were incorrectly maintaining the accumulator in its full

72-bit form across all 4 beats of the insn; in the pseudocode

it is squashed back into the 64 bits of the RdaHi:RdaLo

registers after each beat

In particular, fixing the second of these allows us to recast

the implementation to avoid 128-bit arithmetic entirely.

Since the element size here is always 4, we can also drop the

parameterization of ESIZE to make the code a little more readable.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20210628135835.6690-3-peter.maydell@linaro.org

---

target/arm/mve_helper.c | 38 +++++++++++++++++++++-----------------

1 file changed, 21 insertions(+), 17 deletions(-)

diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/mve_helper.c

+++ b/target/arm/mve_helper.c

@@ -XXX,XX +XXX,XX @@

*/

#include "qemu/osdep.h"

-#include "qemu/int128.h"

#include "cpu.h"

#include "internals.h"

#include "vec_internal.h"

@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=)

DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)

/*

- * Rounding multiply add long dual accumulate high: we must keep

- * a 72-bit internal accumulator value and return the top 64 bits.

+ * Rounding multiply add long dual accumulate high. In the pseudocode

+ * this is implemented with a 72-bit internal accumulator value of which

+ * the top 64 bits are returned. We optimize this to avoid having to

+ * use 128-bit arithmetic -- we can do this because the 74-bit accumulator

+ * is squashed back into 64-bits after each beat.

*/

-#define DO_LDAVH(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC, TO128) \

+#define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB) \

uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \

void *vm, uint64_t a) \

{ \

uint16_t mask = mve_element_mask(env); \

unsigned e; \

TYPE *n = vn, *m = vm; \

- Int128 acc = int128_lshift(TO128(a), 8); \

- for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \

+ for (e = 0; e < 16 / 4; e++, mask >>= 4) { \

if (mask & 1) { \

+ LTYPE mul; \

if (e & 1) { \

- acc = ODDACC(acc, TO128(n[H##ESIZE(e - 1 * XCHG)] * \

- m[H##ESIZE(e)])); \

+ mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)]; \

+ if (SUB) { \

+ mul = -mul; \

+ } \

} else { \

- acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \

- m[H##ESIZE(e)])); \

+ mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)]; \

} \

- acc = int128_add(acc, int128_make64(1 << 7)); \

+ mul = (mul >> 8) + ((mul >> 7) & 1); \

+ a += mul; \

} \

} \

mve_advance_vpt(env); \

- return int128_getlo(int128_rshift(acc, 8)); \

+ return a; \

}

-DO_LDAVH(vrmlaldavhsw, 4, int32_t, false, int128_add, int128_add, int128_makes64)

-DO_LDAVH(vrmlaldavhxsw, 4, int32_t, true, int128_add, int128_add, int128_makes64)

+DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false)

+DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false)

-DO_LDAVH(vrmlaldavhuw, 4, uint32_t, false, int128_add, int128_add, int128_make64)

+DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false)

-DO_LDAVH(vrmlsldavhsw, 4, int32_t, false, int128_add, int128_sub, int128_makes64)

-DO_LDAVH(vrmlsldavhxsw, 4, int32_t, true, int128_add, int128_sub, int128_makes64)

+DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true)

+DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true)

/* Vector add across vector */

#define DO_VADDV(OP, ESIZE, TYPE) \

--

2.20.1

diff --git a/target/arm/translate.h b/target/arm/translate.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate.h

+++ b/target/arm/translate.h

@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)

return opc | s->be_data;

}

+/**

+ * asimd_imm_const: Expand an encoded SIMD constant value

+ *

+ * Expand a SIMD constant value. This is essentially the pseudocode

+ * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for

+ * VMVN and VBIC (when cmode < 14 && op == 1).

+ *

+ * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;

+ * callers must catch this.

+ *

+ * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but

+ * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;

+ * we produce an immediate constant value of 0 in these cases.

+ */

+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);

+

#endif /* TARGET_ARM_TRANSLATE_H */

diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate-neon.c

+++ b/target/arm/translate-neon.c

@@ -XXX,XX +XXX,XX @@ DO_FP_2SH(VCVT_UH, gen_helper_gvec_vcvt_uh)

DO_FP_2SH(VCVT_HS, gen_helper_gvec_vcvt_hs)

DO_FP_2SH(VCVT_HU, gen_helper_gvec_vcvt_hu)

-static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)

-{

- /*

- * Expand the encoded constant.

- * Note that cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.

- * We choose to not special-case this and will behave as if a

- * valid constant encoding of 0 had been given.

- * cmode = 15 op = 1 must UNDEF; we assume decode has handled that.

- */

- switch (cmode) {

- case 0: case 1:

- /* no-op */

- break;

- case 2: case 3:

- imm <<= 8;

- break;

- case 4: case 5:

- imm <<= 16;

- break;

- case 6: case 7:

- imm <<= 24;

- break;

- case 8: case 9:

- imm |= imm << 16;

- break;

- case 10: case 11:

- imm = (imm << 8) | (imm << 24);

- break;

- case 12:

- imm = (imm << 8) | 0xff;

- break;

- case 13:

- imm = (imm << 16) | 0xffff;

- break;

- case 14:

- if (op) {

- /*

- * This is the only case where the top and bottom 32 bits

- * of the encoded constant differ.

- */

- uint64_t imm64 = 0;

- int n;

-

- for (n = 0; n < 8; n++) {

- if (imm & (1 << n)) {

- imm64 |= (0xffULL << (n * 8));

- }

- }

- return imm64;

- }

- imm |= (imm << 8) | (imm << 16) | (imm << 24);

- break;

- case 15:

- imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)

- | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));

- break;

- }

- if (op) {

- imm = ~imm;

- }

- return dup_const(MO_32, imm);

-}

-

static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,

GVecGen2iFn *fn)

{

diff --git a/target/arm/translate.h b/target/arm/translate.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate.h

+++ b/target/arm/translate.h

@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)

* VMVN and VBIC (when cmode < 14 && op == 1).

*

* The combination cmode == 15 op == 1 is a reserved encoding for AArch32;

- * callers must catch this.

+ * callers must catch this; we return the 64-bit constant value defined

+ * for AArch64.

*

* cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but

* is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)

{

int rd = extract32(insn, 0, 5);

int cmode = extract32(insn, 12, 4);

- int cmode_3_1 = extract32(cmode, 1, 3);

- int cmode_0 = extract32(cmode, 0, 1);

int o2 = extract32(insn, 11, 1);

uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5);

bool is_neg = extract32(insn, 29, 1);

@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)

return;

}

- /* See AdvSIMDExpandImm() in ARM ARM */

- switch (cmode_3_1) {

- case 0: /* Replicate(Zeros(24):imm8, 2) */

- case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */

- case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */

- case 3: /* Replicate(imm8:Zeros(24), 2) */

- {

- int shift = cmode_3_1 * 8;

- imm = bitfield_replicate(abcdefgh << shift, 32);

- break;

- }

- case 4: /* Replicate(Zeros(8):imm8, 4) */

- case 5: /* Replicate(imm8:Zeros(8), 4) */

- {

- int shift = (cmode_3_1 & 0x1) * 8;

- imm = bitfield_replicate(abcdefgh << shift, 16);

- break;

- }

- case 6:

- if (cmode_0) {

- /* Replicate(Zeros(8):imm8:Ones(16), 2) */

- imm = (abcdefgh << 16) | 0xffff;

- } else {

- /* Replicate(Zeros(16):imm8:Ones(8), 2) */

- imm = (abcdefgh << 8) | 0xff;

- }

- imm = bitfield_replicate(imm, 32);

- break;

- case 7:

- if (!cmode_0 && !is_neg) {

- imm = bitfield_replicate(abcdefgh, 8);

- } else if (!cmode_0 && is_neg) {

- int i;

- imm = 0;

- for (i = 0; i < 8; i++) {

- if ((abcdefgh) & (1 << i)) {

- imm |= 0xffULL << (i * 8);

- }

- }

- } else if (cmode_0) {

- if (is_neg) {

- imm = (abcdefgh & 0x3f) << 48;

- if (abcdefgh & 0x80) {

- imm |= 0x8000000000000000ULL;

- }

- if (abcdefgh & 0x40) {

- imm |= 0x3fc0000000000000ULL;

- } else {

- imm |= 0x4000000000000000ULL;

- }

- } else {

- if (o2) {

- /* FMOV (vector, immediate) - half-precision */

- imm = vfp_expand_imm(MO_16, abcdefgh);

- /* now duplicate across the lanes */

- imm = bitfield_replicate(imm, 16);

- } else {

- imm = (abcdefgh & 0x3f) << 19;

- if (abcdefgh & 0x80) {

- imm |= 0x80000000;

- }

- if (abcdefgh & 0x40) {

- imm |= 0x3e000000;

- } else {

- imm |= 0x40000000;

- }

- imm |= (imm << 32);

- }

- }

- }

- break;

- default:

- g_assert_not_reached();

- }

-

- if (cmode_3_1 != 7 && is_neg) {

- imm = ~imm;

+ if (cmode == 15 && o2 && !is_neg) {

+ /* FMOV (vector, immediate) - half-precision */

+ imm = vfp_expand_imm(MO_16, abcdefgh);

+ /* now duplicate across the lanes */

+ imm = bitfield_replicate(imm, 16);

+ } else {

+ imm = asimd_imm_const(abcdefgh, cmode, is_neg);

}