Series comparison

-[Qemu-devel] [PULL 00/13] target-arm queue
+[PULL 00/21] target-arm queue
-target-arm queue:
+Arm queue; not huge but I figured I might as well send it out since
- * mostly my latest v8M stuff, plus a couple of minor patches
+I've been doing code review today and there's no queue of unprocessed
 pullreqs...
-The following changes since commit a0b261db8c030813e30a39eae47359ac2a37f7e2:
+thanks
 -- PMM
-  Merge remote-tracking branch 'remotes/ehabkost/tags/python-next-pull-request' into staging (2017-10-12 10:02:09 +0100)
+The following changes since commit b3f846c59d8405bb87c551187721fc92ff2f1b92:
-are available in the git repository at:
+  Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-11v2' into staging (2021-01-11 15:15:35 +0000)
-  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20171012
+are available in the Git repository at:
-for you to fetch changes up to cf5f7937b05c84d5565134f058c00cd48304a117:
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210112
-  nvic: Fix miscalculation of offsets into ITNS array (2017-10-12 16:33:16 +0100)
+for you to fetch changes up to 19d131395ccaf503db21dadd8257e6dc9fc1d7de:
   ui/cocoa: Fix openFile: deprecation on Big Sur (2021-01-12 11:38:37 +0000)
 ----------------------------------------------------------------
 target-arm queue:
- * v8M: SG, BLXNS, secure-return
+ * arm: Support emulation of ARMv8.4-TTST extension
- * v8M: fixes for coverity issues in previous patches
+ * arm: Update cpu.h ID register field definitions
- * arm: fix armv7m_init() declaration to match definition
+ * arm: Fix breakage of XScale instruction emulation
- * watchdog/aspeed: fix variable type to store reload value
+ * hw/net/lan9118: Fix RX Status FIFO PEEK value
  * npcm7xx: Add ADC and PWM emulation
  * ui/cocoa: Make "open docs" help menu entry work again when binary
    is run from the build tree
  * ui/cocoa: Fix openFile: deprecation on Big Sur
  * docs: Add qemu-storage-daemon(1) manpage to meson.build
  * docs: Build and install all the docs in a single manual
 ----------------------------------------------------------------
-Cédric Le Goater (1):
+Hao Wu (6):
-      watchdog/aspeed: fix variable type to store reload value
+      hw/misc: Add clock converter in NPCM7XX CLK module
       hw/timer: Refactor NPCM7XX Timer to use CLK clock
       hw/adc: Add an ADC module for NPCM7XX
       hw/misc: Add a PWM module for NPCM7XX
       hw/misc: Add QTest for NPCM7XX PWM Module
       hw/*: Use type casting for SysBusDevice in NPCM7XX
-Igor Mammedov (1):
+Leif Lindholm (6):
-      arm: fix armv7m_init() declaration to match definition
+      target/arm: fix typo in cpu.h ID_AA64PFR1 field name
       target/arm: make ARMCPU.clidr 64-bit
       target/arm: make ARMCPU.ctr 64-bit
       target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h
       target/arm: add aarch64 ID register fields to cpu.h
       target/arm: add aarch32 ID register fields to cpu.h
-Peter Maydell (11):
+Peter Maydell (5):
-      target/arm: Add M profile secure MMU index values to get_a32_user_mem_index()
+      docs: Add qemu-storage-daemon(1) manpage to meson.build
-      target/arm: Implement SG instruction
+      docs: Build and install all the docs in a single manual
-      target/arm: Implement BLXNS
+      target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns
-      target/arm: Implement secure function return
+      hw/net/lan9118: Fix RX Status FIFO PEEK value
-      target-arm: Don't check for "Thumb2 or M profile" for not-Thumb1
+      hw/net/lan9118: Add symbolic constants for register offsets
       target/arm: Pull Thumb insn word loads up to top level
       target-arm: Simplify insn_crosses_page()
       target/arm: Support some Thumb insns being always unconditional
       target/arm: Implement SG instruction corner cases
       nvic: Add missing 'break'
       nvic: Fix miscalculation of offsets into ITNS array
- include/hw/arm/arm.h     |   2 +-
+Roman Bolshakov (2):
- target/arm/helper.h      |   1 +
+      ui/cocoa: Update path to docs in build tree
- target/arm/internals.h   |   8 ++
+      ui/cocoa: Fix openFile: deprecation on Big Sur
  hw/intc/armv7m_nvic.c    |   5 +-
  hw/watchdog/wdt_aspeed.c |   4 +-
  target/arm/helper.c      | 306 ++++++++++++++++++++++++++++++++++++++++++++--
  target/arm/translate.c   | 310 ++++++++++++++++++++++++++++++++---------------
 files changed, 521 insertions(+), 115 deletions(-)
+Rémi Denis-Courmont (2):
+      target/arm: ARMv8.4-TTST extension
+      target/arm: enable Small Translation tables in max CPU
+ docs/conf.py                     |  46 ++-
+ docs/devel/conf.py               |  15 -
+ docs/index.html.in               |  17 -
+ docs/interop/conf.py             |  28 --
+ docs/meson.build                 |  65 ++--
+ docs/specs/conf.py               |  16 -
+ docs/system/arm/nuvoton.rst      |   4 +-
+ docs/system/conf.py              |  28 --
+ docs/tools/conf.py               |  37 --
+ docs/user/conf.py                |  15 -
+ meson.build                      |   1 +
+ hw/adc/trace.h                   |   1 +
+ include/hw/adc/npcm7xx_adc.h     |  69 ++++
+ include/hw/arm/npcm7xx.h         |   4 +
+ include/hw/misc/npcm7xx_clk.h    | 146 ++++++-
+ include/hw/misc/npcm7xx_pwm.h    | 105 +++++
+ include/hw/timer/npcm7xx_timer.h |   1 +
+ target/arm/cpu.h                 |  85 ++++-
+ hw/adc/npcm7xx_adc.c             | 301 +++++++++++++++
+ hw/arm/npcm7xx.c                 |  55 ++-
+ hw/arm/npcm7xx_boards.c          |   2 +-
+ hw/mem/npcm7xx_mc.c              |   2 +-
+ hw/misc/npcm7xx_clk.c            | 807 ++++++++++++++++++++++++++++++++++++++-
+ hw/misc/npcm7xx_gcr.c            |   2 +-
+ hw/misc/npcm7xx_pwm.c            | 550 ++++++++++++++++++++++++++
+ hw/misc/npcm7xx_rng.c            |   2 +-
+ hw/net/lan9118.c                 |  26 +-
+ hw/nvram/npcm7xx_otp.c           |   2 +-
+ hw/ssi/npcm7xx_fiu.c             |   2 +-
+ hw/timer/npcm7xx_timer.c         |  39 +-
+ target/arm/cpu64.c               |   1 +
+ target/arm/helper.c              |  15 +-
+ target/arm/translate.c           |   7 +
+ tests/qtest/npcm7xx_adc-test.c   | 377 ++++++++++++++++++
+ tests/qtest/npcm7xx_pwm-test.c   | 490 ++++++++++++++++++++++++
+ hw/adc/meson.build               |   1 +
+ hw/adc/trace-events              |   5 +
+ hw/misc/meson.build              |   1 +
+ hw/misc/trace-events             |   6 +
+ tests/qtest/meson.build          |   4 +-
+ ui/cocoa.m                       |   7 +-
+files changed, 3124 insertions(+), 263 deletions(-)
+ delete mode 100644 docs/devel/conf.py
+ delete mode 100644 docs/index.html.in
+ delete mode 100644 docs/interop/conf.py
+ delete mode 100644 docs/specs/conf.py
+ delete mode 100644 docs/system/conf.py
+ delete mode 100644 docs/tools/conf.py
+ delete mode 100644 docs/user/conf.py
+ create mode 100644 hw/adc/trace.h
+ create mode 100644 include/hw/adc/npcm7xx_adc.h
+ create mode 100644 include/hw/misc/npcm7xx_pwm.h
+ create mode 100644 hw/adc/npcm7xx_adc.c
+ create mode 100644 hw/misc/npcm7xx_pwm.c
+ create mode 100644 tests/qtest/npcm7xx_adc-test.c
+ create mode 100644 tests/qtest/npcm7xx_pwm-test.c
+ create mode 100644 hw/adc/trace-events

-[Qemu-devel] [PULL 04/13] target/arm: Implement SG instruction
+[PULL 01/21] target/arm: ARMv8.4-TTST extension
-Implement the SG instruction, which we emulate 'by hand' in the
+From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
 exception handling code path.
+This adds for the Small Translation tables extension in AArch64 state.
+Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 1507556919-24992-3-git-send-email-peter.maydell@linaro.org
 ---
- target/arm/helper.c | 132 ++++++++++++++++++++++++++++++++++++++++++++++++++--
+ target/arm/cpu.h    |  5 +++++
-file changed, 127 insertions(+), 5 deletions(-)
+ target/arm/helper.c | 15 +++++++++++++--
 files changed, 18 insertions(+), 2 deletions(-)
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_uao(const ARMISARegisters *id)
+     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;
+ }
++static inline bool isar_feature_aa64_st(const ARMISARegisters *id)
++{
++    return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0;
++}
++
+ static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
+ {
+     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ typedef struct V8M_SAttributes {
+@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
-     bool irvalid;
+ {
- } V8M_SAttributes;
+     uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
+     bool epd, hpd, using16k, using64k;
-+static void v8m_security_lookup(CPUARMState *env, uint32_t address,
+-    int select, tsz, tbi;
-+                                MMUAccessType access_type, ARMMMUIdx mmu_idx,
++    int select, tsz, tbi, max_tsz;
-+                                V8M_SAttributes *sattrs);
      if (!regime_has_2_ranges(mmu_idx)) {
          select = 0;
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
              hpd = extract64(tcr, 42, 1);
          }
      }
 -    tsz = MIN(tsz, 39);  /* TODO: ARMv8.4-TTST */
 +
- /* Definitions for the PMCCNTR and PMCR registers */
++    if (cpu_isar_feature(aa64_st, env_archcpu(env))) {
- #define PMCRD   0x8
++        max_tsz = 48 - using64k;
- #define PMCRC   0x4
++    } else {
-@@ -XXX,XX +XXX,XX @@ static void arm_log_exception(int idx)
++        max_tsz = 39;
      }
  }
 +static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
 +                               uint32_t addr, uint16_t *insn)
 +{
 +    /* Load a 16-bit portion of a v7M instruction, returning true on success,
 +     * or false on failure (in which case we will have pended the appropriate
 +     * exception).
 +     * We need to do the instruction fetch's MPU and SAU checks
 +     * like this because there is no MMU index that would allow
 +     * doing the load with a single function call. Instead we must
 +     * first check that the security attributes permit the load
 +     * and that they don't mismatch on the two halves of the instruction,
 +     * and then we do the load as a secure load (ie using the security
 +     * attributes of the address, not the CPU, as architecturally required).
 +     */
 +    CPUState *cs = CPU(cpu);
 +    CPUARMState *env = &cpu->env;
 +    V8M_SAttributes sattrs = {};
 +    MemTxAttrs attrs = {};
 +    ARMMMUFaultInfo fi = {};
 +    MemTxResult txres;
 +    target_ulong page_size;
 +    hwaddr physaddr;
 +    int prot;
 +    uint32_t fsr;
 +
 +    v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, &sattrs);
 +    if (!sattrs.nsc || sattrs.ns) {
 +        /* This must be the second half of the insn, and it straddles a
 +         * region boundary with the second half not being S&NSC.
 +         */
 +        env->v7m.sfsr |= R_V7M_SFSR_INVEP_MASK;
 +        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false);
 +        qemu_log_mask(CPU_LOG_INT,
 +                      "...really SecureFault with SFSR.INVEP\n");
 +        return false;
 +    }
 +    if (get_phys_addr(env, addr, MMU_INST_FETCH, mmu_idx,
 +                      &physaddr, &attrs, &prot, &page_size, &fsr, &fi)) {
 +        /* the MPU lookup failed */
 +        env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_IACCVIOL_MASK;
 +        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, env->v7m.secure);
 +        qemu_log_mask(CPU_LOG_INT, "...really MemManage with CFSR.IACCVIOL\n");
 +        return false;
 +    }
 +    *insn = address_space_lduw_le(arm_addressspace(cs, attrs), physaddr,
 +                                 attrs, &txres);
 +    if (txres != MEMTX_OK) {
 +        env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_IBUSERR_MASK;
 +        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false);
 +        qemu_log_mask(CPU_LOG_INT, "...really BusFault with CFSR.IBUSERR\n");
 +        return false;
 +    }
 +    return true;
 +}
 +
 +static bool v7m_handle_execute_nsc(ARMCPU *cpu)
 +{
 +    /* Check whether this attempt to execute code in a Secure & NS-Callable
 +     * memory region is for an SG instruction; if so, then emulate the
 +     * effect of the SG instruction and return true. Otherwise pend
 +     * the correct kind of exception and return false.
 +     */
 +    CPUARMState *env = &cpu->env;
 +    ARMMMUIdx mmu_idx;
 +    uint16_t insn;
 +
 +    /* We should never get here unless get_phys_addr_pmsav8() caused
 +     * an exception for NS executing in S&NSC memory.
 +     */
 +    assert(!env->v7m.secure);
 +    assert(arm_feature(env, ARM_FEATURE_M_SECURITY));
 +
 +    /* We want to do the MPU lookup as secure; work out what mmu_idx that is */
 +    mmu_idx = arm_v7m_mmu_idx_for_secstate(env, true);
 +
 +    if (!v7m_read_half_insn(cpu, mmu_idx, env->regs[15], &insn)) {
 +        return false;
 +    }
 +
-+    if (!env->thumb) {
++    tsz = MIN(tsz, max_tsz);
-+        goto gen_invep;
+     tsz = MAX(tsz, 16);  /* TODO: ARMv8.2-LVA  */
-+    }
      /* Present TBI as a composite with TBID.  */
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
          if (!aarch64 || stride == 9) {
              /* AArch32 or 4KB pages */
              startlevel = 2 - sl0;
 +
-+    if (insn != 0xe97f) {
++            if (cpu_isar_feature(aa64_st, cpu)) {
-+        /* Not an SG instruction first half (we choose the IMPDEF
++                startlevel &= 3;
 +         * early-SG-check option).
 +         */
 +        goto gen_invep;
 +    }
 +
 +    if (!v7m_read_half_insn(cpu, mmu_idx, env->regs[15] + 2, &insn)) {
 +        return false;
 +    }
 +
 +    if (insn != 0xe97f) {
 +        /* Not an SG instruction second half (yes, both halves of the SG
 +         * insn have the same hex value)
 +         */
 +        goto gen_invep;
 +    }
 +
 +    /* OK, we have confirmed that we really have an SG instruction.
 +     * We know we're NS in S memory so don't need to repeat those checks.
 +     */
 +    qemu_log_mask(CPU_LOG_INT, "...really an SG instruction at 0x%08" PRIx32
 +                  ", executing it\n", env->regs[15]);
 +    env->regs[14] &= ~1;
 +    switch_v7m_security_state(env, true);
 +    xpsr_write(env, 0, XPSR_IT);
 +    env->regs[15] += 4;
 +    return true;
 +
 +gen_invep:
 +    env->v7m.sfsr |= R_V7M_SFSR_INVEP_MASK;
 +    armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false);
 +    qemu_log_mask(CPU_LOG_INT,
 +                  "...really SecureFault with SFSR.INVEP\n");
 +    return false;
 +}
 +
  void arm_v7m_cpu_do_interrupt(CPUState *cs)
  {
      ARMCPU *cpu = ARM_CPU(cs);
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
               * the SG instruction have the same security attributes.)
               * Everything else must generate an INVEP SecureFault, so we
               * emulate the SG instruction here.
 -             * TODO: actually emulate SG.
               */
 -            env->v7m.sfsr |= R_V7M_SFSR_INVEP_MASK;
 -            armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false);
 -            qemu_log_mask(CPU_LOG_INT,
 -                          "...really SecureFault with SFSR.INVEP\n");
 +            if (v7m_handle_execute_nsc(cpu)) {
 +                return;
 +            }
-             break;
+         } else {
-         case M_FAKE_FSR_SFAULT:
+             /* 16KB or 64KB pages */
-             /* Various flavours of SecureFault for attempts to execute or
+             startlevel = 3 - sl0;
 --
-.7.4
+.20.1

-New patch
+[PULL 02/21] target/arm: enable Small Translation tables in max CPU
+From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
+Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu64.c | 1 +
+file changed, 1 insertion(+)
+diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu64.c
++++ b/target/arm/cpu64.c
+@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
+         t = cpu->isar.id_aa64mmfr2;
+         t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);
+         t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
++        t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
+         cpu->isar.id_aa64mmfr2 = t;
+         /* Replicate the same data to the 32-bit id registers.  */
+--
+.20.1

-New patch
+[PULL 03/21] target/arm: fix typo in cpu.h ID_AA64PFR1 field name
+From: Leif Lindholm <leif@nuviainc.com>
+SBSS -> SSBS
+Signed-off-by: Leif Lindholm <leif@nuviainc.com>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
+Message-id: 20210108185154.8108-2-leif@nuviainc.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu.h | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64PFR0, RAS, 28, 4)
+ FIELD(ID_AA64PFR0, SVE, 32, 4)
+ FIELD(ID_AA64PFR1, BT, 0, 4)
+-FIELD(ID_AA64PFR1, SBSS, 4, 4)
++FIELD(ID_AA64PFR1, SSBS, 4, 4)
+ FIELD(ID_AA64PFR1, MTE, 8, 4)
+ FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
+--
+.20.1

-New patch
+[PULL 04/21] target/arm: make ARMCPU.clidr 64-bit
+From: Leif Lindholm <leif@nuviainc.com>
+The AArch64 view of CLIDR_EL1 extends the ICB field to include also bit
+, as well as adding a Ttype<n> field when FEAT_MTE is implemented.
+Extend the clidr field to be able to hold this context.
+Signed-off-by: Leif Lindholm <leif@nuviainc.com>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
+Message-id: 20210108185154.8108-3-leif@nuviainc.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu.h | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
+     uint32_t id_afr0;
+     uint64_t id_aa64afr0;
+     uint64_t id_aa64afr1;
+-    uint32_t clidr;
++    uint64_t clidr;
+     uint64_t mp_affinity; /* MP ID without feature bits */
+     /* The elements of this array are the CCSIDR values for each cache,
+      * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
+--
+.20.1

-New patch
+[PULL 05/21] target/arm: make ARMCPU.ctr 64-bit
+From: Leif Lindholm <leif@nuviainc.com>
+When FEAT_MTE is implemented, the AArch64 view of CTR_EL0 adds the
+TminLine field in bits [37:32].
+Extend the ctr field to be able to hold this context.
+Signed-off-by: Leif Lindholm <leif@nuviainc.com>
+Reviewed-by: Hao Wu <wuhaotsh@google.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
+Message-id: 20210108185154.8108-4-leif@nuviainc.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu.h | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
+     uint64_t midr;
+     uint32_t revidr;
+     uint32_t reset_fpsid;
+-    uint32_t ctr;
++    uint64_t ctr;
+     uint32_t reset_sctlr;
+     uint64_t pmceid0;
+     uint64_t pmceid1;
+--
+.20.1

-New patch
+[PULL 06/21] target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h
+From: Leif Lindholm <leif@nuviainc.com>
+Signed-off-by: Leif Lindholm <leif@nuviainc.com>
+Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
+Message-id: 20210108185154.8108-5-leif@nuviainc.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu.h | 31 +++++++++++++++++++++++++++++++
+file changed, 31 insertions(+)
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ FIELD(V7M_FPCCR, ASPEN, 31, 1)
+ /*
+  * System register ID fields.
+  */
++FIELD(CLIDR_EL1, CTYPE1, 0, 3)
++FIELD(CLIDR_EL1, CTYPE2, 3, 3)
++FIELD(CLIDR_EL1, CTYPE3, 6, 3)
++FIELD(CLIDR_EL1, CTYPE4, 9, 3)
++FIELD(CLIDR_EL1, CTYPE5, 12, 3)
++FIELD(CLIDR_EL1, CTYPE6, 15, 3)
++FIELD(CLIDR_EL1, CTYPE7, 18, 3)
++FIELD(CLIDR_EL1, LOUIS, 21, 3)
++FIELD(CLIDR_EL1, LOC, 24, 3)
++FIELD(CLIDR_EL1, LOUU, 27, 3)
++FIELD(CLIDR_EL1, ICB, 30, 3)
++
++/* When FEAT_CCIDX is implemented */
++FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3)
++FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21)
++FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24)
++
++/* When FEAT_CCIDX is not implemented */
++FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
++FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10)
++FIELD(CCSIDR_EL1, NUMSETS, 13, 15)
++
++FIELD(CTR_EL0,  IMINLINE, 0, 4)
++FIELD(CTR_EL0,  L1IP, 14, 2)
++FIELD(CTR_EL0,  DMINLINE, 16, 4)
++FIELD(CTR_EL0,  ERG, 20, 4)
++FIELD(CTR_EL0,  CWG, 24, 4)
++FIELD(CTR_EL0,  IDC, 28, 1)
++FIELD(CTR_EL0,  DIC, 29, 1)
++FIELD(CTR_EL0,  TMINLINE, 32, 6)
++
+ FIELD(MIDR_EL1, REVISION, 0, 4)
+ FIELD(MIDR_EL1, PARTNUM, 4, 12)
+ FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
+--
+.20.1

-New patch
+[PULL 07/21] target/arm: add aarch64 ID register fields to cpu.h
+From: Leif Lindholm <leif@nuviainc.com>
+Add entries present in ARM DDI 0487F.c (August 2020).
+Signed-off-by: Leif Lindholm <leif@nuviainc.com>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
+Message-id: 20210108185154.8108-6-leif@nuviainc.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu.h | 15 +++++++++++++++
+file changed, 15 insertions(+)
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64ISAR1, GPI, 28, 4)
+ FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
+ FIELD(ID_AA64ISAR1, SB, 36, 4)
+ FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
++FIELD(ID_AA64ISAR1, BF16, 44, 4)
++FIELD(ID_AA64ISAR1, DGH, 48, 4)
++FIELD(ID_AA64ISAR1, I8MM, 52, 4)
+ FIELD(ID_AA64PFR0, EL0, 0, 4)
+ FIELD(ID_AA64PFR0, EL1, 4, 4)
+@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
+ FIELD(ID_AA64PFR0, GIC, 24, 4)
+ FIELD(ID_AA64PFR0, RAS, 28, 4)
+ FIELD(ID_AA64PFR0, SVE, 32, 4)
++FIELD(ID_AA64PFR0, SEL2, 36, 4)
++FIELD(ID_AA64PFR0, MPAM, 40, 4)
++FIELD(ID_AA64PFR0, AMU, 44, 4)
++FIELD(ID_AA64PFR0, DIT, 48, 4)
++FIELD(ID_AA64PFR0, CSV2, 56, 4)
++FIELD(ID_AA64PFR0, CSV3, 60, 4)
+ FIELD(ID_AA64PFR1, BT, 0, 4)
+ FIELD(ID_AA64PFR1, SSBS, 4, 4)
+ FIELD(ID_AA64PFR1, MTE, 8, 4)
+ FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
++FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4)
+ FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
+ FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
+@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
+ FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
+ FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
+ FIELD(ID_AA64MMFR0, EXS, 44, 4)
++FIELD(ID_AA64MMFR0, FGT, 56, 4)
++FIELD(ID_AA64MMFR0, ECV, 60, 4)
+ FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
+ FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
+@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR1, LO, 16, 4)
+ FIELD(ID_AA64MMFR1, PAN, 20, 4)
+ FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
+ FIELD(ID_AA64MMFR1, XNX, 28, 4)
++FIELD(ID_AA64MMFR1, TWED, 32, 4)
++FIELD(ID_AA64MMFR1, ETS, 36, 4)
+ FIELD(ID_AA64MMFR2, CNP, 0, 4)
+ FIELD(ID_AA64MMFR2, UAO, 4, 4)
+@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
+ FIELD(ID_AA64DFR0, PMSVER, 32, 4)
+ FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
+ FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
++FIELD(ID_AA64DFR0, MTPMU, 48, 4)
+ FIELD(ID_DFR0, COPDBG, 0, 4)
+ FIELD(ID_DFR0, COPSDBG, 4, 4)
+--
+.20.1

-New patch
+[PULL 08/21] target/arm: add aarch32 ID register fields to cpu.h
+From: Leif Lindholm <leif@nuviainc.com>
+Add entries present in ARM DDI 0487F.c (August 2020).
+Signed-off-by: Leif Lindholm <leif@nuviainc.com>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
+Message-id: 20210108185154.8108-7-leif@nuviainc.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu.h | 28 ++++++++++++++++++++++++++++
+file changed, 28 insertions(+)
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ FIELD(ID_ISAR6, DP, 4, 4)
+ FIELD(ID_ISAR6, FHM, 8, 4)
+ FIELD(ID_ISAR6, SB, 12, 4)
+ FIELD(ID_ISAR6, SPECRES, 16, 4)
++FIELD(ID_ISAR6, BF16, 20, 4)
++FIELD(ID_ISAR6, I8MM, 24, 4)
+ FIELD(ID_MMFR0, VMSA, 0, 4)
+ FIELD(ID_MMFR0, PMSA, 4, 4)
+@@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR0, AUXREG, 20, 4)
+ FIELD(ID_MMFR0, FCSE, 24, 4)
+ FIELD(ID_MMFR0, INNERSHR, 28, 4)
++FIELD(ID_MMFR1, L1HVDVA, 0, 4)
++FIELD(ID_MMFR1, L1UNIVA, 4, 4)
++FIELD(ID_MMFR1, L1HVDSW, 8, 4)
++FIELD(ID_MMFR1, L1UNISW, 12, 4)
++FIELD(ID_MMFR1, L1HVD, 16, 4)
++FIELD(ID_MMFR1, L1UNI, 20, 4)
++FIELD(ID_MMFR1, L1TSTCLN, 24, 4)
++FIELD(ID_MMFR1, BPRED, 28, 4)
++
++FIELD(ID_MMFR2, L1HVDFG, 0, 4)
++FIELD(ID_MMFR2, L1HVDBG, 4, 4)
++FIELD(ID_MMFR2, L1HVDRNG, 8, 4)
++FIELD(ID_MMFR2, HVDTLB, 12, 4)
++FIELD(ID_MMFR2, UNITLB, 16, 4)
++FIELD(ID_MMFR2, MEMBARR, 20, 4)
++FIELD(ID_MMFR2, WFISTALL, 24, 4)
++FIELD(ID_MMFR2, HWACCFLG, 28, 4)
++
+ FIELD(ID_MMFR3, CMAINTVA, 0, 4)
+ FIELD(ID_MMFR3, CMAINTSW, 4, 4)
+ FIELD(ID_MMFR3, BPMAINT, 8, 4)
+@@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR4, LSM, 20, 4)
+ FIELD(ID_MMFR4, CCIDX, 24, 4)
+ FIELD(ID_MMFR4, EVT, 28, 4)
++FIELD(ID_MMFR5, ETS, 0, 4)
++
+ FIELD(ID_PFR0, STATE0, 0, 4)
+ FIELD(ID_PFR0, STATE1, 4, 4)
+ FIELD(ID_PFR0, STATE2, 8, 4)
+@@ -XXX,XX +XXX,XX @@ FIELD(ID_PFR1, SEC_FRAC, 20, 4)
+ FIELD(ID_PFR1, VIRT_FRAC, 24, 4)
+ FIELD(ID_PFR1, GIC, 28, 4)
++FIELD(ID_PFR2, CSV3, 0, 4)
++FIELD(ID_PFR2, SSBS, 4, 4)
++FIELD(ID_PFR2, RAS_FRAC, 8, 4)
++
+ FIELD(ID_AA64ISAR0, AES, 4, 4)
+ FIELD(ID_AA64ISAR0, SHA1, 8, 4)
+ FIELD(ID_AA64ISAR0, SHA2, 12, 4)
+@@ -XXX,XX +XXX,XX @@ FIELD(ID_DFR0, MPROFDBG, 20, 4)
+ FIELD(ID_DFR0, PERFMON, 24, 4)
+ FIELD(ID_DFR0, TRACEFILT, 28, 4)
++FIELD(ID_DFR1, MTPMU, 0, 4)
++
+ FIELD(DBGDIDR, SE_IMP, 12, 1)
+ FIELD(DBGDIDR, NSUHD_IMP, 14, 1)
+ FIELD(DBGDIDR, VERSION, 16, 4)
+--
+.20.1

-[Qemu-devel] [PULL 02/13] arm: fix armv7m_init() declaration to match definition
+[PULL 09/21] ui/cocoa: Update path to docs in build tree
-From: Igor Mammedov <imammedo@redhat.com>
+From: Roman Bolshakov <r.bolshakov@yadro.com>
-s/cpu_model/cpu_type/ that has been forgotten during
+QEMU documentation can't be opened if QEMU is run from build tree
-conversion (ba1ba5cc), while touching the line also
+because executables are placed in the top of build tree after conversion
-fixup alignment.
+to meson.
-Signed-off-by: Igor Mammedov <imammedo@redhat.com>
+Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com>
-Message-id: 1507710805-221721-1-git-send-email-imammedo@redhat.com
+Reported-by: Peter Maydell <peter.maydell@linaro.org>
 Message-id: 20210108213815.64678-1-r.bolshakov@yadro.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/arm/arm.h | 2 +-
+ ui/cocoa.m | 2 +-
 file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h
+diff --git a/ui/cocoa.m b/ui/cocoa.m
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/arm.h
+--- a/ui/cocoa.m
-+++ b/include/hw/arm/arm.h
++++ b/ui/cocoa.m
-@@ -XXX,XX +XXX,XX @@ typedef enum {
+@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
+ - (void) openDocumentation: (NSString *) filename
- /* armv7m.c */
+ {
- DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
+     /* Where to look for local files */
--                      const char *kernel_filename, const char *cpu_model);
+-    NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"../docs/"};
-+                         const char *kernel_filename, const char *cpu_type);
++    NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"docs/"};
- /**
+     NSString *full_file_path;
-  * armv7m_load_kernel:
-  * @cpu: CPU
+     /* iterate thru the possible paths until the file is found */
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 13/13] nvic: Fix miscalculation of offsets into ITNS array
+[PULL 10/21] docs: Add qemu-storage-daemon(1) manpage to meson.build
-This calculation of the first exception vector in
+In commit 1982e1602d15 we added a new qemu-storage-daemon(1) manpage.
-the ITNS<n> register being accessed:
+At the moment new manpages have to be listed both in the conf.py for
-        int startvec = 32 * (offset - 0x380) + NVIC_FIRST_IRQ;
+Sphinx and also in docs/meson.build for Meson. We forgot the second
+of those -- correct the omission.
 is incorrect, because offset is in bytes, so we only want
 to multiply by 8.
 Spotted by Coverity (CID 1381484, CID 1381488), though it is
 not correct that it actually overflows the buffer, because
 we have a 'startvec + i < s->num_irq' guard.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-Message-id: 1507650856-11718-1-git-send-email-peter.maydell@linaro.org
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Message-id: 20210108161416.21129-2-peter.maydell@linaro.org
 ---
- hw/intc/armv7m_nvic.c | 4 ++--
+ docs/meson.build | 1 +
-file changed, 2 insertions(+), 2 deletions(-)
+file changed, 1 insertion(+)
-diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
+diff --git a/docs/meson.build b/docs/meson.build
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/armv7m_nvic.c
+--- a/docs/meson.build
-+++ b/hw/intc/armv7m_nvic.c
++++ b/docs/meson.build
-@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
+@@ -XXX,XX +XXX,XX @@ if build_docs
-         return ((s->num_irq - NVIC_FIRST_IRQ) / 32) - 1;
+         'qemu-img.1': (have_tools ? 'man1' : ''),
-     case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */
+         'qemu-nbd.8': (have_tools ? 'man8' : ''),
-     {
+         'qemu-pr-helper.8': (have_tools ? 'man8' : ''),
--        int startvec = 32 * (offset - 0x380) + NVIC_FIRST_IRQ;
++        'qemu-storage-daemon.1': (have_tools ? 'man1' : ''),
-+        int startvec = 8 * (offset - 0x380) + NVIC_FIRST_IRQ;
+         'qemu-trace-stap.1': (config_host.has_key('CONFIG_TRACE_SYSTEMTAP') ? 'man1' : ''),
-         int i;
+         'virtfs-proxy-helper.1': (have_virtfs_proxy_helper ? 'man1' : ''),
+         'virtiofsd.1': (have_virtiofsd ? 'man1' : ''),
          if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
      switch (offset) {
      case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */
      {
 -        int startvec = 32 * (offset - 0x380) + NVIC_FIRST_IRQ;
 +        int startvec = 8 * (offset - 0x380) + NVIC_FIRST_IRQ;
          int i;
          if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
 --
-.7.4
+.20.1

-New patch
+[PULL 11/21] docs: Build and install all the docs in a single manual
+When we first converted our documentation to Sphinx, we split it into
 multiple manuals (system, interop, tools, etc), which are all built
 separately.  The primary driver for this was wanting to be able to
 avoid shipping the 'devel' manual to end-users.  However, this is
 working against the grain of the way Sphinx wants to be used and
 causes some annoyances:
  * Cross-references between documents become much harder or
    possibly impossible
  * There is no single index to the whole documentation
  * Within one manual there's no links or table-of-contents info
    that lets you easily navigate to the others
  * The devel manual doesn't get published on the QEMU website
    (it would be nice to able to refer to it there)
 Merely hiding our developer documentation from end users seems like
 it's not enough benefit for these costs.  Combine all the
 documentation into a single manual (the same way that the readthedocs
 site builds it) and install the whole thing.  The previous manual
 divisions remain as the new top level sections in the manual.
  * The per-manual conf.py files are no longer needed
  * The man_pages[] specifications previously in each per-manual
    conf.py move to the top level conf.py
  * docs/meson.build logic is simplified as we now only need to run
    Sphinx once for the HTML and then once for the manpages5B
  * The old index.html.in that produced the top-level page with
    links to each manual is no longer needed
 Unfortunately this means that we now have to build the HTML
 documentation into docs/manual in the build tree rather than directly
 into docs/; otherwise it is too awkward to ensure we install only the
 built manual and not also the dependency info, stamp file, etc.  The
 manual still ends up in the same place in the final installed
 directory, but anybody who was consulting documentation from within
 the build tree will have to adjust where they're looking.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
 Message-id: 20210108161416.21129-3-peter.maydell@linaro.org
 ---
  docs/conf.py         | 46 ++++++++++++++++++++++++++++++-
  docs/devel/conf.py   | 15 -----------
  docs/index.html.in   | 17 ------------
  docs/interop/conf.py | 28 -------------------
  docs/meson.build     | 64 +++++++++++++++++---------------------------
  docs/specs/conf.py   | 16 -----------
  docs/system/conf.py  | 28 -------------------
  docs/tools/conf.py   | 37 -------------------------
  docs/user/conf.py    | 15 -----------
 files changed, 70 insertions(+), 196 deletions(-)
  delete mode 100644 docs/devel/conf.py
  delete mode 100644 docs/index.html.in
  delete mode 100644 docs/interop/conf.py
  delete mode 100644 docs/specs/conf.py
  delete mode 100644 docs/system/conf.py
  delete mode 100644 docs/tools/conf.py
  delete mode 100644 docs/user/conf.py
 diff --git a/docs/conf.py b/docs/conf.py
 index XXXXXXX..XXXXXXX 100644
 --- a/docs/conf.py
 +++ b/docs/conf.py
@@ -XXX,XX +XXX,XX @@ latex_documents = [
  # -- Options for manual page output ---------------------------------------
  # Individual manual/conf.py can override this to create man pages
 -man_pages = []
 +man_pages = [
 +    ('interop/qemu-ga', 'qemu-ga',
 +     'QEMU Guest Agent',
 +     ['Michael Roth <mdroth@linux.vnet.ibm.com>'], 8),
 +    ('interop/qemu-ga-ref', 'qemu-ga-ref',
 +     'QEMU Guest Agent Protocol Reference',
 +     [], 7),
 +    ('interop/qemu-qmp-ref', 'qemu-qmp-ref',
 +     'QEMU QMP Reference Manual',
 +     [], 7),
 +    ('interop/qemu-storage-daemon-qmp-ref', 'qemu-storage-daemon-qmp-ref',
 +     'QEMU Storage Daemon QMP Reference Manual',
 +     [], 7),
 +    ('system/qemu-manpage', 'qemu',
 +     'QEMU User Documentation',
 +     ['Fabrice Bellard'], 1),
 +    ('system/qemu-block-drivers', 'qemu-block-drivers',
 +     'QEMU block drivers reference',
 +     ['Fabrice Bellard and the QEMU Project developers'], 7),
 +    ('system/qemu-cpu-models', 'qemu-cpu-models',
 +     'QEMU CPU Models',
 +     ['The QEMU Project developers'], 7),
 +    ('tools/qemu-img', 'qemu-img',
 +     'QEMU disk image utility',
 +     ['Fabrice Bellard'], 1),
 +    ('tools/qemu-nbd', 'qemu-nbd',
 +     'QEMU Disk Network Block Device Server',
 +     ['Anthony Liguori <anthony@codemonkey.ws>'], 8),
 +    ('tools/qemu-pr-helper', 'qemu-pr-helper',
 +     'QEMU persistent reservation helper',
 +     [], 8),
 +    ('tools/qemu-storage-daemon', 'qemu-storage-daemon',
 +     'QEMU storage daemon',
 +     [], 1),
 +    ('tools/qemu-trace-stap', 'qemu-trace-stap',
 +     'QEMU SystemTap trace tool',
 +     [], 1),
 +    ('tools/virtfs-proxy-helper', 'virtfs-proxy-helper',
 +     'QEMU 9p virtfs proxy filesystem helper',
 +     ['M. Mohan Kumar'], 1),
 +    ('tools/virtiofsd', 'virtiofsd',
 +     'QEMU virtio-fs shared file system daemon',
 +     ['Stefan Hajnoczi <stefanha@redhat.com>',
 +      'Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>'], 1),
 +]
  # -- Options for Texinfo output -------------------------------------------
 diff --git a/docs/devel/conf.py b/docs/devel/conf.py
 deleted file mode 100644
 index XXXXXXX..XXXXXXX
 --- a/docs/devel/conf.py
 +++ /dev/null
@@ -XXX,XX +XXX,XX @@
 -# -*- coding: utf-8 -*-
 -#
 -# QEMU documentation build configuration file for the 'devel' manual.
 -#
 -# This includes the top level conf file and then makes any necessary tweaks.
 -import sys
 -import os
 -
 -qemu_docdir = os.path.abspath("..")
 -parent_config = os.path.join(qemu_docdir, "conf.py")
 -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
 -
 -# This slightly misuses the 'description', but is the best way to get
 -# the manual title to appear in the sidebar.
 -html_theme_options['description'] = u'Developer''s Guide'
 diff --git a/docs/index.html.in b/docs/index.html.in
 deleted file mode 100644
 index XXXXXXX..XXXXXXX
 --- a/docs/index.html.in
 +++ /dev/null
@@ -XXX,XX +XXX,XX @@
 -<!DOCTYPE html>
 -<html lang="en">
 -    <head>
 -        <meta charset="UTF-8">
 -        <title>QEMU @VERSION@ Documentation</title>
 -    </head>
 -    <body>
 -        <h1>QEMU @VERSION@ Documentation</h1>
 -        <ul>
 -            <li><a href="system/index.html">System Emulation User's Guide</a></li>
 -            <li><a href="user/index.html">User Mode Emulation User's Guide</a></li>
 -            <li><a href="tools/index.html">Tools Guide</a></li>
 -            <li><a href="interop/index.html">System Emulation Management and Interoperability Guide</a></li>
 -            <li><a href="specs/index.html">System Emulation Guest Hardware Specifications</a></li>
 -        </ul>
 -    </body>
 -</html>
 diff --git a/docs/interop/conf.py b/docs/interop/conf.py
 deleted file mode 100644
 index XXXXXXX..XXXXXXX
 --- a/docs/interop/conf.py
 +++ /dev/null
@@ -XXX,XX +XXX,XX @@
 -# -*- coding: utf-8 -*-
 -#
 -# QEMU documentation build configuration file for the 'interop' manual.
 -#
 -# This includes the top level conf file and then makes any necessary tweaks.
 -import sys
 -import os
 -
 -qemu_docdir = os.path.abspath("..")
 -parent_config = os.path.join(qemu_docdir, "conf.py")
 -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
 -
 -# This slightly misuses the 'description', but is the best way to get
 -# the manual title to appear in the sidebar.
 -html_theme_options['description'] = u'System Emulation Management and Interoperability Guide'
 -
 -# One entry per manual page. List of tuples
 -# (source start file, name, description, authors, manual section).
 -man_pages = [
 -    ('qemu-ga', 'qemu-ga', u'QEMU Guest Agent',
 -     ['Michael Roth <mdroth@linux.vnet.ibm.com>'], 8),
 -    ('qemu-ga-ref', 'qemu-ga-ref', 'QEMU Guest Agent Protocol Reference',
 -     [], 7),
 -    ('qemu-qmp-ref', 'qemu-qmp-ref', 'QEMU QMP Reference Manual',
 -     [], 7),
 -    ('qemu-storage-daemon-qmp-ref', 'qemu-storage-daemon-qmp-ref',
 -     'QEMU Storage Daemon QMP Reference Manual', [], 7),
 -]
 diff --git a/docs/meson.build b/docs/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/docs/meson.build
 +++ b/docs/meson.build
@@ -XXX,XX +XXX,XX @@ if build_docs
                            meson.source_root() / 'docs/sphinx/qmp_lexer.py',
                            qapi_gen_depends ]
 -  configure_file(output: 'index.html',
 -                 input: files('index.html.in'),
 -                 configuration: {'VERSION': meson.project_version()},
 -                 install_dir: qemu_docdir)
 -  manuals = [ 'devel', 'interop', 'tools', 'specs', 'system', 'user' ]
    man_pages = {
 -    'interop' : {
          'qemu-ga.8': (have_tools ? 'man8' : ''),
          'qemu-ga-ref.7': 'man7',
          'qemu-qmp-ref.7': 'man7',
          'qemu-storage-daemon-qmp-ref.7': (have_tools ? 'man7' : ''),
 -    },
 -    'tools': {
          'qemu-img.1': (have_tools ? 'man1' : ''),
          'qemu-nbd.8': (have_tools ? 'man8' : ''),
          'qemu-pr-helper.8': (have_tools ? 'man8' : ''),
@@ -XXX,XX +XXX,XX @@ if build_docs
          'qemu-trace-stap.1': (config_host.has_key('CONFIG_TRACE_SYSTEMTAP') ? 'man1' : ''),
          'virtfs-proxy-helper.1': (have_virtfs_proxy_helper ? 'man1' : ''),
          'virtiofsd.1': (have_virtiofsd ? 'man1' : ''),
 -    },
 -    'system': {
          'qemu.1': 'man1',
          'qemu-block-drivers.7': 'man7',
          'qemu-cpu-models.7': 'man7'
 -    },
    }
    sphinxdocs = []
    sphinxmans = []
 -  foreach manual : manuals
 -    private_dir = meson.current_build_dir() / (manual + '.p')
 -    output_dir = meson.current_build_dir() / manual
 -    input_dir = meson.current_source_dir() / manual
 -    this_manual = custom_target(manual + ' manual',
 +  private_dir = meson.current_build_dir() / 'manual.p'
 +  output_dir = meson.current_build_dir() / 'manual'
 +  input_dir = meson.current_source_dir()
 +
 +  this_manual = custom_target('QEMU manual',
                  build_by_default: build_docs,
 -                output: [manual + '.stamp'],
 -                input: [files('conf.py'), files(manual / 'conf.py')],
 -                depfile: manual + '.d',
 +                output: 'docs.stamp',
 +                input: files('conf.py'),
 +                depfile: 'docs.d',
                  depend_files: sphinx_extn_depends,
                  command: [SPHINX_ARGS, '-Ddepfile=@DEPFILE@',
                            '-Ddepfile_stamp=@OUTPUT0@',
                            '-b', 'html', '-d', private_dir,
                            input_dir, output_dir])
 -    sphinxdocs += this_manual
 -    if build_docs and manual != 'devel'
 -      install_subdir(output_dir, install_dir: qemu_docdir)
 -    endif
 +  sphinxdocs += this_manual
 +  install_subdir(output_dir, install_dir: qemu_docdir, strip_directory: true)
 -    these_man_pages = []
 -    install_dirs = []
 -    foreach page, section : man_pages.get(manual, {})
 -      these_man_pages += page
 -      install_dirs += section == '' ? false : get_option('mandir') / section
 -    endforeach
 -    if these_man_pages.length() > 0
 -      sphinxmans += custom_target(manual + ' man pages',
 -                         build_by_default: build_docs,
 -                         output: these_man_pages,
 -                         input: this_manual,
 -                         install: build_docs,
 -                         install_dir: install_dirs,
 -                         command: [SPHINX_ARGS, '-b', 'man', '-d', private_dir,
 -                                   input_dir, meson.current_build_dir()])
 -    endif
 +  these_man_pages = []
 +  install_dirs = []
 +  foreach page, section : man_pages
 +    these_man_pages += page
 +    install_dirs += section == '' ? false : get_option('mandir') / section
    endforeach
 +
 +  sphinxmans += custom_target('QEMU man pages',
 +                              build_by_default: build_docs,
 +                              output: these_man_pages,
 +                              input: this_manual,
 +                              install: build_docs,
 +                              install_dir: install_dirs,
 +                              command: [SPHINX_ARGS, '-b', 'man', '-d', private_dir,
 +                                        input_dir, meson.current_build_dir()])
 +
    alias_target('sphinxdocs', sphinxdocs)
    alias_target('html', sphinxdocs)
    alias_target('man', sphinxmans)
 diff --git a/docs/specs/conf.py b/docs/specs/conf.py
 deleted file mode 100644
 index XXXXXXX..XXXXXXX
 --- a/docs/specs/conf.py
 +++ /dev/null
@@ -XXX,XX +XXX,XX @@
 -# -*- coding: utf-8 -*-
 -#
 -# QEMU documentation build configuration file for the 'specs' manual.
 -#
 -# This includes the top level conf file and then makes any necessary tweaks.
 -import sys
 -import os
 -
 -qemu_docdir = os.path.abspath("..")
 -parent_config = os.path.join(qemu_docdir, "conf.py")
 -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
 -
 -# This slightly misuses the 'description', but is the best way to get
 -# the manual title to appear in the sidebar.
 -html_theme_options['description'] = \
 -    u'System Emulation Guest Hardware Specifications'
 diff --git a/docs/system/conf.py b/docs/system/conf.py
 deleted file mode 100644
 index XXXXXXX..XXXXXXX
 --- a/docs/system/conf.py
 +++ /dev/null
@@ -XXX,XX +XXX,XX @@
 -# -*- coding: utf-8 -*-
 -#
 -# QEMU documentation build configuration file for the 'system' manual.
 -#
 -# This includes the top level conf file and then makes any necessary tweaks.
 -import sys
 -import os
 -
 -qemu_docdir = os.path.abspath("..")
 -parent_config = os.path.join(qemu_docdir, "conf.py")
 -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
 -
 -# This slightly misuses the 'description', but is the best way to get
 -# the manual title to appear in the sidebar.
 -html_theme_options['description'] = u'System Emulation User''s Guide'
 -
 -# One entry per manual page. List of tuples
 -# (source start file, name, description, authors, manual section).
 -man_pages = [
 -    ('qemu-manpage', 'qemu', u'QEMU User Documentation',
 -     ['Fabrice Bellard'], 1),
 -    ('qemu-block-drivers', 'qemu-block-drivers',
 -     u'QEMU block drivers reference',
 -     ['Fabrice Bellard and the QEMU Project developers'], 7),
 -    ('qemu-cpu-models', 'qemu-cpu-models',
 -     u'QEMU CPU Models',
 -     ['The QEMU Project developers'], 7)
 -]
 diff --git a/docs/tools/conf.py b/docs/tools/conf.py
 deleted file mode 100644
 index XXXXXXX..XXXXXXX
 --- a/docs/tools/conf.py
 +++ /dev/null
@@ -XXX,XX +XXX,XX @@
 -# -*- coding: utf-8 -*-
 -#
 -# QEMU documentation build configuration file for the 'tools' manual.
 -#
 -# This includes the top level conf file and then makes any necessary tweaks.
 -import sys
 -import os
 -
 -qemu_docdir = os.path.abspath("..")
 -parent_config = os.path.join(qemu_docdir, "conf.py")
 -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
 -
 -# This slightly misuses the 'description', but is the best way to get
 -# the manual title to appear in the sidebar.
 -html_theme_options['description'] = \
 -    u'Tools Guide'
 -
 -# One entry per manual page. List of tuples
 -# (source start file, name, description, authors, manual section).
 -man_pages = [
 -    ('qemu-img', 'qemu-img', u'QEMU disk image utility',
 -     ['Fabrice Bellard'], 1),
 -    ('qemu-storage-daemon', 'qemu-storage-daemon', u'QEMU storage daemon',
 -     [], 1),
 -    ('qemu-nbd', 'qemu-nbd', u'QEMU Disk Network Block Device Server',
 -     ['Anthony Liguori <anthony@codemonkey.ws>'], 8),
 -    ('qemu-pr-helper', 'qemu-pr-helper', 'QEMU persistent reservation helper',
 -     [], 8),
 -    ('qemu-trace-stap', 'qemu-trace-stap', u'QEMU SystemTap trace tool',
 -     [], 1),
 -    ('virtfs-proxy-helper', 'virtfs-proxy-helper',
 -     u'QEMU 9p virtfs proxy filesystem helper',
 -     ['M. Mohan Kumar'], 1),
 -    ('virtiofsd', 'virtiofsd', u'QEMU virtio-fs shared file system daemon',
 -     ['Stefan Hajnoczi <stefanha@redhat.com>',
 -      'Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>'], 1),
 -]
 diff --git a/docs/user/conf.py b/docs/user/conf.py
 deleted file mode 100644
 index XXXXXXX..XXXXXXX
 --- a/docs/user/conf.py
 +++ /dev/null
@@ -XXX,XX +XXX,XX @@
 -# -*- coding: utf-8 -*-
 -#
 -# QEMU documentation build configuration file for the 'user' manual.
 -#
 -# This includes the top level conf file and then makes any necessary tweaks.
 -import sys
 -import os
 -
 -qemu_docdir = os.path.abspath("..")
 -parent_config = os.path.join(qemu_docdir, "conf.py")
 -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
 -
 -# This slightly misuses the 'description', but is the best way to get
 -# the manual title to appear in the sidebar.
 -html_theme_options['description'] = u'User Mode Emulation User''s Guide'
 --
 .20.1

-[Qemu-devel] [PULL 10/13] target/arm: Support some Thumb insns being always unconditional
+[PULL 12/21] target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns
-A few Thumb instructions are always unconditional even inside an
+In commit cd8be50e58f63413c0 we converted the A32 coprocessor
-IT block (as opposed to being UNPREDICTABLE if used inside an
+insns to decodetree. This accidentally broke XScale/iWMMXt insns,
-IT block): BKPT, the v8M SG instruction, and the A profile
+because it moved the handling of "cp insns which are handled
-HLT (debug halt) instruction.
+by looking up the cp register in the hashtable" from after the
 call to the legacy disas_xscale_insn() decode to before it,
 with the result that all XScale/iWMMXt insns now UNDEF.
-This means we need to suppress the jump-over-instruction-on-condfail
+Update valid_cp() so that it knows that on XScale cp 0 and 1
-code generation (though the IT state still advances as usual and
+are not standard coprocessor instructions; this will cause
-subsequent insns in the IT block may be conditional).
+the decodetree trans_ functions to ignore them, so that
 execution will correctly get through to the legacy decode again.
+Cc: qemu-stable@nongnu.org
+Reported-by: Guenter Roeck <linux@roeck-us.net>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 1507556919-24992-9-git-send-email-peter.maydell@linaro.org
+Tested-by: Guenter Roeck <linux@roeck-us.net>
 Message-id: 20210108195157.32067-1-peter.maydell@linaro.org
 ---
- target/arm/translate.c | 48 +++++++++++++++++++++++++++++++++++++++++++++++-
+ target/arm/translate.c | 7 +++++++
-file changed, 47 insertions(+), 1 deletion(-)
+file changed, 7 insertions(+)
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
+@@ -XXX,XX +XXX,XX @@ static bool valid_cp(DisasContext *s, int cp)
-        in init_disas_context by adjusting max_insns.  */
+      * only cp14 and cp15 are valid, and other values aren't considered
- }
+      * to be in the coprocessor-instruction space at all. v8M still
+      * permits coprocessors 0..7.
-+static bool thumb_insn_is_unconditional(DisasContext *s, uint32_t insn)
++     * For XScale, we must not decode the XScale cp0, cp1 space as
-+{
++     * a standard coprocessor insn, because we want to fall through to
-+    /* Return true if this Thumb insn is always unconditional,
++     * the legacy disas_xscale_insn() decoder after decodetree is done.
-+     * even inside an IT block. This is true of only a very few
+      */
-+     * instructions: BKPT, HLT, and SG.
++    if (arm_dc_feature(s, ARM_FEATURE_XSCALE) && (cp == 0 || cp == 1)) {
-+     *
++        return false;
 +     * A larger class of instructions are UNPREDICTABLE if used
 +     * inside an IT block; we do not need to detect those here, because
 +     * what we do by default (perform the cc check and update the IT
 +     * bits state machine) is a permitted CONSTRAINED UNPREDICTABLE
 +     * choice for those situations.
 +     *
 +     * insn is either a 16-bit or a 32-bit instruction; the two are
 +     * distinguishable because for the 16-bit case the top 16 bits
 +     * are zeroes, and that isn't a valid 32-bit encoding.
 +     */
 +    if ((insn & 0xffffff00) == 0xbe00) {
 +        /* BKPT */
 +        return true;
 +    }
 +
-+    if ((insn & 0xffffffc0) == 0xba80 && arm_dc_feature(s, ARM_FEATURE_V8) &&
+     if (arm_dc_feature(s, ARM_FEATURE_V8) &&
-+        !arm_dc_feature(s, ARM_FEATURE_M)) {
+         !arm_dc_feature(s, ARM_FEATURE_M)) {
-+        /* HLT: v8A only. This is unconditional even when it is going to
+         return cp >= 14;
 +         * UNDEF; see the v8A ARM ARM DDI0487B.a H3.3.
 +         * For v7 cores this was a plain old undefined encoding and so
 +         * honours its cc check. (We might be using the encoding as
 +         * a semihosting trap, but we don't change the cc check behaviour
 +         * on that account, because a debugger connected to a real v7A
 +         * core and emulating semihosting traps by catching the UNDEF
 +         * exception would also only see cases where the cc check passed.
 +         * No guest code should be trying to do a HLT semihosting trap
 +         * in an IT block anyway.
 +         */
 +        return true;
 +    }
 +
 +    if (insn == 0xe97fe97f && arm_dc_feature(s, ARM_FEATURE_V8) &&
 +        arm_dc_feature(s, ARM_FEATURE_M)) {
 +        /* SG: v8M only */
 +        return true;
 +    }
 +
 +    return false;
 +}
 +
  static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
  {
      DisasContext *dc = container_of(dcbase, DisasContext, base);
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
          dc->pc += 2;
      }
 -    if (dc->condexec_mask) {
 +    if (dc->condexec_mask && !thumb_insn_is_unconditional(dc, insn)) {
          uint32_t cond = dc->condexec_cond;
          if (cond != 0x0e) {     /* Skip conditional when condition is AL. */
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 12/13] nvic: Add missing 'break'
+[PULL 13/21] hw/net/lan9118: Fix RX Status FIFO PEEK value
-Coverity points out that we forgot the 'break' for
+A copy-and-paste error meant that the return value for register offset 0x44
-the SAU_CTRL write case (CID1381683). This has
+(the RX Status FIFO PEEK register) returned a byte from a bogus offset in
-no actual visible consequences because it happens
+the rx status FIFO. Fix the typo.
 that the following case is effectively a no-op.
+Cc: qemu-stable@nongnu.org
+Fixes: https://bugs.launchpad.net/qemu/+bug/1904954
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 1507742676-9908-1-git-send-email-peter.maydell@linaro.org
+Message-id: 20210108180401.2263-2-peter.maydell@linaro.org
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- hw/intc/armv7m_nvic.c | 1 +
+ hw/net/lan9118.c | 2 +-
-file changed, 1 insertion(+)
+file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
+diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/armv7m_nvic.c
+--- a/hw/net/lan9118.c
-+++ b/hw/intc/armv7m_nvic.c
++++ b/hw/net/lan9118.c
-@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
+@@ -XXX,XX +XXX,XX @@ static uint64_t lan9118_readl(void *opaque, hwaddr offset,
-             return;
+     case 0x40:
-         }
+         return rx_status_fifo_pop(s);
-         cpu->env.sau.ctrl = value & 3;
+     case 0x44:
-+        break;
+-        return s->rx_status_fifo[s->tx_status_fifo_head];
-     case 0xdd4: /* SAU_TYPE */
++        return s->rx_status_fifo[s->rx_status_fifo_head];
-         if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
+     case 0x48:
-             goto bad_offset;
+         return tx_status_fifo_pop(s);
      case 0x4c:
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 11/13] target/arm: Implement SG instruction corner cases
+[PULL 14/21] hw/net/lan9118: Add symbolic constants for register offsets
-The common situation of the SG instruction is that it is
+The lan9118 code mostly uses symbolic constants for register offsets;
-executed from S&NSC memory by a CPU in NS state. That case
+the exceptions are those which the datasheet doesn't give an official
-is handled by v7m_handle_execute_nsc(). However the instruction
+symbolic name to.
 also has defined behaviour in a couple of other cases:
  * SG instruction in NS memory (behaves as a NOP)
  * SG in S memory but CPU already secure (clears IT bits and
    does nothing else)
  * SG instruction in v8M without Security Extension (NOP)
-These can be implemented in translate.c.
+Add some names for the registers which don't already have them, based
 on the longer names they are given in the memory map.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 1507556919-24992-10-git-send-email-peter.maydell@linaro.org
+Message-id: 20210108180401.2263-3-peter.maydell@linaro.org
 ---
- target/arm/translate.c | 23 ++++++++++++++++++++++-
+ hw/net/lan9118.c | 24 ++++++++++++++++++------
-file changed, 22 insertions(+), 1 deletion(-)
+file changed, 18 insertions(+), 6 deletions(-)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
+diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
+--- a/hw/net/lan9118.c
-+++ b/target/arm/translate.c
++++ b/hw/net/lan9118.c
-@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(DisasContext *s, uint32_t insn)
+@@ -XXX,XX +XXX,XX @@ do { hw_error("lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
-              * - load/store doubleword, load/store exclusive, ldacq/strel,
+ do { fprintf(stderr, "lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
-              *   table branch.
+ #endif
-              */
--            if (insn & 0x01200000) {
++/* The tx and rx fifo ports are a range of aliased 32-bit registers */
-+            if (insn == 0xe97fe97f && arm_dc_feature(s, ARM_FEATURE_M) &&
++#define RX_DATA_FIFO_PORT_FIRST 0x00
-+                arm_dc_feature(s, ARM_FEATURE_V8)) {
++#define RX_DATA_FIFO_PORT_LAST 0x1f
-+                /* 0b1110_1001_0111_1111_1110_1001_0111_111
++#define TX_DATA_FIFO_PORT_FIRST 0x20
-+                 *  - SG (v8M only)
++#define TX_DATA_FIFO_PORT_LAST 0x3f
-+                 * The bulk of the behaviour for this instruction is implemented
++
-+                 * in v7m_handle_execute_nsc(), which deals with the insn when
++#define RX_STATUS_FIFO_PORT 0x40
-+                 * it is executed by a CPU in non-secure state from memory
++#define RX_STATUS_FIFO_PEEK 0x44
-+                 * which is Secure & NonSecure-Callable.
++#define TX_STATUS_FIFO_PORT 0x48
-+                 * Here we only need to handle the remaining cases:
++#define TX_STATUS_FIFO_PEEK 0x4c
-+                 *  * in NS memory (including the "security extension not
++
-+                 *    implemented" case) : NOP
+ #define CSR_ID_REV      0x50
-+                 *  * in S memory but CPU already secure (clear IT bits)
+ #define CSR_IRQ_CFG     0x54
-+                 * We know that the attribute for the memory this insn is
+ #define CSR_INT_STS     0x58
-+                 * in must match the current CPU state, because otherwise
+@@ -XXX,XX +XXX,XX @@ static void lan9118_writel(void *opaque, hwaddr offset,
-+                 * get_phys_addr_pmsav8 would have generated an exception.
+     offset &= 0xff;
-+                 */
-+                if (s->v8m_secure) {
+     //DPRINTF("Write reg 0x%02x = 0x%08x\n", (int)offset, val);
-+                    /* Like the IT insn, we don't need to generate any code */
+-    if (offset >= 0x20 && offset < 0x40) {
-+                    s->condexec_cond = 0;
++    if (offset >= TX_DATA_FIFO_PORT_FIRST &&
-+                    s->condexec_mask = 0;
++        offset <= TX_DATA_FIFO_PORT_LAST) {
-+                }
+         /* TX FIFO */
-+            } else if (insn & 0x01200000) {
+         tx_fifo_push(s, val);
-                 /* 0b1110_1000_x11x_xxxx_xxxx_xxxx_xxxx_xxxx
+         return;
-                  *  - load/store dual (post-indexed)
+@@ -XXX,XX +XXX,XX @@ static uint64_t lan9118_readl(void *opaque, hwaddr offset,
-                  * 0b1111_1001_x10x_xxxx_xxxx_xxxx_xxxx_xxxx
+     lan9118_state *s = (lan9118_state *)opaque;
      //DPRINTF("Read reg 0x%02x\n", (int)offset);
 -    if (offset < 0x20) {
 +    if (offset <= RX_DATA_FIFO_PORT_LAST) {
          /* RX FIFO */
          return rx_fifo_pop(s);
      }
      switch (offset) {
 -    case 0x40:
 +    case RX_STATUS_FIFO_PORT:
          return rx_status_fifo_pop(s);
 -    case 0x44:
 +    case RX_STATUS_FIFO_PEEK:
          return s->rx_status_fifo[s->rx_status_fifo_head];
 -    case 0x48:
 +    case TX_STATUS_FIFO_PORT:
          return tx_status_fifo_pop(s);
 -    case 0x4c:
 +    case TX_STATUS_FIFO_PEEK:
          return s->tx_status_fifo[s->tx_status_fifo_head];
      case CSR_ID_REV:
          return 0x01180001;
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 08/13] target/arm: Pull Thumb insn word loads up to top level
+[PULL 15/21] hw/misc: Add clock converter in NPCM7XX CLK module
-Refactor the Thumb decode to do the loads of the instruction words at
+From: Hao Wu <wuhaotsh@google.com>
 the top level rather than only loading the second half of a 32-bit
 Thumb insn in the middle of the decode.
-This is simple apart from the awkward case of Thumb1, where the
+This patch allows NPCM7XX CLK module to compute clocks that are used by
-BL/BLX prefix and suffix instructions live in what in Thumb2 is the
+other NPCM7XX modules.
 -bit insn space.  To handle these we decode enough to identify
 whether we're looking at a prefix/suffix that we handle as a 16 bit
 insn, or a prefix that we're going to merge with the following suffix
 to consider as a 32 bit insn.  The translation of the 16 bit cases
 then moves from disas_thumb2_insn() to disas_thumb_insn().
-The refactoring has the benefit that we don't need to pass the
+Add a new struct NPCM7xxClockConverterState which represents a
-CPUARMState* down into the decoder code any more, but the major
+single converter.  Each clock converter in CLK module represents one
-reason for doing this is that some Thumb instructions must be always
+converter in NPCM7XX CLK Module(PLL, SEL or Divider). Each converter
-unconditional regardless of the IT state bits, so we need to know the
+takes one or more input clocks and converts them into one output clock.
-whole insn before we emit the "skip this insn if the IT bits and cond
+They form a clock hierarchy in the CLK module and are responsible for
-state tell us to" code.  (The always unconditional insns are BKPT,
+outputing clocks for various other modules in an NPCM7XX SoC.
 HLT and SG; the last of these is 32 bits.)
+Each converter has a function pointer called "convert" which represents
+the unique logic for that converter.
+The clock contains two initialization information: ConverterInitInfo and
+ConverterConnectionInfo. They represent the vertices and edges in the
+clock diagram respectively.
+Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
+Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
+Signed-off-by: Hao Wu <wuhaotsh@google.com>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20210108190945.949196-2-wuhaotsh@google.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 1507556919-24992-7-git-send-email-peter.maydell@linaro.org
 ---
- target/arm/translate.c | 178 ++++++++++++++++++++++++++++++-------------------
+ include/hw/misc/npcm7xx_clk.h | 140 +++++-
-file changed, 108 insertions(+), 70 deletions(-)
+ hw/misc/npcm7xx_clk.c         | 805 +++++++++++++++++++++++++++++++++-
 files changed, 932 insertions(+), 13 deletions(-)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
+diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
+--- a/include/hw/misc/npcm7xx_clk.h
-+++ b/target/arm/translate.c
++++ b/include/hw/misc/npcm7xx_clk.h
-@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
+@@ -XXX,XX +XXX,XX @@
-     }
+ #define NPCM7XX_CLK_H
- }
+ #include "exec/memory.h"
-+static bool thumb_insn_is_16bit(DisasContext *s, uint32_t insn)
++#include "hw/clock.h"
-+{
+ #include "hw/sysbus.h"
-+    /* Return true if this is a 16 bit instruction. We must be precise
-+     * about this (matching the decode).  We assume that s->pc still
+ /*
-+     * points to the first 16 bits of the insn.
+@@ -XXX,XX +XXX,XX @@
-+     */
-+    if ((insn >> 11) < 0x1d) {
+ #define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in"
-+        /* Definitely a 16-bit instruction */
-+        return true;
+-typedef struct NPCM7xxCLKState {
-+    }
++/* Maximum amount of clock inputs in a SEL module. */
-+
++#define NPCM7XX_CLK_SEL_MAX_INPUT 5
-+    /* Top five bits 0b11101 / 0b11110 / 0b11111 : this is the
++
-+     * first half of a 32-bit Thumb insn. Thumb-1 cores might
++/* PLLs in CLK module. */
-+     * end up actually treating this as two 16-bit insns, though,
++typedef enum NPCM7xxClockPLL {
-+     * if it's half of a bl/blx pair that might span a page boundary.
++    NPCM7XX_CLOCK_PLL0,
-+     */
++    NPCM7XX_CLOCK_PLL1,
-+    if (arm_dc_feature(s, ARM_FEATURE_THUMB2)) {
++    NPCM7XX_CLOCK_PLL2,
-+        /* Thumb2 cores (including all M profile ones) always treat
++    NPCM7XX_CLOCK_PLLG,
-+         * 32-bit insns as 32-bit.
++    NPCM7XX_CLOCK_NR_PLLS,
-+         */
++} NPCM7xxClockPLL;
-+        return false;
++
-+    }
++/* SEL/MUX in CLK module. */
-+
++typedef enum NPCM7xxClockSEL {
-+    if ((insn >> 11) == 0x1e && (s->pc < s->next_page_start - 3)) {
++    NPCM7XX_CLOCK_PIXCKSEL,
-+        /* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix, and the suffix
++    NPCM7XX_CLOCK_MCCKSEL,
-+         * is not on the next page; we merge this into a 32-bit
++    NPCM7XX_CLOCK_CPUCKSEL,
-+         * insn.
++    NPCM7XX_CLOCK_CLKOUTSEL,
-+         */
++    NPCM7XX_CLOCK_UARTCKSEL,
-+        return false;
++    NPCM7XX_CLOCK_TIMCKSEL,
-+    }
++    NPCM7XX_CLOCK_SDCKSEL,
-+    /* 0b1110_1xxx_xxxx_xxxx : BLX suffix (or UNDEF);
++    NPCM7XX_CLOCK_GFXMSEL,
-+     * 0b1111_1xxx_xxxx_xxxx : BL suffix;
++    NPCM7XX_CLOCK_SUCKSEL,
-+     * 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix on the end of a page
++    NPCM7XX_CLOCK_NR_SELS,
-+     *  -- handle as single 16 bit insn
++} NPCM7xxClockSEL;
-+     */
++
-+    return true;
++/* Dividers in CLK module. */
-+}
++typedef enum NPCM7xxClockDivider {
-+
++    NPCM7XX_CLOCK_PLL1D2, /* PLL1/2 */
- /* Return true if this is a Thumb-2 logical op.  */
++    NPCM7XX_CLOCK_PLL2D2, /* PLL2/2 */
- static int
++    NPCM7XX_CLOCK_MC_DIVIDER,
- thumb2_logic_op(int op)
++    NPCM7XX_CLOCK_AXI_DIVIDER,
-@@ -XXX,XX +XXX,XX @@ gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out,
++    NPCM7XX_CLOCK_AHB_DIVIDER,
++    NPCM7XX_CLOCK_AHB3_DIVIDER,
- /* Translate a 32-bit thumb instruction.  Returns nonzero if the instruction
++    NPCM7XX_CLOCK_SPI0_DIVIDER,
-    is not legal.  */
++    NPCM7XX_CLOCK_SPIX_DIVIDER,
--static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw1)
++    NPCM7XX_CLOCK_APB1_DIVIDER,
-+static int disas_thumb2_insn(DisasContext *s, uint32_t insn)
++    NPCM7XX_CLOCK_APB2_DIVIDER,
 +    NPCM7XX_CLOCK_APB3_DIVIDER,
 +    NPCM7XX_CLOCK_APB4_DIVIDER,
 +    NPCM7XX_CLOCK_APB5_DIVIDER,
 +    NPCM7XX_CLOCK_CLKOUT_DIVIDER,
 +    NPCM7XX_CLOCK_UART_DIVIDER,
 +    NPCM7XX_CLOCK_TIMER_DIVIDER,
 +    NPCM7XX_CLOCK_ADC_DIVIDER,
 +    NPCM7XX_CLOCK_MMC_DIVIDER,
 +    NPCM7XX_CLOCK_SDHC_DIVIDER,
 +    NPCM7XX_CLOCK_GFXM_DIVIDER, /* divide by 3 */
 +    NPCM7XX_CLOCK_UTMI_DIVIDER,
 +    NPCM7XX_CLOCK_NR_DIVIDERS,
 +} NPCM7xxClockConverter;
 +
 +typedef struct NPCM7xxCLKState NPCM7xxCLKState;
 +
 +/**
 + * struct NPCM7xxClockPLLState - A PLL module in CLK module.
 + * @name: The name of the module.
 + * @clk: The CLK module that owns this module.
 + * @clock_in: The input clock of this module.
 + * @clock_out: The output clock of this module.
 + * @reg: The control registers for this PLL module.
 + */
 +typedef struct NPCM7xxClockPLLState {
 +    DeviceState parent;
 +
 +    const char *name;
 +    NPCM7xxCLKState *clk;
 +    Clock *clock_in;
 +    Clock *clock_out;
 +
 +    int reg;
 +} NPCM7xxClockPLLState;
 +
 +/**
 + * struct NPCM7xxClockSELState - A SEL module in CLK module.
 + * @name: The name of the module.
 + * @clk: The CLK module that owns this module.
 + * @input_size: The size of inputs of this module.
 + * @clock_in: The input clocks of this module.
 + * @clock_out: The output clocks of this module.
 + * @offset: The offset of this module in the control register.
 + * @len: The length of this module in the control register.
 + */
 +typedef struct NPCM7xxClockSELState {
 +    DeviceState parent;
 +
 +    const char *name;
 +    NPCM7xxCLKState *clk;
 +    uint8_t input_size;
 +    Clock *clock_in[NPCM7XX_CLK_SEL_MAX_INPUT];
 +    Clock *clock_out;
 +
 +    int offset;
 +    int len;
 +} NPCM7xxClockSELState;
 +
 +/**
 + * struct NPCM7xxClockDividerState - A Divider module in CLK module.
 + * @name: The name of the module.
 + * @clk: The CLK module that owns this module.
 + * @clock_in: The input clock of this module.
 + * @clock_out: The output clock of this module.
 + * @divide: The function the divider uses to divide the input.
 + * @reg: The index of the control register that contains the divisor.
 + * @offset: The offset of the divisor in the control register.
 + * @len: The length of the divisor in the control register.
 + * @divisor: The divisor for a constant divisor
 + */
 +typedef struct NPCM7xxClockDividerState {
 +    DeviceState parent;
 +
 +    const char *name;
 +    NPCM7xxCLKState *clk;
 +    Clock *clock_in;
 +    Clock *clock_out;
 +
 +    uint32_t (*divide)(struct NPCM7xxClockDividerState *s);
 +    union {
 +        struct {
 +            int reg;
 +            int offset;
 +            int len;
 +        };
 +        int divisor;
 +    };
 +} NPCM7xxClockDividerState;
 +
 +struct NPCM7xxCLKState {
      SysBusDevice parent;
      MemoryRegion iomem;
 +    /* Clock converters */
 +    NPCM7xxClockPLLState plls[NPCM7XX_CLOCK_NR_PLLS];
 +    NPCM7xxClockSELState sels[NPCM7XX_CLOCK_NR_SELS];
 +    NPCM7xxClockDividerState dividers[NPCM7XX_CLOCK_NR_DIVIDERS];
 +
      uint32_t regs[NPCM7XX_CLK_NR_REGS];
      /* Time reference for SECCNT and CNTR25M, initialized by power on reset */
      int64_t ref_ns;
 -} NPCM7xxCLKState;
 +
 +    /* The incoming reference clock. */
 +    Clock *clkref;
 +};
  #define TYPE_NPCM7XX_CLK "npcm7xx-clk"
  #define NPCM7XX_CLK(obj) OBJECT_CHECK(NPCM7xxCLKState, (obj), TYPE_NPCM7XX_CLK)
 diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/npcm7xx_clk.c
 +++ b/hw/misc/npcm7xx_clk.c
@@ -XXX,XX +XXX,XX @@
  #include "hw/misc/npcm7xx_clk.h"
  #include "hw/timer/npcm7xx_timer.h"
 +#include "hw/qdev-clock.h"
  #include "migration/vmstate.h"
  #include "qemu/error-report.h"
  #include "qemu/log.h"
@@ -XXX,XX +XXX,XX @@
  #include "trace.h"
  #include "sysemu/watchdog.h"
 +/*
 + * The reference clock hz, and the SECCNT and CNTR25M registers in this module,
 + * is always 25 MHz.
 + */
 +#define NPCM7XX_CLOCK_REF_HZ            (25000000)
 +
 +/* Register Field Definitions */
 +#define NPCM7XX_CLK_WDRCR_CA9C  BIT(0) /* Cortex A9 Cores */
 +
  #define PLLCON_LOKI     BIT(31)
  #define PLLCON_LOKS     BIT(30)
  #define PLLCON_PWDEN    BIT(12)
 +#define PLLCON_FBDV(con) extract32((con), 16, 12)
 +#define PLLCON_OTDV2(con) extract32((con), 13, 3)
 +#define PLLCON_OTDV1(con) extract32((con), 8, 3)
 +#define PLLCON_INDV(con) extract32((con), 0, 6)
  enum NPCM7xxCLKRegisters {
      NPCM7XX_CLK_CLKEN1,
@@ -XXX,XX +XXX,XX @@ static const uint32_t cold_reset_values[NPCM7XX_CLK_NR_REGS] = {
      [NPCM7XX_CLK_AHBCKFI]       = 0x000000c8,
  };
 -/* Register Field Definitions */
 -#define NPCM7XX_CLK_WDRCR_CA9C  BIT(0) /* Cortex A9 Cores */
 -
  /* The number of watchdogs that can trigger a reset. */
  #define NPCM7XX_NR_WATCHDOGS    (3)
 +/* Clock converter functions */
 +
 +#define TYPE_NPCM7XX_CLOCK_PLL "npcm7xx-clock-pll"
 +#define NPCM7XX_CLOCK_PLL(obj) OBJECT_CHECK(NPCM7xxClockPLLState, \
 +        (obj), TYPE_NPCM7XX_CLOCK_PLL)
 +#define TYPE_NPCM7XX_CLOCK_SEL "npcm7xx-clock-sel"
 +#define NPCM7XX_CLOCK_SEL(obj) OBJECT_CHECK(NPCM7xxClockSELState, \
 +        (obj), TYPE_NPCM7XX_CLOCK_SEL)
 +#define TYPE_NPCM7XX_CLOCK_DIVIDER "npcm7xx-clock-divider"
 +#define NPCM7XX_CLOCK_DIVIDER(obj) OBJECT_CHECK(NPCM7xxClockDividerState, \
 +        (obj), TYPE_NPCM7XX_CLOCK_DIVIDER)
 +
 +static void npcm7xx_clk_update_pll(void *opaque)
 +{
 +    NPCM7xxClockPLLState *s = opaque;
 +    uint32_t con = s->clk->regs[s->reg];
 +    uint64_t freq;
 +
 +    /* The PLL is grounded if it is not locked yet. */
 +    if (con & PLLCON_LOKI) {
 +        freq = clock_get_hz(s->clock_in);
 +        freq *= PLLCON_FBDV(con);
 +        freq /= PLLCON_INDV(con) * PLLCON_OTDV1(con) * PLLCON_OTDV2(con);
 +    } else {
 +        freq = 0;
 +    }
 +
 +    clock_update_hz(s->clock_out, freq);
 +}
 +
 +static void npcm7xx_clk_update_sel(void *opaque)
 +{
 +    NPCM7xxClockSELState *s = opaque;
 +    uint32_t index = extract32(s->clk->regs[NPCM7XX_CLK_CLKSEL], s->offset,
 +            s->len);
 +
 +    if (index >= s->input_size) {
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: SEL index: %u out of range\n",
 +                      __func__, index);
 +        index = 0;
 +    }
 +    clock_update_hz(s->clock_out, clock_get_hz(s->clock_in[index]));
 +}
 +
 +static void npcm7xx_clk_update_divider(void *opaque)
 +{
 +    NPCM7xxClockDividerState *s = opaque;
 +    uint32_t freq;
 +
 +    freq = s->divide(s);
 +    clock_update_hz(s->clock_out, freq);
 +}
 +
 +static uint32_t divide_by_constant(NPCM7xxClockDividerState *s)
 +{
 +    return clock_get_hz(s->clock_in) / s->divisor;
 +}
 +
 +static uint32_t divide_by_reg_divisor(NPCM7xxClockDividerState *s)
 +{
 +    return clock_get_hz(s->clock_in) /
 +            (extract32(s->clk->regs[s->reg], s->offset, s->len) + 1);
 +}
 +
 +static uint32_t divide_by_reg_divisor_times_2(NPCM7xxClockDividerState *s)
 +{
 +    return divide_by_reg_divisor(s) / 2;
 +}
 +
 +static uint32_t shift_by_reg_divisor(NPCM7xxClockDividerState *s)
 +{
 +    return clock_get_hz(s->clock_in) >>
 +        extract32(s->clk->regs[s->reg], s->offset, s->len);
 +}
 +
 +static NPCM7xxClockPLL find_pll_by_reg(enum NPCM7xxCLKRegisters reg)
 +{
 +    switch (reg) {
 +    case NPCM7XX_CLK_PLLCON0:
 +        return NPCM7XX_CLOCK_PLL0;
 +    case NPCM7XX_CLK_PLLCON1:
 +        return NPCM7XX_CLOCK_PLL1;
 +    case NPCM7XX_CLK_PLLCON2:
 +        return NPCM7XX_CLOCK_PLL2;
 +    case NPCM7XX_CLK_PLLCONG:
 +        return NPCM7XX_CLOCK_PLLG;
 +    default:
 +        g_assert_not_reached();
 +    }
 +}
 +
 +static void npcm7xx_clk_update_all_plls(NPCM7xxCLKState *clk)
 +{
 +    int i;
 +
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
 +        npcm7xx_clk_update_pll(&clk->plls[i]);
 +    }
 +}
 +
 +static void npcm7xx_clk_update_all_sels(NPCM7xxCLKState *clk)
 +{
 +    int i;
 +
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
 +        npcm7xx_clk_update_sel(&clk->sels[i]);
 +    }
 +}
 +
 +static void npcm7xx_clk_update_all_dividers(NPCM7xxCLKState *clk)
 +{
 +    int i;
 +
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
 +        npcm7xx_clk_update_divider(&clk->dividers[i]);
 +    }
 +}
 +
 +static void npcm7xx_clk_update_all_clocks(NPCM7xxCLKState *clk)
 +{
 +    clock_update_hz(clk->clkref, NPCM7XX_CLOCK_REF_HZ);
 +    npcm7xx_clk_update_all_plls(clk);
 +    npcm7xx_clk_update_all_sels(clk);
 +    npcm7xx_clk_update_all_dividers(clk);
 +}
 +
 +/* Types of clock sources. */
 +typedef enum ClockSrcType {
 +    CLKSRC_REF,
 +    CLKSRC_PLL,
 +    CLKSRC_SEL,
 +    CLKSRC_DIV,
 +} ClockSrcType;
 +
 +typedef struct PLLInitInfo {
 +    const char *name;
 +    ClockSrcType src_type;
 +    int src_index;
 +    int reg;
 +    const char *public_name;
 +} PLLInitInfo;
 +
 +typedef struct SELInitInfo {
 +    const char *name;
 +    uint8_t input_size;
 +    ClockSrcType src_type[NPCM7XX_CLK_SEL_MAX_INPUT];
 +    int src_index[NPCM7XX_CLK_SEL_MAX_INPUT];
 +    int offset;
 +    int len;
 +    const char *public_name;
 +} SELInitInfo;
 +
 +typedef struct DividerInitInfo {
 +    const char *name;
 +    ClockSrcType src_type;
 +    int src_index;
 +    uint32_t (*divide)(NPCM7xxClockDividerState *s);
 +    int reg; /* not used when type == CONSTANT */
 +    int offset; /* not used when type == CONSTANT */
 +    int len; /* not used when type == CONSTANT */
 +    int divisor; /* used only when type == CONSTANT */
 +    const char *public_name;
 +} DividerInitInfo;
 +
 +static const PLLInitInfo pll_init_info_list[] = {
 +    [NPCM7XX_CLOCK_PLL0] = {
 +        .name = "pll0",
 +        .src_type = CLKSRC_REF,
 +        .reg = NPCM7XX_CLK_PLLCON0,
 +    },
 +    [NPCM7XX_CLOCK_PLL1] = {
 +        .name = "pll1",
 +        .src_type = CLKSRC_REF,
 +        .reg = NPCM7XX_CLK_PLLCON1,
 +    },
 +    [NPCM7XX_CLOCK_PLL2] = {
 +        .name = "pll2",
 +        .src_type = CLKSRC_REF,
 +        .reg = NPCM7XX_CLK_PLLCON2,
 +    },
 +    [NPCM7XX_CLOCK_PLLG] = {
 +        .name = "pllg",
 +        .src_type = CLKSRC_REF,
 +        .reg = NPCM7XX_CLK_PLLCONG,
 +    },
 +};
 +
 +static const SELInitInfo sel_init_info_list[] = {
 +    [NPCM7XX_CLOCK_PIXCKSEL] = {
 +        .name = "pixcksel",
 +        .input_size = 2,
 +        .src_type = {CLKSRC_PLL, CLKSRC_REF},
 +        .src_index = {NPCM7XX_CLOCK_PLLG, 0},
 +        .offset = 5,
 +        .len = 1,
 +        .public_name = "pixel-clock",
 +    },
 +    [NPCM7XX_CLOCK_MCCKSEL] = {
 +        .name = "mccksel",
 +        .input_size = 4,
 +        .src_type = {CLKSRC_DIV, CLKSRC_REF, CLKSRC_REF,
 +            /*MCBPCK, shouldn't be used in normal operation*/
 +            CLKSRC_REF},
 +        .src_index = {NPCM7XX_CLOCK_PLL1D2, 0, 0, 0},
 +        .offset = 12,
 +        .len = 2,
 +        .public_name = "mc-phy-clock",
 +    },
 +    [NPCM7XX_CLOCK_CPUCKSEL] = {
 +        .name = "cpucksel",
 +        .input_size = 4,
 +        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF,
 +            /*SYSBPCK, shouldn't be used in normal operation*/
 +            CLKSRC_REF},
 +        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, 0},
 +        .offset = 0,
 +        .len = 2,
 +        .public_name = "system-clock",
 +    },
 +    [NPCM7XX_CLOCK_CLKOUTSEL] = {
 +        .name = "clkoutsel",
 +        .input_size = 5,
 +        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF,
 +            CLKSRC_PLL, CLKSRC_DIV},
 +        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
 +            NPCM7XX_CLOCK_PLLG, NPCM7XX_CLOCK_PLL2D2},
 +        .offset = 18,
 +        .len = 3,
 +        .public_name = "tock",
 +    },
 +    [NPCM7XX_CLOCK_UARTCKSEL] = {
 +        .name = "uartcksel",
 +        .input_size = 4,
 +        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
 +        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
 +            NPCM7XX_CLOCK_PLL2D2},
 +        .offset = 8,
 +        .len = 2,
 +    },
 +    [NPCM7XX_CLOCK_TIMCKSEL] = {
 +        .name = "timcksel",
 +        .input_size = 4,
 +        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
 +        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
 +            NPCM7XX_CLOCK_PLL2D2},
 +        .offset = 14,
 +        .len = 2,
 +    },
 +    [NPCM7XX_CLOCK_SDCKSEL] = {
 +        .name = "sdcksel",
 +        .input_size = 4,
 +        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
 +        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
 +            NPCM7XX_CLOCK_PLL2D2},
 +        .offset = 6,
 +        .len = 2,
 +    },
 +    [NPCM7XX_CLOCK_GFXMSEL] = {
 +        .name = "gfxmksel",
 +        .input_size = 2,
 +        .src_type = {CLKSRC_REF, CLKSRC_PLL},
 +        .src_index = {0, NPCM7XX_CLOCK_PLL2},
 +        .offset = 21,
 +        .len = 1,
 +    },
 +    [NPCM7XX_CLOCK_SUCKSEL] = {
 +        .name = "sucksel",
 +        .input_size = 4,
 +        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
 +        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
 +            NPCM7XX_CLOCK_PLL2D2},
 +        .offset = 10,
 +        .len = 2,
 +    },
 +};
 +
 +static const DividerInitInfo divider_init_info_list[] = {
 +    [NPCM7XX_CLOCK_PLL1D2] = {
 +        .name = "pll1d2",
 +        .src_type = CLKSRC_PLL,
 +        .src_index = NPCM7XX_CLOCK_PLL1,
 +        .divide = divide_by_constant,
 +        .divisor = 2,
 +    },
 +    [NPCM7XX_CLOCK_PLL2D2] = {
 +        .name = "pll2d2",
 +        .src_type = CLKSRC_PLL,
 +        .src_index = NPCM7XX_CLOCK_PLL2,
 +        .divide = divide_by_constant,
 +        .divisor = 2,
 +    },
 +    [NPCM7XX_CLOCK_MC_DIVIDER] = {
 +        .name = "mc-divider",
 +        .src_type = CLKSRC_SEL,
 +        .src_index = NPCM7XX_CLOCK_MCCKSEL,
 +        .divide = divide_by_constant,
 +        .divisor = 2,
 +        .public_name = "mc-clock"
 +    },
 +    [NPCM7XX_CLOCK_AXI_DIVIDER] = {
 +        .name = "axi-divider",
 +        .src_type = CLKSRC_SEL,
 +        .src_index = NPCM7XX_CLOCK_CPUCKSEL,
 +        .divide = shift_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV1,
 +        .offset = 0,
 +        .len = 1,
 +        .public_name = "clk2"
 +    },
 +    [NPCM7XX_CLOCK_AHB_DIVIDER] = {
 +        .name = "ahb-divider",
 +        .src_type = CLKSRC_DIV,
 +        .src_index = NPCM7XX_CLOCK_AXI_DIVIDER,
 +        .divide = divide_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV1,
 +        .offset = 26,
 +        .len = 2,
 +        .public_name = "clk4"
 +    },
 +    [NPCM7XX_CLOCK_AHB3_DIVIDER] = {
 +        .name = "ahb3-divider",
 +        .src_type = CLKSRC_DIV,
 +        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
 +        .divide = divide_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV1,
 +        .offset = 6,
 +        .len = 5,
 +        .public_name = "ahb3-spi3-clock"
 +    },
 +    [NPCM7XX_CLOCK_SPI0_DIVIDER] = {
 +        .name = "spi0-divider",
 +        .src_type = CLKSRC_DIV,
 +        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
 +        .divide = divide_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV3,
 +        .offset = 6,
 +        .len = 5,
 +        .public_name = "spi0-clock",
 +    },
 +    [NPCM7XX_CLOCK_SPIX_DIVIDER] = {
 +        .name = "spix-divider",
 +        .src_type = CLKSRC_DIV,
 +        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
 +        .divide = divide_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV3,
 +        .offset = 1,
 +        .len = 5,
 +        .public_name = "spix-clock",
 +    },
 +    [NPCM7XX_CLOCK_APB1_DIVIDER] = {
 +        .name = "apb1-divider",
 +        .src_type = CLKSRC_DIV,
 +        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
 +        .divide = shift_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV2,
 +        .offset = 24,
 +        .len = 2,
 +        .public_name = "apb1-clock",
 +    },
 +    [NPCM7XX_CLOCK_APB2_DIVIDER] = {
 +        .name = "apb2-divider",
 +        .src_type = CLKSRC_DIV,
 +        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
 +        .divide = shift_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV2,
 +        .offset = 26,
 +        .len = 2,
 +        .public_name = "apb2-clock",
 +    },
 +    [NPCM7XX_CLOCK_APB3_DIVIDER] = {
 +        .name = "apb3-divider",
 +        .src_type = CLKSRC_DIV,
 +        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
 +        .divide = shift_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV2,
 +        .offset = 28,
 +        .len = 2,
 +        .public_name = "apb3-clock",
 +    },
 +    [NPCM7XX_CLOCK_APB4_DIVIDER] = {
 +        .name = "apb4-divider",
 +        .src_type = CLKSRC_DIV,
 +        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
 +        .divide = shift_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV2,
 +        .offset = 30,
 +        .len = 2,
 +        .public_name = "apb4-clock",
 +    },
 +    [NPCM7XX_CLOCK_APB5_DIVIDER] = {
 +        .name = "apb5-divider",
 +        .src_type = CLKSRC_DIV,
 +        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
 +        .divide = shift_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV2,
 +        .offset = 22,
 +        .len = 2,
 +        .public_name = "apb5-clock",
 +    },
 +    [NPCM7XX_CLOCK_CLKOUT_DIVIDER] = {
 +        .name = "clkout-divider",
 +        .src_type = CLKSRC_SEL,
 +        .src_index = NPCM7XX_CLOCK_CLKOUTSEL,
 +        .divide = divide_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV2,
 +        .offset = 16,
 +        .len = 5,
 +        .public_name = "clkout",
 +    },
 +    [NPCM7XX_CLOCK_UART_DIVIDER] = {
 +        .name = "uart-divider",
 +        .src_type = CLKSRC_SEL,
 +        .src_index = NPCM7XX_CLOCK_UARTCKSEL,
 +        .divide = divide_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV1,
 +        .offset = 16,
 +        .len = 5,
 +        .public_name = "uart-clock",
 +    },
 +    [NPCM7XX_CLOCK_TIMER_DIVIDER] = {
 +        .name = "timer-divider",
 +        .src_type = CLKSRC_SEL,
 +        .src_index = NPCM7XX_CLOCK_TIMCKSEL,
 +        .divide = divide_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV1,
 +        .offset = 21,
 +        .len = 5,
 +        .public_name = "timer-clock",
 +    },
 +    [NPCM7XX_CLOCK_ADC_DIVIDER] = {
 +        .name = "adc-divider",
 +        .src_type = CLKSRC_DIV,
 +        .src_index = NPCM7XX_CLOCK_TIMER_DIVIDER,
 +        .divide = shift_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV1,
 +        .offset = 28,
 +        .len = 3,
 +        .public_name = "adc-clock",
 +    },
 +    [NPCM7XX_CLOCK_MMC_DIVIDER] = {
 +        .name = "mmc-divider",
 +        .src_type = CLKSRC_SEL,
 +        .src_index = NPCM7XX_CLOCK_SDCKSEL,
 +        .divide = divide_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV1,
 +        .offset = 11,
 +        .len = 5,
 +        .public_name = "mmc-clock",
 +    },
 +    [NPCM7XX_CLOCK_SDHC_DIVIDER] = {
 +        .name = "sdhc-divider",
 +        .src_type = CLKSRC_SEL,
 +        .src_index = NPCM7XX_CLOCK_SDCKSEL,
 +        .divide = divide_by_reg_divisor_times_2,
 +        .reg = NPCM7XX_CLK_CLKDIV2,
 +        .offset = 0,
 +        .len = 4,
 +        .public_name = "sdhc-clock",
 +    },
 +    [NPCM7XX_CLOCK_GFXM_DIVIDER] = {
 +        .name = "gfxm-divider",
 +        .src_type = CLKSRC_SEL,
 +        .src_index = NPCM7XX_CLOCK_GFXMSEL,
 +        .divide = divide_by_constant,
 +        .divisor = 3,
 +        .public_name = "gfxm-clock",
 +    },
 +    [NPCM7XX_CLOCK_UTMI_DIVIDER] = {
 +        .name = "utmi-divider",
 +        .src_type = CLKSRC_SEL,
 +        .src_index = NPCM7XX_CLOCK_SUCKSEL,
 +        .divide = divide_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV2,
 +        .offset = 8,
 +        .len = 5,
 +        .public_name = "utmi-clock",
 +    },
 +};
 +
 +static void npcm7xx_clk_pll_init(Object *obj)
 +{
 +    NPCM7xxClockPLLState *pll = NPCM7XX_CLOCK_PLL(obj);
 +
 +    pll->clock_in = qdev_init_clock_in(DEVICE(pll), "clock-in",
 +            npcm7xx_clk_update_pll, pll);
 +    pll->clock_out = qdev_init_clock_out(DEVICE(pll), "clock-out");
 +}
 +
 +static void npcm7xx_clk_sel_init(Object *obj)
 +{
 +    int i;
 +    NPCM7xxClockSELState *sel = NPCM7XX_CLOCK_SEL(obj);
 +
 +    for (i = 0; i < NPCM7XX_CLK_SEL_MAX_INPUT; ++i) {
 +        sel->clock_in[i] = qdev_init_clock_in(DEVICE(sel),
 +                g_strdup_printf("clock-in[%d]", i),
 +                npcm7xx_clk_update_sel, sel);
 +    }
 +    sel->clock_out = qdev_init_clock_out(DEVICE(sel), "clock-out");
 +}
 +static void npcm7xx_clk_divider_init(Object *obj)
 +{
 +    NPCM7xxClockDividerState *div = NPCM7XX_CLOCK_DIVIDER(obj);
 +
 +    div->clock_in = qdev_init_clock_in(DEVICE(div), "clock-in",
 +            npcm7xx_clk_update_divider, div);
 +    div->clock_out = qdev_init_clock_out(DEVICE(div), "clock-out");
 +}
 +
 +static void npcm7xx_init_clock_pll(NPCM7xxClockPLLState *pll,
 +        NPCM7xxCLKState *clk, const PLLInitInfo *init_info)
 +{
 +    pll->name = init_info->name;
 +    pll->clk = clk;
 +    pll->reg = init_info->reg;
 +    if (init_info->public_name != NULL) {
 +        qdev_alias_clock(DEVICE(pll), "clock-out", DEVICE(clk),
 +                init_info->public_name);
 +    }
 +}
 +
 +static void npcm7xx_init_clock_sel(NPCM7xxClockSELState *sel,
 +        NPCM7xxCLKState *clk, const SELInitInfo *init_info)
 +{
 +    int input_size = init_info->input_size;
 +
 +    sel->name = init_info->name;
 +    sel->clk = clk;
 +    sel->input_size = init_info->input_size;
 +    g_assert(input_size <= NPCM7XX_CLK_SEL_MAX_INPUT);
 +    sel->offset = init_info->offset;
 +    sel->len = init_info->len;
 +    if (init_info->public_name != NULL) {
 +        qdev_alias_clock(DEVICE(sel), "clock-out", DEVICE(clk),
 +                init_info->public_name);
 +    }
 +}
 +
 +static void npcm7xx_init_clock_divider(NPCM7xxClockDividerState *div,
 +        NPCM7xxCLKState *clk, const DividerInitInfo *init_info)
 +{
 +    div->name = init_info->name;
 +    div->clk = clk;
 +
 +    div->divide = init_info->divide;
 +    if (div->divide == divide_by_constant) {
 +        div->divisor = init_info->divisor;
 +    } else {
 +        div->reg = init_info->reg;
 +        div->offset = init_info->offset;
 +        div->len = init_info->len;
 +    }
 +    if (init_info->public_name != NULL) {
 +        qdev_alias_clock(DEVICE(div), "clock-out", DEVICE(clk),
 +                init_info->public_name);
 +    }
 +}
 +
 +static Clock *npcm7xx_get_clock(NPCM7xxCLKState *clk, ClockSrcType type,
 +        int index)
 +{
 +    switch (type) {
 +    case CLKSRC_REF:
 +        return clk->clkref;
 +    case CLKSRC_PLL:
 +        return clk->plls[index].clock_out;
 +    case CLKSRC_SEL:
 +        return clk->sels[index].clock_out;
 +    case CLKSRC_DIV:
 +        return clk->dividers[index].clock_out;
 +    default:
 +        g_assert_not_reached();
 +    }
 +}
 +
 +static void npcm7xx_connect_clocks(NPCM7xxCLKState *clk)
 +{
 +    int i, j;
 +    Clock *src;
 +
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
 +        src = npcm7xx_get_clock(clk, pll_init_info_list[i].src_type,
 +                pll_init_info_list[i].src_index);
 +        clock_set_source(clk->plls[i].clock_in, src);
 +    }
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
 +        for (j = 0; j < sel_init_info_list[i].input_size; ++j) {
 +            src = npcm7xx_get_clock(clk, sel_init_info_list[i].src_type[j],
 +                    sel_init_info_list[i].src_index[j]);
 +            clock_set_source(clk->sels[i].clock_in[j], src);
 +        }
 +    }
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
 +        src = npcm7xx_get_clock(clk, divider_init_info_list[i].src_type,
 +                divider_init_info_list[i].src_index);
 +        clock_set_source(clk->dividers[i].clock_in, src);
 +    }
 +}
 +
  static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size)
  {
--    uint32_t insn, imm, shift, offset;
+     uint32_t reg = offset / sizeof(uint32_t);
-+    uint32_t imm, shift, offset;
+@@ -XXX,XX +XXX,XX @@ static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size)
-     uint32_t rd, rn, rm, rs;
+          *
-     TCGv_i32 tmp;
+          * The 4 LSBs are always zero: (1e9 / 640) << 4 = 25000000.
-     TCGv_i32 tmp2;
+          */
-@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
+-        value = (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_TIMER_REF_HZ;
-     int conds;
++        value = (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_CLOCK_REF_HZ;
-     int logic_cc;
+         break;
--    if (!arm_dc_feature(s, ARM_FEATURE_THUMB2)) {
+     default:
--        /* Thumb-1 cores may need to treat bl and blx as a pair of
+@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_write(void *opaque, hwaddr offset,
--           16-bit instructions to get correct prefetch abort behavior.  */
+                 value |= (value & PLLCON_LOKS);
--        insn = insn_hw1;
+             }
 -        if ((insn & (1 << 12)) == 0) {
 -            ARCH(5);
 -            /* Second half of blx.  */
 -            offset = ((insn & 0x7ff) << 1);
 -            tmp = load_reg(s, 14);
 -            tcg_gen_addi_i32(tmp, tmp, offset);
 -            tcg_gen_andi_i32(tmp, tmp, 0xfffffffc);
 -
 -            tmp2 = tcg_temp_new_i32();
 -            tcg_gen_movi_i32(tmp2, s->pc | 1);
 -            store_reg(s, 14, tmp2);
 -            gen_bx(s, tmp);
 -            return 0;
 -        }
 -        if (insn & (1 << 11)) {
 -            /* Second half of bl.  */
 -            offset = ((insn & 0x7ff) << 1) | 1;
 -            tmp = load_reg(s, 14);
 -            tcg_gen_addi_i32(tmp, tmp, offset);
 -
 -            tmp2 = tcg_temp_new_i32();
 -            tcg_gen_movi_i32(tmp2, s->pc | 1);
 -            store_reg(s, 14, tmp2);
 -            gen_bx(s, tmp);
 -            return 0;
 -        }
 -        if ((s->pc & ~TARGET_PAGE_MASK) == 0) {
 -            /* Instruction spans a page boundary.  Implement it as two
 -               16-bit instructions in case the second half causes an
 -               prefetch abort.  */
 -            offset = ((int32_t)insn << 21) >> 9;
 -            tcg_gen_movi_i32(cpu_R[14], s->pc + 2 + offset);
 -            return 0;
 -        }
 -        /* Fall through to 32-bit decode.  */
 -    }
 -
 -    insn = arm_lduw_code(env, s->pc, s->sctlr_b);
 -    s->pc += 2;
 -    insn |= (uint32_t)insn_hw1 << 16;
 -
 +    /* The only 32 bit insn that's allowed for Thumb1 is the combined
 +     * BL/BLX prefix and suffix.
 +     */
      if ((insn & 0xf800e800) != 0xf000e800) {
          ARCH(6T2);
      }
@@ -XXX,XX +XXX,XX @@ illegal_op:
      return 1;
  }
 -static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
 +static void disas_thumb_insn(DisasContext *s, uint32_t insn)
  {
 -    uint32_t val, insn, op, rm, rn, rd, shift, cond;
 +    uint32_t val, op, rm, rn, rd, shift, cond;
      int32_t offset;
      int i;
      TCGv_i32 tmp;
      TCGv_i32 tmp2;
      TCGv_i32 addr;
 -    if (s->condexec_mask) {
 -        cond = s->condexec_cond;
 -        if (cond != 0x0e) {     /* Skip conditional when condition is AL. */
 -          s->condlabel = gen_new_label();
 -          arm_gen_test_cc(cond ^ 1, s->condlabel);
 -          s->condjmp = 1;
 -        }
 -    }
 -
 -    insn = arm_lduw_code(env, s->pc, s->sctlr_b);
 -    s->pc += 2;
 -
      switch (insn >> 12) {
      case 0: case 1:
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
      case 14:
          if (insn & (1 << 11)) {
 -            if (disas_thumb2_insn(env, s, insn))
 -              goto undef32;
 +            /* thumb_insn_is_16bit() ensures we can't get here for
 +             * a Thumb2 CPU, so this must be a thumb1 split BL/BLX:
 +             * 0b1110_1xxx_xxxx_xxxx : BLX suffix (or UNDEF)
 +             */
 +            assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2));
 +            ARCH(5);
 +            offset = ((insn & 0x7ff) << 1);
 +            tmp = load_reg(s, 14);
 +            tcg_gen_addi_i32(tmp, tmp, offset);
 +            tcg_gen_andi_i32(tmp, tmp, 0xfffffffc);
 +
 +            tmp2 = tcg_temp_new_i32();
 +            tcg_gen_movi_i32(tmp2, s->pc | 1);
 +            store_reg(s, 14, tmp2);
 +            gen_bx(s, tmp);
              break;
          }
-         /* unconditional branch */
++        /* Only update PLL when it is locked. */
-@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
++        if (value & PLLCON_LOKI) {
 +            npcm7xx_clk_update_pll(&s->plls[find_pll_by_reg(reg)]);
 +        }
 +        break;
 +
 +    case NPCM7XX_CLK_CLKSEL:
 +        npcm7xx_clk_update_all_sels(s);
 +        break;
 +
 +    case NPCM7XX_CLK_CLKDIV1:
 +    case NPCM7XX_CLK_CLKDIV2:
 +    case NPCM7XX_CLK_CLKDIV3:
 +        npcm7xx_clk_update_all_dividers(s);
          break;
-     case 15:
+     case NPCM7XX_CLK_CNTR25M:
--        if (disas_thumb2_insn(env, s, insn))
+@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetType type)
--            goto undef32;
+     case RESET_TYPE_COLD:
-+        /* thumb_insn_is_16bit() ensures we can't get here for
+         memcpy(s->regs, cold_reset_values, sizeof(cold_reset_values));
-+         * a Thumb2 CPU, so this must be a thumb1 split BL/BLX.
+         s->ref_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
-+         */
++        npcm7xx_clk_update_all_clocks(s);
 +        assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2));
 +
 +        if (insn & (1 << 11)) {
 +            /* 0b1111_1xxx_xxxx_xxxx : BL suffix */
 +            offset = ((insn & 0x7ff) << 1) | 1;
 +            tmp = load_reg(s, 14);
 +            tcg_gen_addi_i32(tmp, tmp, offset);
 +
 +            tmp2 = tcg_temp_new_i32();
 +            tcg_gen_movi_i32(tmp2, s->pc | 1);
 +            store_reg(s, 14, tmp2);
 +            gen_bx(s, tmp);
 +        } else {
 +            /* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix */
 +            uint32_t uoffset = ((int32_t)insn << 21) >> 9;
 +
 +            tcg_gen_movi_i32(cpu_R[14], s->pc + 2 + uoffset);
 +        }
          break;
      }
      return;
 -undef32:
 -    gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
 -                       default_exception_el(s));
 -    return;
  illegal_op:
  undef:
      gen_exception_insn(s, 2, EXCP_UDEF, syn_uncategorized(),
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
  {
      DisasContext *dc = container_of(dcbase, DisasContext, base);
      CPUARMState *env = cpu->env_ptr;
 +    uint32_t insn;
 +    bool is_16bit;
      if (arm_pre_translate_insn(dc)) {
          return;
      }
--    disas_thumb_insn(env, dc);
+@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetType type)
-+    insn = arm_lduw_code(env, dc->pc, dc->sctlr_b);
+                   __func__, type);
-+    is_16bit = thumb_insn_is_16bit(dc, insn);
+ }
-+    dc->pc += 2;
-+    if (!is_16bit) {
++static void npcm7xx_clk_init_clock_hierarchy(NPCM7xxCLKState *s)
-+        uint32_t insn2 = arm_lduw_code(env, dc->pc, dc->sctlr_b);
++{
-+
++    int i;
-+        insn = insn << 16 | insn2;
++
-+        dc->pc += 2;
++    s->clkref = qdev_init_clock_in(DEVICE(s), "clkref", NULL, NULL);
-+    }
++
-+
++    /* First pass: init all converter modules */
-+    if (dc->condexec_mask) {
++    QEMU_BUILD_BUG_ON(ARRAY_SIZE(pll_init_info_list) != NPCM7XX_CLOCK_NR_PLLS);
-+        uint32_t cond = dc->condexec_cond;
++    QEMU_BUILD_BUG_ON(ARRAY_SIZE(sel_init_info_list) != NPCM7XX_CLOCK_NR_SELS);
-+
++    QEMU_BUILD_BUG_ON(ARRAY_SIZE(divider_init_info_list)
-+        if (cond != 0x0e) {     /* Skip conditional when condition is AL. */
++            != NPCM7XX_CLOCK_NR_DIVIDERS);
-+            dc->condlabel = gen_new_label();
++    for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
-+            arm_gen_test_cc(cond ^ 1, dc->condlabel);
++        object_initialize_child(OBJECT(s), pll_init_info_list[i].name,
-+            dc->condjmp = 1;
++                &s->plls[i], TYPE_NPCM7XX_CLOCK_PLL);
 +        npcm7xx_init_clock_pll(&s->plls[i], s,
 +                &pll_init_info_list[i]);
 +    }
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
 +        object_initialize_child(OBJECT(s), sel_init_info_list[i].name,
 +                &s->sels[i], TYPE_NPCM7XX_CLOCK_SEL);
 +        npcm7xx_init_clock_sel(&s->sels[i], s,
 +                &sel_init_info_list[i]);
 +    }
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
 +        object_initialize_child(OBJECT(s), divider_init_info_list[i].name,
 +                &s->dividers[i], TYPE_NPCM7XX_CLOCK_DIVIDER);
 +        npcm7xx_init_clock_divider(&s->dividers[i], s,
 +                &divider_init_info_list[i]);
 +    }
 +
 +    /* Second pass: connect converter modules */
 +    npcm7xx_connect_clocks(s);
 +
 +    clock_update_hz(s->clkref, NPCM7XX_CLOCK_REF_HZ);
 +}
 +
  static void npcm7xx_clk_init(Object *obj)
  {
      NPCM7xxCLKState *s = NPCM7XX_CLK(obj);
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_init(Object *obj)
      memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s,
                            TYPE_NPCM7XX_CLK, 4 * KiB);
      sysbus_init_mmio(&s->parent, &s->iomem);
 -    qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset,
 -            NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS);
  }
 -static const VMStateDescription vmstate_npcm7xx_clk = {
 -    .name = "npcm7xx-clk",
 +static int npcm7xx_clk_post_load(void *opaque, int version_id)
 +{
 +    if (version_id >= 1) {
 +        NPCM7xxCLKState *clk = opaque;
 +
 +        npcm7xx_clk_update_all_clocks(clk);
 +    }
 +
 +    return 0;
 +}
 +
 +static void npcm7xx_clk_realize(DeviceState *dev, Error **errp)
 +{
 +    int i;
 +    NPCM7xxCLKState *s = NPCM7XX_CLK(dev);
 +
 +    qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset,
 +            NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS);
 +    npcm7xx_clk_init_clock_hierarchy(s);
 +
 +    /* Realize child devices */
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
 +        if (!qdev_realize(DEVICE(&s->plls[i]), NULL, errp)) {
 +            return;
 +        }
 +    }
-+
++    for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
-+    if (is_16bit) {
++        if (!qdev_realize(DEVICE(&s->sels[i]), NULL, errp)) {
-+        disas_thumb_insn(dc, insn);
++            return;
-+    } else {
++        }
-+        disas_thumb2_insn(dc, insn);
++    }
-+    }
++    for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
++        if (!qdev_realize(DEVICE(&s->dividers[i]), NULL, errp)) {
-     /* Advance the Thumb condexec condition.  */
++            return;
-     if (dc->condexec_mask) {
++        }
 +    }
 +}
 +
 +static const VMStateDescription vmstate_npcm7xx_clk_pll = {
 +    .name = "npcm7xx-clock-pll",
      .version_id = 0,
      .minimum_version_id = 0,
 -    .fields = (VMStateField[]) {
 -        VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS),
 -        VMSTATE_INT64(ref_ns, NPCM7xxCLKState),
 +    .fields =  (VMStateField[]) {
 +        VMSTATE_CLOCK(clock_in, NPCM7xxClockPLLState),
          VMSTATE_END_OF_LIST(),
      },
  };
 +static const VMStateDescription vmstate_npcm7xx_clk_sel = {
 +    .name = "npcm7xx-clock-sel",
 +    .version_id = 0,
 +    .minimum_version_id = 0,
 +    .fields =  (VMStateField[]) {
 +        VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(clock_in, NPCM7xxClockSELState,
 +                NPCM7XX_CLK_SEL_MAX_INPUT, 0, vmstate_clock, Clock),
 +        VMSTATE_END_OF_LIST(),
 +    },
 +};
 +
 +static const VMStateDescription vmstate_npcm7xx_clk_divider = {
 +    .name = "npcm7xx-clock-divider",
 +    .version_id = 0,
 +    .minimum_version_id = 0,
 +    .fields =  (VMStateField[]) {
 +        VMSTATE_CLOCK(clock_in, NPCM7xxClockDividerState),
 +        VMSTATE_END_OF_LIST(),
 +    },
 +};
 +
 +static const VMStateDescription vmstate_npcm7xx_clk = {
 +    .name = "npcm7xx-clk",
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .post_load = npcm7xx_clk_post_load,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS),
 +        VMSTATE_INT64(ref_ns, NPCM7xxCLKState),
 +        VMSTATE_CLOCK(clkref, NPCM7xxCLKState),
 +        VMSTATE_END_OF_LIST(),
 +    },
 +};
 +
 +static void npcm7xx_clk_pll_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->desc = "NPCM7xx Clock PLL Module";
 +    dc->vmsd = &vmstate_npcm7xx_clk_pll;
 +}
 +
 +static void npcm7xx_clk_sel_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->desc = "NPCM7xx Clock SEL Module";
 +    dc->vmsd = &vmstate_npcm7xx_clk_sel;
 +}
 +
 +static void npcm7xx_clk_divider_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->desc = "NPCM7xx Clock Divider Module";
 +    dc->vmsd = &vmstate_npcm7xx_clk_divider;
 +}
 +
  static void npcm7xx_clk_class_init(ObjectClass *klass, void *data)
  {
      ResettableClass *rc = RESETTABLE_CLASS(klass);
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_class_init(ObjectClass *klass, void *data)
      dc->desc = "NPCM7xx Clock Control Registers";
      dc->vmsd = &vmstate_npcm7xx_clk;
 +    dc->realize = npcm7xx_clk_realize;
      rc->phases.enter = npcm7xx_clk_enter_reset;
  }
 +static const TypeInfo npcm7xx_clk_pll_info = {
 +    .name               = TYPE_NPCM7XX_CLOCK_PLL,
 +    .parent             = TYPE_DEVICE,
 +    .instance_size      = sizeof(NPCM7xxClockPLLState),
 +    .instance_init      = npcm7xx_clk_pll_init,
 +    .class_init         = npcm7xx_clk_pll_class_init,
 +};
 +
 +static const TypeInfo npcm7xx_clk_sel_info = {
 +    .name               = TYPE_NPCM7XX_CLOCK_SEL,
 +    .parent             = TYPE_DEVICE,
 +    .instance_size      = sizeof(NPCM7xxClockSELState),
 +    .instance_init      = npcm7xx_clk_sel_init,
 +    .class_init         = npcm7xx_clk_sel_class_init,
 +};
 +
 +static const TypeInfo npcm7xx_clk_divider_info = {
 +    .name               = TYPE_NPCM7XX_CLOCK_DIVIDER,
 +    .parent             = TYPE_DEVICE,
 +    .instance_size      = sizeof(NPCM7xxClockDividerState),
 +    .instance_init      = npcm7xx_clk_divider_init,
 +    .class_init         = npcm7xx_clk_divider_class_init,
 +};
 +
  static const TypeInfo npcm7xx_clk_info = {
      .name               = TYPE_NPCM7XX_CLK,
      .parent             = TYPE_SYS_BUS_DEVICE,
@@ -XXX,XX +XXX,XX @@ static const TypeInfo npcm7xx_clk_info = {
  static void npcm7xx_clk_register_type(void)
  {
 +    type_register_static(&npcm7xx_clk_pll_info);
 +    type_register_static(&npcm7xx_clk_sel_info);
 +    type_register_static(&npcm7xx_clk_divider_info);
      type_register_static(&npcm7xx_clk_info);
  }
  type_init(npcm7xx_clk_register_type);
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 05/13] target/arm: Implement BLXNS
+[PULL 16/21] hw/timer: Refactor NPCM7XX Timer to use CLK clock
-Implement the BLXNS instruction, which allows secure code to
+From: Hao Wu <wuhaotsh@google.com>
 call non-secure code.
+This patch makes NPCM7XX Timer to use a the timer clock generated by the
+CLK module instead of the magic number TIMER_REF_HZ.
+Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
+Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
+Signed-off-by: Hao Wu <wuhaotsh@google.com>
+Message-id: 20210108190945.949196-3-wuhaotsh@google.com
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 1507556919-24992-4-git-send-email-peter.maydell@linaro.org
 ---
- target/arm/helper.h    |  1 +
+ include/hw/misc/npcm7xx_clk.h    |  6 -----
- target/arm/internals.h |  1 +
+ include/hw/timer/npcm7xx_timer.h |  1 +
- target/arm/helper.c    | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++
+ hw/arm/npcm7xx.c                 |  5 ++++
- target/arm/translate.c | 17 +++++++++++++--
+ hw/timer/npcm7xx_timer.c         | 39 +++++++++++++++-----------------
-files changed, 76 insertions(+), 2 deletions(-)
+files changed, 24 insertions(+), 27 deletions(-)
-diff --git a/target/arm/helper.h b/target/arm/helper.h
+diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.h
+--- a/include/hw/misc/npcm7xx_clk.h
-+++ b/target/arm/helper.h
++++ b/include/hw/misc/npcm7xx_clk.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(v7m_msr, void, env, i32, i32)
+@@ -XXX,XX +XXX,XX @@
- DEF_HELPER_2(v7m_mrs, i32, env, i32)
+ #include "hw/clock.h"
+ #include "hw/sysbus.h"
- DEF_HELPER_2(v7m_bxns, void, env, i32)
-+DEF_HELPER_2(v7m_blxns, void, env, i32)
+-/*
+- * The reference clock frequency for the timer modules, and the SECCNT and
- DEF_HELPER_4(access_check_cp_reg, void, env, ptr, i32, i32)
+- * CNTR25M registers in this module, is always 25 MHz.
- DEF_HELPER_3(set_cp_reg, void, env, ptr, i32)
+- */
-diff --git a/target/arm/internals.h b/target/arm/internals.h
+-#define NPCM7XX_TIMER_REF_HZ            (25000000)
 -
  /*
   * Number of registers in our device state structure. Don't change this without
   * incrementing the version_id in the vmstate.
 diff --git a/include/hw/timer/npcm7xx_timer.h b/include/hw/timer/npcm7xx_timer.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/internals.h
+--- a/include/hw/timer/npcm7xx_timer.h
-+++ b/target/arm/internals.h
++++ b/include/hw/timer/npcm7xx_timer.h
-@@ -XXX,XX +XXX,XX @@ static inline bool excp_is_internal(int excp)
+@@ -XXX,XX +XXX,XX @@ struct NPCM7xxTimerCtrlState {
- FIELD(V7M_CONTROL, NPRIV, 0, 1)
- FIELD(V7M_CONTROL, SPSEL, 1, 1)
+     uint32_t    tisr;
- FIELD(V7M_CONTROL, FPCA, 2, 1)
-+FIELD(V7M_CONTROL, SFPA, 3, 1)
++    Clock       *clock;
+     NPCM7xxTimer timer[NPCM7XX_TIMERS_PER_CTRL];
- /* Bit definitions for v7M exception return payload */
+     NPCM7xxWatchdogTimer watchdog_timer;
- FIELD(V7M_EXCRET, ES, 0, 1)
+ };
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/hw/arm/npcm7xx.c
-+++ b/target/arm/helper.c
++++ b/hw/arm/npcm7xx.c
-@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)
+@@ -XXX,XX +XXX,XX @@
-     g_assert_not_reached();
+ #include "hw/char/serial.h"
  #include "hw/loader.h"
  #include "hw/misc/unimp.h"
 +#include "hw/qdev-clock.h"
  #include "hw/qdev-properties.h"
  #include "qapi/error.h"
  #include "qemu/units.h"
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
          int first_irq;
          int j;
 +        /* Connect the timer clock. */
 +        qdev_connect_clock_in(DEVICE(&s->tim[i]), "clock", qdev_get_clock_out(
 +                    DEVICE(&s->clk), "timer-clock"));
 +
          sysbus_realize(sbd, &error_abort);
          sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]);
 diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/timer/npcm7xx_timer.c
 +++ b/hw/timer/npcm7xx_timer.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu/osdep.h"
  #include "hw/irq.h"
 +#include "hw/qdev-clock.h"
  #include "hw/qdev-properties.h"
 -#include "hw/misc/npcm7xx_clk.h"
  #include "hw/timer/npcm7xx_timer.h"
  #include "migration/vmstate.h"
  #include "qemu/bitops.h"
@@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_tcsr_prescaler(uint32_t tcsr)
  /* Convert a timer cycle count to a time interval in nanoseconds. */
  static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *t, uint32_t count)
  {
 -    int64_t ns = count;
 +    int64_t ticks = count;
 -    ns *= NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ;
 -    ns *= npcm7xx_tcsr_prescaler(t->tcsr);
 +    ticks *= npcm7xx_tcsr_prescaler(t->tcsr);
 -    return ns;
 +    return clock_ticks_to_ns(t->ctrl->clock, ticks);
  }
-+void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
+ /* Convert a time interval in nanoseconds to a timer cycle count. */
-+{
+ static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, int64_t ns)
 +    /* translate.c should never generate calls here in user-only mode */
 +    g_assert_not_reached();
 +}
 +
  void switch_mode(CPUARMState *env, int mode)
  {
-     ARMCPU *cpu = arm_env_get_cpu(env);
+-    int64_t count;
-@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)
+-
-     env->regs[15] = dest & ~1;
+-    count = ns / (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ);
 -    count /= npcm7xx_tcsr_prescaler(t->tcsr);
 -
 -    return count;
 +    return ns / clock_ticks_to_ns(t->ctrl->clock,
 +                                  npcm7xx_tcsr_prescaler(t->tcsr));
  }
-+void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
+ static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t)
-+{
+@@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t)
-+    /* Handle v7M BLXNS:
+ static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t,
-+     *  - bit 0 of the destination address is the target security state
+         int64_t cycles)
 +     */
 +
 +    /* At this point regs[15] is the address just after the BLXNS */
 +    uint32_t nextinst = env->regs[15] | 1;
 +    uint32_t sp = env->regs[13] - 8;
 +    uint32_t saved_psr;
 +
 +    /* translate.c will have made BLXNS UNDEF unless we're secure */
 +    assert(env->v7m.secure);
 +
 +    if (dest & 1) {
 +        /* target is Secure, so this is just a normal BLX,
 +         * except that the low bit doesn't indicate Thumb/not.
 +         */
 +        env->regs[14] = nextinst;
 +        env->thumb = 1;
 +        env->regs[15] = dest & ~1;
 +        return;
 +    }
 +
 +    /* Target is non-secure: first push a stack frame */
 +    if (!QEMU_IS_ALIGNED(sp, 8)) {
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "BLXNS with misaligned SP is UNPREDICTABLE\n");
 +    }
 +
 +    saved_psr = env->v7m.exception;
 +    if (env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK) {
 +        saved_psr |= XPSR_SFPA;
 +    }
 +
 +    /* Note that these stores can throw exceptions on MPU faults */
 +    cpu_stl_data(env, sp, nextinst);
 +    cpu_stl_data(env, sp + 4, saved_psr);
 +
 +    env->regs[13] = sp;
 +    env->regs[14] = 0xfeffffff;
 +    if (arm_v7m_is_handler_mode(env)) {
 +        /* Write a dummy value to IPSR, to avoid leaking the current secure
 +         * exception number to non-secure code. This is guaranteed not
 +         * to cause write_v7m_exception() to actually change stacks.
 +         */
 +        write_v7m_exception(env, 1);
 +    }
 +    switch_v7m_security_state(env, 0);
 +    env->thumb = 1;
 +    env->regs[15] = dest;
 +}
 +
  static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode,
                                  bool spsel)
  {
-diff --git a/target/arm/translate.c b/target/arm/translate.c
+-    uint32_t prescaler = npcm7xx_watchdog_timer_prescaler(t);
-index XXXXXXX..XXXXXXX 100644
+-    int64_t ns = (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ) * cycles;
---- a/target/arm/translate.c
++    int64_t ticks = cycles * npcm7xx_watchdog_timer_prescaler(t);
-+++ b/target/arm/translate.c
++    int64_t ns = clock_ticks_to_ns(t->ctrl->clock, ticks);
-@@ -XXX,XX +XXX,XX @@ static inline void gen_bxns(DisasContext *s, int rm)
-     s->base.is_jmp = DISAS_EXIT;
+     /*
       * The reset function always clears the current timer. The caller of the
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t,
       */
      npcm7xx_timer_clear(&t->base_timer);
 -    ns *= prescaler;
      t->base_timer.remaining_ns = ns;
  }
-+static inline void gen_blxns(DisasContext *s, int rm)
+@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_hold_reset(Object *obj)
-+{
+     qemu_irq_lower(s->watchdog_timer.irq);
-+    TCGv_i32 var = load_reg(s, rm);
+ }
-+
-+    /* We don't need to sync condexec state, for the same reason as bxns.
+-static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
-+     * We do however need to set the PC, because the blxns helper reads it.
++static void npcm7xx_timer_init(Object *obj)
-+     * The blxns helper may throw an exception.
+ {
-+     */
+-    NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(dev);
-+    gen_set_pc_im(s, s->pc);
+-    SysBusDevice *sbd = &s->parent;
-+    gen_helper_v7m_blxns(cpu_env, var);
++    NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj);
-+    tcg_temp_free_i32(var);
++    DeviceState *dev = DEVICE(obj);
-+    s->base.is_jmp = DISAS_EXIT;
++    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
-+}
+     int i;
-+
+     NPCM7xxWatchdogTimer *w;
- /* Variant of store_reg which uses branch&exchange logic when storing
-    to r15 in ARM architecture v7 and above. The source must be a temporary
+@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
-    and will be marked as dead. */
+             npcm7xx_watchdog_timer_expired, w);
-@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
+     sysbus_init_irq(sbd, &w->irq);
-                         goto undef;
-                     }
+-    memory_region_init_io(&s->iomem, OBJECT(s), &npcm7xx_timer_ops, s,
-                     if (link) {
++    memory_region_init_io(&s->iomem, obj, &npcm7xx_timer_ops, s,
--                        /* BLXNS: not yet implemented */
+                           TYPE_NPCM7XX_TIMER, 4 * KiB);
--                        goto undef;
+     sysbus_init_mmio(sbd, &s->iomem);
-+                        gen_blxns(s, rm);
+     qdev_init_gpio_out_named(dev, &w->reset_signal,
-                     } else {
+             NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 1);
-                         gen_bxns(s, rm);
++    s->clock = qdev_init_clock_in(dev, "clock", NULL, NULL);
-                     }
+ }
  static const VMStateDescription vmstate_npcm7xx_base_timer = {
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_npcm7xx_watchdog_timer = {
  static const VMStateDescription vmstate_npcm7xx_timer_ctrl = {
      .name = "npcm7xx-timer-ctrl",
 -    .version_id = 1,
 -    .minimum_version_id = 1,
 +    .version_id = 2,
 +    .minimum_version_id = 2,
      .fields = (VMStateField[]) {
          VMSTATE_UINT32(tisr, NPCM7xxTimerCtrlState),
 +        VMSTATE_CLOCK(clock, NPCM7xxTimerCtrlState),
          VMSTATE_STRUCT_ARRAY(timer, NPCM7xxTimerCtrlState,
                               NPCM7XX_TIMERS_PER_CTRL, 0, vmstate_npcm7xx_timer,
                               NPCM7xxTimer),
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_class_init(ObjectClass *klass, void *data)
      QEMU_BUILD_BUG_ON(NPCM7XX_TIMER_REGS_END > NPCM7XX_TIMER_NR_REGS);
      dc->desc = "NPCM7xx Timer Controller";
 -    dc->realize = npcm7xx_timer_realize;
      dc->vmsd = &vmstate_npcm7xx_timer_ctrl;
      rc->phases.enter = npcm7xx_timer_enter_reset;
      rc->phases.hold = npcm7xx_timer_hold_reset;
@@ -XXX,XX +XXX,XX @@ static const TypeInfo npcm7xx_timer_info = {
      .parent             = TYPE_SYS_BUS_DEVICE,
      .instance_size      = sizeof(NPCM7xxTimerCtrlState),
      .class_init         = npcm7xx_timer_class_init,
 +    .instance_init      = npcm7xx_timer_init,
  };
  static void npcm7xx_timer_register_type(void)
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 06/13] target/arm: Implement secure function return
+[PULL 17/21] hw/adc: Add an ADC module for NPCM7XX
-Secure function return happens when a non-secure function has been
+From: Hao Wu <wuhaotsh@google.com>
 called using BLXNS and so has a particular magic LR value (either
 xfefffffe or 0xfeffffff). The function return via BX behaves
 specially when the new PC value is this magic value, in the same
 way that exception returns are handled.
-Adjust our BX excret guards so that they recognize the function
+The ADC is part of NPCM7XX Module. Its behavior is controled by the
-return magic number as well, and perform the function-return
+ADC_CON register. It converts one of the eight analog inputs into a
-unstacking in do_v7m_exception_exit().
+digital input and stores it in the ADC_DATA register when enabled.
+Users can alter input value by using qom-set QMP command.
+Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
+Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
+Signed-off-by: Hao Wu <wuhaotsh@google.com>
+Message-id: 20210108190945.949196-4-wuhaotsh@google.com
+[PMM: Added missing hw/adc/trace.h file]
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 1507556919-24992-5-git-send-email-peter.maydell@linaro.org
 ---
- target/arm/internals.h |   7 +++
+ docs/system/arm/nuvoton.rst    |   2 +-
- target/arm/helper.c    | 115 +++++++++++++++++++++++++++++++++++++++++++++----
+ meson.build                    |   1 +
- target/arm/translate.c |  14 +++++-
+ hw/adc/trace.h                 |   1 +
-files changed, 126 insertions(+), 10 deletions(-)
+ include/hw/adc/npcm7xx_adc.h   |  69 ++++++
  include/hw/arm/npcm7xx.h       |   2 +
  hw/adc/npcm7xx_adc.c           | 301 ++++++++++++++++++++++++++
  hw/arm/npcm7xx.c               |  24 ++-
  tests/qtest/npcm7xx_adc-test.c | 377 +++++++++++++++++++++++++++++++++
  hw/adc/meson.build             |   1 +
  hw/adc/trace-events            |   5 +
  tests/qtest/meson.build        |   3 +-
 files changed, 783 insertions(+), 3 deletions(-)
  create mode 100644 hw/adc/trace.h
  create mode 100644 include/hw/adc/npcm7xx_adc.h
  create mode 100644 hw/adc/npcm7xx_adc.c
  create mode 100644 tests/qtest/npcm7xx_adc-test.c
  create mode 100644 hw/adc/trace-events
-diff --git a/target/arm/internals.h b/target/arm/internals.h
+diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/internals.h
+--- a/docs/system/arm/nuvoton.rst
-+++ b/target/arm/internals.h
++++ b/docs/system/arm/nuvoton.rst
-@@ -XXX,XX +XXX,XX @@ FIELD(V7M_EXCRET, DCRS, 5, 1)
+@@ -XXX,XX +XXX,XX @@ Supported devices
- FIELD(V7M_EXCRET, S, 6, 1)
+  * Random Number Generator (RNG)
- FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */
+  * USB host (USBH)
+  * GPIO controller
-+/* Minimum value which is a magic number for exception return */
++ * Analog to Digital Converter (ADC)
-+#define EXC_RETURN_MIN_MAGIC 0xff000000
-+/* Minimum number which is a magic number for function or exception return
+ Missing devices
-+ * when using v8M security extension
+ ---------------
@@ -XXX,XX +XXX,XX @@ Missing devices
   * USB device (USBD)
   * SMBus controller (SMBF)
   * Peripheral SPI controller (PSPI)
 - * Analog to Digital Converter (ADC)
   * SD/MMC host
   * PECI interface
   * Pulse Width Modulation (PWM)
 diff --git a/meson.build b/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/meson.build
 +++ b/meson.build
@@ -XXX,XX +XXX,XX @@ if have_system
      'chardev',
      'hw/9pfs',
      'hw/acpi',
 +    'hw/adc',
      'hw/alpha',
      'hw/arm',
      'hw/audio',
 diff --git a/hw/adc/trace.h b/hw/adc/trace.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/adc/trace.h
@@ -0,0 +1 @@
 +#include "trace/trace-hw_adc.h"
 diff --git a/include/hw/adc/npcm7xx_adc.h b/include/hw/adc/npcm7xx_adc.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/include/hw/adc/npcm7xx_adc.h
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Nuvoton NPCM7xx ADC Module
 + *
 + * Copyright 2020 Google LLC
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms of the GNU General Public License as published by the
 + * Free Software Foundation; either version 2 of the License, or
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 + * for more details.
 + */
-+#define FNC_RETURN_MIN_MAGIC 0xfefffffe
++#ifndef NPCM7XX_ADC_H
-+
++#define NPCM7XX_ADC_H
- /* We use a few fake FSR values for internal purposes in M profile.
++
-  * M profile cores don't have A/R format FSRs, but currently our
++#include "hw/clock.h"
-  * get_phys_addr() code assumes A/R profile and reports failures via
++#include "hw/irq.h"
-diff --git a/target/arm/helper.c b/target/arm/helper.c
++#include "hw/sysbus.h"
 +#include "qemu/timer.h"
 +
 +#define NPCM7XX_ADC_NUM_INPUTS      8
 +/**
 + * This value should not be changed unless write_adc_calibration function in
 + * hw/arm/npcm7xx.c is also changed.
 + */
 +#define NPCM7XX_ADC_NUM_CALIB       2
 +
 +/**
 + * struct NPCM7xxADCState - Analog to Digital Converter Module device state.
 + * @parent: System bus device.
 + * @iomem: Memory region through which registers are accessed.
 + * @conv_timer: The timer counts down remaining cycles for the conversion.
 + * @irq: GIC interrupt line to fire on expiration (if enabled).
 + * @con: The Control Register.
 + * @data: The Data Buffer.
 + * @clock: The ADC Clock.
 + * @adci: The input voltage in units of uV. 1uv = 1e-6V.
 + * @vref: The external reference voltage.
 + * @iref: The internal reference voltage, initialized at launch time.
 + * @rv: The calibrated output values of 0.5V and 1.5V for the ADC.
 + */
 +typedef struct {
 +    SysBusDevice parent;
 +
 +    MemoryRegion iomem;
 +
 +    QEMUTimer    conv_timer;
 +
 +    qemu_irq     irq;
 +    uint32_t     con;
 +    uint32_t     data;
 +    Clock       *clock;
 +
 +    /* Voltages are in unit of uV. 1V = 1000000uV. */
 +    uint32_t     adci[NPCM7XX_ADC_NUM_INPUTS];
 +    uint32_t     vref;
 +    uint32_t     iref;
 +
 +    uint16_t     calibration_r_values[NPCM7XX_ADC_NUM_CALIB];
 +} NPCM7xxADCState;
 +
 +#define TYPE_NPCM7XX_ADC "npcm7xx-adc"
 +#define NPCM7XX_ADC(obj) \
 +    OBJECT_CHECK(NPCM7xxADCState, (obj), TYPE_NPCM7XX_ADC)
 +
 +#endif /* NPCM7XX_ADC_H */
 diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/include/hw/arm/npcm7xx.h
-+++ b/target/arm/helper.c
++++ b/include/hw/arm/npcm7xx.h
-@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)
+@@ -XXX,XX +XXX,XX @@
-      *  - if the return value is a magic value, do exception return (like BX)
+ #define NPCM7XX_H
-      *  - otherwise bit 0 of the return value is the target security state
-      */
+ #include "hw/boards.h"
--    if (dest >= 0xff000000) {
++#include "hw/adc/npcm7xx_adc.h"
-+    uint32_t min_magic;
+ #include "hw/cpu/a9mpcore.h"
-+
+ #include "hw/gpio/npcm7xx_gpio.h"
-+    if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
+ #include "hw/mem/npcm7xx_mc.h"
-+        /* Covers FNC_RETURN and EXC_RETURN magic */
+@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
-+        min_magic = FNC_RETURN_MIN_MAGIC;
+     NPCM7xxGCRState     gcr;
-+    } else {
+     NPCM7xxCLKState     clk;
-+        /* EXC_RETURN magic only */
+     NPCM7xxTimerCtrlState tim[3];
-+        min_magic = EXC_RETURN_MIN_MAGIC;
++    NPCM7xxADCState     adc;
-+    }
+     NPCM7xxOTPState     key_storage;
-+
+     NPCM7xxOTPState     fuse_array;
-+    if (dest >= min_magic) {
+     NPCM7xxMCState      mc;
-         /* This is an exception return magic value; put it where
+diff --git a/hw/adc/npcm7xx_adc.c b/hw/adc/npcm7xx_adc.c
-          * do_v7m_exception_exit() expects and raise EXCEPTION_EXIT.
+new file mode 100644
-          * Note that if we ever add gen_ss_advance() singlestep support to
+index XXXXXXX..XXXXXXX
-@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
+--- /dev/null
-     bool exc_secure = false;
++++ b/hw/adc/npcm7xx_adc.c
-     bool return_to_secure;
+@@ -XXX,XX +XXX,XX @@
++/*
--    /* We can only get here from an EXCP_EXCEPTION_EXIT, and
++ * Nuvoton NPCM7xx ADC Module
--     * gen_bx_excret() enforces the architectural rule
++ *
--     * that jumps to magic addresses don't have magic behaviour unless
++ * Copyright 2020 Google LLC
--     * we're in Handler mode (compare pseudocode BXWritePC()).
++ *
-+    /* If we're not in Handler mode then jumps to magic exception-exit
++ * This program is free software; you can redistribute it and/or modify it
-+     * addresses don't have magic behaviour. However for the v8M
++ * under the terms of the GNU General Public License as published by the
-+     * security extensions the magic secure-function-return has to
++ * Free Software Foundation; either version 2 of the License, or
-+     * work in thread mode too, so to avoid doing an extra check in
++ * (at your option) any later version.
-+     * the generated code we allow exception-exit magic to also cause the
++ *
-+     * internal exception and bring us here in thread mode. Correct code
++ * This program is distributed in the hope that it will be useful, but WITHOUT
-+     * will never try to do this (the following insn fetch will always
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+     * fault) so we the overhead of having taken an unnecessary exception
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-+     * doesn't matter.
++ * for more details.
-      */
++ */
--    assert(arm_v7m_is_handler_mode(env));
++
-+    if (!arm_v7m_is_handler_mode(env)) {
++#include "qemu/osdep.h"
 +#include "hw/adc/npcm7xx_adc.h"
 +#include "hw/qdev-clock.h"
 +#include "hw/qdev-properties.h"
 +#include "hw/registerfields.h"
 +#include "migration/vmstate.h"
 +#include "qemu/log.h"
 +#include "qemu/module.h"
 +#include "qemu/timer.h"
 +#include "qemu/units.h"
 +#include "trace.h"
 +
 +REG32(NPCM7XX_ADC_CON, 0x0)
 +REG32(NPCM7XX_ADC_DATA, 0x4)
 +
 +/* Register field definitions. */
 +#define NPCM7XX_ADC_CON_MUX(rv) extract32(rv, 24, 4)
 +#define NPCM7XX_ADC_CON_INT_EN  BIT(21)
 +#define NPCM7XX_ADC_CON_REFSEL  BIT(19)
 +#define NPCM7XX_ADC_CON_INT     BIT(18)
 +#define NPCM7XX_ADC_CON_EN      BIT(17)
 +#define NPCM7XX_ADC_CON_RST     BIT(16)
 +#define NPCM7XX_ADC_CON_CONV    BIT(14)
 +#define NPCM7XX_ADC_CON_DIV(rv) extract32(rv, 1, 8)
 +
 +#define NPCM7XX_ADC_MAX_RESULT      1023
 +#define NPCM7XX_ADC_DEFAULT_IREF    2000000
 +#define NPCM7XX_ADC_CONV_CYCLES     20
 +#define NPCM7XX_ADC_RESET_CYCLES    10
 +#define NPCM7XX_ADC_R0_INPUT        500000
 +#define NPCM7XX_ADC_R1_INPUT        1500000
 +
 +static void npcm7xx_adc_reset(NPCM7xxADCState *s)
 +{
 +    timer_del(&s->conv_timer);
 +    s->con = 0x000c0001;
 +    s->data = 0x00000000;
 +}
 +
 +static uint32_t npcm7xx_adc_convert(uint32_t input, uint32_t ref)
 +{
 +    uint32_t result;
 +
 +    result = input * (NPCM7XX_ADC_MAX_RESULT + 1) / ref;
 +    if (result > NPCM7XX_ADC_MAX_RESULT) {
 +        result = NPCM7XX_ADC_MAX_RESULT;
 +    }
 +
 +    return result;
 +}
 +
 +static uint32_t npcm7xx_adc_prescaler(NPCM7xxADCState *s)
 +{
 +    return 2 * (NPCM7XX_ADC_CON_DIV(s->con) + 1);
 +}
 +
 +static void npcm7xx_adc_start_timer(Clock *clk, QEMUTimer *timer,
 +        uint32_t cycles, uint32_t prescaler)
 +{
 +    int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 +    int64_t ticks = cycles;
 +    int64_t ns;
 +
 +    ticks *= prescaler;
 +    ns = clock_ticks_to_ns(clk, ticks);
 +    ns += now;
 +    timer_mod(timer, ns);
 +}
 +
 +static void npcm7xx_adc_start_convert(NPCM7xxADCState *s)
 +{
 +    uint32_t prescaler = npcm7xx_adc_prescaler(s);
 +
 +    npcm7xx_adc_start_timer(s->clock, &s->conv_timer, NPCM7XX_ADC_CONV_CYCLES,
 +            prescaler);
 +}
 +
 +static void npcm7xx_adc_convert_done(void *opaque)
 +{
 +    NPCM7xxADCState *s = opaque;
 +    uint32_t input = NPCM7XX_ADC_CON_MUX(s->con);
 +    uint32_t ref = (s->con & NPCM7XX_ADC_CON_REFSEL)
 +        ? s->iref : s->vref;
 +
 +    if (input >= NPCM7XX_ADC_NUM_INPUTS) {
 +        qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid input: %u\n",
 +                      __func__, input);
 +        return;
 +    }
++    s->data = npcm7xx_adc_convert(s->adci[input], ref);
-     /* In the spec pseudocode ExceptionReturn() is called directly
++    if (s->con & NPCM7XX_ADC_CON_INT_EN) {
-      * from BXWritePC() and gets the full target PC value including
++        s->con |= NPCM7XX_ADC_CON_INT;
-@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
++        qemu_irq_raise(s->irq);
-     qemu_log_mask(CPU_LOG_INT, "...successful exception return\n");
++    }
- }
++    s->con &= ~NPCM7XX_ADC_CON_CONV;
++}
-+static bool do_v7m_function_return(ARMCPU *cpu)
++
-+{
++static void npcm7xx_adc_calibrate(NPCM7xxADCState *adc)
-+    /* v8M security extensions magic function return.
++{
-+     * We may either:
++    adc->calibration_r_values[0] = npcm7xx_adc_convert(NPCM7XX_ADC_R0_INPUT,
-+     *  (1) throw an exception (longjump)
++            adc->iref);
-+     *  (2) return true if we successfully handled the function return
++    adc->calibration_r_values[1] = npcm7xx_adc_convert(NPCM7XX_ADC_R1_INPUT,
-+     *  (3) return false if we failed a consistency check and have
++            adc->iref);
-+     *      pended a UsageFault that needs to be taken now
++}
-+     *
++
-+     * At this point the magic return value is split between env->regs[15]
++static void npcm7xx_adc_write_con(NPCM7xxADCState *s, uint32_t new_con)
-+     * and env->thumb. We don't bother to reconstitute it because we don't
++{
-+     * need it (all values are handled the same way).
++    uint32_t old_con = s->con;
-+     */
++
-+    CPUARMState *env = &cpu->env;
++    /* Write ADC_INT to 1 to clear it */
-+    uint32_t newpc, newpsr, newpsr_exc;
++    if (new_con & NPCM7XX_ADC_CON_INT) {
-+
++        new_con &= ~NPCM7XX_ADC_CON_INT;
-+    qemu_log_mask(CPU_LOG_INT, "...really v7M secure function return\n");
++        qemu_irq_lower(s->irq);
-+
++    } else if (old_con & NPCM7XX_ADC_CON_INT) {
-+    {
++        new_con |= NPCM7XX_ADC_CON_INT;
-+        bool threadmode, spsel;
++    }
-+        TCGMemOpIdx oi;
++
-+        ARMMMUIdx mmu_idx;
++    s->con = new_con;
-+        uint32_t *frame_sp_p;
++
-+        uint32_t frameptr;
++    if (s->con & NPCM7XX_ADC_CON_RST) {
-+
++        npcm7xx_adc_reset(s);
-+        /* Pull the return address and IPSR from the Secure stack */
++        return;
-+        threadmode = !arm_v7m_is_handler_mode(env);
++    }
-+        spsel = env->v7m.control[M_REG_S] & R_V7M_CONTROL_SPSEL_MASK;
++
-+
++    if ((s->con & NPCM7XX_ADC_CON_EN)) {
-+        frame_sp_p = get_v7m_sp_ptr(env, true, threadmode, spsel);
++        if (s->con & NPCM7XX_ADC_CON_CONV) {
-+        frameptr = *frame_sp_p;
++            if (!(old_con & NPCM7XX_ADC_CON_CONV)) {
-+
++                npcm7xx_adc_start_convert(s);
 +        /* These loads may throw an exception (for MPU faults). We want to
 +         * do them as secure, so work out what MMU index that is.
 +         */
 +        mmu_idx = arm_v7m_mmu_idx_for_secstate(env, true);
 +        oi = make_memop_idx(MO_LE, arm_to_core_mmu_idx(mmu_idx));
 +        newpc = helper_le_ldul_mmu(env, frameptr, oi, 0);
 +        newpsr = helper_le_ldul_mmu(env, frameptr + 4, oi, 0);
 +
 +        /* Consistency checks on new IPSR */
 +        newpsr_exc = newpsr & XPSR_EXCP;
 +        if (!((env->v7m.exception == 0 && newpsr_exc == 0) ||
 +              (env->v7m.exception == 1 && newpsr_exc != 0))) {
 +            /* Pend the fault and tell our caller to take it */
 +            env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;
 +            armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE,
 +                                    env->v7m.secure);
 +            qemu_log_mask(CPU_LOG_INT,
 +                          "...taking INVPC UsageFault: "
 +                          "IPSR consistency check failed\n");
 +            return false;
 +        }
 +
 +        *frame_sp_p = frameptr + 8;
 +    }
 +
 +    /* This invalidates frame_sp_p */
 +    switch_v7m_security_state(env, true);
 +    env->v7m.exception = newpsr_exc;
 +    env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK;
 +    if (newpsr & XPSR_SFPA) {
 +        env->v7m.control[M_REG_S] |= R_V7M_CONTROL_SFPA_MASK;
 +    }
 +    xpsr_write(env, 0, XPSR_IT);
 +    env->thumb = newpc & 1;
 +    env->regs[15] = newpc & ~1;
 +
 +    qemu_log_mask(CPU_LOG_INT, "...function return successful\n");
 +    return true;
 +}
 +
  static void arm_log_exception(int idx)
  {
      if (qemu_loglevel_mask(CPU_LOG_INT)) {
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
      case EXCP_IRQ:
          break;
      case EXCP_EXCEPTION_EXIT:
 -        do_v7m_exception_exit(cpu);
 -        return;
 +        if (env->regs[15] < EXC_RETURN_MIN_MAGIC) {
 +            /* Must be v8M security extension function return */
 +            assert(env->regs[15] >= FNC_RETURN_MIN_MAGIC);
 +            assert(arm_feature(env, ARM_FEATURE_M_SECURITY));
 +            if (do_v7m_function_return(cpu)) {
 +                return;
 +            }
 +        } else {
-+            do_v7m_exception_exit(cpu);
++            timer_del(&s->conv_timer);
 +            return;
 +        }
++    }
++}
++
++static uint64_t npcm7xx_adc_read(void *opaque, hwaddr offset, unsigned size)
++{
++    uint64_t value = 0;
++    NPCM7xxADCState *s = opaque;
++
++    switch (offset) {
++    case A_NPCM7XX_ADC_CON:
++        value = s->con;
 +        break;
-     default:
++
-         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
++    case A_NPCM7XX_ADC_DATA:
-         return; /* Never happens.  Keep compiler happy.  */
++        value = s->data;
-diff --git a/target/arm/translate.c b/target/arm/translate.c
++        break;
 +
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
 +                      __func__, offset);
 +        break;
 +    }
 +
 +    trace_npcm7xx_adc_read(DEVICE(s)->canonical_path, offset, value);
 +    return value;
 +}
 +
 +static void npcm7xx_adc_write(void *opaque, hwaddr offset, uint64_t v,
 +        unsigned size)
 +{
 +    NPCM7xxADCState *s = opaque;
 +
 +    trace_npcm7xx_adc_write(DEVICE(s)->canonical_path, offset, v);
 +    switch (offset) {
 +    case A_NPCM7XX_ADC_CON:
 +        npcm7xx_adc_write_con(s, v);
 +        break;
 +
 +    case A_NPCM7XX_ADC_DATA:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
 +                      __func__, offset);
 +        break;
 +
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
 +                      __func__, offset);
 +        break;
 +    }
 +
 +}
 +
 +static const struct MemoryRegionOps npcm7xx_adc_ops = {
 +    .read       = npcm7xx_adc_read,
 +    .write      = npcm7xx_adc_write,
 +    .endianness = DEVICE_LITTLE_ENDIAN,
 +    .valid      = {
 +        .min_access_size        = 4,
 +        .max_access_size        = 4,
 +        .unaligned              = false,
 +    },
 +};
 +
 +static void npcm7xx_adc_enter_reset(Object *obj, ResetType type)
 +{
 +    NPCM7xxADCState *s = NPCM7XX_ADC(obj);
 +
 +    npcm7xx_adc_reset(s);
 +}
 +
 +static void npcm7xx_adc_hold_reset(Object *obj)
 +{
 +    NPCM7xxADCState *s = NPCM7XX_ADC(obj);
 +
 +    qemu_irq_lower(s->irq);
 +}
 +
 +static void npcm7xx_adc_init(Object *obj)
 +{
 +    NPCM7xxADCState *s = NPCM7XX_ADC(obj);
 +    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 +    int i;
 +
 +    sysbus_init_irq(sbd, &s->irq);
 +
 +    timer_init_ns(&s->conv_timer, QEMU_CLOCK_VIRTUAL,
 +            npcm7xx_adc_convert_done, s);
 +    memory_region_init_io(&s->iomem, obj, &npcm7xx_adc_ops, s,
 +                          TYPE_NPCM7XX_ADC, 4 * KiB);
 +    sysbus_init_mmio(sbd, &s->iomem);
 +    s->clock = qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL);
 +
 +    for (i = 0; i < NPCM7XX_ADC_NUM_INPUTS; ++i) {
 +        object_property_add_uint32_ptr(obj, "adci[*]",
 +                &s->adci[i], OBJ_PROP_FLAG_WRITE);
 +    }
 +    object_property_add_uint32_ptr(obj, "vref",
 +            &s->vref, OBJ_PROP_FLAG_WRITE);
 +    npcm7xx_adc_calibrate(s);
 +}
 +
 +static const VMStateDescription vmstate_npcm7xx_adc = {
 +    .name = "npcm7xx-adc",
 +    .version_id = 0,
 +    .minimum_version_id = 0,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_TIMER(conv_timer, NPCM7xxADCState),
 +        VMSTATE_UINT32(con, NPCM7xxADCState),
 +        VMSTATE_UINT32(data, NPCM7xxADCState),
 +        VMSTATE_CLOCK(clock, NPCM7xxADCState),
 +        VMSTATE_UINT32_ARRAY(adci, NPCM7xxADCState, NPCM7XX_ADC_NUM_INPUTS),
 +        VMSTATE_UINT32(vref, NPCM7xxADCState),
 +        VMSTATE_UINT32(iref, NPCM7xxADCState),
 +        VMSTATE_UINT16_ARRAY(calibration_r_values, NPCM7xxADCState,
 +                NPCM7XX_ADC_NUM_CALIB),
 +        VMSTATE_END_OF_LIST(),
 +    },
 +};
 +
 +static Property npcm7xx_timer_properties[] = {
 +    DEFINE_PROP_UINT32("iref", NPCM7xxADCState, iref, NPCM7XX_ADC_DEFAULT_IREF),
 +    DEFINE_PROP_END_OF_LIST(),
 +};
 +
 +static void npcm7xx_adc_class_init(ObjectClass *klass, void *data)
 +{
 +    ResettableClass *rc = RESETTABLE_CLASS(klass);
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->desc = "NPCM7xx ADC Module";
 +    dc->vmsd = &vmstate_npcm7xx_adc;
 +    rc->phases.enter = npcm7xx_adc_enter_reset;
 +    rc->phases.hold = npcm7xx_adc_hold_reset;
 +
 +    device_class_set_props(dc, npcm7xx_timer_properties);
 +}
 +
 +static const TypeInfo npcm7xx_adc_info = {
 +    .name               = TYPE_NPCM7XX_ADC,
 +    .parent             = TYPE_SYS_BUS_DEVICE,
 +    .instance_size      = sizeof(NPCM7xxADCState),
 +    .class_init         = npcm7xx_adc_class_init,
 +    .instance_init      = npcm7xx_adc_init,
 +};
 +
 +static void npcm7xx_adc_register_types(void)
 +{
 +    type_register_static(&npcm7xx_adc_info);
 +}
 +
 +type_init(npcm7xx_adc_register_types);
 diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
+--- a/hw/arm/npcm7xx.c
-+++ b/target/arm/translate.c
++++ b/hw/arm/npcm7xx.c
-@@ -XXX,XX +XXX,XX @@ static inline void gen_bx_excret(DisasContext *s, TCGv_i32 var)
+@@ -XXX,XX +XXX,XX @@
-      * s->base.is_jmp that we need to do the rest of the work later.
+ #define NPCM7XX_EHCI_BA         (0xf0806000)
-      */
+ #define NPCM7XX_OHCI_BA         (0xf0807000)
-     gen_bx(s, var);
--    if (s->v7m_handler_mode && arm_dc_feature(s, ARM_FEATURE_M)) {
++/* ADC Module */
-+    if (arm_dc_feature(s, ARM_FEATURE_M_SECURITY) ||
++#define NPCM7XX_ADC_BA          (0xf000c000)
-+        (s->v7m_handler_mode && arm_dc_feature(s, ARM_FEATURE_M))) {
++
-         s->base.is_jmp = DISAS_BX_EXCRET;
+ /* Internal AHB SRAM */
-     }
+ #define NPCM7XX_RAM3_BA         (0xc0008000)
  #define NPCM7XX_RAM3_SZ         (4 * KiB)
@@ -XXX,XX +XXX,XX @@
  #define NPCM7XX_ROM_BA          (0xffff0000)
  #define NPCM7XX_ROM_SZ          (64 * KiB)
 +
  /* Clock configuration values to be fixed up when bypassing bootloader */
  /* Run PLL1 at 1600 MHz */
@@ -XXX,XX +XXX,XX @@
   * interrupts.
   */
  enum NPCM7xxInterrupt {
 +    NPCM7XX_ADC_IRQ             = 0,
      NPCM7XX_UART0_IRQ           = 2,
      NPCM7XX_UART1_IRQ,
      NPCM7XX_UART2_IRQ,
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init_fuses(NPCM7xxState *s)
                              sizeof(value));
  }
-@@ -XXX,XX +XXX,XX @@ static inline void gen_bx_excret_final_code(DisasContext *s)
 +static void npcm7xx_write_adc_calibration(NPCM7xxState *s)
 +{
 +    /* Both ADC and the fuse array must have realized. */
 +    QEMU_BUILD_BUG_ON(sizeof(s->adc.calibration_r_values) != 4);
 +    npcm7xx_otp_array_write(&s->fuse_array, s->adc.calibration_r_values,
 +            NPCM7XX_FUSE_ADC_CALIB, sizeof(s->adc.calibration_r_values));
 +}
 +
  static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n)
  {
-     /* Generate the code to finish possible exception return and end the TB */
+     return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
-     TCGLabel *excret_label = gen_new_label();
+@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
-+    uint32_t min_magic;
+                             TYPE_NPCM7XX_FUSE_ARRAY);
-+
+     object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC);
-+    if (arm_dc_feature(s, ARM_FEATURE_M_SECURITY)) {
+     object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG);
-+        /* Covers FNC_RETURN and EXC_RETURN magic */
++    object_initialize_child(obj, "adc", &s->adc, TYPE_NPCM7XX_ADC);
-+        min_magic = FNC_RETURN_MIN_MAGIC;
-+    } else {
+     for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
-+        /* EXC_RETURN magic only */
+         object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
-+        min_magic = EXC_RETURN_MIN_MAGIC;
+@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
-+    }
+     sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort);
+     sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM7XX_MC_BA);
-     /* Is the new PC value in the magic range indicating exception return? */
--    tcg_gen_brcondi_i32(TCG_COND_GEU, cpu_R[15], 0xff000000, excret_label);
++    /* ADC Modules. Cannot fail. */
-+    tcg_gen_brcondi_i32(TCG_COND_GEU, cpu_R[15], min_magic, excret_label);
++    qdev_connect_clock_in(DEVICE(&s->adc), "clock", qdev_get_clock_out(
-     /* No: end the TB as we would for a DISAS_JMP */
++                          DEVICE(&s->clk), "adc-clock"));
-     if (is_singlestepping(s)) {
++    sysbus_realize(SYS_BUS_DEVICE(&s->adc), &error_abort);
-         gen_singlestep_exception(s);
++    sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, NPCM7XX_ADC_BA);
 +    sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
 +            npcm7xx_irq(s, NPCM7XX_ADC_IRQ));
 +    npcm7xx_write_adc_calibration(s);
 +
      /* Timer Modules (TIM). Cannot fail. */
      QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim));
      for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
      create_unimplemented_device("npcm7xx.vdmx",         0xe0800000,   4 * KiB);
      create_unimplemented_device("npcm7xx.pcierc",       0xe1000000,  64 * KiB);
      create_unimplemented_device("npcm7xx.kcs",          0xf0007000,   4 * KiB);
 -    create_unimplemented_device("npcm7xx.adc",          0xf000c000,   4 * KiB);
      create_unimplemented_device("npcm7xx.gfxi",         0xf000e000,   4 * KiB);
      create_unimplemented_device("npcm7xx.gpio[0]",      0xf0010000,   4 * KiB);
      create_unimplemented_device("npcm7xx.gpio[1]",      0xf0011000,   4 * KiB);
 diff --git a/tests/qtest/npcm7xx_adc-test.c b/tests/qtest/npcm7xx_adc-test.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/tests/qtest/npcm7xx_adc-test.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * QTests for Nuvoton NPCM7xx ADCModules.
 + *
 + * Copyright 2020 Google LLC
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms of the GNU General Public License as published by the
 + * Free Software Foundation; either version 2 of the License, or
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 + * for more details.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qemu/bitops.h"
 +#include "qemu/timer.h"
 +#include "libqos/libqtest.h"
 +#include "qapi/qmp/qdict.h"
 +
 +#define REF_HZ          (25000000)
 +
 +#define CON_OFFSET      0x0
 +#define DATA_OFFSET     0x4
 +
 +#define NUM_INPUTS      8
 +#define DEFAULT_IREF    2000000
 +#define CONV_CYCLES     20
 +#define RESET_CYCLES    10
 +#define R0_INPUT        500000
 +#define R1_INPUT        1500000
 +#define MAX_RESULT      1023
 +
 +#define DEFAULT_CLKDIV  5
 +
 +#define FUSE_ARRAY_BA   0xf018a000
 +#define FCTL_OFFSET     0x14
 +#define FST_OFFSET      0x0
 +#define FADDR_OFFSET    0x4
 +#define FDATA_OFFSET    0x8
 +#define ADC_CALIB_ADDR  24
 +#define FUSE_READ       0x2
 +
 +/* Register field definitions. */
 +#define CON_MUX(rv) ((rv) << 24)
 +#define CON_INT_EN  BIT(21)
 +#define CON_REFSEL  BIT(19)
 +#define CON_INT     BIT(18)
 +#define CON_EN      BIT(17)
 +#define CON_RST     BIT(16)
 +#define CON_CONV    BIT(14)
 +#define CON_DIV(rv) extract32(rv, 1, 8)
 +
 +#define FST_RDST    BIT(1)
 +#define FDATA_MASK  0xff
 +
 +#define MAX_ERROR   10000
 +#define MIN_CALIB_INPUT 100000
 +#define MAX_CALIB_INPUT 1800000
 +
 +static const uint32_t input_list[] = {
 +    100000,
 +    500000,
 +    1000000,
 +    1500000,
 +    1800000,
 +    2000000,
 +};
 +
 +static const uint32_t vref_list[] = {
 +    2000000,
 +    2200000,
 +    2500000,
 +};
 +
 +static const uint32_t iref_list[] = {
 +    1800000,
 +    1900000,
 +    2000000,
 +    2100000,
 +    2200000,
 +};
 +
 +static const uint32_t div_list[] = {0, 1, 3, 7, 15};
 +
 +typedef struct ADC {
 +    int irq;
 +    uint64_t base_addr;
 +} ADC;
 +
 +ADC adc = {
 +    .irq        = 0,
 +    .base_addr  = 0xf000c000
 +};
 +
 +static uint32_t adc_read_con(QTestState *qts, const ADC *adc)
 +{
 +    return qtest_readl(qts, adc->base_addr + CON_OFFSET);
 +}
 +
 +static void adc_write_con(QTestState *qts, const ADC *adc, uint32_t value)
 +{
 +    qtest_writel(qts, adc->base_addr + CON_OFFSET, value);
 +}
 +
 +static uint32_t adc_read_data(QTestState *qts, const ADC *adc)
 +{
 +    return qtest_readl(qts, adc->base_addr + DATA_OFFSET);
 +}
 +
 +static uint32_t adc_calibrate(uint32_t measured, uint32_t *rv)
 +{
 +    return R0_INPUT + (R1_INPUT - R0_INPUT) * (int32_t)(measured - rv[0])
 +        / (int32_t)(rv[1] - rv[0]);
 +}
 +
 +static void adc_qom_set(QTestState *qts, const ADC *adc,
 +        const char *name, uint32_t value)
 +{
 +    QDict *response;
 +    const char *path = "/machine/soc/adc";
 +
 +    g_test_message("Setting properties %s of %s with value %u",
 +            name, path, value);
 +    response = qtest_qmp(qts, "{ 'execute': 'qom-set',"
 +            " 'arguments': { 'path': %s, 'property': %s, 'value': %u}}",
 +            path, name, value);
 +    /* The qom set message returns successfully. */
 +    g_assert_true(qdict_haskey(response, "return"));
 +}
 +
 +static void adc_write_input(QTestState *qts, const ADC *adc,
 +        uint32_t index, uint32_t value)
 +{
 +    char name[100];
 +
 +    sprintf(name, "adci[%u]", index);
 +    adc_qom_set(qts, adc, name, value);
 +}
 +
 +static void adc_write_vref(QTestState *qts, const ADC *adc, uint32_t value)
 +{
 +    adc_qom_set(qts, adc, "vref", value);
 +}
 +
 +static uint32_t adc_calculate_output(uint32_t input, uint32_t ref)
 +{
 +    uint32_t output;
 +
 +    g_assert_cmpuint(input, <=, ref);
 +    output = (input * (MAX_RESULT + 1)) / ref;
 +    if (output > MAX_RESULT) {
 +        output = MAX_RESULT;
 +    }
 +
 +    return output;
 +}
 +
 +static uint32_t adc_prescaler(QTestState *qts, const ADC *adc)
 +{
 +    uint32_t div = extract32(adc_read_con(qts, adc), 1, 8);
 +
 +    return 2 * (div + 1);
 +}
 +
 +static int64_t adc_calculate_steps(uint32_t cycles, uint32_t prescale,
 +        uint32_t clkdiv)
 +{
 +    return (NANOSECONDS_PER_SECOND / (REF_HZ >> clkdiv)) * cycles * prescale;
 +}
 +
 +static void adc_wait_conv_finished(QTestState *qts, const ADC *adc,
 +        uint32_t clkdiv)
 +{
 +    uint32_t prescaler = adc_prescaler(qts, adc);
 +
 +    /*
 +     * ADC should takes roughly 20 cycles to convert one sample. So we assert it
 +     * should take 10~30 cycles here.
 +     */
 +    qtest_clock_step(qts, adc_calculate_steps(CONV_CYCLES / 2, prescaler,
 +                clkdiv));
 +    /* ADC is still converting. */
 +    g_assert_true(adc_read_con(qts, adc) & CON_CONV);
 +    qtest_clock_step(qts, adc_calculate_steps(CONV_CYCLES, prescaler, clkdiv));
 +    /* ADC has finished conversion. */
 +    g_assert_false(adc_read_con(qts, adc) & CON_CONV);
 +}
 +
 +/* Check ADC can be reset to default value. */
 +static void test_init(gconstpointer adc_p)
 +{
 +    const ADC *adc = adc_p;
 +
 +    QTestState *qts = qtest_init("-machine quanta-gsj");
 +    adc_write_con(qts, adc, CON_REFSEL | CON_INT);
 +    g_assert_cmphex(adc_read_con(qts, adc), ==, CON_REFSEL);
 +    qtest_quit(qts);
 +}
 +
 +/* Check ADC can convert from an internal reference. */
 +static void test_convert_internal(gconstpointer adc_p)
 +{
 +    const ADC *adc = adc_p;
 +    uint32_t index, input, output, expected_output;
 +    QTestState *qts = qtest_init("-machine quanta-gsj");
 +    qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
 +
 +    for (index = 0; index < NUM_INPUTS; ++index) {
 +        for (size_t i = 0; i < ARRAY_SIZE(input_list); ++i) {
 +            input = input_list[i];
 +            expected_output = adc_calculate_output(input, DEFAULT_IREF);
 +
 +            adc_write_input(qts, adc, index, input);
 +            adc_write_con(qts, adc, CON_MUX(index) | CON_REFSEL | CON_INT |
 +                    CON_EN | CON_CONV);
 +            adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
 +            g_assert_cmphex(adc_read_con(qts, adc), ==, CON_MUX(index) |
 +                    CON_REFSEL | CON_EN);
 +            g_assert_false(qtest_get_irq(qts, adc->irq));
 +            output = adc_read_data(qts, adc);
 +            g_assert_cmpuint(output, ==, expected_output);
 +        }
 +    }
 +
 +    qtest_quit(qts);
 +}
 +
 +/* Check ADC can convert from an external reference. */
 +static void test_convert_external(gconstpointer adc_p)
 +{
 +    const ADC *adc = adc_p;
 +    uint32_t index, input, vref, output, expected_output;
 +    QTestState *qts = qtest_init("-machine quanta-gsj");
 +    qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
 +
 +    for (index = 0; index < NUM_INPUTS; ++index) {
 +        for (size_t i = 0; i < ARRAY_SIZE(input_list); ++i) {
 +            for (size_t j = 0; j < ARRAY_SIZE(vref_list); ++j) {
 +                input = input_list[i];
 +                vref = vref_list[j];
 +                expected_output = adc_calculate_output(input, vref);
 +
 +                adc_write_input(qts, adc, index, input);
 +                adc_write_vref(qts, adc, vref);
 +                adc_write_con(qts, adc, CON_MUX(index) | CON_INT | CON_EN |
 +                        CON_CONV);
 +                adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
 +                g_assert_cmphex(adc_read_con(qts, adc), ==,
 +                        CON_MUX(index) | CON_EN);
 +                g_assert_false(qtest_get_irq(qts, adc->irq));
 +                output = adc_read_data(qts, adc);
 +                g_assert_cmpuint(output, ==, expected_output);
 +            }
 +        }
 +    }
 +
 +    qtest_quit(qts);
 +}
 +
 +/* Check ADC interrupt files if and only if CON_INT_EN is set. */
 +static void test_interrupt(gconstpointer adc_p)
 +{
 +    const ADC *adc = adc_p;
 +    uint32_t index, input, output, expected_output;
 +    QTestState *qts = qtest_init("-machine quanta-gsj");
 +
 +    index = 1;
 +    input = input_list[1];
 +    expected_output = adc_calculate_output(input, DEFAULT_IREF);
 +
 +    qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
 +    adc_write_input(qts, adc, index, input);
 +    g_assert_false(qtest_get_irq(qts, adc->irq));
 +    adc_write_con(qts, adc, CON_MUX(index) | CON_INT_EN | CON_REFSEL | CON_INT
 +            | CON_EN | CON_CONV);
 +    adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
 +    g_assert_cmphex(adc_read_con(qts, adc), ==, CON_MUX(index) | CON_INT_EN
 +            | CON_REFSEL | CON_INT | CON_EN);
 +    g_assert_true(qtest_get_irq(qts, adc->irq));
 +    output = adc_read_data(qts, adc);
 +    g_assert_cmpuint(output, ==, expected_output);
 +
 +    qtest_quit(qts);
 +}
 +
 +/* Check ADC is reset after setting ADC_RST for 10 ADC cycles. */
 +static void test_reset(gconstpointer adc_p)
 +{
 +    const ADC *adc = adc_p;
 +    QTestState *qts = qtest_init("-machine quanta-gsj");
 +
 +    for (size_t i = 0; i < ARRAY_SIZE(div_list); ++i) {
 +        uint32_t div = div_list[i];
 +
 +        adc_write_con(qts, adc, CON_INT | CON_EN | CON_RST | CON_DIV(div));
 +        qtest_clock_step(qts, adc_calculate_steps(RESET_CYCLES,
 +                    adc_prescaler(qts, adc), DEFAULT_CLKDIV));
 +        g_assert_false(adc_read_con(qts, adc) & CON_EN);
 +    }
 +    qtest_quit(qts);
 +}
 +
 +/* Check ADC Calibration works as desired. */
 +static void test_calibrate(gconstpointer adc_p)
 +{
 +    int i, j;
 +    const ADC *adc = adc_p;
 +
 +    for (j = 0; j < ARRAY_SIZE(iref_list); ++j) {
 +        uint32_t iref = iref_list[j];
 +        uint32_t expected_rv[] = {
 +            adc_calculate_output(R0_INPUT, iref),
 +            adc_calculate_output(R1_INPUT, iref),
 +        };
 +        char buf[100];
 +        QTestState *qts;
 +
 +        sprintf(buf, "-machine quanta-gsj -global npcm7xx-adc.iref=%u", iref);
 +        qts = qtest_init(buf);
 +
 +        /* Check the converted value is correct using the calibration value. */
 +        for (i = 0; i < ARRAY_SIZE(input_list); ++i) {
 +            uint32_t input;
 +            uint32_t output;
 +            uint32_t expected_output;
 +            uint32_t calibrated_voltage;
 +            uint32_t index = 0;
 +
 +            input = input_list[i];
 +            /* Calibration only works for input range 0.1V ~ 1.8V. */
 +            if (input < MIN_CALIB_INPUT || input > MAX_CALIB_INPUT) {
 +                continue;
 +            }
 +            expected_output = adc_calculate_output(input, iref);
 +
 +            adc_write_input(qts, adc, index, input);
 +            adc_write_con(qts, adc, CON_MUX(index) | CON_REFSEL | CON_INT |
 +                    CON_EN | CON_CONV);
 +            adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
 +            g_assert_cmphex(adc_read_con(qts, adc), ==,
 +                    CON_REFSEL | CON_MUX(index) | CON_EN);
 +            output = adc_read_data(qts, adc);
 +            g_assert_cmpuint(output, ==, expected_output);
 +
 +            calibrated_voltage = adc_calibrate(output, expected_rv);
 +            g_assert_cmpuint(calibrated_voltage, >, input - MAX_ERROR);
 +            g_assert_cmpuint(calibrated_voltage, <, input + MAX_ERROR);
 +        }
 +
 +        qtest_quit(qts);
 +    }
 +}
 +
 +static void adc_add_test(const char *name, const ADC* wd,
 +        GTestDataFunc fn)
 +{
 +    g_autofree char *full_name = g_strdup_printf("npcm7xx_adc/%s",  name);
 +    qtest_add_data_func(full_name, wd, fn);
 +}
 +#define add_test(name, td) adc_add_test(#name, td, test_##name)
 +
 +int main(int argc, char **argv)
 +{
 +    g_test_init(&argc, &argv, NULL);
 +
 +    add_test(init, &adc);
 +    add_test(convert_internal, &adc);
 +    add_test(convert_external, &adc);
 +    add_test(interrupt, &adc);
 +    add_test(reset, &adc);
 +    add_test(calibrate, &adc);
 +
 +    return g_test_run();
 +}
 diff --git a/hw/adc/meson.build b/hw/adc/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/adc/meson.build
 +++ b/hw/adc/meson.build
@@ -1 +1,2 @@
  softmmu_ss.add(when: 'CONFIG_STM32F2XX_ADC', if_true: files('stm32f2xx_adc.c'))
 +softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_adc.c'))
 diff --git a/hw/adc/trace-events b/hw/adc/trace-events
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/adc/trace-events
@@ -XXX,XX +XXX,XX @@
 +# See docs/devel/tracing.txt for syntax documentation.
 +
 +# npcm7xx_adc.c
 +npcm7xx_adc_read(const char *id, uint64_t offset, uint32_t value) " %s offset: 0x%04" PRIx64 " value 0x%04" PRIx32
 +npcm7xx_adc_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value 0x%04" PRIx32
 diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/qtest/meson.build
 +++ b/tests/qtest/meson.build
@@ -XXX,XX +XXX,XX @@ qtests_sparc64 = \
    ['prom-env-test', 'boot-serial-test']
  qtests_npcm7xx = \
 -  ['npcm7xx_gpio-test',
 +  ['npcm7xx_adc-test',
 +   'npcm7xx_gpio-test',
     'npcm7xx_rng-test',
     'npcm7xx_timer-test',
     'npcm7xx_watchdog_timer-test']
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 01/13] watchdog/aspeed: fix variable type to store reload value
+[PULL 18/21] hw/misc: Add a PWM module for NPCM7XX
-From: Cédric Le Goater <clg@kaod.org>
+From: Hao Wu <wuhaotsh@google.com>
-Initially from Anton D. Kachalov" <mouse@yandex-team.ru> but the SoB was
+The PWM module is part of NPCM7XX module. Each NPCM7XX module has two
-missing.
+identical PWM modules. Each module contains 4 PWM entries. Each PWM has
 two outputs: frequency and duty_cycle. Both are computed using inputs
 from software side.
-Signed-off-by: Cédric Le Goater <clg@kaod.org>
+This module does not model detail pulse signals since it is expensive.
-Acked-by: Andrew Jeffery <andrew@aj.id.au>
+It also does not model interrupts and watchdogs that are dependant on
-Message-id: 20170920064915.30027-1-clg@kaod.org
+the detail models. The interfaces for these are left in the module so
-[clg: change commit log and subject
+that anyone in need for these functionalities can implement on their
-      replace UL suffix by ULL ]
+own.
-Signed-off-by: Cédric Le Goater <clg@kaod.org>
 The user can read the duty cycle and frequency using qom-get command.
 Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
 Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
 Signed-off-by: Hao Wu <wuhaotsh@google.com>
 Message-id: 20210108190945.949196-5-wuhaotsh@google.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/watchdog/wdt_aspeed.c | 4 ++--
+ docs/system/arm/nuvoton.rst   |   2 +-
-file changed, 2 insertions(+), 2 deletions(-)
+ include/hw/arm/npcm7xx.h      |   2 +
  include/hw/misc/npcm7xx_pwm.h | 105 +++++++
  hw/arm/npcm7xx.c              |  26 +-
  hw/misc/npcm7xx_pwm.c         | 550 ++++++++++++++++++++++++++++++++++
  hw/misc/meson.build           |   1 +
  hw/misc/trace-events          |   6 +
 files changed, 689 insertions(+), 3 deletions(-)
  create mode 100644 include/hw/misc/npcm7xx_pwm.h
  create mode 100644 hw/misc/npcm7xx_pwm.c
-diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c
+diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
 index XXXXXXX..XXXXXXX 100644
---- a/hw/watchdog/wdt_aspeed.c
+--- a/docs/system/arm/nuvoton.rst
-+++ b/hw/watchdog/wdt_aspeed.c
++++ b/docs/system/arm/nuvoton.rst
-@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size)
+@@ -XXX,XX +XXX,XX @@ Supported devices
+  * USB host (USBH)
- static void aspeed_wdt_reload(AspeedWDTState *s, bool pclk)
+  * GPIO controller
- {
+  * Analog to Digital Converter (ADC)
--    uint32_t reload;
++ * Pulse Width Modulation (PWM)
-+    uint64_t reload;
+ Missing devices
-     if (pclk) {
+ ---------------
-         reload = muldiv64(s->regs[WDT_RELOAD_VALUE], NANOSECONDS_PER_SECOND,
+@@ -XXX,XX +XXX,XX @@ Missing devices
-                           s->pclk_freq);
+  * Peripheral SPI controller (PSPI)
-     } else {
+  * SD/MMC host
--        reload = s->regs[WDT_RELOAD_VALUE] * 1000;
+  * PECI interface
-+        reload = s->regs[WDT_RELOAD_VALUE] * 1000ULL;
+- * Pulse Width Modulation (PWM)
   * Tachometer
   * PCI and PCIe root complex and bridges
   * VDM and MCTP support
 diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/npcm7xx.h
 +++ b/include/hw/arm/npcm7xx.h
@@ -XXX,XX +XXX,XX @@
  #include "hw/mem/npcm7xx_mc.h"
  #include "hw/misc/npcm7xx_clk.h"
  #include "hw/misc/npcm7xx_gcr.h"
 +#include "hw/misc/npcm7xx_pwm.h"
  #include "hw/misc/npcm7xx_rng.h"
  #include "hw/nvram/npcm7xx_otp.h"
  #include "hw/timer/npcm7xx_timer.h"
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
      NPCM7xxCLKState     clk;
      NPCM7xxTimerCtrlState tim[3];
      NPCM7xxADCState     adc;
 +    NPCM7xxPWMState     pwm[2];
      NPCM7xxOTPState     key_storage;
      NPCM7xxOTPState     fuse_array;
      NPCM7xxMCState      mc;
 diff --git a/include/hw/misc/npcm7xx_pwm.h b/include/hw/misc/npcm7xx_pwm.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/include/hw/misc/npcm7xx_pwm.h
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Nuvoton NPCM7xx PWM Module
 + *
 + * Copyright 2020 Google LLC
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms of the GNU General Public License as published by the
 + * Free Software Foundation; either version 2 of the License, or
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 + * for more details.
 + */
 +#ifndef NPCM7XX_PWM_H
 +#define NPCM7XX_PWM_H
 +
 +#include "hw/clock.h"
 +#include "hw/sysbus.h"
 +#include "hw/irq.h"
 +
 +/* Each PWM module holds 4 PWM channels. */
 +#define NPCM7XX_PWM_PER_MODULE 4
 +
 +/*
 + * Number of registers in one pwm module. Don't change this without increasing
 + * the version_id in vmstate.
 + */
 +#define NPCM7XX_PWM_NR_REGS (0x54 / sizeof(uint32_t))
 +
 +/*
 + * The maximum duty values. Each duty unit represents 1/NPCM7XX_PWM_MAX_DUTY
 + * cycles. For example, if NPCM7XX_PWM_MAX_DUTY=1,000,000 and a PWM has a duty
 + * value of 100,000 the duty cycle for that PWM is 10%.
 + */
 +#define NPCM7XX_PWM_MAX_DUTY 1000000
 +
 +typedef struct NPCM7xxPWMState NPCM7xxPWMState;
 +
 +/**
 + * struct NPCM7xxPWM - The state of a single PWM channel.
 + * @module: The PWM module that contains this channel.
 + * @irq: GIC interrupt line to fire on expiration if enabled.
 + * @running: Whether this PWM channel is generating output.
 + * @inverted: Whether this PWM channel is inverted.
 + * @index: The index of this PWM channel.
 + * @cnr: The counter register.
 + * @cmr: The comparator register.
 + * @pdr: The data register.
 + * @pwdr: The watchdog register.
 + * @freq: The frequency of this PWM channel.
 + * @duty: The duty cycle of this PWM channel. One unit represents
 + *   1/NPCM7XX_MAX_DUTY cycles.
 + */
 +typedef struct NPCM7xxPWM {
 +    NPCM7xxPWMState         *module;
 +
 +    qemu_irq                irq;
 +
 +    bool                    running;
 +    bool                    inverted;
 +
 +    uint8_t                 index;
 +    uint32_t                cnr;
 +    uint32_t                cmr;
 +    uint32_t                pdr;
 +    uint32_t                pwdr;
 +
 +    uint32_t                freq;
 +    uint32_t                duty;
 +} NPCM7xxPWM;
 +
 +/**
 + * struct NPCM7xxPWMState - Pulse Width Modulation device state.
 + * @parent: System bus device.
 + * @iomem: Memory region through which registers are accessed.
 + * @clock: The PWM clock.
 + * @pwm: The PWM channels owned by this module.
 + * @ppr: The prescaler register.
 + * @csr: The clock selector register.
 + * @pcr: The control register.
 + * @pier: The interrupt enable register.
 + * @piir: The interrupt indication register.
 + */
 +struct NPCM7xxPWMState {
 +    SysBusDevice parent;
 +
 +    MemoryRegion iomem;
 +
 +    Clock       *clock;
 +    NPCM7xxPWM pwm[NPCM7XX_PWM_PER_MODULE];
 +
 +    uint32_t    ppr;
 +    uint32_t    csr;
 +    uint32_t    pcr;
 +    uint32_t    pier;
 +    uint32_t    piir;
 +};
 +
 +#define TYPE_NPCM7XX_PWM "npcm7xx-pwm"
 +#define NPCM7XX_PWM(obj) \
 +    OBJECT_CHECK(NPCM7xxPWMState, (obj), TYPE_NPCM7XX_PWM)
 +
 +#endif /* NPCM7XX_PWM_H */
 diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/npcm7xx.c
 +++ b/hw/arm/npcm7xx.c
@@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt {
      NPCM7XX_WDG2_IRQ,                   /* Timer Module 2 Watchdog */
      NPCM7XX_EHCI_IRQ            = 61,
      NPCM7XX_OHCI_IRQ            = 62,
 +    NPCM7XX_PWM0_IRQ            = 93,   /* PWM module 0 */
 +    NPCM7XX_PWM1_IRQ,                   /* PWM module 1 */
      NPCM7XX_GPIO0_IRQ           = 116,
      NPCM7XX_GPIO1_IRQ,
      NPCM7XX_GPIO2_IRQ,
@@ -XXX,XX +XXX,XX @@ static const hwaddr npcm7xx_fiu3_flash_addr[] = {
 xb8000000, /* CS3 */
  };
 +/* Register base address for each PWM Module */
 +static const hwaddr npcm7xx_pwm_addr[] = {
 +    0xf0103000,
 +    0xf0104000,
 +};
 +
  static const struct {
      hwaddr regs_addr;
      uint32_t unconnected_pins;
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
          object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i],
                                  TYPE_NPCM7XX_FIU);
      }
++
-     if (aspeed_wdt_is_enabled(s)) {
++    for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
 +        object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PWM);
 +    }
  }
  static void npcm7xx_realize(DeviceState *dev, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci), 0,
                         npcm7xx_irq(s, NPCM7XX_OHCI_IRQ));
 +    /* PWM Modules. Cannot fail. */
 +    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pwm_addr) != ARRAY_SIZE(s->pwm));
 +    for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
 +        SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pwm[i]);
 +
 +        qdev_connect_clock_in(DEVICE(&s->pwm[i]), "clock", qdev_get_clock_out(
 +                    DEVICE(&s->clk), "apb3-clock"));
 +        sysbus_realize(sbd, &error_abort);
 +        sysbus_mmio_map(sbd, 0, npcm7xx_pwm_addr[i]);
 +        sysbus_connect_irq(sbd, i, npcm7xx_irq(s, NPCM7XX_PWM0_IRQ + i));
 +    }
 +
      /*
       * Flash Interface Unit (FIU). Can fail if incorrect number of chip selects
       * specified, but this is a programming error.
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
      create_unimplemented_device("npcm7xx.peci",         0xf0100000,   4 * KiB);
      create_unimplemented_device("npcm7xx.siox[1]",      0xf0101000,   4 * KiB);
      create_unimplemented_device("npcm7xx.siox[2]",      0xf0102000,   4 * KiB);
 -    create_unimplemented_device("npcm7xx.pwm[0]",       0xf0103000,   4 * KiB);
 -    create_unimplemented_device("npcm7xx.pwm[1]",       0xf0104000,   4 * KiB);
      create_unimplemented_device("npcm7xx.mft[0]",       0xf0180000,   4 * KiB);
      create_unimplemented_device("npcm7xx.mft[1]",       0xf0181000,   4 * KiB);
      create_unimplemented_device("npcm7xx.mft[2]",       0xf0182000,   4 * KiB);
 diff --git a/hw/misc/npcm7xx_pwm.c b/hw/misc/npcm7xx_pwm.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/misc/npcm7xx_pwm.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Nuvoton NPCM7xx PWM Module
 + *
 + * Copyright 2020 Google LLC
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms of the GNU General Public License as published by the
 + * Free Software Foundation; either version 2 of the License, or
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 + * for more details.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "hw/irq.h"
 +#include "hw/qdev-clock.h"
 +#include "hw/qdev-properties.h"
 +#include "hw/misc/npcm7xx_pwm.h"
 +#include "hw/registerfields.h"
 +#include "migration/vmstate.h"
 +#include "qemu/bitops.h"
 +#include "qemu/error-report.h"
 +#include "qemu/log.h"
 +#include "qemu/module.h"
 +#include "qemu/units.h"
 +#include "trace.h"
 +
 +REG32(NPCM7XX_PWM_PPR, 0x00);
 +REG32(NPCM7XX_PWM_CSR, 0x04);
 +REG32(NPCM7XX_PWM_PCR, 0x08);
 +REG32(NPCM7XX_PWM_CNR0, 0x0c);
 +REG32(NPCM7XX_PWM_CMR0, 0x10);
 +REG32(NPCM7XX_PWM_PDR0, 0x14);
 +REG32(NPCM7XX_PWM_CNR1, 0x18);
 +REG32(NPCM7XX_PWM_CMR1, 0x1c);
 +REG32(NPCM7XX_PWM_PDR1, 0x20);
 +REG32(NPCM7XX_PWM_CNR2, 0x24);
 +REG32(NPCM7XX_PWM_CMR2, 0x28);
 +REG32(NPCM7XX_PWM_PDR2, 0x2c);
 +REG32(NPCM7XX_PWM_CNR3, 0x30);
 +REG32(NPCM7XX_PWM_CMR3, 0x34);
 +REG32(NPCM7XX_PWM_PDR3, 0x38);
 +REG32(NPCM7XX_PWM_PIER, 0x3c);
 +REG32(NPCM7XX_PWM_PIIR, 0x40);
 +REG32(NPCM7XX_PWM_PWDR0, 0x44);
 +REG32(NPCM7XX_PWM_PWDR1, 0x48);
 +REG32(NPCM7XX_PWM_PWDR2, 0x4c);
 +REG32(NPCM7XX_PWM_PWDR3, 0x50);
 +
 +/* Register field definitions. */
 +#define NPCM7XX_PPR(rv, index)      extract32((rv), npcm7xx_ppr_base[index], 8)
 +#define NPCM7XX_CSR(rv, index)      extract32((rv), npcm7xx_csr_base[index], 3)
 +#define NPCM7XX_CH(rv, index)       extract32((rv), npcm7xx_ch_base[index], 4)
 +#define NPCM7XX_CH_EN               BIT(0)
 +#define NPCM7XX_CH_INV              BIT(2)
 +#define NPCM7XX_CH_MOD              BIT(3)
 +
 +/* Offset of each PWM channel's prescaler in the PPR register. */
 +static const int npcm7xx_ppr_base[] = { 0, 0, 8, 8 };
 +/* Offset of each PWM channel's clock selector in the CSR register. */
 +static const int npcm7xx_csr_base[] = { 0, 4, 8, 12 };
 +/* Offset of each PWM channel's control variable in the PCR register. */
 +static const int npcm7xx_ch_base[] = { 0, 8, 12, 16 };
 +
 +static uint32_t npcm7xx_pwm_calculate_freq(NPCM7xxPWM *p)
 +{
 +    uint32_t ppr;
 +    uint32_t csr;
 +    uint32_t freq;
 +
 +    if (!p->running) {
 +        return 0;
 +    }
 +
 +    csr = NPCM7XX_CSR(p->module->csr, p->index);
 +    ppr = NPCM7XX_PPR(p->module->ppr, p->index);
 +    freq = clock_get_hz(p->module->clock);
 +    freq /= ppr + 1;
 +    /* csr can only be 0~4 */
 +    if (csr > 4) {
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: invalid csr value %u\n",
 +                      __func__, csr);
 +        csr = 4;
 +    }
 +    /* freq won't be changed if csr == 4. */
 +    if (csr < 4) {
 +        freq >>= csr + 1;
 +    }
 +
 +    return freq / (p->cnr + 1);
 +}
 +
 +static uint32_t npcm7xx_pwm_calculate_duty(NPCM7xxPWM *p)
 +{
 +    uint64_t duty;
 +
 +    if (p->running) {
 +        if (p->cnr == 0) {
 +            duty = 0;
 +        } else if (p->cmr >= p->cnr) {
 +            duty = NPCM7XX_PWM_MAX_DUTY;
 +        } else {
 +            duty = NPCM7XX_PWM_MAX_DUTY * (p->cmr + 1) / (p->cnr + 1);
 +        }
 +    } else {
 +        duty = 0;
 +    }
 +
 +    if (p->inverted) {
 +        duty = NPCM7XX_PWM_MAX_DUTY - duty;
 +    }
 +
 +    return duty;
 +}
 +
 +static void npcm7xx_pwm_update_freq(NPCM7xxPWM *p)
 +{
 +    uint32_t freq = npcm7xx_pwm_calculate_freq(p);
 +
 +    if (freq != p->freq) {
 +        trace_npcm7xx_pwm_update_freq(DEVICE(p->module)->canonical_path,
 +                                      p->index, p->freq, freq);
 +        p->freq = freq;
 +    }
 +}
 +
 +static void npcm7xx_pwm_update_duty(NPCM7xxPWM *p)
 +{
 +    uint32_t duty = npcm7xx_pwm_calculate_duty(p);
 +
 +    if (duty != p->duty) {
 +        trace_npcm7xx_pwm_update_duty(DEVICE(p->module)->canonical_path,
 +                                      p->index, p->duty, duty);
 +        p->duty = duty;
 +    }
 +}
 +
 +static void npcm7xx_pwm_update_output(NPCM7xxPWM *p)
 +{
 +    npcm7xx_pwm_update_freq(p);
 +    npcm7xx_pwm_update_duty(p);
 +}
 +
 +static void npcm7xx_pwm_write_ppr(NPCM7xxPWMState *s, uint32_t new_ppr)
 +{
 +    int i;
 +    uint32_t old_ppr = s->ppr;
 +
 +    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_ppr_base) != NPCM7XX_PWM_PER_MODULE);
 +    s->ppr = new_ppr;
 +    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
 +        if (NPCM7XX_PPR(old_ppr, i) != NPCM7XX_PPR(new_ppr, i)) {
 +            npcm7xx_pwm_update_freq(&s->pwm[i]);
 +        }
 +    }
 +}
 +
 +static void npcm7xx_pwm_write_csr(NPCM7xxPWMState *s, uint32_t new_csr)
 +{
 +    int i;
 +    uint32_t old_csr = s->csr;
 +
 +    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_csr_base) != NPCM7XX_PWM_PER_MODULE);
 +    s->csr = new_csr;
 +    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
 +        if (NPCM7XX_CSR(old_csr, i) != NPCM7XX_CSR(new_csr, i)) {
 +            npcm7xx_pwm_update_freq(&s->pwm[i]);
 +        }
 +    }
 +}
 +
 +static void npcm7xx_pwm_write_pcr(NPCM7xxPWMState *s, uint32_t new_pcr)
 +{
 +    int i;
 +    bool inverted;
 +    uint32_t pcr;
 +    NPCM7xxPWM *p;
 +
 +    s->pcr = new_pcr;
 +    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_ch_base) != NPCM7XX_PWM_PER_MODULE);
 +    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
 +        p = &s->pwm[i];
 +        pcr = NPCM7XX_CH(new_pcr, i);
 +        inverted = pcr & NPCM7XX_CH_INV;
 +
 +        /*
 +         * We only run a PWM channel with toggle mode. Single-shot mode does not
 +         * generate frequency and duty-cycle values.
 +         */
 +        if ((pcr & NPCM7XX_CH_EN) && (pcr & NPCM7XX_CH_MOD)) {
 +            if (p->running) {
 +                /* Re-run this PWM channel if inverted changed. */
 +                if (p->inverted ^ inverted) {
 +                    p->inverted = inverted;
 +                    npcm7xx_pwm_update_duty(p);
 +                }
 +            } else {
 +                /* Run this PWM channel. */
 +                p->running = true;
 +                p->inverted = inverted;
 +                npcm7xx_pwm_update_output(p);
 +            }
 +        } else {
 +            /* Clear this PWM channel. */
 +            p->running = false;
 +            p->inverted = inverted;
 +            npcm7xx_pwm_update_output(p);
 +        }
 +    }
 +
 +}
 +
 +static hwaddr npcm7xx_cnr_index(hwaddr offset)
 +{
 +    switch (offset) {
 +    case A_NPCM7XX_PWM_CNR0:
 +        return 0;
 +    case A_NPCM7XX_PWM_CNR1:
 +        return 1;
 +    case A_NPCM7XX_PWM_CNR2:
 +        return 2;
 +    case A_NPCM7XX_PWM_CNR3:
 +        return 3;
 +    default:
 +        g_assert_not_reached();
 +    }
 +}
 +
 +static hwaddr npcm7xx_cmr_index(hwaddr offset)
 +{
 +    switch (offset) {
 +    case A_NPCM7XX_PWM_CMR0:
 +        return 0;
 +    case A_NPCM7XX_PWM_CMR1:
 +        return 1;
 +    case A_NPCM7XX_PWM_CMR2:
 +        return 2;
 +    case A_NPCM7XX_PWM_CMR3:
 +        return 3;
 +    default:
 +        g_assert_not_reached();
 +    }
 +}
 +
 +static hwaddr npcm7xx_pdr_index(hwaddr offset)
 +{
 +    switch (offset) {
 +    case A_NPCM7XX_PWM_PDR0:
 +        return 0;
 +    case A_NPCM7XX_PWM_PDR1:
 +        return 1;
 +    case A_NPCM7XX_PWM_PDR2:
 +        return 2;
 +    case A_NPCM7XX_PWM_PDR3:
 +        return 3;
 +    default:
 +        g_assert_not_reached();
 +    }
 +}
 +
 +static hwaddr npcm7xx_pwdr_index(hwaddr offset)
 +{
 +    switch (offset) {
 +    case A_NPCM7XX_PWM_PWDR0:
 +        return 0;
 +    case A_NPCM7XX_PWM_PWDR1:
 +        return 1;
 +    case A_NPCM7XX_PWM_PWDR2:
 +        return 2;
 +    case A_NPCM7XX_PWM_PWDR3:
 +        return 3;
 +    default:
 +        g_assert_not_reached();
 +    }
 +}
 +
 +static uint64_t npcm7xx_pwm_read(void *opaque, hwaddr offset, unsigned size)
 +{
 +    NPCM7xxPWMState *s = opaque;
 +    uint64_t value = 0;
 +
 +    switch (offset) {
 +    case A_NPCM7XX_PWM_CNR0:
 +    case A_NPCM7XX_PWM_CNR1:
 +    case A_NPCM7XX_PWM_CNR2:
 +    case A_NPCM7XX_PWM_CNR3:
 +        value = s->pwm[npcm7xx_cnr_index(offset)].cnr;
 +        break;
 +
 +    case A_NPCM7XX_PWM_CMR0:
 +    case A_NPCM7XX_PWM_CMR1:
 +    case A_NPCM7XX_PWM_CMR2:
 +    case A_NPCM7XX_PWM_CMR3:
 +        value = s->pwm[npcm7xx_cmr_index(offset)].cmr;
 +        break;
 +
 +    case A_NPCM7XX_PWM_PDR0:
 +    case A_NPCM7XX_PWM_PDR1:
 +    case A_NPCM7XX_PWM_PDR2:
 +    case A_NPCM7XX_PWM_PDR3:
 +        value = s->pwm[npcm7xx_pdr_index(offset)].pdr;
 +        break;
 +
 +    case A_NPCM7XX_PWM_PWDR0:
 +    case A_NPCM7XX_PWM_PWDR1:
 +    case A_NPCM7XX_PWM_PWDR2:
 +    case A_NPCM7XX_PWM_PWDR3:
 +        value = s->pwm[npcm7xx_pwdr_index(offset)].pwdr;
 +        break;
 +
 +    case A_NPCM7XX_PWM_PPR:
 +        value = s->ppr;
 +        break;
 +
 +    case A_NPCM7XX_PWM_CSR:
 +        value = s->csr;
 +        break;
 +
 +    case A_NPCM7XX_PWM_PCR:
 +        value = s->pcr;
 +        break;
 +
 +    case A_NPCM7XX_PWM_PIER:
 +        value = s->pier;
 +        break;
 +
 +    case A_NPCM7XX_PWM_PIIR:
 +        value = s->piir;
 +        break;
 +
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
 +                      __func__, offset);
 +        break;
 +    }
 +
 +    trace_npcm7xx_pwm_read(DEVICE(s)->canonical_path, offset, value);
 +    return value;
 +}
 +
 +static void npcm7xx_pwm_write(void *opaque, hwaddr offset,
 +                                uint64_t v, unsigned size)
 +{
 +    NPCM7xxPWMState *s = opaque;
 +    NPCM7xxPWM *p;
 +    uint32_t value = v;
 +
 +    trace_npcm7xx_pwm_write(DEVICE(s)->canonical_path, offset, value);
 +    switch (offset) {
 +    case A_NPCM7XX_PWM_CNR0:
 +    case A_NPCM7XX_PWM_CNR1:
 +    case A_NPCM7XX_PWM_CNR2:
 +    case A_NPCM7XX_PWM_CNR3:
 +        p = &s->pwm[npcm7xx_cnr_index(offset)];
 +        p->cnr = value;
 +        npcm7xx_pwm_update_output(p);
 +        break;
 +
 +    case A_NPCM7XX_PWM_CMR0:
 +    case A_NPCM7XX_PWM_CMR1:
 +    case A_NPCM7XX_PWM_CMR2:
 +    case A_NPCM7XX_PWM_CMR3:
 +        p = &s->pwm[npcm7xx_cmr_index(offset)];
 +        p->cmr = value;
 +        npcm7xx_pwm_update_output(p);
 +        break;
 +
 +    case A_NPCM7XX_PWM_PDR0:
 +    case A_NPCM7XX_PWM_PDR1:
 +    case A_NPCM7XX_PWM_PDR2:
 +    case A_NPCM7XX_PWM_PDR3:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
 +                      __func__, offset);
 +        break;
 +
 +    case A_NPCM7XX_PWM_PWDR0:
 +    case A_NPCM7XX_PWM_PWDR1:
 +    case A_NPCM7XX_PWM_PWDR2:
 +    case A_NPCM7XX_PWM_PWDR3:
 +        qemu_log_mask(LOG_UNIMP,
 +                     "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n",
 +                     __func__, offset);
 +        break;
 +
 +    case A_NPCM7XX_PWM_PPR:
 +        npcm7xx_pwm_write_ppr(s, value);
 +        break;
 +
 +    case A_NPCM7XX_PWM_CSR:
 +        npcm7xx_pwm_write_csr(s, value);
 +        break;
 +
 +    case A_NPCM7XX_PWM_PCR:
 +        npcm7xx_pwm_write_pcr(s, value);
 +        break;
 +
 +    case A_NPCM7XX_PWM_PIER:
 +        qemu_log_mask(LOG_UNIMP,
 +                     "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n",
 +                     __func__, offset);
 +        break;
 +
 +    case A_NPCM7XX_PWM_PIIR:
 +        qemu_log_mask(LOG_UNIMP,
 +                     "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n",
 +                     __func__, offset);
 +        break;
 +
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
 +                      __func__, offset);
 +        break;
 +    }
 +}
 +
 +static const struct MemoryRegionOps npcm7xx_pwm_ops = {
 +    .read       = npcm7xx_pwm_read,
 +    .write      = npcm7xx_pwm_write,
 +    .endianness = DEVICE_LITTLE_ENDIAN,
 +    .valid      = {
 +        .min_access_size        = 4,
 +        .max_access_size        = 4,
 +        .unaligned              = false,
 +    },
 +};
 +
 +static void npcm7xx_pwm_enter_reset(Object *obj, ResetType type)
 +{
 +    NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
 +    int i;
 +
 +    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
 +        NPCM7xxPWM *p = &s->pwm[i];
 +
 +        p->cnr = 0x00000000;
 +        p->cmr = 0x00000000;
 +        p->pdr = 0x00000000;
 +        p->pwdr = 0x00000000;
 +    }
 +
 +    s->ppr = 0x00000000;
 +    s->csr = 0x00000000;
 +    s->pcr = 0x00000000;
 +    s->pier = 0x00000000;
 +    s->piir = 0x00000000;
 +}
 +
 +static void npcm7xx_pwm_hold_reset(Object *obj)
 +{
 +    NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
 +    int i;
 +
 +    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
 +        qemu_irq_lower(s->pwm[i].irq);
 +    }
 +}
 +
 +static void npcm7xx_pwm_init(Object *obj)
 +{
 +    NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
 +    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 +    int i;
 +
 +    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
 +        NPCM7xxPWM *p = &s->pwm[i];
 +        p->module = s;
 +        p->index = i;
 +        sysbus_init_irq(sbd, &p->irq);
 +    }
 +
 +    memory_region_init_io(&s->iomem, obj, &npcm7xx_pwm_ops, s,
 +                          TYPE_NPCM7XX_PWM, 4 * KiB);
 +    sysbus_init_mmio(sbd, &s->iomem);
 +    s->clock = qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL);
 +
 +    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
 +        object_property_add_uint32_ptr(obj, "freq[*]",
 +                &s->pwm[i].freq, OBJ_PROP_FLAG_READ);
 +        object_property_add_uint32_ptr(obj, "duty[*]",
 +                &s->pwm[i].duty, OBJ_PROP_FLAG_READ);
 +    }
 +}
 +
 +static const VMStateDescription vmstate_npcm7xx_pwm = {
 +    .name = "npcm7xx-pwm",
 +    .version_id = 0,
 +    .minimum_version_id = 0,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_BOOL(running, NPCM7xxPWM),
 +        VMSTATE_BOOL(inverted, NPCM7xxPWM),
 +        VMSTATE_UINT8(index, NPCM7xxPWM),
 +        VMSTATE_UINT32(cnr, NPCM7xxPWM),
 +        VMSTATE_UINT32(cmr, NPCM7xxPWM),
 +        VMSTATE_UINT32(pdr, NPCM7xxPWM),
 +        VMSTATE_UINT32(pwdr, NPCM7xxPWM),
 +        VMSTATE_UINT32(freq, NPCM7xxPWM),
 +        VMSTATE_UINT32(duty, NPCM7xxPWM),
 +        VMSTATE_END_OF_LIST(),
 +    },
 +};
 +
 +static const VMStateDescription vmstate_npcm7xx_pwm_module = {
 +    .name = "npcm7xx-pwm-module",
 +    .version_id = 0,
 +    .minimum_version_id = 0,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_CLOCK(clock, NPCM7xxPWMState),
 +        VMSTATE_STRUCT_ARRAY(pwm, NPCM7xxPWMState,
 +                             NPCM7XX_PWM_PER_MODULE, 0, vmstate_npcm7xx_pwm,
 +                             NPCM7xxPWM),
 +        VMSTATE_UINT32(ppr, NPCM7xxPWMState),
 +        VMSTATE_UINT32(csr, NPCM7xxPWMState),
 +        VMSTATE_UINT32(pcr, NPCM7xxPWMState),
 +        VMSTATE_UINT32(pier, NPCM7xxPWMState),
 +        VMSTATE_UINT32(piir, NPCM7xxPWMState),
 +        VMSTATE_END_OF_LIST(),
 +    },
 +};
 +
 +static void npcm7xx_pwm_class_init(ObjectClass *klass, void *data)
 +{
 +    ResettableClass *rc = RESETTABLE_CLASS(klass);
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->desc = "NPCM7xx PWM Controller";
 +    dc->vmsd = &vmstate_npcm7xx_pwm_module;
 +    rc->phases.enter = npcm7xx_pwm_enter_reset;
 +    rc->phases.hold = npcm7xx_pwm_hold_reset;
 +}
 +
 +static const TypeInfo npcm7xx_pwm_info = {
 +    .name               = TYPE_NPCM7XX_PWM,
 +    .parent             = TYPE_SYS_BUS_DEVICE,
 +    .instance_size      = sizeof(NPCM7xxPWMState),
 +    .class_init         = npcm7xx_pwm_class_init,
 +    .instance_init      = npcm7xx_pwm_init,
 +};
 +
 +static void npcm7xx_pwm_register_type(void)
 +{
 +    type_register_static(&npcm7xx_pwm_info);
 +}
 +type_init(npcm7xx_pwm_register_type);
 diff --git a/hw/misc/meson.build b/hw/misc/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/meson.build
 +++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mst_fpga.c'))
  softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files(
    'npcm7xx_clk.c',
    'npcm7xx_gcr.c',
 +  'npcm7xx_pwm.c',
    'npcm7xx_rng.c',
  ))
  softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files(
 diff --git a/hw/misc/trace-events b/hw/misc/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/trace-events
 +++ b/hw/misc/trace-events
@@ -XXX,XX +XXX,XX @@ npcm7xx_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " valu
  npcm7xx_rng_read(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
  npcm7xx_rng_write(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
 +# npcm7xx_pwm.c
 +npcm7xx_pwm_read(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
 +npcm7xx_pwm_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
 +npcm7xx_pwm_update_freq(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Freq: old_freq: %u, new_freq: %u"
 +npcm7xx_pwm_update_duty(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Duty: old_duty: %u, new_duty: %u"
 +
  # stm32f4xx_syscfg.c
  stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interupt: GPIO: %d, Line: %d; Level: %d"
  stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d"
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 07/13] target-arm: Don't check for "Thumb2 or M profile" for not-Thumb1
+[PULL 19/21] hw/misc: Add QTest for NPCM7XX PWM Module
-The code which implements the Thumb1 split BL/BLX instructions
+From: Hao Wu <wuhaotsh@google.com>
 is guarded by a check on "not M or THUMB2". All we really need
 to check here is "not THUMB2" (and we assume that elsewhere too,
 eg in the ARCH(6T2) test that UNDEFs the Thumb2 insns).
-This doesn't change behaviour because all M profile cores
+We add a qtest for the PWM in the previous patch. It proves it works as
-have Thumb2 and so ARM_FEATURE_M implies ARM_FEATURE_THUMB2.
+expected.
 (v6M implements a very restricted subset of Thumb2, but we
 can cross that bridge when we get to it with appropriate
 feature bits.)
+Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
+Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
+Signed-off-by: Hao Wu <wuhaotsh@google.com>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20210108190945.949196-6-wuhaotsh@google.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 1507556919-24992-6-git-send-email-peter.maydell@linaro.org
 ---
- target/arm/translate.c | 3 +--
+ tests/qtest/npcm7xx_pwm-test.c | 490 +++++++++++++++++++++++++++++++++
-file changed, 1 insertion(+), 2 deletions(-)
+ tests/qtest/meson.build        |   1 +
 files changed, 491 insertions(+)
  create mode 100644 tests/qtest/npcm7xx_pwm-test.c
-diff --git a/target/arm/translate.c b/target/arm/translate.c
+diff --git a/tests/qtest/npcm7xx_pwm-test.c b/tests/qtest/npcm7xx_pwm-test.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/tests/qtest/npcm7xx_pwm-test.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * QTests for Nuvoton NPCM7xx PWM Modules.
 + *
 + * Copyright 2020 Google LLC
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms of the GNU General Public License as published by the
 + * Free Software Foundation; either version 2 of the License, or
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 + * for more details.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qemu/bitops.h"
 +#include "libqos/libqtest.h"
 +#include "qapi/qmp/qdict.h"
 +#include "qapi/qmp/qnum.h"
 +
 +#define REF_HZ          25000000
 +
 +/* Register field definitions. */
 +#define CH_EN           BIT(0)
 +#define CH_INV          BIT(2)
 +#define CH_MOD          BIT(3)
 +
 +/* Registers shared between all PWMs in a module */
 +#define PPR             0x00
 +#define CSR             0x04
 +#define PCR             0x08
 +#define PIER            0x3c
 +#define PIIR            0x40
 +
 +/* CLK module related */
 +#define CLK_BA          0xf0801000
 +#define CLKSEL          0x04
 +#define CLKDIV1         0x08
 +#define CLKDIV2         0x2c
 +#define PLLCON0         0x0c
 +#define PLLCON1         0x10
 +#define PLL_INDV(rv)    extract32((rv), 0, 6)
 +#define PLL_FBDV(rv)    extract32((rv), 16, 12)
 +#define PLL_OTDV1(rv)   extract32((rv), 8, 3)
 +#define PLL_OTDV2(rv)   extract32((rv), 13, 3)
 +#define APB3CKDIV(rv)   extract32((rv), 28, 2)
 +#define CLK2CKDIV(rv)   extract32((rv), 0, 1)
 +#define CLK4CKDIV(rv)   extract32((rv), 26, 2)
 +#define CPUCKSEL(rv)    extract32((rv), 0, 2)
 +
 +#define MAX_DUTY        1000000
 +
 +typedef struct PWMModule {
 +    int irq;
 +    uint64_t base_addr;
 +} PWMModule;
 +
 +typedef struct PWM {
 +    uint32_t cnr_offset;
 +    uint32_t cmr_offset;
 +    uint32_t pdr_offset;
 +    uint32_t pwdr_offset;
 +} PWM;
 +
 +typedef struct TestData {
 +    const PWMModule *module;
 +    const PWM *pwm;
 +} TestData;
 +
 +static const PWMModule pwm_module_list[] = {
 +    {
 +        .irq        = 93,
 +        .base_addr  = 0xf0103000
 +    },
 +    {
 +        .irq        = 94,
 +        .base_addr  = 0xf0104000
 +    }
 +};
 +
 +static const PWM pwm_list[] = {
 +    {
 +        .cnr_offset     = 0x0c,
 +        .cmr_offset     = 0x10,
 +        .pdr_offset     = 0x14,
 +        .pwdr_offset    = 0x44,
 +    },
 +    {
 +        .cnr_offset     = 0x18,
 +        .cmr_offset     = 0x1c,
 +        .pdr_offset     = 0x20,
 +        .pwdr_offset    = 0x48,
 +    },
 +    {
 +        .cnr_offset     = 0x24,
 +        .cmr_offset     = 0x28,
 +        .pdr_offset     = 0x2c,
 +        .pwdr_offset    = 0x4c,
 +    },
 +    {
 +        .cnr_offset     = 0x30,
 +        .cmr_offset     = 0x34,
 +        .pdr_offset     = 0x38,
 +        .pwdr_offset    = 0x50,
 +    },
 +};
 +
 +static const int ppr_base[] = { 0, 0, 8, 8 };
 +static const int csr_base[] = { 0, 4, 8, 12 };
 +static const int pcr_base[] = { 0, 8, 12, 16 };
 +
 +static const uint32_t ppr_list[] = {
 +    0,
 +    1,
 +    10,
 +    100,
 +    255, /* Max possible value. */
 +};
 +
 +static const uint32_t csr_list[] = {
 +    0,
 +    1,
 +    2,
 +    3,
 +    4, /* Max possible value. */
 +};
 +
 +static const uint32_t cnr_list[] = {
 +    0,
 +    1,
 +    50,
 +    100,
 +    150,
 +    200,
 +    1000,
 +    10000,
 +    65535, /* Max possible value. */
 +};
 +
 +static const uint32_t cmr_list[] = {
 +    0,
 +    1,
 +    10,
 +    50,
 +    100,
 +    150,
 +    200,
 +    1000,
 +    10000,
 +    65535, /* Max possible value. */
 +};
 +
 +/* Returns the index of the PWM module. */
 +static int pwm_module_index(const PWMModule *module)
 +{
 +    ptrdiff_t diff = module - pwm_module_list;
 +
 +    g_assert_true(diff >= 0 && diff < ARRAY_SIZE(pwm_module_list));
 +
 +    return diff;
 +}
 +
 +/* Returns the index of the PWM entry. */
 +static int pwm_index(const PWM *pwm)
 +{
 +    ptrdiff_t diff = pwm - pwm_list;
 +
 +    g_assert_true(diff >= 0 && diff < ARRAY_SIZE(pwm_list));
 +
 +    return diff;
 +}
 +
 +static uint64_t pwm_qom_get(QTestState *qts, const char *path, const char *name)
 +{
 +    QDict *response;
 +
 +    g_test_message("Getting properties %s from %s", name, path);
 +    response = qtest_qmp(qts, "{ 'execute': 'qom-get',"
 +            " 'arguments': { 'path': %s, 'property': %s}}",
 +            path, name);
 +    /* The qom set message returns successfully. */
 +    g_assert_true(qdict_haskey(response, "return"));
 +    return qnum_get_uint(qobject_to(QNum, qdict_get(response, "return")));
 +}
 +
 +static uint64_t pwm_get_freq(QTestState *qts, int module_index, int pwm_index)
 +{
 +    char path[100];
 +    char name[100];
 +
 +    sprintf(path, "/machine/soc/pwm[%d]", module_index);
 +    sprintf(name, "freq[%d]", pwm_index);
 +
 +    return pwm_qom_get(qts, path, name);
 +}
 +
 +static uint64_t pwm_get_duty(QTestState *qts, int module_index, int pwm_index)
 +{
 +    char path[100];
 +    char name[100];
 +
 +    sprintf(path, "/machine/soc/pwm[%d]", module_index);
 +    sprintf(name, "duty[%d]", pwm_index);
 +
 +    return pwm_qom_get(qts, path, name);
 +}
 +
 +static uint32_t get_pll(uint32_t con)
 +{
 +    return REF_HZ * PLL_FBDV(con) / (PLL_INDV(con) * PLL_OTDV1(con)
 +            * PLL_OTDV2(con));
 +}
 +
 +static uint64_t read_pclk(QTestState *qts)
 +{
 +    uint64_t freq = REF_HZ;
 +    uint32_t clksel = qtest_readl(qts, CLK_BA + CLKSEL);
 +    uint32_t pllcon;
 +    uint32_t clkdiv1 = qtest_readl(qts, CLK_BA + CLKDIV1);
 +    uint32_t clkdiv2 = qtest_readl(qts, CLK_BA + CLKDIV2);
 +
 +    switch (CPUCKSEL(clksel)) {
 +    case 0:
 +        pllcon = qtest_readl(qts, CLK_BA + PLLCON0);
 +        freq = get_pll(pllcon);
 +        break;
 +    case 1:
 +        pllcon = qtest_readl(qts, CLK_BA + PLLCON1);
 +        freq = get_pll(pllcon);
 +        break;
 +    case 2:
 +        break;
 +    case 3:
 +        break;
 +    default:
 +        g_assert_not_reached();
 +    }
 +
 +    freq >>= (CLK2CKDIV(clkdiv1) + CLK4CKDIV(clkdiv1) + APB3CKDIV(clkdiv2));
 +
 +    return freq;
 +}
 +
 +static uint32_t pwm_selector(uint32_t csr)
 +{
 +    switch (csr) {
 +    case 0:
 +        return 2;
 +    case 1:
 +        return 4;
 +    case 2:
 +        return 8;
 +    case 3:
 +        return 16;
 +    case 4:
 +        return 1;
 +    default:
 +        g_assert_not_reached();
 +    }
 +}
 +
 +static uint64_t pwm_compute_freq(QTestState *qts, uint32_t ppr, uint32_t csr,
 +        uint32_t cnr)
 +{
 +    return read_pclk(qts) / ((ppr + 1) * pwm_selector(csr) * (cnr + 1));
 +}
 +
 +static uint64_t pwm_compute_duty(uint32_t cnr, uint32_t cmr, bool inverted)
 +{
 +    uint64_t duty;
 +
 +    if (cnr == 0) {
 +        /* PWM is stopped. */
 +        duty = 0;
 +    } else if (cmr >= cnr) {
 +        duty = MAX_DUTY;
 +    } else {
 +        duty = MAX_DUTY * (cmr + 1) / (cnr + 1);
 +    }
 +
 +    if (inverted) {
 +        duty = MAX_DUTY - duty;
 +    }
 +
 +    return duty;
 +}
 +
 +static uint32_t pwm_read(QTestState *qts, const TestData *td, unsigned offset)
 +{
 +    return qtest_readl(qts, td->module->base_addr + offset);
 +}
 +
 +static void pwm_write(QTestState *qts, const TestData *td, unsigned offset,
 +        uint32_t value)
 +{
 +    qtest_writel(qts, td->module->base_addr + offset, value);
 +}
 +
 +static uint32_t pwm_read_ppr(QTestState *qts, const TestData *td)
 +{
 +    return extract32(pwm_read(qts, td, PPR), ppr_base[pwm_index(td->pwm)], 8);
 +}
 +
 +static void pwm_write_ppr(QTestState *qts, const TestData *td, uint32_t value)
 +{
 +    pwm_write(qts, td, PPR, value << ppr_base[pwm_index(td->pwm)]);
 +}
 +
 +static uint32_t pwm_read_csr(QTestState *qts, const TestData *td)
 +{
 +    return extract32(pwm_read(qts, td, CSR), csr_base[pwm_index(td->pwm)], 3);
 +}
 +
 +static void pwm_write_csr(QTestState *qts, const TestData *td, uint32_t value)
 +{
 +    pwm_write(qts, td, CSR, value << csr_base[pwm_index(td->pwm)]);
 +}
 +
 +static uint32_t pwm_read_pcr(QTestState *qts, const TestData *td)
 +{
 +    return extract32(pwm_read(qts, td, PCR), pcr_base[pwm_index(td->pwm)], 4);
 +}
 +
 +static void pwm_write_pcr(QTestState *qts, const TestData *td, uint32_t value)
 +{
 +    pwm_write(qts, td, PCR, value << pcr_base[pwm_index(td->pwm)]);
 +}
 +
 +static uint32_t pwm_read_cnr(QTestState *qts, const TestData *td)
 +{
 +    return pwm_read(qts, td, td->pwm->cnr_offset);
 +}
 +
 +static void pwm_write_cnr(QTestState *qts, const TestData *td, uint32_t value)
 +{
 +    pwm_write(qts, td, td->pwm->cnr_offset, value);
 +}
 +
 +static uint32_t pwm_read_cmr(QTestState *qts, const TestData *td)
 +{
 +    return pwm_read(qts, td, td->pwm->cmr_offset);
 +}
 +
 +static void pwm_write_cmr(QTestState *qts, const TestData *td, uint32_t value)
 +{
 +    pwm_write(qts, td, td->pwm->cmr_offset, value);
 +}
 +
 +/* Check pwm registers can be reset to default value */
 +static void test_init(gconstpointer test_data)
 +{
 +    const TestData *td = test_data;
 +    QTestState *qts = qtest_init("-machine quanta-gsj");
 +    int module = pwm_module_index(td->module);
 +    int pwm = pwm_index(td->pwm);
 +
 +    g_assert_cmpuint(pwm_get_freq(qts, module, pwm), ==, 0);
 +    g_assert_cmpuint(pwm_get_duty(qts, module, pwm), ==, 0);
 +
 +    qtest_quit(qts);
 +}
 +
 +/* One-shot mode should not change frequency and duty cycle. */
 +static void test_oneshot(gconstpointer test_data)
 +{
 +    const TestData *td = test_data;
 +    QTestState *qts = qtest_init("-machine quanta-gsj");
 +    int module = pwm_module_index(td->module);
 +    int pwm = pwm_index(td->pwm);
 +    uint32_t ppr, csr, pcr;
 +    int i, j;
 +
 +    pcr = CH_EN;
 +    for (i = 0; i < ARRAY_SIZE(ppr_list); ++i) {
 +        ppr = ppr_list[i];
 +        pwm_write_ppr(qts, td, ppr);
 +
 +        for (j = 0; j < ARRAY_SIZE(csr_list); ++j) {
 +            csr = csr_list[j];
 +            pwm_write_csr(qts, td, csr);
 +            pwm_write_pcr(qts, td, pcr);
 +
 +            g_assert_cmpuint(pwm_read_ppr(qts, td), ==, ppr);
 +            g_assert_cmpuint(pwm_read_csr(qts, td), ==, csr);
 +            g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr);
 +            g_assert_cmpuint(pwm_get_freq(qts, module, pwm), ==, 0);
 +            g_assert_cmpuint(pwm_get_duty(qts, module, pwm), ==, 0);
 +        }
 +    }
 +
 +    qtest_quit(qts);
 +}
 +
 +/* In toggle mode, the PWM generates correct outputs. */
 +static void test_toggle(gconstpointer test_data)
 +{
 +    const TestData *td = test_data;
 +    QTestState *qts = qtest_init("-machine quanta-gsj");
 +    int module = pwm_module_index(td->module);
 +    int pwm = pwm_index(td->pwm);
 +    uint32_t ppr, csr, pcr, cnr, cmr;
 +    int i, j, k, l;
 +    uint64_t expected_freq, expected_duty;
 +
 +    pcr = CH_EN | CH_MOD;
 +    for (i = 0; i < ARRAY_SIZE(ppr_list); ++i) {
 +        ppr = ppr_list[i];
 +        pwm_write_ppr(qts, td, ppr);
 +
 +        for (j = 0; j < ARRAY_SIZE(csr_list); ++j) {
 +            csr = csr_list[j];
 +            pwm_write_csr(qts, td, csr);
 +
 +            for (k = 0; k < ARRAY_SIZE(cnr_list); ++k) {
 +                cnr = cnr_list[k];
 +                pwm_write_cnr(qts, td, cnr);
 +
 +                for (l = 0; l < ARRAY_SIZE(cmr_list); ++l) {
 +                    cmr = cmr_list[l];
 +                    pwm_write_cmr(qts, td, cmr);
 +                    expected_freq = pwm_compute_freq(qts, ppr, csr, cnr);
 +                    expected_duty = pwm_compute_duty(cnr, cmr, false);
 +
 +                    pwm_write_pcr(qts, td, pcr);
 +                    g_assert_cmpuint(pwm_read_ppr(qts, td), ==, ppr);
 +                    g_assert_cmpuint(pwm_read_csr(qts, td), ==, csr);
 +                    g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr);
 +                    g_assert_cmpuint(pwm_read_cnr(qts, td), ==, cnr);
 +                    g_assert_cmpuint(pwm_read_cmr(qts, td), ==, cmr);
 +                    g_assert_cmpuint(pwm_get_duty(qts, module, pwm),
 +                            ==, expected_duty);
 +                    if (expected_duty != 0 && expected_duty != 100) {
 +                        /* Duty cycle with 0 or 100 doesn't need frequency. */
 +                        g_assert_cmpuint(pwm_get_freq(qts, module, pwm),
 +                                ==, expected_freq);
 +                    }
 +
 +                    /* Test inverted mode */
 +                    expected_duty = pwm_compute_duty(cnr, cmr, true);
 +                    pwm_write_pcr(qts, td, pcr | CH_INV);
 +                    g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr | CH_INV);
 +                    g_assert_cmpuint(pwm_get_duty(qts, module, pwm),
 +                            ==, expected_duty);
 +                    if (expected_duty != 0 && expected_duty != 100) {
 +                        /* Duty cycle with 0 or 100 doesn't need frequency. */
 +                        g_assert_cmpuint(pwm_get_freq(qts, module, pwm),
 +                                ==, expected_freq);
 +                    }
 +
 +                }
 +            }
 +        }
 +    }
 +
 +    qtest_quit(qts);
 +}
 +
 +static void pwm_add_test(const char *name, const TestData* td,
 +        GTestDataFunc fn)
 +{
 +    g_autofree char *full_name = g_strdup_printf(
 +            "npcm7xx_pwm/module[%d]/pwm[%d]/%s", pwm_module_index(td->module),
 +            pwm_index(td->pwm), name);
 +    qtest_add_data_func(full_name, td, fn);
 +}
 +#define add_test(name, td) pwm_add_test(#name, td, test_##name)
 +
 +int main(int argc, char **argv)
 +{
 +    TestData test_data_list[ARRAY_SIZE(pwm_module_list) * ARRAY_SIZE(pwm_list)];
 +
 +    g_test_init(&argc, &argv, NULL);
 +
 +    for (int i = 0; i < ARRAY_SIZE(pwm_module_list); ++i) {
 +        for (int j = 0; j < ARRAY_SIZE(pwm_list); ++j) {
 +            TestData *td = &test_data_list[i * ARRAY_SIZE(pwm_list) + j];
 +
 +            td->module = &pwm_module_list[i];
 +            td->pwm = &pwm_list[j];
 +
 +            add_test(init, td);
 +            add_test(oneshot, td);
 +            add_test(toggle, td);
 +        }
 +    }
 +
 +    return g_test_run();
 +}
 diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
+--- a/tests/qtest/meson.build
-+++ b/target/arm/translate.c
++++ b/tests/qtest/meson.build
-@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
+@@ -XXX,XX +XXX,XX @@ qtests_sparc64 = \
-     int conds;
+ qtests_npcm7xx = \
-     int logic_cc;
+   ['npcm7xx_adc-test',
+    'npcm7xx_gpio-test',
--    if (!(arm_dc_feature(s, ARM_FEATURE_THUMB2)
++   'npcm7xx_pwm-test',
--          || arm_dc_feature(s, ARM_FEATURE_M))) {
+    'npcm7xx_rng-test',
-+    if (!arm_dc_feature(s, ARM_FEATURE_THUMB2)) {
+    'npcm7xx_timer-test',
-         /* Thumb-1 cores may need to treat bl and blx as a pair of
+    'npcm7xx_watchdog_timer-test']
 -bit instructions to get correct prefetch abort behavior.  */
          insn = insn_hw1;
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 09/13] target-arm: Simplify insn_crosses_page()
+[PULL 20/21] hw/*: Use type casting for SysBusDevice in NPCM7XX
-Recent changes have left insn_crosses_page() more complicated
+From: Hao Wu <wuhaotsh@google.com>
 than it needed to be:
  * it's only called from thumb_tr_translate_insn() so we know
    for certain that we're looking at a Thumb insn
  * the caller's check for dc->pc >= dc->next_page_start - 3
    means that dc->pc can't possibly be 4 aligned, so there's
    no need to check that (the check was partly there to ensure
    that we didn't treat an ARM insn as Thumb, I think)
  * we now have thumb_insn_is_16bit() which lets us do a precise
    check of the length of the next insn, rather than opencoding
    an inaccurate check
-Simplify it down to just loading the first half of the insn
+A device shouldn't access its parent object which is QOM internal.
-and calling thumb_insn_is_16bit() on it.
+Instead it should use type cast for this purporse. This patch fixes this
 issue for all NPCM7XX Devices.
+Signed-off-by: Hao Wu <wuhaotsh@google.com>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20210108190945.949196-7-wuhaotsh@google.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 1507556919-24992-8-git-send-email-peter.maydell@linaro.org
 ---
- target/arm/translate.c | 27 ++++++---------------------
+ hw/arm/npcm7xx_boards.c | 2 +-
-file changed, 6 insertions(+), 21 deletions(-)
+ hw/mem/npcm7xx_mc.c     | 2 +-
  hw/misc/npcm7xx_clk.c   | 2 +-
  hw/misc/npcm7xx_gcr.c   | 2 +-
  hw/misc/npcm7xx_rng.c   | 2 +-
  hw/nvram/npcm7xx_otp.c  | 2 +-
  hw/ssi/npcm7xx_fiu.c    | 2 +-
 files changed, 7 insertions(+), 7 deletions(-)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
+diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
+--- a/hw/arm/npcm7xx_boards.c
-+++ b/target/arm/translate.c
++++ b/hw/arm/npcm7xx_boards.c
-@@ -XXX,XX +XXX,XX @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
+@@ -XXX,XX +XXX,XX @@ static NPCM7xxState *npcm7xx_create_soc(MachineState *machine,
                                          uint32_t hw_straps)
  {
-     /* Return true if the insn at dc->pc might cross a page boundary.
+     NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_GET_CLASS(machine);
-      * (False positives are OK, false negatives are not.)
+-    MachineClass *mc = &nmc->parent;
-+     * We know this is a Thumb insn, and our caller ensures we are
++    MachineClass *mc = MACHINE_CLASS(nmc);
-+     * only called if dc->pc is less than 4 bytes from the page
+     Object *obj;
-+     * boundary, so we cross the page if the first 16 bits indicate
-+     * that this is a 32 bit insn.
+     if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
-      */
+diff --git a/hw/mem/npcm7xx_mc.c b/hw/mem/npcm7xx_mc.c
--    uint16_t insn;
+index XXXXXXX..XXXXXXX 100644
-+    uint16_t insn = arm_lduw_code(env, s->pc, s->sctlr_b);
+--- a/hw/mem/npcm7xx_mc.c
++++ b/hw/mem/npcm7xx_mc.c
--    if ((s->pc & 3) == 0) {
+@@ -XXX,XX +XXX,XX @@ static void npcm7xx_mc_realize(DeviceState *dev, Error **errp)
--        /* At a 4-aligned address we can't be crossing a page */
--        return false;
+     memory_region_init_io(&s->mmio, OBJECT(s), &npcm7xx_mc_ops, s, "regs",
--    }
+                           NPCM7XX_MC_REGS_SIZE);
--
+-    sysbus_init_mmio(&s->parent, &s->mmio);
--    /* This must be a Thumb insn */
++    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
 -    insn = arm_lduw_code(env, s->pc, s->sctlr_b);
 -
 -    if ((insn >> 11) >= 0x1d) {
 -        /* Top five bits 0b11101 / 0b11110 / 0b11111 : this is the
 -         * First half of a 32-bit Thumb insn. Thumb-1 cores might
 -         * end up actually treating this as two 16-bit insns (see the
 -         * code at the start of disas_thumb2_insn()) but we don't bother
 -         * to check for that as it is unlikely, and false positives here
 -         * are harmless.
 -         */
 -        return true;
 -    }
 -    /* Definitely a 16-bit insn, can't be crossing a page. */
 -    return false;
 +    return !thumb_insn_is_16bit(s, insn);
  }
- static int arm_tr_init_disas_context(DisasContextBase *dcbase,
+ static void npcm7xx_mc_class_init(ObjectClass *klass, void *data)
 diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/npcm7xx_clk.c
 +++ b/hw/misc/npcm7xx_clk.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_init(Object *obj)
      memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s,
                            TYPE_NPCM7XX_CLK, 4 * KiB);
 -    sysbus_init_mmio(&s->parent, &s->iomem);
 +    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
  }
  static int npcm7xx_clk_post_load(void *opaque, int version_id)
 diff --git a/hw/misc/npcm7xx_gcr.c b/hw/misc/npcm7xx_gcr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/npcm7xx_gcr.c
 +++ b/hw/misc/npcm7xx_gcr.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_gcr_init(Object *obj)
      memory_region_init_io(&s->iomem, obj, &npcm7xx_gcr_ops, s,
                            TYPE_NPCM7XX_GCR, 4 * KiB);
 -    sysbus_init_mmio(&s->parent, &s->iomem);
 +    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
  }
  static const VMStateDescription vmstate_npcm7xx_gcr = {
 diff --git a/hw/misc/npcm7xx_rng.c b/hw/misc/npcm7xx_rng.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/npcm7xx_rng.c
 +++ b/hw/misc/npcm7xx_rng.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_rng_init(Object *obj)
      memory_region_init_io(&s->iomem, obj, &npcm7xx_rng_ops, s, "regs",
                            NPCM7XX_RNG_REGS_SIZE);
 -    sysbus_init_mmio(&s->parent, &s->iomem);
 +    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
  }
  static const VMStateDescription vmstate_npcm7xx_rng = {
 diff --git a/hw/nvram/npcm7xx_otp.c b/hw/nvram/npcm7xx_otp.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/nvram/npcm7xx_otp.c
 +++ b/hw/nvram/npcm7xx_otp.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_otp_realize(DeviceState *dev, Error **errp)
  {
      NPCM7xxOTPClass *oc = NPCM7XX_OTP_GET_CLASS(dev);
      NPCM7xxOTPState *s = NPCM7XX_OTP(dev);
 -    SysBusDevice *sbd = &s->parent;
 +    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
      memset(s->array, 0, sizeof(s->array));
 diff --git a/hw/ssi/npcm7xx_fiu.c b/hw/ssi/npcm7xx_fiu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/ssi/npcm7xx_fiu.c
 +++ b/hw/ssi/npcm7xx_fiu.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_fiu_hold_reset(Object *obj)
  static void npcm7xx_fiu_realize(DeviceState *dev, Error **errp)
  {
      NPCM7xxFIUState *s = NPCM7XX_FIU(dev);
 -    SysBusDevice *sbd = &s->parent;
 +    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
      int i;
      if (s->cs_count <= 0) {
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 03/13] target/arm: Add M profile secure MMU index values to get_a32_user_mem_index()
+[PULL 21/21] ui/cocoa: Fix openFile: deprecation on Big Sur
-Add the M profile secure MMU index values to the switch in
+From: Roman Bolshakov <r.bolshakov@yadro.com>
 get_a32_user_mem_index() so that LDRT/STRT work correctly
 rather than asserting at translate time.
+ui/cocoa.m:1188:44: warning: 'openFile:' is deprecated: first deprecated in macOS 11.0 - Use -[NSWorkspace openURL:] instead.
+      [-Wdeprecated-declarations]
+        if ([[NSWorkspace sharedWorkspace] openFile: full_file_path] == YES) {
+                                           ^
+/Library/Developer/CommandLineTools/SDKs/MacOSX.sdk/System/Library/Frameworks/AppKit.framework/Headers/NSWorkspace.h:350:1: note:
+      'openFile:' has been explicitly marked deprecated here
+- (BOOL)openFile:(NSString *)fullPath API_DEPRECATED("Use -[NSWorkspace openURL:] instead.", macos(10.0, 11.0));
+^
+Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20210102150718.47618-1-r.bolshakov@yadro.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 1507556919-24992-2-git-send-email-peter.maydell@linaro.org
 ---
- target/arm/translate.c | 4 ++++
+ ui/cocoa.m | 5 ++++-
-file changed, 4 insertions(+)
+file changed, 4 insertions(+), 1 deletion(-)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
+diff --git a/ui/cocoa.m b/ui/cocoa.m
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
+--- a/ui/cocoa.m
-+++ b/target/arm/translate.c
++++ b/ui/cocoa.m
-@@ -XXX,XX +XXX,XX @@ static inline int get_a32_user_mem_index(DisasContext *s)
+@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
-     case ARMMMUIdx_MPriv:
+     /* Where to look for local files */
-     case ARMMMUIdx_MNegPri:
+     NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"docs/"};
-         return arm_to_core_mmu_idx(ARMMMUIdx_MUser);
+     NSString *full_file_path;
-+    case ARMMMUIdx_MSUser:
++    NSURL *full_file_url;
-+    case ARMMMUIdx_MSPriv:
-+    case ARMMMUIdx_MSNegPri:
+     /* iterate thru the possible paths until the file is found */
-+        return arm_to_core_mmu_idx(ARMMMUIdx_MSUser);
+     int index;
-     case ARMMMUIdx_S2NS:
+@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
-     default:
+         full_file_path = [full_file_path stringByDeletingLastPathComponent];
-         g_assert_not_reached();
+         full_file_path = [NSString stringWithFormat: @"%@/%@%@", full_file_path,
                            path_array[index], filename];
 -        if ([[NSWorkspace sharedWorkspace] openFile: full_file_path] == YES) {
 +        full_file_url = [NSURL fileURLWithPath: full_file_path
 +                                   isDirectory: false];
 +        if ([[NSWorkspace sharedWorkspace] openURL: full_file_url] == YES) {
              return;
          }
      }
 --
-.7.4
+.20.1

target-arm queue:
 * mostly my latest v8M stuff, plus a couple of minor patches

The following changes since commit a0b261db8c030813e30a39eae47359ac2a37f7e2:

Merge remote-tracking branch 'remotes/ehabkost/tags/python-next-pull-request' into staging (2017-10-12 10:02:09 +0100)

are available in the git repository at:

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20171012

for you to fetch changes up to cf5f7937b05c84d5565134f058c00cd48304a117:

nvic: Fix miscalculation of offsets into ITNS array (2017-10-12 16:33:16 +0100)

----------------------------------------------------------------
target-arm queue:
 * v8M: SG, BLXNS, secure-return
 * v8M: fixes for coverity issues in previous patches
 * arm: fix armv7m_init() declaration to match definition
 * watchdog/aspeed: fix variable type to store reload value

----------------------------------------------------------------
Cédric Le Goater (1):
      watchdog/aspeed: fix variable type to store reload value

Igor Mammedov (1):
      arm: fix armv7m_init() declaration to match definition

Peter Maydell (11):
      target/arm: Add M profile secure MMU index values to get_a32_user_mem_index()
      target/arm: Implement SG instruction
      target/arm: Implement BLXNS
      target/arm: Implement secure function return
      target-arm: Don't check for "Thumb2 or M profile" for not-Thumb1
      target/arm: Pull Thumb insn word loads up to top level
      target-arm: Simplify insn_crosses_page()
      target/arm: Support some Thumb insns being always unconditional
      target/arm: Implement SG instruction corner cases
      nvic: Add missing 'break'
      nvic: Fix miscalculation of offsets into ITNS array

include/hw/arm/arm.h     |   2 +-
 target/arm/helper.h      |   1 +
 target/arm/internals.h   |   8 ++
 hw/intc/armv7m_nvic.c    |   5 +-
 hw/watchdog/wdt_aspeed.c |   4 +-
 target/arm/helper.c      | 306 ++++++++++++++++++++++++++++++++++++++++++++--
 target/arm/translate.c   | 310 ++++++++++++++++++++++++++++++++---------------
 7 files changed, 521 insertions(+), 115 deletions(-)

From: Cédric Le Goater <clg@kaod.org>

Initially from Anton D. Kachalov" <mouse@yandex-team.ru> but the SoB was
missing.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Message-id: 20170920064915.30027-1-clg@kaod.org
[clg: change commit log and subject
      replace UL suffix by ULL ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/watchdog/wdt_aspeed.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/watchdog/wdt_aspeed.c
+++ b/hw/watchdog/wdt_aspeed.c
@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size)
 
 static void aspeed_wdt_reload(AspeedWDTState *s, bool pclk)
 {
-    uint32_t reload;
+    uint64_t reload;
 
     if (pclk) {
         reload = muldiv64(s->regs[WDT_RELOAD_VALUE], NANOSECONDS_PER_SECOND,
                           s->pclk_freq);
     } else {
-        reload = s->regs[WDT_RELOAD_VALUE] * 1000;
+        reload = s->regs[WDT_RELOAD_VALUE] * 1000ULL;
     }
 
     if (aspeed_wdt_is_enabled(s)) {
-- 
2.7.4

Implement the SG instruction, which we emulate 'by hand' in the
exception handling code path.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1507556919-24992-3-git-send-email-peter.maydell@linaro.org
---
 target/arm/helper.c | 132 ++++++++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 127 insertions(+), 5 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ typedef struct V8M_SAttributes {
     bool irvalid;
 } V8M_SAttributes;
 
+static void v8m_security_lookup(CPUARMState *env, uint32_t address,
+                                MMUAccessType access_type, ARMMMUIdx mmu_idx,
+                                V8M_SAttributes *sattrs);
+
 /* Definitions for the PMCCNTR and PMCR registers */
 #define PMCRD   0x8
 #define PMCRC   0x4
@@ -XXX,XX +XXX,XX @@ static void arm_log_exception(int idx)
     }
 }
 
+static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
+                               uint32_t addr, uint16_t *insn)
+{
+    /* Load a 16-bit portion of a v7M instruction, returning true on success,
+     * or false on failure (in which case we will have pended the appropriate
+     * exception).
+     * We need to do the instruction fetch's MPU and SAU checks
+     * like this because there is no MMU index that would allow
+     * doing the load with a single function call. Instead we must
+     * first check that the security attributes permit the load
+     * and that they don't mismatch on the two halves of the instruction,
+     * and then we do the load as a secure load (ie using the security
+     * attributes of the address, not the CPU, as architecturally required).
+     */
+    CPUState *cs = CPU(cpu);
+    CPUARMState *env = &cpu->env;
+    V8M_SAttributes sattrs = {};
+    MemTxAttrs attrs = {};
+    ARMMMUFaultInfo fi = {};
+    MemTxResult txres;
+    target_ulong page_size;
+    hwaddr physaddr;
+    int prot;
+    uint32_t fsr;
+
+    v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, &sattrs);
+    if (!sattrs.nsc || sattrs.ns) {
+        /* This must be the second half of the insn, and it straddles a
+         * region boundary with the second half not being S&NSC.
+         */
+        env->v7m.sfsr |= R_V7M_SFSR_INVEP_MASK;
+        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false);
+        qemu_log_mask(CPU_LOG_INT,
+                      "...really SecureFault with SFSR.INVEP\n");
+        return false;
+    }
+    if (get_phys_addr(env, addr, MMU_INST_FETCH, mmu_idx,
+                      &physaddr, &attrs, &prot, &page_size, &fsr, &fi)) {
+        /* the MPU lookup failed */
+        env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_IACCVIOL_MASK;
+        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, env->v7m.secure);
+        qemu_log_mask(CPU_LOG_INT, "...really MemManage with CFSR.IACCVIOL\n");
+        return false;
+    }
+    *insn = address_space_lduw_le(arm_addressspace(cs, attrs), physaddr,
+                                 attrs, &txres);
+    if (txres != MEMTX_OK) {
+        env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_IBUSERR_MASK;
+        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false);
+        qemu_log_mask(CPU_LOG_INT, "...really BusFault with CFSR.IBUSERR\n");
+        return false;
+    }
+    return true;
+}
+
+static bool v7m_handle_execute_nsc(ARMCPU *cpu)
+{
+    /* Check whether this attempt to execute code in a Secure & NS-Callable
+     * memory region is for an SG instruction; if so, then emulate the
+     * effect of the SG instruction and return true. Otherwise pend
+     * the correct kind of exception and return false.
+     */
+    CPUARMState *env = &cpu->env;
+    ARMMMUIdx mmu_idx;
+    uint16_t insn;
+
+    /* We should never get here unless get_phys_addr_pmsav8() caused
+     * an exception for NS executing in S&NSC memory.
+     */
+    assert(!env->v7m.secure);
+    assert(arm_feature(env, ARM_FEATURE_M_SECURITY));
+
+    /* We want to do the MPU lookup as secure; work out what mmu_idx that is */
+    mmu_idx = arm_v7m_mmu_idx_for_secstate(env, true);
+
+    if (!v7m_read_half_insn(cpu, mmu_idx, env->regs[15], &insn)) {
+        return false;
+    }
+
+    if (!env->thumb) {
+        goto gen_invep;
+    }
+
+    if (insn != 0xe97f) {
+        /* Not an SG instruction first half (we choose the IMPDEF
+         * early-SG-check option).
+         */
+        goto gen_invep;
+    }
+
+    if (!v7m_read_half_insn(cpu, mmu_idx, env->regs[15] + 2, &insn)) {
+        return false;
+    }
+
+    if (insn != 0xe97f) {
+        /* Not an SG instruction second half (yes, both halves of the SG
+         * insn have the same hex value)
+         */
+        goto gen_invep;
+    }
+
+    /* OK, we have confirmed that we really have an SG instruction.
+     * We know we're NS in S memory so don't need to repeat those checks.
+     */
+    qemu_log_mask(CPU_LOG_INT, "...really an SG instruction at 0x%08" PRIx32
+                  ", executing it\n", env->regs[15]);
+    env->regs[14] &= ~1;
+    switch_v7m_security_state(env, true);
+    xpsr_write(env, 0, XPSR_IT);
+    env->regs[15] += 4;
+    return true;
+
+gen_invep:
+    env->v7m.sfsr |= R_V7M_SFSR_INVEP_MASK;
+    armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false);
+    qemu_log_mask(CPU_LOG_INT,
+                  "...really SecureFault with SFSR.INVEP\n");
+    return false;
+}
+
 void arm_v7m_cpu_do_interrupt(CPUState *cs)
 {
     ARMCPU *cpu = ARM_CPU(cs);
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
              * the SG instruction have the same security attributes.)
              * Everything else must generate an INVEP SecureFault, so we
              * emulate the SG instruction here.
-             * TODO: actually emulate SG.
              */
-            env->v7m.sfsr |= R_V7M_SFSR_INVEP_MASK;
-            armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false);
-            qemu_log_mask(CPU_LOG_INT,
-                          "...really SecureFault with SFSR.INVEP\n");
+            if (v7m_handle_execute_nsc(cpu)) {
+                return;
+            }
             break;
         case M_FAKE_FSR_SFAULT:
             /* Various flavours of SecureFault for attempts to execute or
-- 
2.7.4

Implement the BLXNS instruction, which allows secure code to
call non-secure code.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1507556919-24992-4-git-send-email-peter.maydell@linaro.org
---
 target/arm/helper.h    |  1 +
 target/arm/internals.h |  1 +
 target/arm/helper.c    | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++
 target/arm/translate.c | 17 +++++++++++++--
 4 files changed, 76 insertions(+), 2 deletions(-)

diff --git a/target/arm/helper.h b/target/arm/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(v7m_msr, void, env, i32, i32)
 DEF_HELPER_2(v7m_mrs, i32, env, i32)
 
 DEF_HELPER_2(v7m_bxns, void, env, i32)
+DEF_HELPER_2(v7m_blxns, void, env, i32)
 
 DEF_HELPER_4(access_check_cp_reg, void, env, ptr, i32, i32)
 DEF_HELPER_3(set_cp_reg, void, env, ptr, i32)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ static inline bool excp_is_internal(int excp)
 FIELD(V7M_CONTROL, NPRIV, 0, 1)
 FIELD(V7M_CONTROL, SPSEL, 1, 1)
 FIELD(V7M_CONTROL, FPCA, 2, 1)
+FIELD(V7M_CONTROL, SFPA, 3, 1)
 
 /* Bit definitions for v7M exception return payload */
 FIELD(V7M_EXCRET, ES, 0, 1)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)
     g_assert_not_reached();
 }
 
+void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
+{
+    /* translate.c should never generate calls here in user-only mode */
+    g_assert_not_reached();
+}
+
 void switch_mode(CPUARMState *env, int mode)
 {
     ARMCPU *cpu = arm_env_get_cpu(env);
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)
     env->regs[15] = dest & ~1;
 }
 
+void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
+{
+    /* Handle v7M BLXNS:
+     *  - bit 0 of the destination address is the target security state
+     */
+
+    /* At this point regs[15] is the address just after the BLXNS */
+    uint32_t nextinst = env->regs[15] | 1;
+    uint32_t sp = env->regs[13] - 8;
+    uint32_t saved_psr;
+
+    /* translate.c will have made BLXNS UNDEF unless we're secure */
+    assert(env->v7m.secure);
+
+    if (dest & 1) {
+        /* target is Secure, so this is just a normal BLX,
+         * except that the low bit doesn't indicate Thumb/not.
+         */
+        env->regs[14] = nextinst;
+        env->thumb = 1;
+        env->regs[15] = dest & ~1;
+        return;
+    }
+
+    /* Target is non-secure: first push a stack frame */
+    if (!QEMU_IS_ALIGNED(sp, 8)) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "BLXNS with misaligned SP is UNPREDICTABLE\n");
+    }
+
+    saved_psr = env->v7m.exception;
+    if (env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK) {
+        saved_psr |= XPSR_SFPA;
+    }
+
+    /* Note that these stores can throw exceptions on MPU faults */
+    cpu_stl_data(env, sp, nextinst);
+    cpu_stl_data(env, sp + 4, saved_psr);
+
+    env->regs[13] = sp;
+    env->regs[14] = 0xfeffffff;
+    if (arm_v7m_is_handler_mode(env)) {
+        /* Write a dummy value to IPSR, to avoid leaking the current secure
+         * exception number to non-secure code. This is guaranteed not
+         * to cause write_v7m_exception() to actually change stacks.
+         */
+        write_v7m_exception(env, 1);
+    }
+    switch_v7m_security_state(env, 0);
+    env->thumb = 1;
+    env->regs[15] = dest;
+}
+
 static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode,
                                 bool spsel)
 {
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static inline void gen_bxns(DisasContext *s, int rm)
     s->base.is_jmp = DISAS_EXIT;
 }
 
+static inline void gen_blxns(DisasContext *s, int rm)
+{
+    TCGv_i32 var = load_reg(s, rm);
+
+    /* We don't need to sync condexec state, for the same reason as bxns.
+     * We do however need to set the PC, because the blxns helper reads it.
+     * The blxns helper may throw an exception.
+     */
+    gen_set_pc_im(s, s->pc);
+    gen_helper_v7m_blxns(cpu_env, var);
+    tcg_temp_free_i32(var);
+    s->base.is_jmp = DISAS_EXIT;
+}
+
 /* Variant of store_reg which uses branch&exchange logic when storing
    to r15 in ARM architecture v7 and above. The source must be a temporary
    and will be marked as dead. */
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
                         goto undef;
                     }
                     if (link) {
-                        /* BLXNS: not yet implemented */
-                        goto undef;
+                        gen_blxns(s, rm);
                     } else {
                         gen_bxns(s, rm);
                     }
-- 
2.7.4

Secure function return happens when a non-secure function has been
called using BLXNS and so has a particular magic LR value (either
0xfefffffe or 0xfeffffff). The function return via BX behaves
specially when the new PC value is this magic value, in the same
way that exception returns are handled.

Adjust our BX excret guards so that they recognize the function
return magic number as well, and perform the function-return
unstacking in do_v7m_exception_exit().

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1507556919-24992-5-git-send-email-peter.maydell@linaro.org
---
 target/arm/internals.h |   7 +++
 target/arm/helper.c    | 115 +++++++++++++++++++++++++++++++++++++++++++++----
 target/arm/translate.c |  14 +++++-
 3 files changed, 126 insertions(+), 10 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ FIELD(V7M_EXCRET, DCRS, 5, 1)
 FIELD(V7M_EXCRET, S, 6, 1)
 FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */
 
+/* Minimum value which is a magic number for exception return */
+#define EXC_RETURN_MIN_MAGIC 0xff000000
+/* Minimum number which is a magic number for function or exception return
+ * when using v8M security extension
+ */
+#define FNC_RETURN_MIN_MAGIC 0xfefffffe
+
 /* We use a few fake FSR values for internal purposes in M profile.
  * M profile cores don't have A/R format FSRs, but currently our
  * get_phys_addr() code assumes A/R profile and reports failures via
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)
      *  - if the return value is a magic value, do exception return (like BX)
      *  - otherwise bit 0 of the return value is the target security state
      */
-    if (dest >= 0xff000000) {
+    uint32_t min_magic;
+
+    if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
+        /* Covers FNC_RETURN and EXC_RETURN magic */
+        min_magic = FNC_RETURN_MIN_MAGIC;
+    } else {
+        /* EXC_RETURN magic only */
+        min_magic = EXC_RETURN_MIN_MAGIC;
+    }
+
+    if (dest >= min_magic) {
         /* This is an exception return magic value; put it where
          * do_v7m_exception_exit() expects and raise EXCEPTION_EXIT.
          * Note that if we ever add gen_ss_advance() singlestep support to
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
     bool exc_secure = false;
     bool return_to_secure;
 
-    /* We can only get here from an EXCP_EXCEPTION_EXIT, and
-     * gen_bx_excret() enforces the architectural rule
-     * that jumps to magic addresses don't have magic behaviour unless
-     * we're in Handler mode (compare pseudocode BXWritePC()).
+    /* If we're not in Handler mode then jumps to magic exception-exit
+     * addresses don't have magic behaviour. However for the v8M
+     * security extensions the magic secure-function-return has to
+     * work in thread mode too, so to avoid doing an extra check in
+     * the generated code we allow exception-exit magic to also cause the
+     * internal exception and bring us here in thread mode. Correct code
+     * will never try to do this (the following insn fetch will always
+     * fault) so we the overhead of having taken an unnecessary exception
+     * doesn't matter.
      */
-    assert(arm_v7m_is_handler_mode(env));
+    if (!arm_v7m_is_handler_mode(env)) {
+        return;
+    }
 
     /* In the spec pseudocode ExceptionReturn() is called directly
      * from BXWritePC() and gets the full target PC value including
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
     qemu_log_mask(CPU_LOG_INT, "...successful exception return\n");
 }
 
+static bool do_v7m_function_return(ARMCPU *cpu)
+{
+    /* v8M security extensions magic function return.
+     * We may either:
+     *  (1) throw an exception (longjump)
+     *  (2) return true if we successfully handled the function return
+     *  (3) return false if we failed a consistency check and have
+     *      pended a UsageFault that needs to be taken now
+     *
+     * At this point the magic return value is split between env->regs[15]
+     * and env->thumb. We don't bother to reconstitute it because we don't
+     * need it (all values are handled the same way).
+     */
+    CPUARMState *env = &cpu->env;
+    uint32_t newpc, newpsr, newpsr_exc;
+
+    qemu_log_mask(CPU_LOG_INT, "...really v7M secure function return\n");
+
+    {
+        bool threadmode, spsel;
+        TCGMemOpIdx oi;
+        ARMMMUIdx mmu_idx;
+        uint32_t *frame_sp_p;
+        uint32_t frameptr;
+
+        /* Pull the return address and IPSR from the Secure stack */
+        threadmode = !arm_v7m_is_handler_mode(env);
+        spsel = env->v7m.control[M_REG_S] & R_V7M_CONTROL_SPSEL_MASK;
+
+        frame_sp_p = get_v7m_sp_ptr(env, true, threadmode, spsel);
+        frameptr = *frame_sp_p;
+
+        /* These loads may throw an exception (for MPU faults). We want to
+         * do them as secure, so work out what MMU index that is.
+         */
+        mmu_idx = arm_v7m_mmu_idx_for_secstate(env, true);
+        oi = make_memop_idx(MO_LE, arm_to_core_mmu_idx(mmu_idx));
+        newpc = helper_le_ldul_mmu(env, frameptr, oi, 0);
+        newpsr = helper_le_ldul_mmu(env, frameptr + 4, oi, 0);
+
+        /* Consistency checks on new IPSR */
+        newpsr_exc = newpsr & XPSR_EXCP;
+        if (!((env->v7m.exception == 0 && newpsr_exc == 0) ||
+              (env->v7m.exception == 1 && newpsr_exc != 0))) {
+            /* Pend the fault and tell our caller to take it */
+            env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;
+            armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE,
+                                    env->v7m.secure);
+            qemu_log_mask(CPU_LOG_INT,
+                          "...taking INVPC UsageFault: "
+                          "IPSR consistency check failed\n");
+            return false;
+        }
+
+        *frame_sp_p = frameptr + 8;
+    }
+
+    /* This invalidates frame_sp_p */
+    switch_v7m_security_state(env, true);
+    env->v7m.exception = newpsr_exc;
+    env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK;
+    if (newpsr & XPSR_SFPA) {
+        env->v7m.control[M_REG_S] |= R_V7M_CONTROL_SFPA_MASK;
+    }
+    xpsr_write(env, 0, XPSR_IT);
+    env->thumb = newpc & 1;
+    env->regs[15] = newpc & ~1;
+
+    qemu_log_mask(CPU_LOG_INT, "...function return successful\n");
+    return true;
+}
+
 static void arm_log_exception(int idx)
 {
     if (qemu_loglevel_mask(CPU_LOG_INT)) {
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
     case EXCP_IRQ:
         break;
     case EXCP_EXCEPTION_EXIT:
-        do_v7m_exception_exit(cpu);
-        return;
+        if (env->regs[15] < EXC_RETURN_MIN_MAGIC) {
+            /* Must be v8M security extension function return */
+            assert(env->regs[15] >= FNC_RETURN_MIN_MAGIC);
+            assert(arm_feature(env, ARM_FEATURE_M_SECURITY));
+            if (do_v7m_function_return(cpu)) {
+                return;
+            }
+        } else {
+            do_v7m_exception_exit(cpu);
+            return;
+        }
+        break;
     default:
         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
         return; /* Never happens.  Keep compiler happy.  */
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static inline void gen_bx_excret(DisasContext *s, TCGv_i32 var)
      * s->base.is_jmp that we need to do the rest of the work later.
      */
     gen_bx(s, var);
-    if (s->v7m_handler_mode && arm_dc_feature(s, ARM_FEATURE_M)) {
+    if (arm_dc_feature(s, ARM_FEATURE_M_SECURITY) ||
+        (s->v7m_handler_mode && arm_dc_feature(s, ARM_FEATURE_M))) {
         s->base.is_jmp = DISAS_BX_EXCRET;
     }
 }
@@ -XXX,XX +XXX,XX @@ static inline void gen_bx_excret_final_code(DisasContext *s)
 {
     /* Generate the code to finish possible exception return and end the TB */
     TCGLabel *excret_label = gen_new_label();
+    uint32_t min_magic;
+
+    if (arm_dc_feature(s, ARM_FEATURE_M_SECURITY)) {
+        /* Covers FNC_RETURN and EXC_RETURN magic */
+        min_magic = FNC_RETURN_MIN_MAGIC;
+    } else {
+        /* EXC_RETURN magic only */
+        min_magic = EXC_RETURN_MIN_MAGIC;
+    }
 
     /* Is the new PC value in the magic range indicating exception return? */
-    tcg_gen_brcondi_i32(TCG_COND_GEU, cpu_R[15], 0xff000000, excret_label);
+    tcg_gen_brcondi_i32(TCG_COND_GEU, cpu_R[15], min_magic, excret_label);
     /* No: end the TB as we would for a DISAS_JMP */
     if (is_singlestepping(s)) {
         gen_singlestep_exception(s);
-- 
2.7.4

The code which implements the Thumb1 split BL/BLX instructions
is guarded by a check on "not M or THUMB2". All we really need
to check here is "not THUMB2" (and we assume that elsewhere too,
eg in the ARCH(6T2) test that UNDEFs the Thumb2 insns).

This doesn't change behaviour because all M profile cores
have Thumb2 and so ARM_FEATURE_M implies ARM_FEATURE_THUMB2.
(v6M implements a very restricted subset of Thumb2, but we
can cross that bridge when we get to it with appropriate
feature bits.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1507556919-24992-6-git-send-email-peter.maydell@linaro.org
---
 target/arm/translate.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
     int conds;
     int logic_cc;
 
-    if (!(arm_dc_feature(s, ARM_FEATURE_THUMB2)
-          || arm_dc_feature(s, ARM_FEATURE_M))) {
+    if (!arm_dc_feature(s, ARM_FEATURE_THUMB2)) {
         /* Thumb-1 cores may need to treat bl and blx as a pair of
            16-bit instructions to get correct prefetch abort behavior.  */
         insn = insn_hw1;
-- 
2.7.4

Refactor the Thumb decode to do the loads of the instruction words at
the top level rather than only loading the second half of a 32-bit
Thumb insn in the middle of the decode.

This is simple apart from the awkward case of Thumb1, where the
BL/BLX prefix and suffix instructions live in what in Thumb2 is the
32-bit insn space.  To handle these we decode enough to identify
whether we're looking at a prefix/suffix that we handle as a 16 bit
insn, or a prefix that we're going to merge with the following suffix
to consider as a 32 bit insn.  The translation of the 16 bit cases
then moves from disas_thumb2_insn() to disas_thumb_insn().

The refactoring has the benefit that we don't need to pass the
CPUARMState* down into the decoder code any more, but the major
reason for doing this is that some Thumb instructions must be always
unconditional regardless of the IT state bits, so we need to know the
whole insn before we emit the "skip this insn if the IT bits and cond
state tell us to" code.  (The always unconditional insns are BKPT,
HLT and SG; the last of these is 32 bits.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1507556919-24992-7-git-send-email-peter.maydell@linaro.org
---
 target/arm/translate.c | 178 ++++++++++++++++++++++++++++++-------------------
 1 file changed, 108 insertions(+), 70 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
     }
 }
 
+static bool thumb_insn_is_16bit(DisasContext *s, uint32_t insn)
+{
+    /* Return true if this is a 16 bit instruction. We must be precise
+     * about this (matching the decode).  We assume that s->pc still
+     * points to the first 16 bits of the insn.
+     */
+    if ((insn >> 11) < 0x1d) {
+        /* Definitely a 16-bit instruction */
+        return true;
+    }
+
+    /* Top five bits 0b11101 / 0b11110 / 0b11111 : this is the
+     * first half of a 32-bit Thumb insn. Thumb-1 cores might
+     * end up actually treating this as two 16-bit insns, though,
+     * if it's half of a bl/blx pair that might span a page boundary.
+     */
+    if (arm_dc_feature(s, ARM_FEATURE_THUMB2)) {
+        /* Thumb2 cores (including all M profile ones) always treat
+         * 32-bit insns as 32-bit.
+         */
+        return false;
+    }
+
+    if ((insn >> 11) == 0x1e && (s->pc < s->next_page_start - 3)) {
+        /* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix, and the suffix
+         * is not on the next page; we merge this into a 32-bit
+         * insn.
+         */
+        return false;
+    }
+    /* 0b1110_1xxx_xxxx_xxxx : BLX suffix (or UNDEF);
+     * 0b1111_1xxx_xxxx_xxxx : BL suffix;
+     * 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix on the end of a page
+     *  -- handle as single 16 bit insn
+     */
+    return true;
+}
+
 /* Return true if this is a Thumb-2 logical op.  */
 static int
 thumb2_logic_op(int op)
@@ -XXX,XX +XXX,XX @@ gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out,
 
 /* Translate a 32-bit thumb instruction.  Returns nonzero if the instruction
    is not legal.  */
-static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw1)
+static int disas_thumb2_insn(DisasContext *s, uint32_t insn)
 {
-    uint32_t insn, imm, shift, offset;
+    uint32_t imm, shift, offset;
     uint32_t rd, rn, rm, rs;
     TCGv_i32 tmp;
     TCGv_i32 tmp2;
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
     int conds;
     int logic_cc;
 
-    if (!arm_dc_feature(s, ARM_FEATURE_THUMB2)) {
-        /* Thumb-1 cores may need to treat bl and blx as a pair of
-           16-bit instructions to get correct prefetch abort behavior.  */
-        insn = insn_hw1;
-        if ((insn & (1 << 12)) == 0) {
-            ARCH(5);
-            /* Second half of blx.  */
-            offset = ((insn & 0x7ff) << 1);
-            tmp = load_reg(s, 14);
-            tcg_gen_addi_i32(tmp, tmp, offset);
-            tcg_gen_andi_i32(tmp, tmp, 0xfffffffc);
-
-            tmp2 = tcg_temp_new_i32();
-            tcg_gen_movi_i32(tmp2, s->pc | 1);
-            store_reg(s, 14, tmp2);
-            gen_bx(s, tmp);
-            return 0;
-        }
-        if (insn & (1 << 11)) {
-            /* Second half of bl.  */
-            offset = ((insn & 0x7ff) << 1) | 1;
-            tmp = load_reg(s, 14);
-            tcg_gen_addi_i32(tmp, tmp, offset);
-
-            tmp2 = tcg_temp_new_i32();
-            tcg_gen_movi_i32(tmp2, s->pc | 1);
-            store_reg(s, 14, tmp2);
-            gen_bx(s, tmp);
-            return 0;
-        }
-        if ((s->pc & ~TARGET_PAGE_MASK) == 0) {
-            /* Instruction spans a page boundary.  Implement it as two
-               16-bit instructions in case the second half causes an
-               prefetch abort.  */
-            offset = ((int32_t)insn << 21) >> 9;
-            tcg_gen_movi_i32(cpu_R[14], s->pc + 2 + offset);
-            return 0;
-        }
-        /* Fall through to 32-bit decode.  */
-    }
-
-    insn = arm_lduw_code(env, s->pc, s->sctlr_b);
-    s->pc += 2;
-    insn |= (uint32_t)insn_hw1 << 16;
-
+    /* The only 32 bit insn that's allowed for Thumb1 is the combined
+     * BL/BLX prefix and suffix.
+     */
     if ((insn & 0xf800e800) != 0xf000e800) {
         ARCH(6T2);
     }
@@ -XXX,XX +XXX,XX @@ illegal_op:
     return 1;
 }
 
-static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
+static void disas_thumb_insn(DisasContext *s, uint32_t insn)
 {
-    uint32_t val, insn, op, rm, rn, rd, shift, cond;
+    uint32_t val, op, rm, rn, rd, shift, cond;
     int32_t offset;
     int i;
     TCGv_i32 tmp;
     TCGv_i32 tmp2;
     TCGv_i32 addr;
 
-    if (s->condexec_mask) {
-        cond = s->condexec_cond;
-        if (cond != 0x0e) {     /* Skip conditional when condition is AL. */
-          s->condlabel = gen_new_label();
-          arm_gen_test_cc(cond ^ 1, s->condlabel);
-          s->condjmp = 1;
-        }
-    }
-
-    insn = arm_lduw_code(env, s->pc, s->sctlr_b);
-    s->pc += 2;
-
     switch (insn >> 12) {
     case 0: case 1:
 
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
 
     case 14:
         if (insn & (1 << 11)) {
-            if (disas_thumb2_insn(env, s, insn))
-              goto undef32;
+            /* thumb_insn_is_16bit() ensures we can't get here for
+             * a Thumb2 CPU, so this must be a thumb1 split BL/BLX:
+             * 0b1110_1xxx_xxxx_xxxx : BLX suffix (or UNDEF)
+             */
+            assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2));
+            ARCH(5);
+            offset = ((insn & 0x7ff) << 1);
+            tmp = load_reg(s, 14);
+            tcg_gen_addi_i32(tmp, tmp, offset);
+            tcg_gen_andi_i32(tmp, tmp, 0xfffffffc);
+
+            tmp2 = tcg_temp_new_i32();
+            tcg_gen_movi_i32(tmp2, s->pc | 1);
+            store_reg(s, 14, tmp2);
+            gen_bx(s, tmp);
             break;
         }
         /* unconditional branch */
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
         break;
 
     case 15:
-        if (disas_thumb2_insn(env, s, insn))
-            goto undef32;
+        /* thumb_insn_is_16bit() ensures we can't get here for
+         * a Thumb2 CPU, so this must be a thumb1 split BL/BLX.
+         */
+        assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2));
+
+        if (insn & (1 << 11)) {
+            /* 0b1111_1xxx_xxxx_xxxx : BL suffix */
+            offset = ((insn & 0x7ff) << 1) | 1;
+            tmp = load_reg(s, 14);
+            tcg_gen_addi_i32(tmp, tmp, offset);
+
+            tmp2 = tcg_temp_new_i32();
+            tcg_gen_movi_i32(tmp2, s->pc | 1);
+            store_reg(s, 14, tmp2);
+            gen_bx(s, tmp);
+        } else {
+            /* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix */
+            uint32_t uoffset = ((int32_t)insn << 21) >> 9;
+
+            tcg_gen_movi_i32(cpu_R[14], s->pc + 2 + uoffset);
+        }
         break;
     }
     return;
-undef32:
-    gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
-                       default_exception_el(s));
-    return;
 illegal_op:
 undef:
     gen_exception_insn(s, 2, EXCP_UDEF, syn_uncategorized(),
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
 {
     DisasContext *dc = container_of(dcbase, DisasContext, base);
     CPUARMState *env = cpu->env_ptr;
+    uint32_t insn;
+    bool is_16bit;
 
     if (arm_pre_translate_insn(dc)) {
         return;
     }
 
-    disas_thumb_insn(env, dc);
+    insn = arm_lduw_code(env, dc->pc, dc->sctlr_b);
+    is_16bit = thumb_insn_is_16bit(dc, insn);
+    dc->pc += 2;
+    if (!is_16bit) {
+        uint32_t insn2 = arm_lduw_code(env, dc->pc, dc->sctlr_b);
+
+        insn = insn << 16 | insn2;
+        dc->pc += 2;
+    }
+
+    if (dc->condexec_mask) {
+        uint32_t cond = dc->condexec_cond;
+
+        if (cond != 0x0e) {     /* Skip conditional when condition is AL. */
+            dc->condlabel = gen_new_label();
+            arm_gen_test_cc(cond ^ 1, dc->condlabel);
+            dc->condjmp = 1;
+        }
+    }
+
+    if (is_16bit) {
+        disas_thumb_insn(dc, insn);
+    } else {
+        disas_thumb2_insn(dc, insn);
+    }
 
     /* Advance the Thumb condexec condition.  */
     if (dc->condexec_mask) {
-- 
2.7.4

Recent changes have left insn_crosses_page() more complicated
than it needed to be:
 * it's only called from thumb_tr_translate_insn() so we know
   for certain that we're looking at a Thumb insn
 * the caller's check for dc->pc >= dc->next_page_start - 3
   means that dc->pc can't possibly be 4 aligned, so there's
   no need to check that (the check was partly there to ensure
   that we didn't treat an ARM insn as Thumb, I think)
 * we now have thumb_insn_is_16bit() which lets us do a precise
   check of the length of the next insn, rather than opencoding
   an inaccurate check

Simplify it down to just loading the first half of the insn
and calling thumb_insn_is_16bit() on it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1507556919-24992-8-git-send-email-peter.maydell@linaro.org
---
 target/arm/translate.c | 27 ++++++---------------------
 1 file changed, 6 insertions(+), 21 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
 {
     /* Return true if the insn at dc->pc might cross a page boundary.
      * (False positives are OK, false negatives are not.)
+     * We know this is a Thumb insn, and our caller ensures we are
+     * only called if dc->pc is less than 4 bytes from the page
+     * boundary, so we cross the page if the first 16 bits indicate
+     * that this is a 32 bit insn.
      */
-    uint16_t insn;
+    uint16_t insn = arm_lduw_code(env, s->pc, s->sctlr_b);
 
-    if ((s->pc & 3) == 0) {
-        /* At a 4-aligned address we can't be crossing a page */
-        return false;
-    }
-
-    /* This must be a Thumb insn */
-    insn = arm_lduw_code(env, s->pc, s->sctlr_b);
-
-    if ((insn >> 11) >= 0x1d) {
-        /* Top five bits 0b11101 / 0b11110 / 0b11111 : this is the
-         * First half of a 32-bit Thumb insn. Thumb-1 cores might
-         * end up actually treating this as two 16-bit insns (see the
-         * code at the start of disas_thumb2_insn()) but we don't bother
-         * to check for that as it is unlikely, and false positives here
-         * are harmless.
-         */
-        return true;
-    }
-    /* Definitely a 16-bit insn, can't be crossing a page. */
-    return false;
+    return !thumb_insn_is_16bit(s, insn);
 }
 
 static int arm_tr_init_disas_context(DisasContextBase *dcbase,
-- 
2.7.4

A few Thumb instructions are always unconditional even inside an
IT block (as opposed to being UNPREDICTABLE if used inside an
IT block): BKPT, the v8M SG instruction, and the A profile
HLT (debug halt) instruction.

This means we need to suppress the jump-over-instruction-on-condfail
code generation (though the IT state still advances as usual and
subsequent insns in the IT block may be conditional).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1507556919-24992-9-git-send-email-peter.maydell@linaro.org
---
 target/arm/translate.c | 48 +++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 47 insertions(+), 1 deletion(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
        in init_disas_context by adjusting max_insns.  */
 }
 
+static bool thumb_insn_is_unconditional(DisasContext *s, uint32_t insn)
+{
+    /* Return true if this Thumb insn is always unconditional,
+     * even inside an IT block. This is true of only a very few
+     * instructions: BKPT, HLT, and SG.
+     *
+     * A larger class of instructions are UNPREDICTABLE if used
+     * inside an IT block; we do not need to detect those here, because
+     * what we do by default (perform the cc check and update the IT
+     * bits state machine) is a permitted CONSTRAINED UNPREDICTABLE
+     * choice for those situations.
+     *
+     * insn is either a 16-bit or a 32-bit instruction; the two are
+     * distinguishable because for the 16-bit case the top 16 bits
+     * are zeroes, and that isn't a valid 32-bit encoding.
+     */
+    if ((insn & 0xffffff00) == 0xbe00) {
+        /* BKPT */
+        return true;
+    }
+
+    if ((insn & 0xffffffc0) == 0xba80 && arm_dc_feature(s, ARM_FEATURE_V8) &&
+        !arm_dc_feature(s, ARM_FEATURE_M)) {
+        /* HLT: v8A only. This is unconditional even when it is going to
+         * UNDEF; see the v8A ARM ARM DDI0487B.a H3.3.
+         * For v7 cores this was a plain old undefined encoding and so
+         * honours its cc check. (We might be using the encoding as
+         * a semihosting trap, but we don't change the cc check behaviour
+         * on that account, because a debugger connected to a real v7A
+         * core and emulating semihosting traps by catching the UNDEF
+         * exception would also only see cases where the cc check passed.
+         * No guest code should be trying to do a HLT semihosting trap
+         * in an IT block anyway.
+         */
+        return true;
+    }
+
+    if (insn == 0xe97fe97f && arm_dc_feature(s, ARM_FEATURE_V8) &&
+        arm_dc_feature(s, ARM_FEATURE_M)) {
+        /* SG: v8M only */
+        return true;
+    }
+
+    return false;
+}
+
 static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
 {
     DisasContext *dc = container_of(dcbase, DisasContext, base);
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
         dc->pc += 2;
     }
 
-    if (dc->condexec_mask) {
+    if (dc->condexec_mask && !thumb_insn_is_unconditional(dc, insn)) {
         uint32_t cond = dc->condexec_cond;
 
         if (cond != 0x0e) {     /* Skip conditional when condition is AL. */
-- 
2.7.4

The common situation of the SG instruction is that it is
executed from S&NSC memory by a CPU in NS state. That case
is handled by v7m_handle_execute_nsc(). However the instruction
also has defined behaviour in a couple of other cases:
 * SG instruction in NS memory (behaves as a NOP)
 * SG in S memory but CPU already secure (clears IT bits and
   does nothing else)
 * SG instruction in v8M without Security Extension (NOP)

These can be implemented in translate.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1507556919-24992-10-git-send-email-peter.maydell@linaro.org
---
 target/arm/translate.c | 23 ++++++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(DisasContext *s, uint32_t insn)
              * - load/store doubleword, load/store exclusive, ldacq/strel,
              *   table branch.
              */
-            if (insn & 0x01200000) {
+            if (insn == 0xe97fe97f && arm_dc_feature(s, ARM_FEATURE_M) &&
+                arm_dc_feature(s, ARM_FEATURE_V8)) {
+                /* 0b1110_1001_0111_1111_1110_1001_0111_111
+                 *  - SG (v8M only)
+                 * The bulk of the behaviour for this instruction is implemented
+                 * in v7m_handle_execute_nsc(), which deals with the insn when
+                 * it is executed by a CPU in non-secure state from memory
+                 * which is Secure & NonSecure-Callable.
+                 * Here we only need to handle the remaining cases:
+                 *  * in NS memory (including the "security extension not
+                 *    implemented" case) : NOP
+                 *  * in S memory but CPU already secure (clear IT bits)
+                 * We know that the attribute for the memory this insn is
+                 * in must match the current CPU state, because otherwise
+                 * get_phys_addr_pmsav8 would have generated an exception.
+                 */
+                if (s->v8m_secure) {
+                    /* Like the IT insn, we don't need to generate any code */
+                    s->condexec_cond = 0;
+                    s->condexec_mask = 0;
+                }
+            } else if (insn & 0x01200000) {
                 /* 0b1110_1000_x11x_xxxx_xxxx_xxxx_xxxx_xxxx
                  *  - load/store dual (post-indexed)
                  * 0b1111_1001_x10x_xxxx_xxxx_xxxx_xxxx_xxxx
-- 
2.7.4

This calculation of the first exception vector in
the ITNS<n> register being accessed:
        int startvec = 32 * (offset - 0x380) + NVIC_FIRST_IRQ;

is incorrect, because offset is in bytes, so we only want
to multiply by 8.

Spotted by Coverity (CID 1381484, CID 1381488), though it is
not correct that it actually overflows the buffer, because
we have a 'startvec + i < s->num_irq' guard.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1507650856-11718-1-git-send-email-peter.maydell@linaro.org
---
 hw/intc/armv7m_nvic.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
         return ((s->num_irq - NVIC_FIRST_IRQ) / 32) - 1;
     case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */
     {
-        int startvec = 32 * (offset - 0x380) + NVIC_FIRST_IRQ;
+        int startvec = 8 * (offset - 0x380) + NVIC_FIRST_IRQ;
         int i;
 
         if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
     switch (offset) {
     case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */
     {
-        int startvec = 32 * (offset - 0x380) + NVIC_FIRST_IRQ;
+        int startvec = 8 * (offset - 0x380) + NVIC_FIRST_IRQ;
         int i;
 
         if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
-- 
2.7.4

Arm queue; not huge but I figured I might as well send it out since
I've been doing code review today and there's no queue of unprocessed
pullreqs...

thanks
-- PMM

The following changes since commit b3f846c59d8405bb87c551187721fc92ff2f1b92:

Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-11v2' into staging (2021-01-11 15:15:35 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210112

for you to fetch changes up to 19d131395ccaf503db21dadd8257e6dc9fc1d7de:

ui/cocoa: Fix openFile: deprecation on Big Sur (2021-01-12 11:38:37 +0000)

----------------------------------------------------------------
target-arm queue:
 * arm: Support emulation of ARMv8.4-TTST extension
 * arm: Update cpu.h ID register field definitions
 * arm: Fix breakage of XScale instruction emulation
 * hw/net/lan9118: Fix RX Status FIFO PEEK value
 * npcm7xx: Add ADC and PWM emulation
 * ui/cocoa: Make "open docs" help menu entry work again when binary
   is run from the build tree
 * ui/cocoa: Fix openFile: deprecation on Big Sur
 * docs: Add qemu-storage-daemon(1) manpage to meson.build
 * docs: Build and install all the docs in a single manual

----------------------------------------------------------------
Hao Wu (6):
      hw/misc: Add clock converter in NPCM7XX CLK module
      hw/timer: Refactor NPCM7XX Timer to use CLK clock
      hw/adc: Add an ADC module for NPCM7XX
      hw/misc: Add a PWM module for NPCM7XX
      hw/misc: Add QTest for NPCM7XX PWM Module
      hw/*: Use type casting for SysBusDevice in NPCM7XX

Leif Lindholm (6):
      target/arm: fix typo in cpu.h ID_AA64PFR1 field name
      target/arm: make ARMCPU.clidr 64-bit
      target/arm: make ARMCPU.ctr 64-bit
      target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h
      target/arm: add aarch64 ID register fields to cpu.h
      target/arm: add aarch32 ID register fields to cpu.h

Peter Maydell (5):
      docs: Add qemu-storage-daemon(1) manpage to meson.build
      docs: Build and install all the docs in a single manual
      target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns
      hw/net/lan9118: Fix RX Status FIFO PEEK value
      hw/net/lan9118: Add symbolic constants for register offsets

Roman Bolshakov (2):
      ui/cocoa: Update path to docs in build tree
      ui/cocoa: Fix openFile: deprecation on Big Sur

Rémi Denis-Courmont (2):
      target/arm: ARMv8.4-TTST extension
      target/arm: enable Small Translation tables in max CPU

docs/conf.py                     |  46 ++-
 docs/devel/conf.py               |  15 -
 docs/index.html.in               |  17 -
 docs/interop/conf.py             |  28 --
 docs/meson.build                 |  65 ++--
 docs/specs/conf.py               |  16 -
 docs/system/arm/nuvoton.rst      |   4 +-
 docs/system/conf.py              |  28 --
 docs/tools/conf.py               |  37 --
 docs/user/conf.py                |  15 -
 meson.build                      |   1 +
 hw/adc/trace.h                   |   1 +
 include/hw/adc/npcm7xx_adc.h     |  69 ++++
 include/hw/arm/npcm7xx.h         |   4 +
 include/hw/misc/npcm7xx_clk.h    | 146 ++++++-
 include/hw/misc/npcm7xx_pwm.h    | 105 +++++
 include/hw/timer/npcm7xx_timer.h |   1 +
 target/arm/cpu.h                 |  85 ++++-
 hw/adc/npcm7xx_adc.c             | 301 +++++++++++++++
 hw/arm/npcm7xx.c                 |  55 ++-
 hw/arm/npcm7xx_boards.c          |   2 +-
 hw/mem/npcm7xx_mc.c              |   2 +-
 hw/misc/npcm7xx_clk.c            | 807 ++++++++++++++++++++++++++++++++++++++-
 hw/misc/npcm7xx_gcr.c            |   2 +-
 hw/misc/npcm7xx_pwm.c            | 550 ++++++++++++++++++++++++++
 hw/misc/npcm7xx_rng.c            |   2 +-
 hw/net/lan9118.c                 |  26 +-
 hw/nvram/npcm7xx_otp.c           |   2 +-
 hw/ssi/npcm7xx_fiu.c             |   2 +-
 hw/timer/npcm7xx_timer.c         |  39 +-
 target/arm/cpu64.c               |   1 +
 target/arm/helper.c              |  15 +-
 target/arm/translate.c           |   7 +
 tests/qtest/npcm7xx_adc-test.c   | 377 ++++++++++++++++++
 tests/qtest/npcm7xx_pwm-test.c   | 490 ++++++++++++++++++++++++
 hw/adc/meson.build               |   1 +
 hw/adc/trace-events              |   5 +
 hw/misc/meson.build              |   1 +
 hw/misc/trace-events             |   6 +
 tests/qtest/meson.build          |   4 +-
 ui/cocoa.m                       |   7 +-
 41 files changed, 3124 insertions(+), 263 deletions(-)
 delete mode 100644 docs/devel/conf.py
 delete mode 100644 docs/index.html.in
 delete mode 100644 docs/interop/conf.py
 delete mode 100644 docs/specs/conf.py
 delete mode 100644 docs/system/conf.py
 delete mode 100644 docs/tools/conf.py
 delete mode 100644 docs/user/conf.py
 create mode 100644 hw/adc/trace.h
 create mode 100644 include/hw/adc/npcm7xx_adc.h
 create mode 100644 include/hw/misc/npcm7xx_pwm.h
 create mode 100644 hw/adc/npcm7xx_adc.c
 create mode 100644 hw/misc/npcm7xx_pwm.c
 create mode 100644 tests/qtest/npcm7xx_adc-test.c
 create mode 100644 tests/qtest/npcm7xx_pwm-test.c
 create mode 100644 hw/adc/trace-events

From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>

This adds for the Small Translation tables extension in AArch64 state.

Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h    |  5 +++++
 target/arm/helper.c | 15 +++++++++++++--
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_uao(const ARMISARegisters *id)
     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;
 }
 
+static inline bool isar_feature_aa64_st(const ARMISARegisters *id)
+{
+    return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0;
+}
+
 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
 {
     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
 {
     uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
     bool epd, hpd, using16k, using64k;
-    int select, tsz, tbi;
+    int select, tsz, tbi, max_tsz;
 
     if (!regime_has_2_ranges(mmu_idx)) {
         select = 0;
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
             hpd = extract64(tcr, 42, 1);
         }
     }
-    tsz = MIN(tsz, 39);  /* TODO: ARMv8.4-TTST */
+
+    if (cpu_isar_feature(aa64_st, env_archcpu(env))) {
+        max_tsz = 48 - using64k;
+    } else {
+        max_tsz = 39;
+    }
+
+    tsz = MIN(tsz, max_tsz);
     tsz = MAX(tsz, 16);  /* TODO: ARMv8.2-LVA  */
 
     /* Present TBI as a composite with TBID.  */
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
         if (!aarch64 || stride == 9) {
             /* AArch32 or 4KB pages */
             startlevel = 2 - sl0;
+
+            if (cpu_isar_feature(aa64_st, cpu)) {
+                startlevel &= 3;
+            }
         } else {
             /* 16KB or 64KB pages */
             startlevel = 3 - sl0;
-- 
2.20.1

From: Leif Lindholm <leif@nuviainc.com>

The AArch64 view of CLIDR_EL1 extends the ICB field to include also bit
32, as well as adding a Ttype<n> field when FEAT_MTE is implemented.
Extend the clidr field to be able to hold this context.

Signed-off-by: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20210108185154.8108-3-leif@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
     uint32_t id_afr0;
     uint64_t id_aa64afr0;
     uint64_t id_aa64afr1;
-    uint32_t clidr;
+    uint64_t clidr;
     uint64_t mp_affinity; /* MP ID without feature bits */
     /* The elements of this array are the CCSIDR values for each cache,
      * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
-- 
2.20.1

From: Leif Lindholm <leif@nuviainc.com>

Signed-off-by: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20210108185154.8108-5-leif@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(V7M_FPCCR, ASPEN, 31, 1)
 /*
  * System register ID fields.
  */
+FIELD(CLIDR_EL1, CTYPE1, 0, 3)
+FIELD(CLIDR_EL1, CTYPE2, 3, 3)
+FIELD(CLIDR_EL1, CTYPE3, 6, 3)
+FIELD(CLIDR_EL1, CTYPE4, 9, 3)
+FIELD(CLIDR_EL1, CTYPE5, 12, 3)
+FIELD(CLIDR_EL1, CTYPE6, 15, 3)
+FIELD(CLIDR_EL1, CTYPE7, 18, 3)
+FIELD(CLIDR_EL1, LOUIS, 21, 3)
+FIELD(CLIDR_EL1, LOC, 24, 3)
+FIELD(CLIDR_EL1, LOUU, 27, 3)
+FIELD(CLIDR_EL1, ICB, 30, 3)
+
+/* When FEAT_CCIDX is implemented */
+FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3)
+FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21)
+FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24)
+
+/* When FEAT_CCIDX is not implemented */
+FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
+FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10)
+FIELD(CCSIDR_EL1, NUMSETS, 13, 15)
+
+FIELD(CTR_EL0,  IMINLINE, 0, 4)
+FIELD(CTR_EL0,  L1IP, 14, 2)
+FIELD(CTR_EL0,  DMINLINE, 16, 4)
+FIELD(CTR_EL0,  ERG, 20, 4)
+FIELD(CTR_EL0,  CWG, 24, 4)
+FIELD(CTR_EL0,  IDC, 28, 1)
+FIELD(CTR_EL0,  DIC, 29, 1)
+FIELD(CTR_EL0,  TMINLINE, 32, 6)
+
 FIELD(MIDR_EL1, REVISION, 0, 4)
 FIELD(MIDR_EL1, PARTNUM, 4, 12)
 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
-- 
2.20.1

From: Leif Lindholm <leif@nuviainc.com>

Add entries present in ARM DDI 0487F.c (August 2020).

Signed-off-by: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20210108185154.8108-6-leif@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64ISAR1, GPI, 28, 4)
 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
 FIELD(ID_AA64ISAR1, SB, 36, 4)
 FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
+FIELD(ID_AA64ISAR1, BF16, 44, 4)
+FIELD(ID_AA64ISAR1, DGH, 48, 4)
+FIELD(ID_AA64ISAR1, I8MM, 52, 4)
 
 FIELD(ID_AA64PFR0, EL0, 0, 4)
 FIELD(ID_AA64PFR0, EL1, 4, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
 FIELD(ID_AA64PFR0, GIC, 24, 4)
 FIELD(ID_AA64PFR0, RAS, 28, 4)
 FIELD(ID_AA64PFR0, SVE, 32, 4)
+FIELD(ID_AA64PFR0, SEL2, 36, 4)
+FIELD(ID_AA64PFR0, MPAM, 40, 4)
+FIELD(ID_AA64PFR0, AMU, 44, 4)
+FIELD(ID_AA64PFR0, DIT, 48, 4)
+FIELD(ID_AA64PFR0, CSV2, 56, 4)
+FIELD(ID_AA64PFR0, CSV3, 60, 4)
 
 FIELD(ID_AA64PFR1, BT, 0, 4)
 FIELD(ID_AA64PFR1, SSBS, 4, 4)
 FIELD(ID_AA64PFR1, MTE, 8, 4)
 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
+FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4)
 
 FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
 FIELD(ID_AA64MMFR0, EXS, 44, 4)
+FIELD(ID_AA64MMFR0, FGT, 56, 4)
+FIELD(ID_AA64MMFR0, ECV, 60, 4)
 
 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR1, LO, 16, 4)
 FIELD(ID_AA64MMFR1, PAN, 20, 4)
 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
 FIELD(ID_AA64MMFR1, XNX, 28, 4)
+FIELD(ID_AA64MMFR1, TWED, 32, 4)
+FIELD(ID_AA64MMFR1, ETS, 36, 4)
 
 FIELD(ID_AA64MMFR2, CNP, 0, 4)
 FIELD(ID_AA64MMFR2, UAO, 4, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
 FIELD(ID_AA64DFR0, PMSVER, 32, 4)
 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
+FIELD(ID_AA64DFR0, MTPMU, 48, 4)
 
 FIELD(ID_DFR0, COPDBG, 0, 4)
 FIELD(ID_DFR0, COPSDBG, 4, 4)
-- 
2.20.1

From: Leif Lindholm <leif@nuviainc.com>

Add entries present in ARM DDI 0487F.c (August 2020).

Signed-off-by: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20210108185154.8108-7-leif@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(ID_ISAR6, DP, 4, 4)
 FIELD(ID_ISAR6, FHM, 8, 4)
 FIELD(ID_ISAR6, SB, 12, 4)
 FIELD(ID_ISAR6, SPECRES, 16, 4)
+FIELD(ID_ISAR6, BF16, 20, 4)
+FIELD(ID_ISAR6, I8MM, 24, 4)
 
 FIELD(ID_MMFR0, VMSA, 0, 4)
 FIELD(ID_MMFR0, PMSA, 4, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR0, AUXREG, 20, 4)
 FIELD(ID_MMFR0, FCSE, 24, 4)
 FIELD(ID_MMFR0, INNERSHR, 28, 4)
 
+FIELD(ID_MMFR1, L1HVDVA, 0, 4)
+FIELD(ID_MMFR1, L1UNIVA, 4, 4)
+FIELD(ID_MMFR1, L1HVDSW, 8, 4)
+FIELD(ID_MMFR1, L1UNISW, 12, 4)
+FIELD(ID_MMFR1, L1HVD, 16, 4)
+FIELD(ID_MMFR1, L1UNI, 20, 4)
+FIELD(ID_MMFR1, L1TSTCLN, 24, 4)
+FIELD(ID_MMFR1, BPRED, 28, 4)
+
+FIELD(ID_MMFR2, L1HVDFG, 0, 4)
+FIELD(ID_MMFR2, L1HVDBG, 4, 4)
+FIELD(ID_MMFR2, L1HVDRNG, 8, 4)
+FIELD(ID_MMFR2, HVDTLB, 12, 4)
+FIELD(ID_MMFR2, UNITLB, 16, 4)
+FIELD(ID_MMFR2, MEMBARR, 20, 4)
+FIELD(ID_MMFR2, WFISTALL, 24, 4)
+FIELD(ID_MMFR2, HWACCFLG, 28, 4)
+
 FIELD(ID_MMFR3, CMAINTVA, 0, 4)
 FIELD(ID_MMFR3, CMAINTSW, 4, 4)
 FIELD(ID_MMFR3, BPMAINT, 8, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR4, LSM, 20, 4)
 FIELD(ID_MMFR4, CCIDX, 24, 4)
 FIELD(ID_MMFR4, EVT, 28, 4)
 
+FIELD(ID_MMFR5, ETS, 0, 4)
+
 FIELD(ID_PFR0, STATE0, 0, 4)
 FIELD(ID_PFR0, STATE1, 4, 4)
 FIELD(ID_PFR0, STATE2, 8, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_PFR1, SEC_FRAC, 20, 4)
 FIELD(ID_PFR1, VIRT_FRAC, 24, 4)
 FIELD(ID_PFR1, GIC, 28, 4)
 
+FIELD(ID_PFR2, CSV3, 0, 4)
+FIELD(ID_PFR2, SSBS, 4, 4)
+FIELD(ID_PFR2, RAS_FRAC, 8, 4)
+
 FIELD(ID_AA64ISAR0, AES, 4, 4)
 FIELD(ID_AA64ISAR0, SHA1, 8, 4)
 FIELD(ID_AA64ISAR0, SHA2, 12, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_DFR0, MPROFDBG, 20, 4)
 FIELD(ID_DFR0, PERFMON, 24, 4)
 FIELD(ID_DFR0, TRACEFILT, 28, 4)
 
+FIELD(ID_DFR1, MTPMU, 0, 4)
+
 FIELD(DBGDIDR, SE_IMP, 12, 1)
 FIELD(DBGDIDR, NSUHD_IMP, 14, 1)
 FIELD(DBGDIDR, VERSION, 16, 4)
-- 
2.20.1

From: Roman Bolshakov <r.bolshakov@yadro.com>

QEMU documentation can't be opened if QEMU is run from build tree
because executables are placed in the top of build tree after conversion
to meson.

Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com>
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210108213815.64678-1-r.bolshakov@yadro.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 ui/cocoa.m | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/ui/cocoa.m b/ui/cocoa.m
index XXXXXXX..XXXXXXX 100644
--- a/ui/cocoa.m
+++ b/ui/cocoa.m
@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
 - (void) openDocumentation: (NSString *) filename
 {
     /* Where to look for local files */
-    NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"../docs/"};
+    NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"docs/"};
     NSString *full_file_path;
 
     /* iterate thru the possible paths until the file is found */
-- 
2.20.1

In commit 1982e1602d15 we added a new qemu-storage-daemon(1) manpage.
At the moment new manpages have to be listed both in the conf.py for
Sphinx and also in docs/meson.build for Meson. We forgot the second
of those -- correct the omission.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20210108161416.21129-2-peter.maydell@linaro.org
---
 docs/meson.build | 1 +
 1 file changed, 1 insertion(+)

diff --git a/docs/meson.build b/docs/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/docs/meson.build
+++ b/docs/meson.build
@@ -XXX,XX +XXX,XX @@ if build_docs
         'qemu-img.1': (have_tools ? 'man1' : ''),
         'qemu-nbd.8': (have_tools ? 'man8' : ''),
         'qemu-pr-helper.8': (have_tools ? 'man8' : ''),
+        'qemu-storage-daemon.1': (have_tools ? 'man1' : ''),
         'qemu-trace-stap.1': (config_host.has_key('CONFIG_TRACE_SYSTEMTAP') ? 'man1' : ''),
         'virtfs-proxy-helper.1': (have_virtfs_proxy_helper ? 'man1' : ''),
         'virtiofsd.1': (have_virtiofsd ? 'man1' : ''),
-- 
2.20.1

When we first converted our documentation to Sphinx, we split it into
multiple manuals (system, interop, tools, etc), which are all built
separately.  The primary driver for this was wanting to be able to
avoid shipping the 'devel' manual to end-users.  However, this is
working against the grain of the way Sphinx wants to be used and
causes some annoyances:
 * Cross-references between documents become much harder or
   possibly impossible
 * There is no single index to the whole documentation
 * Within one manual there's no links or table-of-contents info
   that lets you easily navigate to the others
 * The devel manual doesn't get published on the QEMU website
   (it would be nice to able to refer to it there)

Merely hiding our developer documentation from end users seems like
it's not enough benefit for these costs.  Combine all the
documentation into a single manual (the same way that the readthedocs
site builds it) and install the whole thing.  The previous manual
divisions remain as the new top level sections in the manual.

* The per-manual conf.py files are no longer needed
 * The man_pages[] specifications previously in each per-manual
   conf.py move to the top level conf.py
 * docs/meson.build logic is simplified as we now only need to run
   Sphinx once for the HTML and then once for the manpages5B
 * The old index.html.in that produced the top-level page with
   links to each manual is no longer needed

Unfortunately this means that we now have to build the HTML
documentation into docs/manual in the build tree rather than directly
into docs/; otherwise it is too awkward to ensure we install only the
built manual and not also the dependency info, stamp file, etc.  The
manual still ends up in the same place in the final installed
directory, but anybody who was consulting documentation from within
the build tree will have to adjust where they're looking.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-id: 20210108161416.21129-3-peter.maydell@linaro.org
---
 docs/conf.py         | 46 ++++++++++++++++++++++++++++++-
 docs/devel/conf.py   | 15 -----------
 docs/index.html.in   | 17 ------------
 docs/interop/conf.py | 28 -------------------
 docs/meson.build     | 64 +++++++++++++++++---------------------------
 docs/specs/conf.py   | 16 -----------
 docs/system/conf.py  | 28 -------------------
 docs/tools/conf.py   | 37 -------------------------
 docs/user/conf.py    | 15 -----------
 9 files changed, 70 insertions(+), 196 deletions(-)
 delete mode 100644 docs/devel/conf.py
 delete mode 100644 docs/index.html.in
 delete mode 100644 docs/interop/conf.py
 delete mode 100644 docs/specs/conf.py
 delete mode 100644 docs/system/conf.py
 delete mode 100644 docs/tools/conf.py
 delete mode 100644 docs/user/conf.py

diff --git a/docs/conf.py b/docs/conf.py
index XXXXXXX..XXXXXXX 100644
--- a/docs/conf.py
+++ b/docs/conf.py
@@ -XXX,XX +XXX,XX @@ latex_documents = [
 
 # -- Options for manual page output ---------------------------------------
 # Individual manual/conf.py can override this to create man pages
-man_pages = []
+man_pages = [
+    ('interop/qemu-ga', 'qemu-ga',
+     'QEMU Guest Agent',
+     ['Michael Roth <mdroth@linux.vnet.ibm.com>'], 8),
+    ('interop/qemu-ga-ref', 'qemu-ga-ref',
+     'QEMU Guest Agent Protocol Reference',
+     [], 7),
+    ('interop/qemu-qmp-ref', 'qemu-qmp-ref',
+     'QEMU QMP Reference Manual',
+     [], 7),
+    ('interop/qemu-storage-daemon-qmp-ref', 'qemu-storage-daemon-qmp-ref',
+     'QEMU Storage Daemon QMP Reference Manual',
+     [], 7),
+    ('system/qemu-manpage', 'qemu',
+     'QEMU User Documentation',
+     ['Fabrice Bellard'], 1),
+    ('system/qemu-block-drivers', 'qemu-block-drivers',
+     'QEMU block drivers reference',
+     ['Fabrice Bellard and the QEMU Project developers'], 7),
+    ('system/qemu-cpu-models', 'qemu-cpu-models',
+     'QEMU CPU Models',
+     ['The QEMU Project developers'], 7),
+    ('tools/qemu-img', 'qemu-img',
+     'QEMU disk image utility',
+     ['Fabrice Bellard'], 1),
+    ('tools/qemu-nbd', 'qemu-nbd',
+     'QEMU Disk Network Block Device Server',
+     ['Anthony Liguori <anthony@codemonkey.ws>'], 8),
+    ('tools/qemu-pr-helper', 'qemu-pr-helper',
+     'QEMU persistent reservation helper',
+     [], 8),
+    ('tools/qemu-storage-daemon', 'qemu-storage-daemon',
+     'QEMU storage daemon',
+     [], 1),
+    ('tools/qemu-trace-stap', 'qemu-trace-stap',
+     'QEMU SystemTap trace tool',
+     [], 1),
+    ('tools/virtfs-proxy-helper', 'virtfs-proxy-helper',
+     'QEMU 9p virtfs proxy filesystem helper',
+     ['M. Mohan Kumar'], 1),
+    ('tools/virtiofsd', 'virtiofsd',
+     'QEMU virtio-fs shared file system daemon',
+     ['Stefan Hajnoczi <stefanha@redhat.com>',
+      'Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>'], 1),
+]
 
 # -- Options for Texinfo output -------------------------------------------
 
diff --git a/docs/devel/conf.py b/docs/devel/conf.py
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/docs/devel/conf.py
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-# -*- coding: utf-8 -*-
-#
-# QEMU documentation build configuration file for the 'devel' manual.
-#
-# This includes the top level conf file and then makes any necessary tweaks.
-import sys
-import os
-
-qemu_docdir = os.path.abspath("..")
-parent_config = os.path.join(qemu_docdir, "conf.py")
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
-
-# This slightly misuses the 'description', but is the best way to get
-# the manual title to appear in the sidebar.
-html_theme_options['description'] = u'Developer''s Guide'
diff --git a/docs/index.html.in b/docs/index.html.in
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/docs/index.html.in
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-<!DOCTYPE html>
-<html lang="en">
-    <head>
-        <meta charset="UTF-8">
-        <title>QEMU @VERSION@ Documentation</title>
-    </head>
-    <body>
-        <h1>QEMU @VERSION@ Documentation</h1>
-        <ul>
-            <li><a href="system/index.html">System Emulation User's Guide</a></li>
-            <li><a href="user/index.html">User Mode Emulation User's Guide</a></li>
-            <li><a href="tools/index.html">Tools Guide</a></li>
-            <li><a href="interop/index.html">System Emulation Management and Interoperability Guide</a></li>
-            <li><a href="specs/index.html">System Emulation Guest Hardware Specifications</a></li>
-        </ul>
-    </body>
-</html>
diff --git a/docs/interop/conf.py b/docs/interop/conf.py
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/docs/interop/conf.py
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-# -*- coding: utf-8 -*-
-#
-# QEMU documentation build configuration file for the 'interop' manual.
-#
-# This includes the top level conf file and then makes any necessary tweaks.
-import sys
-import os
-
-qemu_docdir = os.path.abspath("..")
-parent_config = os.path.join(qemu_docdir, "conf.py")
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
-
-# This slightly misuses the 'description', but is the best way to get
-# the manual title to appear in the sidebar.
-html_theme_options['description'] = u'System Emulation Management and Interoperability Guide'
-
-# One entry per manual page. List of tuples
-# (source start file, name, description, authors, manual section).
-man_pages = [
-    ('qemu-ga', 'qemu-ga', u'QEMU Guest Agent',
-     ['Michael Roth <mdroth@linux.vnet.ibm.com>'], 8),
-    ('qemu-ga-ref', 'qemu-ga-ref', 'QEMU Guest Agent Protocol Reference',
-     [], 7),
-    ('qemu-qmp-ref', 'qemu-qmp-ref', 'QEMU QMP Reference Manual',
-     [], 7),
-    ('qemu-storage-daemon-qmp-ref', 'qemu-storage-daemon-qmp-ref',
-     'QEMU Storage Daemon QMP Reference Manual', [], 7),
-]
diff --git a/docs/meson.build b/docs/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/docs/meson.build
+++ b/docs/meson.build
@@ -XXX,XX +XXX,XX @@ if build_docs
                           meson.source_root() / 'docs/sphinx/qmp_lexer.py',
                           qapi_gen_depends ]
 
-  configure_file(output: 'index.html',
-                 input: files('index.html.in'),
-                 configuration: {'VERSION': meson.project_version()},
-                 install_dir: qemu_docdir)
-  manuals = [ 'devel', 'interop', 'tools', 'specs', 'system', 'user' ]
   man_pages = {
-    'interop' : {
         'qemu-ga.8': (have_tools ? 'man8' : ''),
         'qemu-ga-ref.7': 'man7',
         'qemu-qmp-ref.7': 'man7',
         'qemu-storage-daemon-qmp-ref.7': (have_tools ? 'man7' : ''),
-    },
-    'tools': {
         'qemu-img.1': (have_tools ? 'man1' : ''),
         'qemu-nbd.8': (have_tools ? 'man8' : ''),
         'qemu-pr-helper.8': (have_tools ? 'man8' : ''),
@@ -XXX,XX +XXX,XX @@ if build_docs
         'qemu-trace-stap.1': (config_host.has_key('CONFIG_TRACE_SYSTEMTAP') ? 'man1' : ''),
         'virtfs-proxy-helper.1': (have_virtfs_proxy_helper ? 'man1' : ''),
         'virtiofsd.1': (have_virtiofsd ? 'man1' : ''),
-    },
-    'system': {
         'qemu.1': 'man1',
         'qemu-block-drivers.7': 'man7',
         'qemu-cpu-models.7': 'man7'
-    },
   }
 
   sphinxdocs = []
   sphinxmans = []
-  foreach manual : manuals
-    private_dir = meson.current_build_dir() / (manual + '.p')
-    output_dir = meson.current_build_dir() / manual
-    input_dir = meson.current_source_dir() / manual
 
-    this_manual = custom_target(manual + ' manual',
+  private_dir = meson.current_build_dir() / 'manual.p'
+  output_dir = meson.current_build_dir() / 'manual'
+  input_dir = meson.current_source_dir()
+
+  this_manual = custom_target('QEMU manual',
                 build_by_default: build_docs,
-                output: [manual + '.stamp'],
-                input: [files('conf.py'), files(manual / 'conf.py')],
-                depfile: manual + '.d',
+                output: 'docs.stamp',
+                input: files('conf.py'),
+                depfile: 'docs.d',
                 depend_files: sphinx_extn_depends,
                 command: [SPHINX_ARGS, '-Ddepfile=@DEPFILE@',
                           '-Ddepfile_stamp=@OUTPUT0@',
                           '-b', 'html', '-d', private_dir,
                           input_dir, output_dir])
-    sphinxdocs += this_manual
-    if build_docs and manual != 'devel'
-      install_subdir(output_dir, install_dir: qemu_docdir)
-    endif
+  sphinxdocs += this_manual
+  install_subdir(output_dir, install_dir: qemu_docdir, strip_directory: true)
 
-    these_man_pages = []
-    install_dirs = []
-    foreach page, section : man_pages.get(manual, {})
-      these_man_pages += page
-      install_dirs += section == '' ? false : get_option('mandir') / section
-    endforeach
-    if these_man_pages.length() > 0
-      sphinxmans += custom_target(manual + ' man pages',
-                         build_by_default: build_docs,
-                         output: these_man_pages,
-                         input: this_manual,
-                         install: build_docs,
-                         install_dir: install_dirs,
-                         command: [SPHINX_ARGS, '-b', 'man', '-d', private_dir,
-                                   input_dir, meson.current_build_dir()])
-    endif
+  these_man_pages = []
+  install_dirs = []
+  foreach page, section : man_pages
+    these_man_pages += page
+    install_dirs += section == '' ? false : get_option('mandir') / section
   endforeach
+
+  sphinxmans += custom_target('QEMU man pages',
+                              build_by_default: build_docs,
+                              output: these_man_pages,
+                              input: this_manual,
+                              install: build_docs,
+                              install_dir: install_dirs,
+                              command: [SPHINX_ARGS, '-b', 'man', '-d', private_dir,
+                                        input_dir, meson.current_build_dir()])
+
   alias_target('sphinxdocs', sphinxdocs)
   alias_target('html', sphinxdocs)
   alias_target('man', sphinxmans)
diff --git a/docs/specs/conf.py b/docs/specs/conf.py
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/docs/specs/conf.py
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-# -*- coding: utf-8 -*-
-#
-# QEMU documentation build configuration file for the 'specs' manual.
-#
-# This includes the top level conf file and then makes any necessary tweaks.
-import sys
-import os
-
-qemu_docdir = os.path.abspath("..")
-parent_config = os.path.join(qemu_docdir, "conf.py")
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
-
-# This slightly misuses the 'description', but is the best way to get
-# the manual title to appear in the sidebar.
-html_theme_options['description'] = \
-    u'System Emulation Guest Hardware Specifications'
diff --git a/docs/system/conf.py b/docs/system/conf.py
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/docs/system/conf.py
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-# -*- coding: utf-8 -*-
-#
-# QEMU documentation build configuration file for the 'system' manual.
-#
-# This includes the top level conf file and then makes any necessary tweaks.
-import sys
-import os
-
-qemu_docdir = os.path.abspath("..")
-parent_config = os.path.join(qemu_docdir, "conf.py")
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
-
-# This slightly misuses the 'description', but is the best way to get
-# the manual title to appear in the sidebar.
-html_theme_options['description'] = u'System Emulation User''s Guide'
-
-# One entry per manual page. List of tuples
-# (source start file, name, description, authors, manual section).
-man_pages = [
-    ('qemu-manpage', 'qemu', u'QEMU User Documentation',
-     ['Fabrice Bellard'], 1),
-    ('qemu-block-drivers', 'qemu-block-drivers',
-     u'QEMU block drivers reference',
-     ['Fabrice Bellard and the QEMU Project developers'], 7),
-    ('qemu-cpu-models', 'qemu-cpu-models',
-     u'QEMU CPU Models',
-     ['The QEMU Project developers'], 7)
-]
diff --git a/docs/tools/conf.py b/docs/tools/conf.py
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/docs/tools/conf.py
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-# -*- coding: utf-8 -*-
-#
-# QEMU documentation build configuration file for the 'tools' manual.
-#
-# This includes the top level conf file and then makes any necessary tweaks.
-import sys
-import os
-
-qemu_docdir = os.path.abspath("..")
-parent_config = os.path.join(qemu_docdir, "conf.py")
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
-
-# This slightly misuses the 'description', but is the best way to get
-# the manual title to appear in the sidebar.
-html_theme_options['description'] = \
-    u'Tools Guide'
-
-# One entry per manual page. List of tuples
-# (source start file, name, description, authors, manual section).
-man_pages = [
-    ('qemu-img', 'qemu-img', u'QEMU disk image utility',
-     ['Fabrice Bellard'], 1),
-    ('qemu-storage-daemon', 'qemu-storage-daemon', u'QEMU storage daemon',
-     [], 1),
-    ('qemu-nbd', 'qemu-nbd', u'QEMU Disk Network Block Device Server',
-     ['Anthony Liguori <anthony@codemonkey.ws>'], 8),
-    ('qemu-pr-helper', 'qemu-pr-helper', 'QEMU persistent reservation helper',
-     [], 8),
-    ('qemu-trace-stap', 'qemu-trace-stap', u'QEMU SystemTap trace tool',
-     [], 1),
-    ('virtfs-proxy-helper', 'virtfs-proxy-helper',
-     u'QEMU 9p virtfs proxy filesystem helper',
-     ['M. Mohan Kumar'], 1),
-    ('virtiofsd', 'virtiofsd', u'QEMU virtio-fs shared file system daemon',
-     ['Stefan Hajnoczi <stefanha@redhat.com>',
-      'Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>'], 1),
-]
diff --git a/docs/user/conf.py b/docs/user/conf.py
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/docs/user/conf.py
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-# -*- coding: utf-8 -*-
-#
-# QEMU documentation build configuration file for the 'user' manual.
-#
-# This includes the top level conf file and then makes any necessary tweaks.
-import sys
-import os
-
-qemu_docdir = os.path.abspath("..")
-parent_config = os.path.join(qemu_docdir, "conf.py")
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
-
-# This slightly misuses the 'description', but is the best way to get
-# the manual title to appear in the sidebar.
-html_theme_options['description'] = u'User Mode Emulation User''s Guide'
-- 
2.20.1

In commit cd8be50e58f63413c0 we converted the A32 coprocessor
insns to decodetree. This accidentally broke XScale/iWMMXt insns,
because it moved the handling of "cp insns which are handled
by looking up the cp register in the hashtable" from after the
call to the legacy disas_xscale_insn() decode to before it,
with the result that all XScale/iWMMXt insns now UNDEF.

Update valid_cp() so that it knows that on XScale cp 0 and 1
are not standard coprocessor instructions; this will cause
the decodetree trans_ functions to ignore them, so that
execution will correctly get through to the legacy decode again.

Cc: qemu-stable@nongnu.org
Reported-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20210108195157.32067-1-peter.maydell@linaro.org
---
 target/arm/translate.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static bool valid_cp(DisasContext *s, int cp)
      * only cp14 and cp15 are valid, and other values aren't considered
      * to be in the coprocessor-instruction space at all. v8M still
      * permits coprocessors 0..7.
+     * For XScale, we must not decode the XScale cp0, cp1 space as
+     * a standard coprocessor insn, because we want to fall through to
+     * the legacy disas_xscale_insn() decoder after decodetree is done.
      */
+    if (arm_dc_feature(s, ARM_FEATURE_XSCALE) && (cp == 0 || cp == 1)) {
+        return false;
+    }
+
     if (arm_dc_feature(s, ARM_FEATURE_V8) &&
         !arm_dc_feature(s, ARM_FEATURE_M)) {
         return cp >= 14;
-- 
2.20.1

The lan9118 code mostly uses symbolic constants for register offsets;
the exceptions are those which the datasheet doesn't give an official
symbolic name to.

Add some names for the registers which don't already have them, based
on the longer names they are given in the memory map.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210108180401.2263-3-peter.maydell@linaro.org
---
 hw/net/lan9118.c | 24 ++++++++++++++++++------
 1 file changed, 18 insertions(+), 6 deletions(-)

diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/net/lan9118.c
+++ b/hw/net/lan9118.c
@@ -XXX,XX +XXX,XX @@ do { hw_error("lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
 do { fprintf(stderr, "lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
 #endif
 
+/* The tx and rx fifo ports are a range of aliased 32-bit registers */
+#define RX_DATA_FIFO_PORT_FIRST 0x00
+#define RX_DATA_FIFO_PORT_LAST 0x1f
+#define TX_DATA_FIFO_PORT_FIRST 0x20
+#define TX_DATA_FIFO_PORT_LAST 0x3f
+
+#define RX_STATUS_FIFO_PORT 0x40
+#define RX_STATUS_FIFO_PEEK 0x44
+#define TX_STATUS_FIFO_PORT 0x48
+#define TX_STATUS_FIFO_PEEK 0x4c
+
 #define CSR_ID_REV      0x50
 #define CSR_IRQ_CFG     0x54
 #define CSR_INT_STS     0x58
@@ -XXX,XX +XXX,XX @@ static void lan9118_writel(void *opaque, hwaddr offset,
     offset &= 0xff;
 
     //DPRINTF("Write reg 0x%02x = 0x%08x\n", (int)offset, val);
-    if (offset >= 0x20 && offset < 0x40) {
+    if (offset >= TX_DATA_FIFO_PORT_FIRST &&
+        offset <= TX_DATA_FIFO_PORT_LAST) {
         /* TX FIFO */
         tx_fifo_push(s, val);
         return;
@@ -XXX,XX +XXX,XX @@ static uint64_t lan9118_readl(void *opaque, hwaddr offset,
     lan9118_state *s = (lan9118_state *)opaque;
 
     //DPRINTF("Read reg 0x%02x\n", (int)offset);
-    if (offset < 0x20) {
+    if (offset <= RX_DATA_FIFO_PORT_LAST) {
         /* RX FIFO */
         return rx_fifo_pop(s);
     }
     switch (offset) {
-    case 0x40:
+    case RX_STATUS_FIFO_PORT:
         return rx_status_fifo_pop(s);
-    case 0x44:
+    case RX_STATUS_FIFO_PEEK:
         return s->rx_status_fifo[s->rx_status_fifo_head];
-    case 0x48:
+    case TX_STATUS_FIFO_PORT:
         return tx_status_fifo_pop(s);
-    case 0x4c:
+    case TX_STATUS_FIFO_PEEK:
         return s->tx_status_fifo[s->tx_status_fifo_head];
     case CSR_ID_REV:
         return 0x01180001;
-- 
2.20.1

From: Hao Wu <wuhaotsh@google.com>

This patch allows NPCM7XX CLK module to compute clocks that are used by
other NPCM7XX modules.

Add a new struct NPCM7xxClockConverterState which represents a
single converter.  Each clock converter in CLK module represents one
converter in NPCM7XX CLK Module(PLL, SEL or Divider). Each converter
takes one or more input clocks and converts them into one output clock.
They form a clock hierarchy in the CLK module and are responsible for
outputing clocks for various other modules in an NPCM7XX SoC.

Each converter has a function pointer called "convert" which represents
the unique logic for that converter.

The clock contains two initialization information: ConverterInitInfo and
ConverterConnectionInfo. They represent the vertices and edges in the
clock diagram respectively.

Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210108190945.949196-2-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/misc/npcm7xx_clk.h | 140 +++++-
 hw/misc/npcm7xx_clk.c         | 805 +++++++++++++++++++++++++++++++++-
 2 files changed, 932 insertions(+), 13 deletions(-)

diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/misc/npcm7xx_clk.h
+++ b/include/hw/misc/npcm7xx_clk.h
@@ -XXX,XX +XXX,XX @@
 #define NPCM7XX_CLK_H
 
 #include "exec/memory.h"
+#include "hw/clock.h"
 #include "hw/sysbus.h"
 
 /*
@@ -XXX,XX +XXX,XX @@
 
 #define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in"
 
-typedef struct NPCM7xxCLKState {
+/* Maximum amount of clock inputs in a SEL module. */
+#define NPCM7XX_CLK_SEL_MAX_INPUT 5
+
+/* PLLs in CLK module. */
+typedef enum NPCM7xxClockPLL {
+    NPCM7XX_CLOCK_PLL0,
+    NPCM7XX_CLOCK_PLL1,
+    NPCM7XX_CLOCK_PLL2,
+    NPCM7XX_CLOCK_PLLG,
+    NPCM7XX_CLOCK_NR_PLLS,
+} NPCM7xxClockPLL;
+
+/* SEL/MUX in CLK module. */
+typedef enum NPCM7xxClockSEL {
+    NPCM7XX_CLOCK_PIXCKSEL,
+    NPCM7XX_CLOCK_MCCKSEL,
+    NPCM7XX_CLOCK_CPUCKSEL,
+    NPCM7XX_CLOCK_CLKOUTSEL,
+    NPCM7XX_CLOCK_UARTCKSEL,
+    NPCM7XX_CLOCK_TIMCKSEL,
+    NPCM7XX_CLOCK_SDCKSEL,
+    NPCM7XX_CLOCK_GFXMSEL,
+    NPCM7XX_CLOCK_SUCKSEL,
+    NPCM7XX_CLOCK_NR_SELS,
+} NPCM7xxClockSEL;
+
+/* Dividers in CLK module. */
+typedef enum NPCM7xxClockDivider {
+    NPCM7XX_CLOCK_PLL1D2, /* PLL1/2 */
+    NPCM7XX_CLOCK_PLL2D2, /* PLL2/2 */
+    NPCM7XX_CLOCK_MC_DIVIDER,
+    NPCM7XX_CLOCK_AXI_DIVIDER,
+    NPCM7XX_CLOCK_AHB_DIVIDER,
+    NPCM7XX_CLOCK_AHB3_DIVIDER,
+    NPCM7XX_CLOCK_SPI0_DIVIDER,
+    NPCM7XX_CLOCK_SPIX_DIVIDER,
+    NPCM7XX_CLOCK_APB1_DIVIDER,
+    NPCM7XX_CLOCK_APB2_DIVIDER,
+    NPCM7XX_CLOCK_APB3_DIVIDER,
+    NPCM7XX_CLOCK_APB4_DIVIDER,
+    NPCM7XX_CLOCK_APB5_DIVIDER,
+    NPCM7XX_CLOCK_CLKOUT_DIVIDER,
+    NPCM7XX_CLOCK_UART_DIVIDER,
+    NPCM7XX_CLOCK_TIMER_DIVIDER,
+    NPCM7XX_CLOCK_ADC_DIVIDER,
+    NPCM7XX_CLOCK_MMC_DIVIDER,
+    NPCM7XX_CLOCK_SDHC_DIVIDER,
+    NPCM7XX_CLOCK_GFXM_DIVIDER, /* divide by 3 */
+    NPCM7XX_CLOCK_UTMI_DIVIDER,
+    NPCM7XX_CLOCK_NR_DIVIDERS,
+} NPCM7xxClockConverter;
+
+typedef struct NPCM7xxCLKState NPCM7xxCLKState;
+
+/**
+ * struct NPCM7xxClockPLLState - A PLL module in CLK module.
+ * @name: The name of the module.
+ * @clk: The CLK module that owns this module.
+ * @clock_in: The input clock of this module.
+ * @clock_out: The output clock of this module.
+ * @reg: The control registers for this PLL module.
+ */
+typedef struct NPCM7xxClockPLLState {
+    DeviceState parent;
+
+    const char *name;
+    NPCM7xxCLKState *clk;
+    Clock *clock_in;
+    Clock *clock_out;
+
+    int reg;
+} NPCM7xxClockPLLState;
+
+/**
+ * struct NPCM7xxClockSELState - A SEL module in CLK module.
+ * @name: The name of the module.
+ * @clk: The CLK module that owns this module.
+ * @input_size: The size of inputs of this module.
+ * @clock_in: The input clocks of this module.
+ * @clock_out: The output clocks of this module.
+ * @offset: The offset of this module in the control register.
+ * @len: The length of this module in the control register.
+ */
+typedef struct NPCM7xxClockSELState {
+    DeviceState parent;
+
+    const char *name;
+    NPCM7xxCLKState *clk;
+    uint8_t input_size;
+    Clock *clock_in[NPCM7XX_CLK_SEL_MAX_INPUT];
+    Clock *clock_out;
+
+    int offset;
+    int len;
+} NPCM7xxClockSELState;
+
+/**
+ * struct NPCM7xxClockDividerState - A Divider module in CLK module.
+ * @name: The name of the module.
+ * @clk: The CLK module that owns this module.
+ * @clock_in: The input clock of this module.
+ * @clock_out: The output clock of this module.
+ * @divide: The function the divider uses to divide the input.
+ * @reg: The index of the control register that contains the divisor.
+ * @offset: The offset of the divisor in the control register.
+ * @len: The length of the divisor in the control register.
+ * @divisor: The divisor for a constant divisor
+ */
+typedef struct NPCM7xxClockDividerState {
+    DeviceState parent;
+
+    const char *name;
+    NPCM7xxCLKState *clk;
+    Clock *clock_in;
+    Clock *clock_out;
+
+    uint32_t (*divide)(struct NPCM7xxClockDividerState *s);
+    union {
+        struct {
+            int reg;
+            int offset;
+            int len;
+        };
+        int divisor;
+    };
+} NPCM7xxClockDividerState;
+
+struct NPCM7xxCLKState {
     SysBusDevice parent;
 
     MemoryRegion iomem;
 
+    /* Clock converters */
+    NPCM7xxClockPLLState plls[NPCM7XX_CLOCK_NR_PLLS];
+    NPCM7xxClockSELState sels[NPCM7XX_CLOCK_NR_SELS];
+    NPCM7xxClockDividerState dividers[NPCM7XX_CLOCK_NR_DIVIDERS];
+
     uint32_t regs[NPCM7XX_CLK_NR_REGS];
 
     /* Time reference for SECCNT and CNTR25M, initialized by power on reset */
     int64_t ref_ns;
-} NPCM7xxCLKState;
+
+    /* The incoming reference clock. */
+    Clock *clkref;
+};
 
 #define TYPE_NPCM7XX_CLK "npcm7xx-clk"
 #define NPCM7XX_CLK(obj) OBJECT_CHECK(NPCM7xxCLKState, (obj), TYPE_NPCM7XX_CLK)
diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/npcm7xx_clk.c
+++ b/hw/misc/npcm7xx_clk.c
@@ -XXX,XX +XXX,XX @@
 
 #include "hw/misc/npcm7xx_clk.h"
 #include "hw/timer/npcm7xx_timer.h"
+#include "hw/qdev-clock.h"
 #include "migration/vmstate.h"
 #include "qemu/error-report.h"
 #include "qemu/log.h"
@@ -XXX,XX +XXX,XX @@
 #include "trace.h"
 #include "sysemu/watchdog.h"
 
+/*
+ * The reference clock hz, and the SECCNT and CNTR25M registers in this module,
+ * is always 25 MHz.
+ */
+#define NPCM7XX_CLOCK_REF_HZ            (25000000)
+
+/* Register Field Definitions */
+#define NPCM7XX_CLK_WDRCR_CA9C  BIT(0) /* Cortex A9 Cores */
+
 #define PLLCON_LOKI     BIT(31)
 #define PLLCON_LOKS     BIT(30)
 #define PLLCON_PWDEN    BIT(12)
+#define PLLCON_FBDV(con) extract32((con), 16, 12)
+#define PLLCON_OTDV2(con) extract32((con), 13, 3)
+#define PLLCON_OTDV1(con) extract32((con), 8, 3)
+#define PLLCON_INDV(con) extract32((con), 0, 6)
 
 enum NPCM7xxCLKRegisters {
     NPCM7XX_CLK_CLKEN1,
@@ -XXX,XX +XXX,XX @@ static const uint32_t cold_reset_values[NPCM7XX_CLK_NR_REGS] = {
     [NPCM7XX_CLK_AHBCKFI]       = 0x000000c8,
 };
 
-/* Register Field Definitions */
-#define NPCM7XX_CLK_WDRCR_CA9C  BIT(0) /* Cortex A9 Cores */
-
 /* The number of watchdogs that can trigger a reset. */
 #define NPCM7XX_NR_WATCHDOGS    (3)
 
+/* Clock converter functions */
+
+#define TYPE_NPCM7XX_CLOCK_PLL "npcm7xx-clock-pll"
+#define NPCM7XX_CLOCK_PLL(obj) OBJECT_CHECK(NPCM7xxClockPLLState, \
+        (obj), TYPE_NPCM7XX_CLOCK_PLL)
+#define TYPE_NPCM7XX_CLOCK_SEL "npcm7xx-clock-sel"
+#define NPCM7XX_CLOCK_SEL(obj) OBJECT_CHECK(NPCM7xxClockSELState, \
+        (obj), TYPE_NPCM7XX_CLOCK_SEL)
+#define TYPE_NPCM7XX_CLOCK_DIVIDER "npcm7xx-clock-divider"
+#define NPCM7XX_CLOCK_DIVIDER(obj) OBJECT_CHECK(NPCM7xxClockDividerState, \
+        (obj), TYPE_NPCM7XX_CLOCK_DIVIDER)
+
+static void npcm7xx_clk_update_pll(void *opaque)
+{
+    NPCM7xxClockPLLState *s = opaque;
+    uint32_t con = s->clk->regs[s->reg];
+    uint64_t freq;
+
+    /* The PLL is grounded if it is not locked yet. */
+    if (con & PLLCON_LOKI) {
+        freq = clock_get_hz(s->clock_in);
+        freq *= PLLCON_FBDV(con);
+        freq /= PLLCON_INDV(con) * PLLCON_OTDV1(con) * PLLCON_OTDV2(con);
+    } else {
+        freq = 0;
+    }
+
+    clock_update_hz(s->clock_out, freq);
+}
+
+static void npcm7xx_clk_update_sel(void *opaque)
+{
+    NPCM7xxClockSELState *s = opaque;
+    uint32_t index = extract32(s->clk->regs[NPCM7XX_CLK_CLKSEL], s->offset,
+            s->len);
+
+    if (index >= s->input_size) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: SEL index: %u out of range\n",
+                      __func__, index);
+        index = 0;
+    }
+    clock_update_hz(s->clock_out, clock_get_hz(s->clock_in[index]));
+}
+
+static void npcm7xx_clk_update_divider(void *opaque)
+{
+    NPCM7xxClockDividerState *s = opaque;
+    uint32_t freq;
+
+    freq = s->divide(s);
+    clock_update_hz(s->clock_out, freq);
+}
+
+static uint32_t divide_by_constant(NPCM7xxClockDividerState *s)
+{
+    return clock_get_hz(s->clock_in) / s->divisor;
+}
+
+static uint32_t divide_by_reg_divisor(NPCM7xxClockDividerState *s)
+{
+    return clock_get_hz(s->clock_in) /
+            (extract32(s->clk->regs[s->reg], s->offset, s->len) + 1);
+}
+
+static uint32_t divide_by_reg_divisor_times_2(NPCM7xxClockDividerState *s)
+{
+    return divide_by_reg_divisor(s) / 2;
+}
+
+static uint32_t shift_by_reg_divisor(NPCM7xxClockDividerState *s)
+{
+    return clock_get_hz(s->clock_in) >>
+        extract32(s->clk->regs[s->reg], s->offset, s->len);
+}
+
+static NPCM7xxClockPLL find_pll_by_reg(enum NPCM7xxCLKRegisters reg)
+{
+    switch (reg) {
+    case NPCM7XX_CLK_PLLCON0:
+        return NPCM7XX_CLOCK_PLL0;
+    case NPCM7XX_CLK_PLLCON1:
+        return NPCM7XX_CLOCK_PLL1;
+    case NPCM7XX_CLK_PLLCON2:
+        return NPCM7XX_CLOCK_PLL2;
+    case NPCM7XX_CLK_PLLCONG:
+        return NPCM7XX_CLOCK_PLLG;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static void npcm7xx_clk_update_all_plls(NPCM7xxCLKState *clk)
+{
+    int i;
+
+    for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
+        npcm7xx_clk_update_pll(&clk->plls[i]);
+    }
+}
+
+static void npcm7xx_clk_update_all_sels(NPCM7xxCLKState *clk)
+{
+    int i;
+
+    for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
+        npcm7xx_clk_update_sel(&clk->sels[i]);
+    }
+}
+
+static void npcm7xx_clk_update_all_dividers(NPCM7xxCLKState *clk)
+{
+    int i;
+
+    for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
+        npcm7xx_clk_update_divider(&clk->dividers[i]);
+    }
+}
+
+static void npcm7xx_clk_update_all_clocks(NPCM7xxCLKState *clk)
+{
+    clock_update_hz(clk->clkref, NPCM7XX_CLOCK_REF_HZ);
+    npcm7xx_clk_update_all_plls(clk);
+    npcm7xx_clk_update_all_sels(clk);
+    npcm7xx_clk_update_all_dividers(clk);
+}
+
+/* Types of clock sources. */
+typedef enum ClockSrcType {
+    CLKSRC_REF,
+    CLKSRC_PLL,
+    CLKSRC_SEL,
+    CLKSRC_DIV,
+} ClockSrcType;
+
+typedef struct PLLInitInfo {
+    const char *name;
+    ClockSrcType src_type;
+    int src_index;
+    int reg;
+    const char *public_name;
+} PLLInitInfo;
+
+typedef struct SELInitInfo {
+    const char *name;
+    uint8_t input_size;
+    ClockSrcType src_type[NPCM7XX_CLK_SEL_MAX_INPUT];
+    int src_index[NPCM7XX_CLK_SEL_MAX_INPUT];
+    int offset;
+    int len;
+    const char *public_name;
+} SELInitInfo;
+
+typedef struct DividerInitInfo {
+    const char *name;
+    ClockSrcType src_type;
+    int src_index;
+    uint32_t (*divide)(NPCM7xxClockDividerState *s);
+    int reg; /* not used when type == CONSTANT */
+    int offset; /* not used when type == CONSTANT */
+    int len; /* not used when type == CONSTANT */
+    int divisor; /* used only when type == CONSTANT */
+    const char *public_name;
+} DividerInitInfo;
+
+static const PLLInitInfo pll_init_info_list[] = {
+    [NPCM7XX_CLOCK_PLL0] = {
+        .name = "pll0",
+        .src_type = CLKSRC_REF,
+        .reg = NPCM7XX_CLK_PLLCON0,
+    },
+    [NPCM7XX_CLOCK_PLL1] = {
+        .name = "pll1",
+        .src_type = CLKSRC_REF,
+        .reg = NPCM7XX_CLK_PLLCON1,
+    },
+    [NPCM7XX_CLOCK_PLL2] = {
+        .name = "pll2",
+        .src_type = CLKSRC_REF,
+        .reg = NPCM7XX_CLK_PLLCON2,
+    },
+    [NPCM7XX_CLOCK_PLLG] = {
+        .name = "pllg",
+        .src_type = CLKSRC_REF,
+        .reg = NPCM7XX_CLK_PLLCONG,
+    },
+};
+
+static const SELInitInfo sel_init_info_list[] = {
+    [NPCM7XX_CLOCK_PIXCKSEL] = {
+        .name = "pixcksel",
+        .input_size = 2,
+        .src_type = {CLKSRC_PLL, CLKSRC_REF},
+        .src_index = {NPCM7XX_CLOCK_PLLG, 0},
+        .offset = 5,
+        .len = 1,
+        .public_name = "pixel-clock",
+    },
+    [NPCM7XX_CLOCK_MCCKSEL] = {
+        .name = "mccksel",
+        .input_size = 4,
+        .src_type = {CLKSRC_DIV, CLKSRC_REF, CLKSRC_REF,
+            /*MCBPCK, shouldn't be used in normal operation*/
+            CLKSRC_REF},
+        .src_index = {NPCM7XX_CLOCK_PLL1D2, 0, 0, 0},
+        .offset = 12,
+        .len = 2,
+        .public_name = "mc-phy-clock",
+    },
+    [NPCM7XX_CLOCK_CPUCKSEL] = {
+        .name = "cpucksel",
+        .input_size = 4,
+        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF,
+            /*SYSBPCK, shouldn't be used in normal operation*/
+            CLKSRC_REF},
+        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, 0},
+        .offset = 0,
+        .len = 2,
+        .public_name = "system-clock",
+    },
+    [NPCM7XX_CLOCK_CLKOUTSEL] = {
+        .name = "clkoutsel",
+        .input_size = 5,
+        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF,
+            CLKSRC_PLL, CLKSRC_DIV},
+        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
+            NPCM7XX_CLOCK_PLLG, NPCM7XX_CLOCK_PLL2D2},
+        .offset = 18,
+        .len = 3,
+        .public_name = "tock",
+    },
+    [NPCM7XX_CLOCK_UARTCKSEL] = {
+        .name = "uartcksel",
+        .input_size = 4,
+        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
+        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
+            NPCM7XX_CLOCK_PLL2D2},
+        .offset = 8,
+        .len = 2,
+    },
+    [NPCM7XX_CLOCK_TIMCKSEL] = {
+        .name = "timcksel",
+        .input_size = 4,
+        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
+        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
+            NPCM7XX_CLOCK_PLL2D2},
+        .offset = 14,
+        .len = 2,
+    },
+    [NPCM7XX_CLOCK_SDCKSEL] = {
+        .name = "sdcksel",
+        .input_size = 4,
+        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
+        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
+            NPCM7XX_CLOCK_PLL2D2},
+        .offset = 6,
+        .len = 2,
+    },
+    [NPCM7XX_CLOCK_GFXMSEL] = {
+        .name = "gfxmksel",
+        .input_size = 2,
+        .src_type = {CLKSRC_REF, CLKSRC_PLL},
+        .src_index = {0, NPCM7XX_CLOCK_PLL2},
+        .offset = 21,
+        .len = 1,
+    },
+    [NPCM7XX_CLOCK_SUCKSEL] = {
+        .name = "sucksel",
+        .input_size = 4,
+        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
+        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
+            NPCM7XX_CLOCK_PLL2D2},
+        .offset = 10,
+        .len = 2,
+    },
+};
+
+static const DividerInitInfo divider_init_info_list[] = {
+    [NPCM7XX_CLOCK_PLL1D2] = {
+        .name = "pll1d2",
+        .src_type = CLKSRC_PLL,
+        .src_index = NPCM7XX_CLOCK_PLL1,
+        .divide = divide_by_constant,
+        .divisor = 2,
+    },
+    [NPCM7XX_CLOCK_PLL2D2] = {
+        .name = "pll2d2",
+        .src_type = CLKSRC_PLL,
+        .src_index = NPCM7XX_CLOCK_PLL2,
+        .divide = divide_by_constant,
+        .divisor = 2,
+    },
+    [NPCM7XX_CLOCK_MC_DIVIDER] = {
+        .name = "mc-divider",
+        .src_type = CLKSRC_SEL,
+        .src_index = NPCM7XX_CLOCK_MCCKSEL,
+        .divide = divide_by_constant,
+        .divisor = 2,
+        .public_name = "mc-clock"
+    },
+    [NPCM7XX_CLOCK_AXI_DIVIDER] = {
+        .name = "axi-divider",
+        .src_type = CLKSRC_SEL,
+        .src_index = NPCM7XX_CLOCK_CPUCKSEL,
+        .divide = shift_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV1,
+        .offset = 0,
+        .len = 1,
+        .public_name = "clk2"
+    },
+    [NPCM7XX_CLOCK_AHB_DIVIDER] = {
+        .name = "ahb-divider",
+        .src_type = CLKSRC_DIV,
+        .src_index = NPCM7XX_CLOCK_AXI_DIVIDER,
+        .divide = divide_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV1,
+        .offset = 26,
+        .len = 2,
+        .public_name = "clk4"
+    },
+    [NPCM7XX_CLOCK_AHB3_DIVIDER] = {
+        .name = "ahb3-divider",
+        .src_type = CLKSRC_DIV,
+        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
+        .divide = divide_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV1,
+        .offset = 6,
+        .len = 5,
+        .public_name = "ahb3-spi3-clock"
+    },
+    [NPCM7XX_CLOCK_SPI0_DIVIDER] = {
+        .name = "spi0-divider",
+        .src_type = CLKSRC_DIV,
+        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
+        .divide = divide_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV3,
+        .offset = 6,
+        .len = 5,
+        .public_name = "spi0-clock",
+    },
+    [NPCM7XX_CLOCK_SPIX_DIVIDER] = {
+        .name = "spix-divider",
+        .src_type = CLKSRC_DIV,
+        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
+        .divide = divide_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV3,
+        .offset = 1,
+        .len = 5,
+        .public_name = "spix-clock",
+    },
+    [NPCM7XX_CLOCK_APB1_DIVIDER] = {
+        .name = "apb1-divider",
+        .src_type = CLKSRC_DIV,
+        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
+        .divide = shift_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV2,
+        .offset = 24,
+        .len = 2,
+        .public_name = "apb1-clock",
+    },
+    [NPCM7XX_CLOCK_APB2_DIVIDER] = {
+        .name = "apb2-divider",
+        .src_type = CLKSRC_DIV,
+        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
+        .divide = shift_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV2,
+        .offset = 26,
+        .len = 2,
+        .public_name = "apb2-clock",
+    },
+    [NPCM7XX_CLOCK_APB3_DIVIDER] = {
+        .name = "apb3-divider",
+        .src_type = CLKSRC_DIV,
+        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
+        .divide = shift_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV2,
+        .offset = 28,
+        .len = 2,
+        .public_name = "apb3-clock",
+    },
+    [NPCM7XX_CLOCK_APB4_DIVIDER] = {
+        .name = "apb4-divider",
+        .src_type = CLKSRC_DIV,
+        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
+        .divide = shift_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV2,
+        .offset = 30,
+        .len = 2,
+        .public_name = "apb4-clock",
+    },
+    [NPCM7XX_CLOCK_APB5_DIVIDER] = {
+        .name = "apb5-divider",
+        .src_type = CLKSRC_DIV,
+        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
+        .divide = shift_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV2,
+        .offset = 22,
+        .len = 2,
+        .public_name = "apb5-clock",
+    },
+    [NPCM7XX_CLOCK_CLKOUT_DIVIDER] = {
+        .name = "clkout-divider",
+        .src_type = CLKSRC_SEL,
+        .src_index = NPCM7XX_CLOCK_CLKOUTSEL,
+        .divide = divide_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV2,
+        .offset = 16,
+        .len = 5,
+        .public_name = "clkout",
+    },
+    [NPCM7XX_CLOCK_UART_DIVIDER] = {
+        .name = "uart-divider",
+        .src_type = CLKSRC_SEL,
+        .src_index = NPCM7XX_CLOCK_UARTCKSEL,
+        .divide = divide_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV1,
+        .offset = 16,
+        .len = 5,
+        .public_name = "uart-clock",
+    },
+    [NPCM7XX_CLOCK_TIMER_DIVIDER] = {
+        .name = "timer-divider",
+        .src_type = CLKSRC_SEL,
+        .src_index = NPCM7XX_CLOCK_TIMCKSEL,
+        .divide = divide_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV1,
+        .offset = 21,
+        .len = 5,
+        .public_name = "timer-clock",
+    },
+    [NPCM7XX_CLOCK_ADC_DIVIDER] = {
+        .name = "adc-divider",
+        .src_type = CLKSRC_DIV,
+        .src_index = NPCM7XX_CLOCK_TIMER_DIVIDER,
+        .divide = shift_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV1,
+        .offset = 28,
+        .len = 3,
+        .public_name = "adc-clock",
+    },
+    [NPCM7XX_CLOCK_MMC_DIVIDER] = {
+        .name = "mmc-divider",
+        .src_type = CLKSRC_SEL,
+        .src_index = NPCM7XX_CLOCK_SDCKSEL,
+        .divide = divide_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV1,
+        .offset = 11,
+        .len = 5,
+        .public_name = "mmc-clock",
+    },
+    [NPCM7XX_CLOCK_SDHC_DIVIDER] = {
+        .name = "sdhc-divider",
+        .src_type = CLKSRC_SEL,
+        .src_index = NPCM7XX_CLOCK_SDCKSEL,
+        .divide = divide_by_reg_divisor_times_2,
+        .reg = NPCM7XX_CLK_CLKDIV2,
+        .offset = 0,
+        .len = 4,
+        .public_name = "sdhc-clock",
+    },
+    [NPCM7XX_CLOCK_GFXM_DIVIDER] = {
+        .name = "gfxm-divider",
+        .src_type = CLKSRC_SEL,
+        .src_index = NPCM7XX_CLOCK_GFXMSEL,
+        .divide = divide_by_constant,
+        .divisor = 3,
+        .public_name = "gfxm-clock",
+    },
+    [NPCM7XX_CLOCK_UTMI_DIVIDER] = {
+        .name = "utmi-divider",
+        .src_type = CLKSRC_SEL,
+        .src_index = NPCM7XX_CLOCK_SUCKSEL,
+        .divide = divide_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV2,
+        .offset = 8,
+        .len = 5,
+        .public_name = "utmi-clock",
+    },
+};
+
+static void npcm7xx_clk_pll_init(Object *obj)
+{
+    NPCM7xxClockPLLState *pll = NPCM7XX_CLOCK_PLL(obj);
+
+    pll->clock_in = qdev_init_clock_in(DEVICE(pll), "clock-in",
+            npcm7xx_clk_update_pll, pll);
+    pll->clock_out = qdev_init_clock_out(DEVICE(pll), "clock-out");
+}
+
+static void npcm7xx_clk_sel_init(Object *obj)
+{
+    int i;
+    NPCM7xxClockSELState *sel = NPCM7XX_CLOCK_SEL(obj);
+
+    for (i = 0; i < NPCM7XX_CLK_SEL_MAX_INPUT; ++i) {
+        sel->clock_in[i] = qdev_init_clock_in(DEVICE(sel),
+                g_strdup_printf("clock-in[%d]", i),
+                npcm7xx_clk_update_sel, sel);
+    }
+    sel->clock_out = qdev_init_clock_out(DEVICE(sel), "clock-out");
+}
+static void npcm7xx_clk_divider_init(Object *obj)
+{
+    NPCM7xxClockDividerState *div = NPCM7XX_CLOCK_DIVIDER(obj);
+
+    div->clock_in = qdev_init_clock_in(DEVICE(div), "clock-in",
+            npcm7xx_clk_update_divider, div);
+    div->clock_out = qdev_init_clock_out(DEVICE(div), "clock-out");
+}
+
+static void npcm7xx_init_clock_pll(NPCM7xxClockPLLState *pll,
+        NPCM7xxCLKState *clk, const PLLInitInfo *init_info)
+{
+    pll->name = init_info->name;
+    pll->clk = clk;
+    pll->reg = init_info->reg;
+    if (init_info->public_name != NULL) {
+        qdev_alias_clock(DEVICE(pll), "clock-out", DEVICE(clk),
+                init_info->public_name);
+    }
+}
+
+static void npcm7xx_init_clock_sel(NPCM7xxClockSELState *sel,
+        NPCM7xxCLKState *clk, const SELInitInfo *init_info)
+{
+    int input_size = init_info->input_size;
+
+    sel->name = init_info->name;
+    sel->clk = clk;
+    sel->input_size = init_info->input_size;
+    g_assert(input_size <= NPCM7XX_CLK_SEL_MAX_INPUT);
+    sel->offset = init_info->offset;
+    sel->len = init_info->len;
+    if (init_info->public_name != NULL) {
+        qdev_alias_clock(DEVICE(sel), "clock-out", DEVICE(clk),
+                init_info->public_name);
+    }
+}
+
+static void npcm7xx_init_clock_divider(NPCM7xxClockDividerState *div,
+        NPCM7xxCLKState *clk, const DividerInitInfo *init_info)
+{
+    div->name = init_info->name;
+    div->clk = clk;
+
+    div->divide = init_info->divide;
+    if (div->divide == divide_by_constant) {
+        div->divisor = init_info->divisor;
+    } else {
+        div->reg = init_info->reg;
+        div->offset = init_info->offset;
+        div->len = init_info->len;
+    }
+    if (init_info->public_name != NULL) {
+        qdev_alias_clock(DEVICE(div), "clock-out", DEVICE(clk),
+                init_info->public_name);
+    }
+}
+
+static Clock *npcm7xx_get_clock(NPCM7xxCLKState *clk, ClockSrcType type,
+        int index)
+{
+    switch (type) {
+    case CLKSRC_REF:
+        return clk->clkref;
+    case CLKSRC_PLL:
+        return clk->plls[index].clock_out;
+    case CLKSRC_SEL:
+        return clk->sels[index].clock_out;
+    case CLKSRC_DIV:
+        return clk->dividers[index].clock_out;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static void npcm7xx_connect_clocks(NPCM7xxCLKState *clk)
+{
+    int i, j;
+    Clock *src;
+
+    for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
+        src = npcm7xx_get_clock(clk, pll_init_info_list[i].src_type,
+                pll_init_info_list[i].src_index);
+        clock_set_source(clk->plls[i].clock_in, src);
+    }
+    for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
+        for (j = 0; j < sel_init_info_list[i].input_size; ++j) {
+            src = npcm7xx_get_clock(clk, sel_init_info_list[i].src_type[j],
+                    sel_init_info_list[i].src_index[j]);
+            clock_set_source(clk->sels[i].clock_in[j], src);
+        }
+    }
+    for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
+        src = npcm7xx_get_clock(clk, divider_init_info_list[i].src_type,
+                divider_init_info_list[i].src_index);
+        clock_set_source(clk->dividers[i].clock_in, src);
+    }
+}
+
 static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size)
 {
     uint32_t reg = offset / sizeof(uint32_t);
@@ -XXX,XX +XXX,XX @@ static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size)
          *
          * The 4 LSBs are always zero: (1e9 / 640) << 4 = 25000000.
          */
-        value = (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_TIMER_REF_HZ;
+        value = (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_CLOCK_REF_HZ;
         break;
 
     default:
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_write(void *opaque, hwaddr offset,
                 value |= (value & PLLCON_LOKS);
             }
         }
+        /* Only update PLL when it is locked. */
+        if (value & PLLCON_LOKI) {
+            npcm7xx_clk_update_pll(&s->plls[find_pll_by_reg(reg)]);
+        }
+        break;
+
+    case NPCM7XX_CLK_CLKSEL:
+        npcm7xx_clk_update_all_sels(s);
+        break;
+
+    case NPCM7XX_CLK_CLKDIV1:
+    case NPCM7XX_CLK_CLKDIV2:
+    case NPCM7XX_CLK_CLKDIV3:
+        npcm7xx_clk_update_all_dividers(s);
         break;
 
     case NPCM7XX_CLK_CNTR25M:
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetType type)
     case RESET_TYPE_COLD:
         memcpy(s->regs, cold_reset_values, sizeof(cold_reset_values));
         s->ref_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+        npcm7xx_clk_update_all_clocks(s);
         return;
     }
 
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetType type)
                   __func__, type);
 }
 
+static void npcm7xx_clk_init_clock_hierarchy(NPCM7xxCLKState *s)
+{
+    int i;
+
+    s->clkref = qdev_init_clock_in(DEVICE(s), "clkref", NULL, NULL);
+
+    /* First pass: init all converter modules */
+    QEMU_BUILD_BUG_ON(ARRAY_SIZE(pll_init_info_list) != NPCM7XX_CLOCK_NR_PLLS);
+    QEMU_BUILD_BUG_ON(ARRAY_SIZE(sel_init_info_list) != NPCM7XX_CLOCK_NR_SELS);
+    QEMU_BUILD_BUG_ON(ARRAY_SIZE(divider_init_info_list)
+            != NPCM7XX_CLOCK_NR_DIVIDERS);
+    for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
+        object_initialize_child(OBJECT(s), pll_init_info_list[i].name,
+                &s->plls[i], TYPE_NPCM7XX_CLOCK_PLL);
+        npcm7xx_init_clock_pll(&s->plls[i], s,
+                &pll_init_info_list[i]);
+    }
+    for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
+        object_initialize_child(OBJECT(s), sel_init_info_list[i].name,
+                &s->sels[i], TYPE_NPCM7XX_CLOCK_SEL);
+        npcm7xx_init_clock_sel(&s->sels[i], s,
+                &sel_init_info_list[i]);
+    }
+    for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
+        object_initialize_child(OBJECT(s), divider_init_info_list[i].name,
+                &s->dividers[i], TYPE_NPCM7XX_CLOCK_DIVIDER);
+        npcm7xx_init_clock_divider(&s->dividers[i], s,
+                &divider_init_info_list[i]);
+    }
+
+    /* Second pass: connect converter modules */
+    npcm7xx_connect_clocks(s);
+
+    clock_update_hz(s->clkref, NPCM7XX_CLOCK_REF_HZ);
+}
+
 static void npcm7xx_clk_init(Object *obj)
 {
     NPCM7xxCLKState *s = NPCM7XX_CLK(obj);
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_init(Object *obj)
     memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s,
                           TYPE_NPCM7XX_CLK, 4 * KiB);
     sysbus_init_mmio(&s->parent, &s->iomem);
-    qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset,
-            NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS);
 }
 
-static const VMStateDescription vmstate_npcm7xx_clk = {
-    .name = "npcm7xx-clk",
+static int npcm7xx_clk_post_load(void *opaque, int version_id)
+{
+    if (version_id >= 1) {
+        NPCM7xxCLKState *clk = opaque;
+
+        npcm7xx_clk_update_all_clocks(clk);
+    }
+
+    return 0;
+}
+
+static void npcm7xx_clk_realize(DeviceState *dev, Error **errp)
+{
+    int i;
+    NPCM7xxCLKState *s = NPCM7XX_CLK(dev);
+
+    qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset,
+            NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS);
+    npcm7xx_clk_init_clock_hierarchy(s);
+
+    /* Realize child devices */
+    for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
+        if (!qdev_realize(DEVICE(&s->plls[i]), NULL, errp)) {
+            return;
+        }
+    }
+    for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
+        if (!qdev_realize(DEVICE(&s->sels[i]), NULL, errp)) {
+            return;
+        }
+    }
+    for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
+        if (!qdev_realize(DEVICE(&s->dividers[i]), NULL, errp)) {
+            return;
+        }
+    }
+}
+
+static const VMStateDescription vmstate_npcm7xx_clk_pll = {
+    .name = "npcm7xx-clock-pll",
     .version_id = 0,
     .minimum_version_id = 0,
-    .fields = (VMStateField[]) {
-        VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS),
-        VMSTATE_INT64(ref_ns, NPCM7xxCLKState),
+    .fields =  (VMStateField[]) {
+        VMSTATE_CLOCK(clock_in, NPCM7xxClockPLLState),
         VMSTATE_END_OF_LIST(),
     },
 };
 
+static const VMStateDescription vmstate_npcm7xx_clk_sel = {
+    .name = "npcm7xx-clock-sel",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields =  (VMStateField[]) {
+        VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(clock_in, NPCM7xxClockSELState,
+                NPCM7XX_CLK_SEL_MAX_INPUT, 0, vmstate_clock, Clock),
+        VMSTATE_END_OF_LIST(),
+    },
+};
+
+static const VMStateDescription vmstate_npcm7xx_clk_divider = {
+    .name = "npcm7xx-clock-divider",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields =  (VMStateField[]) {
+        VMSTATE_CLOCK(clock_in, NPCM7xxClockDividerState),
+        VMSTATE_END_OF_LIST(),
+    },
+};
+
+static const VMStateDescription vmstate_npcm7xx_clk = {
+    .name = "npcm7xx-clk",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .post_load = npcm7xx_clk_post_load,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS),
+        VMSTATE_INT64(ref_ns, NPCM7xxCLKState),
+        VMSTATE_CLOCK(clkref, NPCM7xxCLKState),
+        VMSTATE_END_OF_LIST(),
+    },
+};
+
+static void npcm7xx_clk_pll_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->desc = "NPCM7xx Clock PLL Module";
+    dc->vmsd = &vmstate_npcm7xx_clk_pll;
+}
+
+static void npcm7xx_clk_sel_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->desc = "NPCM7xx Clock SEL Module";
+    dc->vmsd = &vmstate_npcm7xx_clk_sel;
+}
+
+static void npcm7xx_clk_divider_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->desc = "NPCM7xx Clock Divider Module";
+    dc->vmsd = &vmstate_npcm7xx_clk_divider;
+}
+
 static void npcm7xx_clk_class_init(ObjectClass *klass, void *data)
 {
     ResettableClass *rc = RESETTABLE_CLASS(klass);
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_class_init(ObjectClass *klass, void *data)
 
     dc->desc = "NPCM7xx Clock Control Registers";
     dc->vmsd = &vmstate_npcm7xx_clk;
+    dc->realize = npcm7xx_clk_realize;
     rc->phases.enter = npcm7xx_clk_enter_reset;
 }
 
+static const TypeInfo npcm7xx_clk_pll_info = {
+    .name               = TYPE_NPCM7XX_CLOCK_PLL,
+    .parent             = TYPE_DEVICE,
+    .instance_size      = sizeof(NPCM7xxClockPLLState),
+    .instance_init      = npcm7xx_clk_pll_init,
+    .class_init         = npcm7xx_clk_pll_class_init,
+};
+
+static const TypeInfo npcm7xx_clk_sel_info = {
+    .name               = TYPE_NPCM7XX_CLOCK_SEL,
+    .parent             = TYPE_DEVICE,
+    .instance_size      = sizeof(NPCM7xxClockSELState),
+    .instance_init      = npcm7xx_clk_sel_init,
+    .class_init         = npcm7xx_clk_sel_class_init,
+};
+
+static const TypeInfo npcm7xx_clk_divider_info = {
+    .name               = TYPE_NPCM7XX_CLOCK_DIVIDER,
+    .parent             = TYPE_DEVICE,
+    .instance_size      = sizeof(NPCM7xxClockDividerState),
+    .instance_init      = npcm7xx_clk_divider_init,
+    .class_init         = npcm7xx_clk_divider_class_init,
+};
+
 static const TypeInfo npcm7xx_clk_info = {
     .name               = TYPE_NPCM7XX_CLK,
     .parent             = TYPE_SYS_BUS_DEVICE,
@@ -XXX,XX +XXX,XX @@ static const TypeInfo npcm7xx_clk_info = {
 
 static void npcm7xx_clk_register_type(void)
 {
+    type_register_static(&npcm7xx_clk_pll_info);
+    type_register_static(&npcm7xx_clk_sel_info);
+    type_register_static(&npcm7xx_clk_divider_info);
     type_register_static(&npcm7xx_clk_info);
 }
 type_init(npcm7xx_clk_register_type);
-- 
2.20.1

From: Hao Wu <wuhaotsh@google.com>

This patch makes NPCM7XX Timer to use a the timer clock generated by the
CLK module instead of the magic number TIMER_REF_HZ.

diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/misc/npcm7xx_clk.h
+++ b/include/hw/misc/npcm7xx_clk.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/clock.h"
 #include "hw/sysbus.h"
 
-/*
- * The reference clock frequency for the timer modules, and the SECCNT and
- * CNTR25M registers in this module, is always 25 MHz.
- */
-#define NPCM7XX_TIMER_REF_HZ            (25000000)
-
 /*
  * Number of registers in our device state structure. Don't change this without
  * incrementing the version_id in the vmstate.
diff --git a/include/hw/timer/npcm7xx_timer.h b/include/hw/timer/npcm7xx_timer.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/timer/npcm7xx_timer.h
+++ b/include/hw/timer/npcm7xx_timer.h
@@ -XXX,XX +XXX,XX @@ struct NPCM7xxTimerCtrlState {
 
     uint32_t    tisr;
 
+    Clock       *clock;
     NPCM7xxTimer timer[NPCM7XX_TIMERS_PER_CTRL];
     NPCM7xxWatchdogTimer watchdog_timer;
 };
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/char/serial.h"
 #include "hw/loader.h"
 #include "hw/misc/unimp.h"
+#include "hw/qdev-clock.h"
 #include "hw/qdev-properties.h"
 #include "qapi/error.h"
 #include "qemu/units.h"
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
         int first_irq;
         int j;
 
+        /* Connect the timer clock. */
+        qdev_connect_clock_in(DEVICE(&s->tim[i]), "clock", qdev_get_clock_out(
+                    DEVICE(&s->clk), "timer-clock"));
+
         sysbus_realize(sbd, &error_abort);
         sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]);
 
diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/npcm7xx_timer.c
+++ b/hw/timer/npcm7xx_timer.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 
 #include "hw/irq.h"
+#include "hw/qdev-clock.h"
 #include "hw/qdev-properties.h"
-#include "hw/misc/npcm7xx_clk.h"
 #include "hw/timer/npcm7xx_timer.h"
 #include "migration/vmstate.h"
 #include "qemu/bitops.h"
@@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_tcsr_prescaler(uint32_t tcsr)
 /* Convert a timer cycle count to a time interval in nanoseconds. */
 static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *t, uint32_t count)
 {
-    int64_t ns = count;
+    int64_t ticks = count;
 
-    ns *= NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ;
-    ns *= npcm7xx_tcsr_prescaler(t->tcsr);
+    ticks *= npcm7xx_tcsr_prescaler(t->tcsr);
 
-    return ns;
+    return clock_ticks_to_ns(t->ctrl->clock, ticks);
 }
 
 /* Convert a time interval in nanoseconds to a timer cycle count. */
 static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, int64_t ns)
 {
-    int64_t count;
-
-    count = ns / (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ);
-    count /= npcm7xx_tcsr_prescaler(t->tcsr);
-
-    return count;
+    return ns / clock_ticks_to_ns(t->ctrl->clock,
+                                  npcm7xx_tcsr_prescaler(t->tcsr));
 }
 
 static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t)
@@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t)
 static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t,
         int64_t cycles)
 {
-    uint32_t prescaler = npcm7xx_watchdog_timer_prescaler(t);
-    int64_t ns = (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ) * cycles;
+    int64_t ticks = cycles * npcm7xx_watchdog_timer_prescaler(t);
+    int64_t ns = clock_ticks_to_ns(t->ctrl->clock, ticks);
 
     /*
      * The reset function always clears the current timer. The caller of the
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t,
      */
     npcm7xx_timer_clear(&t->base_timer);
 
-    ns *= prescaler;
     t->base_timer.remaining_ns = ns;
 }
 
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_hold_reset(Object *obj)
     qemu_irq_lower(s->watchdog_timer.irq);
 }
 
-static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
+static void npcm7xx_timer_init(Object *obj)
 {
-    NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(dev);
-    SysBusDevice *sbd = &s->parent;
+    NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj);
+    DeviceState *dev = DEVICE(obj);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
     int i;
     NPCM7xxWatchdogTimer *w;
 
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
             npcm7xx_watchdog_timer_expired, w);
     sysbus_init_irq(sbd, &w->irq);
 
-    memory_region_init_io(&s->iomem, OBJECT(s), &npcm7xx_timer_ops, s,
+    memory_region_init_io(&s->iomem, obj, &npcm7xx_timer_ops, s,
                           TYPE_NPCM7XX_TIMER, 4 * KiB);
     sysbus_init_mmio(sbd, &s->iomem);
     qdev_init_gpio_out_named(dev, &w->reset_signal,
             NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 1);
+    s->clock = qdev_init_clock_in(dev, "clock", NULL, NULL);
 }
 
 static const VMStateDescription vmstate_npcm7xx_base_timer = {
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_npcm7xx_watchdog_timer = {
 
 static const VMStateDescription vmstate_npcm7xx_timer_ctrl = {
     .name = "npcm7xx-timer-ctrl",
-    .version_id = 1,
-    .minimum_version_id = 1,
+    .version_id = 2,
+    .minimum_version_id = 2,
     .fields = (VMStateField[]) {
         VMSTATE_UINT32(tisr, NPCM7xxTimerCtrlState),
+        VMSTATE_CLOCK(clock, NPCM7xxTimerCtrlState),
         VMSTATE_STRUCT_ARRAY(timer, NPCM7xxTimerCtrlState,
                              NPCM7XX_TIMERS_PER_CTRL, 0, vmstate_npcm7xx_timer,
                              NPCM7xxTimer),
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_class_init(ObjectClass *klass, void *data)
     QEMU_BUILD_BUG_ON(NPCM7XX_TIMER_REGS_END > NPCM7XX_TIMER_NR_REGS);
 
     dc->desc = "NPCM7xx Timer Controller";
-    dc->realize = npcm7xx_timer_realize;
     dc->vmsd = &vmstate_npcm7xx_timer_ctrl;
     rc->phases.enter = npcm7xx_timer_enter_reset;
     rc->phases.hold = npcm7xx_timer_hold_reset;
@@ -XXX,XX +XXX,XX @@ static const TypeInfo npcm7xx_timer_info = {
     .parent             = TYPE_SYS_BUS_DEVICE,
     .instance_size      = sizeof(NPCM7xxTimerCtrlState),
     .class_init         = npcm7xx_timer_class_init,
+    .instance_init      = npcm7xx_timer_init,
 };
 
 static void npcm7xx_timer_register_type(void)
-- 
2.20.1

From: Hao Wu <wuhaotsh@google.com>

The ADC is part of NPCM7XX Module. Its behavior is controled by the
ADC_CON register. It converts one of the eight analog inputs into a
digital input and stores it in the ADC_DATA register when enabled.

Users can alter input value by using qom-set QMP command.

Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Message-id: 20210108190945.949196-4-wuhaotsh@google.com
[PMM: Added missing hw/adc/trace.h file]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/nuvoton.rst    |   2 +-
 meson.build                    |   1 +
 hw/adc/trace.h                 |   1 +
 include/hw/adc/npcm7xx_adc.h   |  69 ++++++
 include/hw/arm/npcm7xx.h       |   2 +
 hw/adc/npcm7xx_adc.c           | 301 ++++++++++++++++++++++++++
 hw/arm/npcm7xx.c               |  24 ++-
 tests/qtest/npcm7xx_adc-test.c | 377 +++++++++++++++++++++++++++++++++
 hw/adc/meson.build             |   1 +
 hw/adc/trace-events            |   5 +
 tests/qtest/meson.build        |   3 +-
 11 files changed, 783 insertions(+), 3 deletions(-)
 create mode 100644 hw/adc/trace.h
 create mode 100644 include/hw/adc/npcm7xx_adc.h
 create mode 100644 hw/adc/npcm7xx_adc.c
 create mode 100644 tests/qtest/npcm7xx_adc-test.c
 create mode 100644 hw/adc/trace-events

diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/nuvoton.rst
+++ b/docs/system/arm/nuvoton.rst
@@ -XXX,XX +XXX,XX @@ Supported devices
  * Random Number Generator (RNG)
  * USB host (USBH)
  * GPIO controller
+ * Analog to Digital Converter (ADC)
 
 Missing devices
 ---------------
@@ -XXX,XX +XXX,XX @@ Missing devices
  * USB device (USBD)
  * SMBus controller (SMBF)
  * Peripheral SPI controller (PSPI)
- * Analog to Digital Converter (ADC)
  * SD/MMC host
  * PECI interface
  * Pulse Width Modulation (PWM)
diff --git a/meson.build b/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/meson.build
+++ b/meson.build
@@ -XXX,XX +XXX,XX @@ if have_system
     'chardev',
     'hw/9pfs',
     'hw/acpi',
+    'hw/adc',
     'hw/alpha',
     'hw/arm',
     'hw/audio',
diff --git a/hw/adc/trace.h b/hw/adc/trace.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/adc/trace.h
@@ -0,0 +1 @@
+#include "trace/trace-hw_adc.h"
diff --git a/include/hw/adc/npcm7xx_adc.h b/include/hw/adc/npcm7xx_adc.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/adc/npcm7xx_adc.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Nuvoton NPCM7xx ADC Module
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+#ifndef NPCM7XX_ADC_H
+#define NPCM7XX_ADC_H
+
+#include "hw/clock.h"
+#include "hw/irq.h"
+#include "hw/sysbus.h"
+#include "qemu/timer.h"
+
+#define NPCM7XX_ADC_NUM_INPUTS      8
+/**
+ * This value should not be changed unless write_adc_calibration function in
+ * hw/arm/npcm7xx.c is also changed.
+ */
+#define NPCM7XX_ADC_NUM_CALIB       2
+
+/**
+ * struct NPCM7xxADCState - Analog to Digital Converter Module device state.
+ * @parent: System bus device.
+ * @iomem: Memory region through which registers are accessed.
+ * @conv_timer: The timer counts down remaining cycles for the conversion.
+ * @irq: GIC interrupt line to fire on expiration (if enabled).
+ * @con: The Control Register.
+ * @data: The Data Buffer.
+ * @clock: The ADC Clock.
+ * @adci: The input voltage in units of uV. 1uv = 1e-6V.
+ * @vref: The external reference voltage.
+ * @iref: The internal reference voltage, initialized at launch time.
+ * @rv: The calibrated output values of 0.5V and 1.5V for the ADC.
+ */
+typedef struct {
+    SysBusDevice parent;
+
+    MemoryRegion iomem;
+
+    QEMUTimer    conv_timer;
+
+    qemu_irq     irq;
+    uint32_t     con;
+    uint32_t     data;
+    Clock       *clock;
+
+    /* Voltages are in unit of uV. 1V = 1000000uV. */
+    uint32_t     adci[NPCM7XX_ADC_NUM_INPUTS];
+    uint32_t     vref;
+    uint32_t     iref;
+
+    uint16_t     calibration_r_values[NPCM7XX_ADC_NUM_CALIB];
+} NPCM7xxADCState;
+
+#define TYPE_NPCM7XX_ADC "npcm7xx-adc"
+#define NPCM7XX_ADC(obj) \
+    OBJECT_CHECK(NPCM7xxADCState, (obj), TYPE_NPCM7XX_ADC)
+
+#endif /* NPCM7XX_ADC_H */
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/npcm7xx.h
+++ b/include/hw/arm/npcm7xx.h
@@ -XXX,XX +XXX,XX @@
 #define NPCM7XX_H
 
 #include "hw/boards.h"
+#include "hw/adc/npcm7xx_adc.h"
 #include "hw/cpu/a9mpcore.h"
 #include "hw/gpio/npcm7xx_gpio.h"
 #include "hw/mem/npcm7xx_mc.h"
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
     NPCM7xxGCRState     gcr;
     NPCM7xxCLKState     clk;
     NPCM7xxTimerCtrlState tim[3];
+    NPCM7xxADCState     adc;
     NPCM7xxOTPState     key_storage;
     NPCM7xxOTPState     fuse_array;
     NPCM7xxMCState      mc;
diff --git a/hw/adc/npcm7xx_adc.c b/hw/adc/npcm7xx_adc.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/adc/npcm7xx_adc.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Nuvoton NPCM7xx ADC Module
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/adc/npcm7xx_adc.h"
+#include "hw/qdev-clock.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "migration/vmstate.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu/timer.h"
+#include "qemu/units.h"
+#include "trace.h"
+
+REG32(NPCM7XX_ADC_CON, 0x0)
+REG32(NPCM7XX_ADC_DATA, 0x4)
+
+/* Register field definitions. */
+#define NPCM7XX_ADC_CON_MUX(rv) extract32(rv, 24, 4)
+#define NPCM7XX_ADC_CON_INT_EN  BIT(21)
+#define NPCM7XX_ADC_CON_REFSEL  BIT(19)
+#define NPCM7XX_ADC_CON_INT     BIT(18)
+#define NPCM7XX_ADC_CON_EN      BIT(17)
+#define NPCM7XX_ADC_CON_RST     BIT(16)
+#define NPCM7XX_ADC_CON_CONV    BIT(14)
+#define NPCM7XX_ADC_CON_DIV(rv) extract32(rv, 1, 8)
+
+#define NPCM7XX_ADC_MAX_RESULT      1023
+#define NPCM7XX_ADC_DEFAULT_IREF    2000000
+#define NPCM7XX_ADC_CONV_CYCLES     20
+#define NPCM7XX_ADC_RESET_CYCLES    10
+#define NPCM7XX_ADC_R0_INPUT        500000
+#define NPCM7XX_ADC_R1_INPUT        1500000
+
+static void npcm7xx_adc_reset(NPCM7xxADCState *s)
+{
+    timer_del(&s->conv_timer);
+    s->con = 0x000c0001;
+    s->data = 0x00000000;
+}
+
+static uint32_t npcm7xx_adc_convert(uint32_t input, uint32_t ref)
+{
+    uint32_t result;
+
+    result = input * (NPCM7XX_ADC_MAX_RESULT + 1) / ref;
+    if (result > NPCM7XX_ADC_MAX_RESULT) {
+        result = NPCM7XX_ADC_MAX_RESULT;
+    }
+
+    return result;
+}
+
+static uint32_t npcm7xx_adc_prescaler(NPCM7xxADCState *s)
+{
+    return 2 * (NPCM7XX_ADC_CON_DIV(s->con) + 1);
+}
+
+static void npcm7xx_adc_start_timer(Clock *clk, QEMUTimer *timer,
+        uint32_t cycles, uint32_t prescaler)
+{
+    int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+    int64_t ticks = cycles;
+    int64_t ns;
+
+    ticks *= prescaler;
+    ns = clock_ticks_to_ns(clk, ticks);
+    ns += now;
+    timer_mod(timer, ns);
+}
+
+static void npcm7xx_adc_start_convert(NPCM7xxADCState *s)
+{
+    uint32_t prescaler = npcm7xx_adc_prescaler(s);
+
+    npcm7xx_adc_start_timer(s->clock, &s->conv_timer, NPCM7XX_ADC_CONV_CYCLES,
+            prescaler);
+}
+
+static void npcm7xx_adc_convert_done(void *opaque)
+{
+    NPCM7xxADCState *s = opaque;
+    uint32_t input = NPCM7XX_ADC_CON_MUX(s->con);
+    uint32_t ref = (s->con & NPCM7XX_ADC_CON_REFSEL)
+        ? s->iref : s->vref;
+
+    if (input >= NPCM7XX_ADC_NUM_INPUTS) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid input: %u\n",
+                      __func__, input);
+        return;
+    }
+    s->data = npcm7xx_adc_convert(s->adci[input], ref);
+    if (s->con & NPCM7XX_ADC_CON_INT_EN) {
+        s->con |= NPCM7XX_ADC_CON_INT;
+        qemu_irq_raise(s->irq);
+    }
+    s->con &= ~NPCM7XX_ADC_CON_CONV;
+}
+
+static void npcm7xx_adc_calibrate(NPCM7xxADCState *adc)
+{
+    adc->calibration_r_values[0] = npcm7xx_adc_convert(NPCM7XX_ADC_R0_INPUT,
+            adc->iref);
+    adc->calibration_r_values[1] = npcm7xx_adc_convert(NPCM7XX_ADC_R1_INPUT,
+            adc->iref);
+}
+
+static void npcm7xx_adc_write_con(NPCM7xxADCState *s, uint32_t new_con)
+{
+    uint32_t old_con = s->con;
+
+    /* Write ADC_INT to 1 to clear it */
+    if (new_con & NPCM7XX_ADC_CON_INT) {
+        new_con &= ~NPCM7XX_ADC_CON_INT;
+        qemu_irq_lower(s->irq);
+    } else if (old_con & NPCM7XX_ADC_CON_INT) {
+        new_con |= NPCM7XX_ADC_CON_INT;
+    }
+
+    s->con = new_con;
+
+    if (s->con & NPCM7XX_ADC_CON_RST) {
+        npcm7xx_adc_reset(s);
+        return;
+    }
+
+    if ((s->con & NPCM7XX_ADC_CON_EN)) {
+        if (s->con & NPCM7XX_ADC_CON_CONV) {
+            if (!(old_con & NPCM7XX_ADC_CON_CONV)) {
+                npcm7xx_adc_start_convert(s);
+            }
+        } else {
+            timer_del(&s->conv_timer);
+        }
+    }
+}
+
+static uint64_t npcm7xx_adc_read(void *opaque, hwaddr offset, unsigned size)
+{
+    uint64_t value = 0;
+    NPCM7xxADCState *s = opaque;
+
+    switch (offset) {
+    case A_NPCM7XX_ADC_CON:
+        value = s->con;
+        break;
+
+    case A_NPCM7XX_ADC_DATA:
+        value = s->data;
+        break;
+
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
+                      __func__, offset);
+        break;
+    }
+
+    trace_npcm7xx_adc_read(DEVICE(s)->canonical_path, offset, value);
+    return value;
+}
+
+static void npcm7xx_adc_write(void *opaque, hwaddr offset, uint64_t v,
+        unsigned size)
+{
+    NPCM7xxADCState *s = opaque;
+
+    trace_npcm7xx_adc_write(DEVICE(s)->canonical_path, offset, v);
+    switch (offset) {
+    case A_NPCM7XX_ADC_CON:
+        npcm7xx_adc_write_con(s, v);
+        break;
+
+    case A_NPCM7XX_ADC_DATA:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
+                      __func__, offset);
+        break;
+
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
+                      __func__, offset);
+        break;
+    }
+
+}
+
+static const struct MemoryRegionOps npcm7xx_adc_ops = {
+    .read       = npcm7xx_adc_read,
+    .write      = npcm7xx_adc_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .valid      = {
+        .min_access_size        = 4,
+        .max_access_size        = 4,
+        .unaligned              = false,
+    },
+};
+
+static void npcm7xx_adc_enter_reset(Object *obj, ResetType type)
+{
+    NPCM7xxADCState *s = NPCM7XX_ADC(obj);
+
+    npcm7xx_adc_reset(s);
+}
+
+static void npcm7xx_adc_hold_reset(Object *obj)
+{
+    NPCM7xxADCState *s = NPCM7XX_ADC(obj);
+
+    qemu_irq_lower(s->irq);
+}
+
+static void npcm7xx_adc_init(Object *obj)
+{
+    NPCM7xxADCState *s = NPCM7XX_ADC(obj);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+    int i;
+
+    sysbus_init_irq(sbd, &s->irq);
+
+    timer_init_ns(&s->conv_timer, QEMU_CLOCK_VIRTUAL,
+            npcm7xx_adc_convert_done, s);
+    memory_region_init_io(&s->iomem, obj, &npcm7xx_adc_ops, s,
+                          TYPE_NPCM7XX_ADC, 4 * KiB);
+    sysbus_init_mmio(sbd, &s->iomem);
+    s->clock = qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL);
+
+    for (i = 0; i < NPCM7XX_ADC_NUM_INPUTS; ++i) {
+        object_property_add_uint32_ptr(obj, "adci[*]",
+                &s->adci[i], OBJ_PROP_FLAG_WRITE);
+    }
+    object_property_add_uint32_ptr(obj, "vref",
+            &s->vref, OBJ_PROP_FLAG_WRITE);
+    npcm7xx_adc_calibrate(s);
+}
+
+static const VMStateDescription vmstate_npcm7xx_adc = {
+    .name = "npcm7xx-adc",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_TIMER(conv_timer, NPCM7xxADCState),
+        VMSTATE_UINT32(con, NPCM7xxADCState),
+        VMSTATE_UINT32(data, NPCM7xxADCState),
+        VMSTATE_CLOCK(clock, NPCM7xxADCState),
+        VMSTATE_UINT32_ARRAY(adci, NPCM7xxADCState, NPCM7XX_ADC_NUM_INPUTS),
+        VMSTATE_UINT32(vref, NPCM7xxADCState),
+        VMSTATE_UINT32(iref, NPCM7xxADCState),
+        VMSTATE_UINT16_ARRAY(calibration_r_values, NPCM7xxADCState,
+                NPCM7XX_ADC_NUM_CALIB),
+        VMSTATE_END_OF_LIST(),
+    },
+};
+
+static Property npcm7xx_timer_properties[] = {
+    DEFINE_PROP_UINT32("iref", NPCM7xxADCState, iref, NPCM7XX_ADC_DEFAULT_IREF),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void npcm7xx_adc_class_init(ObjectClass *klass, void *data)
+{
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->desc = "NPCM7xx ADC Module";
+    dc->vmsd = &vmstate_npcm7xx_adc;
+    rc->phases.enter = npcm7xx_adc_enter_reset;
+    rc->phases.hold = npcm7xx_adc_hold_reset;
+
+    device_class_set_props(dc, npcm7xx_timer_properties);
+}
+
+static const TypeInfo npcm7xx_adc_info = {
+    .name               = TYPE_NPCM7XX_ADC,
+    .parent             = TYPE_SYS_BUS_DEVICE,
+    .instance_size      = sizeof(NPCM7xxADCState),
+    .class_init         = npcm7xx_adc_class_init,
+    .instance_init      = npcm7xx_adc_init,
+};
+
+static void npcm7xx_adc_register_types(void)
+{
+    type_register_static(&npcm7xx_adc_info);
+}
+
+type_init(npcm7xx_adc_register_types);
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
@@ -XXX,XX +XXX,XX @@
 #define NPCM7XX_EHCI_BA         (0xf0806000)
 #define NPCM7XX_OHCI_BA         (0xf0807000)
 
+/* ADC Module */
+#define NPCM7XX_ADC_BA          (0xf000c000)
+
 /* Internal AHB SRAM */
 #define NPCM7XX_RAM3_BA         (0xc0008000)
 #define NPCM7XX_RAM3_SZ         (4 * KiB)
@@ -XXX,XX +XXX,XX @@
 #define NPCM7XX_ROM_BA          (0xffff0000)
 #define NPCM7XX_ROM_SZ          (64 * KiB)
 
+
 /* Clock configuration values to be fixed up when bypassing bootloader */
 
 /* Run PLL1 at 1600 MHz */
@@ -XXX,XX +XXX,XX @@
  * interrupts.
  */
 enum NPCM7xxInterrupt {
+    NPCM7XX_ADC_IRQ             = 0,
     NPCM7XX_UART0_IRQ           = 2,
     NPCM7XX_UART1_IRQ,
     NPCM7XX_UART2_IRQ,
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init_fuses(NPCM7xxState *s)
                             sizeof(value));
 }
 
+static void npcm7xx_write_adc_calibration(NPCM7xxState *s)
+{
+    /* Both ADC and the fuse array must have realized. */
+    QEMU_BUILD_BUG_ON(sizeof(s->adc.calibration_r_values) != 4);
+    npcm7xx_otp_array_write(&s->fuse_array, s->adc.calibration_r_values,
+            NPCM7XX_FUSE_ADC_CALIB, sizeof(s->adc.calibration_r_values));
+}
+
 static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n)
 {
     return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
                             TYPE_NPCM7XX_FUSE_ARRAY);
     object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC);
     object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG);
+    object_initialize_child(obj, "adc", &s->adc, TYPE_NPCM7XX_ADC);
 
     for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
         object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
     sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort);
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM7XX_MC_BA);
 
+    /* ADC Modules. Cannot fail. */
+    qdev_connect_clock_in(DEVICE(&s->adc), "clock", qdev_get_clock_out(
+                          DEVICE(&s->clk), "adc-clock"));
+    sysbus_realize(SYS_BUS_DEVICE(&s->adc), &error_abort);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, NPCM7XX_ADC_BA);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
+            npcm7xx_irq(s, NPCM7XX_ADC_IRQ));
+    npcm7xx_write_adc_calibration(s);
+
     /* Timer Modules (TIM). Cannot fail. */
     QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim));
     for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
     create_unimplemented_device("npcm7xx.vdmx",         0xe0800000,   4 * KiB);
     create_unimplemented_device("npcm7xx.pcierc",       0xe1000000,  64 * KiB);
     create_unimplemented_device("npcm7xx.kcs",          0xf0007000,   4 * KiB);
-    create_unimplemented_device("npcm7xx.adc",          0xf000c000,   4 * KiB);
     create_unimplemented_device("npcm7xx.gfxi",         0xf000e000,   4 * KiB);
     create_unimplemented_device("npcm7xx.gpio[0]",      0xf0010000,   4 * KiB);
     create_unimplemented_device("npcm7xx.gpio[1]",      0xf0011000,   4 * KiB);
diff --git a/tests/qtest/npcm7xx_adc-test.c b/tests/qtest/npcm7xx_adc-test.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tests/qtest/npcm7xx_adc-test.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * QTests for Nuvoton NPCM7xx ADCModules.
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bitops.h"
+#include "qemu/timer.h"
+#include "libqos/libqtest.h"
+#include "qapi/qmp/qdict.h"
+
+#define REF_HZ          (25000000)
+
+#define CON_OFFSET      0x0
+#define DATA_OFFSET     0x4
+
+#define NUM_INPUTS      8
+#define DEFAULT_IREF    2000000
+#define CONV_CYCLES     20
+#define RESET_CYCLES    10
+#define R0_INPUT        500000
+#define R1_INPUT        1500000
+#define MAX_RESULT      1023
+
+#define DEFAULT_CLKDIV  5
+
+#define FUSE_ARRAY_BA   0xf018a000
+#define FCTL_OFFSET     0x14
+#define FST_OFFSET      0x0
+#define FADDR_OFFSET    0x4
+#define FDATA_OFFSET    0x8
+#define ADC_CALIB_ADDR  24
+#define FUSE_READ       0x2
+
+/* Register field definitions. */
+#define CON_MUX(rv) ((rv) << 24)
+#define CON_INT_EN  BIT(21)
+#define CON_REFSEL  BIT(19)
+#define CON_INT     BIT(18)
+#define CON_EN      BIT(17)
+#define CON_RST     BIT(16)
+#define CON_CONV    BIT(14)
+#define CON_DIV(rv) extract32(rv, 1, 8)
+
+#define FST_RDST    BIT(1)
+#define FDATA_MASK  0xff
+
+#define MAX_ERROR   10000
+#define MIN_CALIB_INPUT 100000
+#define MAX_CALIB_INPUT 1800000
+
+static const uint32_t input_list[] = {
+    100000,
+    500000,
+    1000000,
+    1500000,
+    1800000,
+    2000000,
+};
+
+static const uint32_t vref_list[] = {
+    2000000,
+    2200000,
+    2500000,
+};
+
+static const uint32_t iref_list[] = {
+    1800000,
+    1900000,
+    2000000,
+    2100000,
+    2200000,
+};
+
+static const uint32_t div_list[] = {0, 1, 3, 7, 15};
+
+typedef struct ADC {
+    int irq;
+    uint64_t base_addr;
+} ADC;
+
+ADC adc = {
+    .irq        = 0,
+    .base_addr  = 0xf000c000
+};
+
+static uint32_t adc_read_con(QTestState *qts, const ADC *adc)
+{
+    return qtest_readl(qts, adc->base_addr + CON_OFFSET);
+}
+
+static void adc_write_con(QTestState *qts, const ADC *adc, uint32_t value)
+{
+    qtest_writel(qts, adc->base_addr + CON_OFFSET, value);
+}
+
+static uint32_t adc_read_data(QTestState *qts, const ADC *adc)
+{
+    return qtest_readl(qts, adc->base_addr + DATA_OFFSET);
+}
+
+static uint32_t adc_calibrate(uint32_t measured, uint32_t *rv)
+{
+    return R0_INPUT + (R1_INPUT - R0_INPUT) * (int32_t)(measured - rv[0])
+        / (int32_t)(rv[1] - rv[0]);
+}
+
+static void adc_qom_set(QTestState *qts, const ADC *adc,
+        const char *name, uint32_t value)
+{
+    QDict *response;
+    const char *path = "/machine/soc/adc";
+
+    g_test_message("Setting properties %s of %s with value %u",
+            name, path, value);
+    response = qtest_qmp(qts, "{ 'execute': 'qom-set',"
+            " 'arguments': { 'path': %s, 'property': %s, 'value': %u}}",
+            path, name, value);
+    /* The qom set message returns successfully. */
+    g_assert_true(qdict_haskey(response, "return"));
+}
+
+static void adc_write_input(QTestState *qts, const ADC *adc,
+        uint32_t index, uint32_t value)
+{
+    char name[100];
+
+    sprintf(name, "adci[%u]", index);
+    adc_qom_set(qts, adc, name, value);
+}
+
+static void adc_write_vref(QTestState *qts, const ADC *adc, uint32_t value)
+{
+    adc_qom_set(qts, adc, "vref", value);
+}
+
+static uint32_t adc_calculate_output(uint32_t input, uint32_t ref)
+{
+    uint32_t output;
+
+    g_assert_cmpuint(input, <=, ref);
+    output = (input * (MAX_RESULT + 1)) / ref;
+    if (output > MAX_RESULT) {
+        output = MAX_RESULT;
+    }
+
+    return output;
+}
+
+static uint32_t adc_prescaler(QTestState *qts, const ADC *adc)
+{
+    uint32_t div = extract32(adc_read_con(qts, adc), 1, 8);
+
+    return 2 * (div + 1);
+}
+
+static int64_t adc_calculate_steps(uint32_t cycles, uint32_t prescale,
+        uint32_t clkdiv)
+{
+    return (NANOSECONDS_PER_SECOND / (REF_HZ >> clkdiv)) * cycles * prescale;
+}
+
+static void adc_wait_conv_finished(QTestState *qts, const ADC *adc,
+        uint32_t clkdiv)
+{
+    uint32_t prescaler = adc_prescaler(qts, adc);
+
+    /*
+     * ADC should takes roughly 20 cycles to convert one sample. So we assert it
+     * should take 10~30 cycles here.
+     */
+    qtest_clock_step(qts, adc_calculate_steps(CONV_CYCLES / 2, prescaler,
+                clkdiv));
+    /* ADC is still converting. */
+    g_assert_true(adc_read_con(qts, adc) & CON_CONV);
+    qtest_clock_step(qts, adc_calculate_steps(CONV_CYCLES, prescaler, clkdiv));
+    /* ADC has finished conversion. */
+    g_assert_false(adc_read_con(qts, adc) & CON_CONV);
+}
+
+/* Check ADC can be reset to default value. */
+static void test_init(gconstpointer adc_p)
+{
+    const ADC *adc = adc_p;
+
+    QTestState *qts = qtest_init("-machine quanta-gsj");
+    adc_write_con(qts, adc, CON_REFSEL | CON_INT);
+    g_assert_cmphex(adc_read_con(qts, adc), ==, CON_REFSEL);
+    qtest_quit(qts);
+}
+
+/* Check ADC can convert from an internal reference. */
+static void test_convert_internal(gconstpointer adc_p)
+{
+    const ADC *adc = adc_p;
+    uint32_t index, input, output, expected_output;
+    QTestState *qts = qtest_init("-machine quanta-gsj");
+    qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
+
+    for (index = 0; index < NUM_INPUTS; ++index) {
+        for (size_t i = 0; i < ARRAY_SIZE(input_list); ++i) {
+            input = input_list[i];
+            expected_output = adc_calculate_output(input, DEFAULT_IREF);
+
+            adc_write_input(qts, adc, index, input);
+            adc_write_con(qts, adc, CON_MUX(index) | CON_REFSEL | CON_INT |
+                    CON_EN | CON_CONV);
+            adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
+            g_assert_cmphex(adc_read_con(qts, adc), ==, CON_MUX(index) |
+                    CON_REFSEL | CON_EN);
+            g_assert_false(qtest_get_irq(qts, adc->irq));
+            output = adc_read_data(qts, adc);
+            g_assert_cmpuint(output, ==, expected_output);
+        }
+    }
+
+    qtest_quit(qts);
+}
+
+/* Check ADC can convert from an external reference. */
+static void test_convert_external(gconstpointer adc_p)
+{
+    const ADC *adc = adc_p;
+    uint32_t index, input, vref, output, expected_output;
+    QTestState *qts = qtest_init("-machine quanta-gsj");
+    qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
+
+    for (index = 0; index < NUM_INPUTS; ++index) {
+        for (size_t i = 0; i < ARRAY_SIZE(input_list); ++i) {
+            for (size_t j = 0; j < ARRAY_SIZE(vref_list); ++j) {
+                input = input_list[i];
+                vref = vref_list[j];
+                expected_output = adc_calculate_output(input, vref);
+
+                adc_write_input(qts, adc, index, input);
+                adc_write_vref(qts, adc, vref);
+                adc_write_con(qts, adc, CON_MUX(index) | CON_INT | CON_EN |
+                        CON_CONV);
+                adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
+                g_assert_cmphex(adc_read_con(qts, adc), ==,
+                        CON_MUX(index) | CON_EN);
+                g_assert_false(qtest_get_irq(qts, adc->irq));
+                output = adc_read_data(qts, adc);
+                g_assert_cmpuint(output, ==, expected_output);
+            }
+        }
+    }
+
+    qtest_quit(qts);
+}
+
+/* Check ADC interrupt files if and only if CON_INT_EN is set. */
+static void test_interrupt(gconstpointer adc_p)
+{
+    const ADC *adc = adc_p;
+    uint32_t index, input, output, expected_output;
+    QTestState *qts = qtest_init("-machine quanta-gsj");
+
+    index = 1;
+    input = input_list[1];
+    expected_output = adc_calculate_output(input, DEFAULT_IREF);
+
+    qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
+    adc_write_input(qts, adc, index, input);
+    g_assert_false(qtest_get_irq(qts, adc->irq));
+    adc_write_con(qts, adc, CON_MUX(index) | CON_INT_EN | CON_REFSEL | CON_INT
+            | CON_EN | CON_CONV);
+    adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
+    g_assert_cmphex(adc_read_con(qts, adc), ==, CON_MUX(index) | CON_INT_EN
+            | CON_REFSEL | CON_INT | CON_EN);
+    g_assert_true(qtest_get_irq(qts, adc->irq));
+    output = adc_read_data(qts, adc);
+    g_assert_cmpuint(output, ==, expected_output);
+
+    qtest_quit(qts);
+}
+
+/* Check ADC is reset after setting ADC_RST for 10 ADC cycles. */
+static void test_reset(gconstpointer adc_p)
+{
+    const ADC *adc = adc_p;
+    QTestState *qts = qtest_init("-machine quanta-gsj");
+
+    for (size_t i = 0; i < ARRAY_SIZE(div_list); ++i) {
+        uint32_t div = div_list[i];
+
+        adc_write_con(qts, adc, CON_INT | CON_EN | CON_RST | CON_DIV(div));
+        qtest_clock_step(qts, adc_calculate_steps(RESET_CYCLES,
+                    adc_prescaler(qts, adc), DEFAULT_CLKDIV));
+        g_assert_false(adc_read_con(qts, adc) & CON_EN);
+    }
+    qtest_quit(qts);
+}
+
+/* Check ADC Calibration works as desired. */
+static void test_calibrate(gconstpointer adc_p)
+{
+    int i, j;
+    const ADC *adc = adc_p;
+
+    for (j = 0; j < ARRAY_SIZE(iref_list); ++j) {
+        uint32_t iref = iref_list[j];
+        uint32_t expected_rv[] = {
+            adc_calculate_output(R0_INPUT, iref),
+            adc_calculate_output(R1_INPUT, iref),
+        };
+        char buf[100];
+        QTestState *qts;
+
+        sprintf(buf, "-machine quanta-gsj -global npcm7xx-adc.iref=%u", iref);
+        qts = qtest_init(buf);
+
+        /* Check the converted value is correct using the calibration value. */
+        for (i = 0; i < ARRAY_SIZE(input_list); ++i) {
+            uint32_t input;
+            uint32_t output;
+            uint32_t expected_output;
+            uint32_t calibrated_voltage;
+            uint32_t index = 0;
+
+            input = input_list[i];
+            /* Calibration only works for input range 0.1V ~ 1.8V. */
+            if (input < MIN_CALIB_INPUT || input > MAX_CALIB_INPUT) {
+                continue;
+            }
+            expected_output = adc_calculate_output(input, iref);
+
+            adc_write_input(qts, adc, index, input);
+            adc_write_con(qts, adc, CON_MUX(index) | CON_REFSEL | CON_INT |
+                    CON_EN | CON_CONV);
+            adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
+            g_assert_cmphex(adc_read_con(qts, adc), ==,
+                    CON_REFSEL | CON_MUX(index) | CON_EN);
+            output = adc_read_data(qts, adc);
+            g_assert_cmpuint(output, ==, expected_output);
+
+            calibrated_voltage = adc_calibrate(output, expected_rv);
+            g_assert_cmpuint(calibrated_voltage, >, input - MAX_ERROR);
+            g_assert_cmpuint(calibrated_voltage, <, input + MAX_ERROR);
+        }
+
+        qtest_quit(qts);
+    }
+}
+
+static void adc_add_test(const char *name, const ADC* wd,
+        GTestDataFunc fn)
+{
+    g_autofree char *full_name = g_strdup_printf("npcm7xx_adc/%s",  name);
+    qtest_add_data_func(full_name, wd, fn);
+}
+#define add_test(name, td) adc_add_test(#name, td, test_##name)
+
+int main(int argc, char **argv)
+{
+    g_test_init(&argc, &argv, NULL);
+
+    add_test(init, &adc);
+    add_test(convert_internal, &adc);
+    add_test(convert_external, &adc);
+    add_test(interrupt, &adc);
+    add_test(reset, &adc);
+    add_test(calibrate, &adc);
+
+    return g_test_run();
+}
diff --git a/hw/adc/meson.build b/hw/adc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/adc/meson.build
+++ b/hw/adc/meson.build
@@ -1 +1,2 @@
 softmmu_ss.add(when: 'CONFIG_STM32F2XX_ADC', if_true: files('stm32f2xx_adc.c'))
+softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_adc.c'))
diff --git a/hw/adc/trace-events b/hw/adc/trace-events
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/adc/trace-events
@@ -XXX,XX +XXX,XX @@
+# See docs/devel/tracing.txt for syntax documentation.
+
+# npcm7xx_adc.c
+npcm7xx_adc_read(const char *id, uint64_t offset, uint32_t value) " %s offset: 0x%04" PRIx64 " value 0x%04" PRIx32
+npcm7xx_adc_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value 0x%04" PRIx32
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -XXX,XX +XXX,XX @@ qtests_sparc64 = \
   ['prom-env-test', 'boot-serial-test']
 
 qtests_npcm7xx = \
-  ['npcm7xx_gpio-test',
+  ['npcm7xx_adc-test',
+   'npcm7xx_gpio-test',
    'npcm7xx_rng-test',
    'npcm7xx_timer-test',
    'npcm7xx_watchdog_timer-test']
-- 
2.20.1

From: Hao Wu <wuhaotsh@google.com>

The PWM module is part of NPCM7XX module. Each NPCM7XX module has two
identical PWM modules. Each module contains 4 PWM entries. Each PWM has
two outputs: frequency and duty_cycle. Both are computed using inputs
from software side.

This module does not model detail pulse signals since it is expensive.
It also does not model interrupts and watchdogs that are dependant on
the detail models. The interfaces for these are left in the module so
that anyone in need for these functionalities can implement on their
own.

The user can read the duty cycle and frequency using qom-get command.

diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/nuvoton.rst
+++ b/docs/system/arm/nuvoton.rst
@@ -XXX,XX +XXX,XX @@ Supported devices
  * USB host (USBH)
  * GPIO controller
  * Analog to Digital Converter (ADC)
+ * Pulse Width Modulation (PWM)
 
 Missing devices
 ---------------
@@ -XXX,XX +XXX,XX @@ Missing devices
  * Peripheral SPI controller (PSPI)
  * SD/MMC host
  * PECI interface
- * Pulse Width Modulation (PWM)
  * Tachometer
  * PCI and PCIe root complex and bridges
  * VDM and MCTP support
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/npcm7xx.h
+++ b/include/hw/arm/npcm7xx.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/mem/npcm7xx_mc.h"
 #include "hw/misc/npcm7xx_clk.h"
 #include "hw/misc/npcm7xx_gcr.h"
+#include "hw/misc/npcm7xx_pwm.h"
 #include "hw/misc/npcm7xx_rng.h"
 #include "hw/nvram/npcm7xx_otp.h"
 #include "hw/timer/npcm7xx_timer.h"
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
     NPCM7xxCLKState     clk;
     NPCM7xxTimerCtrlState tim[3];
     NPCM7xxADCState     adc;
+    NPCM7xxPWMState     pwm[2];
     NPCM7xxOTPState     key_storage;
     NPCM7xxOTPState     fuse_array;
     NPCM7xxMCState      mc;
diff --git a/include/hw/misc/npcm7xx_pwm.h b/include/hw/misc/npcm7xx_pwm.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/misc/npcm7xx_pwm.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Nuvoton NPCM7xx PWM Module
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+#ifndef NPCM7XX_PWM_H
+#define NPCM7XX_PWM_H
+
+#include "hw/clock.h"
+#include "hw/sysbus.h"
+#include "hw/irq.h"
+
+/* Each PWM module holds 4 PWM channels. */
+#define NPCM7XX_PWM_PER_MODULE 4
+
+/*
+ * Number of registers in one pwm module. Don't change this without increasing
+ * the version_id in vmstate.
+ */
+#define NPCM7XX_PWM_NR_REGS (0x54 / sizeof(uint32_t))
+
+/*
+ * The maximum duty values. Each duty unit represents 1/NPCM7XX_PWM_MAX_DUTY
+ * cycles. For example, if NPCM7XX_PWM_MAX_DUTY=1,000,000 and a PWM has a duty
+ * value of 100,000 the duty cycle for that PWM is 10%.
+ */
+#define NPCM7XX_PWM_MAX_DUTY 1000000
+
+typedef struct NPCM7xxPWMState NPCM7xxPWMState;
+
+/**
+ * struct NPCM7xxPWM - The state of a single PWM channel.
+ * @module: The PWM module that contains this channel.
+ * @irq: GIC interrupt line to fire on expiration if enabled.
+ * @running: Whether this PWM channel is generating output.
+ * @inverted: Whether this PWM channel is inverted.
+ * @index: The index of this PWM channel.
+ * @cnr: The counter register.
+ * @cmr: The comparator register.
+ * @pdr: The data register.
+ * @pwdr: The watchdog register.
+ * @freq: The frequency of this PWM channel.
+ * @duty: The duty cycle of this PWM channel. One unit represents
+ *   1/NPCM7XX_MAX_DUTY cycles.
+ */
+typedef struct NPCM7xxPWM {
+    NPCM7xxPWMState         *module;
+
+    qemu_irq                irq;
+
+    bool                    running;
+    bool                    inverted;
+
+    uint8_t                 index;
+    uint32_t                cnr;
+    uint32_t                cmr;
+    uint32_t                pdr;
+    uint32_t                pwdr;
+
+    uint32_t                freq;
+    uint32_t                duty;
+} NPCM7xxPWM;
+
+/**
+ * struct NPCM7xxPWMState - Pulse Width Modulation device state.
+ * @parent: System bus device.
+ * @iomem: Memory region through which registers are accessed.
+ * @clock: The PWM clock.
+ * @pwm: The PWM channels owned by this module.
+ * @ppr: The prescaler register.
+ * @csr: The clock selector register.
+ * @pcr: The control register.
+ * @pier: The interrupt enable register.
+ * @piir: The interrupt indication register.
+ */
+struct NPCM7xxPWMState {
+    SysBusDevice parent;
+
+    MemoryRegion iomem;
+
+    Clock       *clock;
+    NPCM7xxPWM pwm[NPCM7XX_PWM_PER_MODULE];
+
+    uint32_t    ppr;
+    uint32_t    csr;
+    uint32_t    pcr;
+    uint32_t    pier;
+    uint32_t    piir;
+};
+
+#define TYPE_NPCM7XX_PWM "npcm7xx-pwm"
+#define NPCM7XX_PWM(obj) \
+    OBJECT_CHECK(NPCM7xxPWMState, (obj), TYPE_NPCM7XX_PWM)
+
+#endif /* NPCM7XX_PWM_H */
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
@@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt {
     NPCM7XX_WDG2_IRQ,                   /* Timer Module 2 Watchdog */
     NPCM7XX_EHCI_IRQ            = 61,
     NPCM7XX_OHCI_IRQ            = 62,
+    NPCM7XX_PWM0_IRQ            = 93,   /* PWM module 0 */
+    NPCM7XX_PWM1_IRQ,                   /* PWM module 1 */
     NPCM7XX_GPIO0_IRQ           = 116,
     NPCM7XX_GPIO1_IRQ,
     NPCM7XX_GPIO2_IRQ,
@@ -XXX,XX +XXX,XX @@ static const hwaddr npcm7xx_fiu3_flash_addr[] = {
     0xb8000000, /* CS3 */
 };
 
+/* Register base address for each PWM Module */
+static const hwaddr npcm7xx_pwm_addr[] = {
+    0xf0103000,
+    0xf0104000,
+};
+
 static const struct {
     hwaddr regs_addr;
     uint32_t unconnected_pins;
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
         object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i],
                                 TYPE_NPCM7XX_FIU);
     }
+
+    for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
+        object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PWM);
+    }
 }
 
 static void npcm7xx_realize(DeviceState *dev, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci), 0,
                        npcm7xx_irq(s, NPCM7XX_OHCI_IRQ));
 
+    /* PWM Modules. Cannot fail. */
+    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pwm_addr) != ARRAY_SIZE(s->pwm));
+    for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
+        SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pwm[i]);
+
+        qdev_connect_clock_in(DEVICE(&s->pwm[i]), "clock", qdev_get_clock_out(
+                    DEVICE(&s->clk), "apb3-clock"));
+        sysbus_realize(sbd, &error_abort);
+        sysbus_mmio_map(sbd, 0, npcm7xx_pwm_addr[i]);
+        sysbus_connect_irq(sbd, i, npcm7xx_irq(s, NPCM7XX_PWM0_IRQ + i));
+    }
+
     /*
      * Flash Interface Unit (FIU). Can fail if incorrect number of chip selects
      * specified, but this is a programming error.
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
     create_unimplemented_device("npcm7xx.peci",         0xf0100000,   4 * KiB);
     create_unimplemented_device("npcm7xx.siox[1]",      0xf0101000,   4 * KiB);
     create_unimplemented_device("npcm7xx.siox[2]",      0xf0102000,   4 * KiB);
-    create_unimplemented_device("npcm7xx.pwm[0]",       0xf0103000,   4 * KiB);
-    create_unimplemented_device("npcm7xx.pwm[1]",       0xf0104000,   4 * KiB);
     create_unimplemented_device("npcm7xx.mft[0]",       0xf0180000,   4 * KiB);
     create_unimplemented_device("npcm7xx.mft[1]",       0xf0181000,   4 * KiB);
     create_unimplemented_device("npcm7xx.mft[2]",       0xf0182000,   4 * KiB);
diff --git a/hw/misc/npcm7xx_pwm.c b/hw/misc/npcm7xx_pwm.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/misc/npcm7xx_pwm.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Nuvoton NPCM7xx PWM Module
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/irq.h"
+#include "hw/qdev-clock.h"
+#include "hw/qdev-properties.h"
+#include "hw/misc/npcm7xx_pwm.h"
+#include "hw/registerfields.h"
+#include "migration/vmstate.h"
+#include "qemu/bitops.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu/units.h"
+#include "trace.h"
+
+REG32(NPCM7XX_PWM_PPR, 0x00);
+REG32(NPCM7XX_PWM_CSR, 0x04);
+REG32(NPCM7XX_PWM_PCR, 0x08);
+REG32(NPCM7XX_PWM_CNR0, 0x0c);
+REG32(NPCM7XX_PWM_CMR0, 0x10);
+REG32(NPCM7XX_PWM_PDR0, 0x14);
+REG32(NPCM7XX_PWM_CNR1, 0x18);
+REG32(NPCM7XX_PWM_CMR1, 0x1c);
+REG32(NPCM7XX_PWM_PDR1, 0x20);
+REG32(NPCM7XX_PWM_CNR2, 0x24);
+REG32(NPCM7XX_PWM_CMR2, 0x28);
+REG32(NPCM7XX_PWM_PDR2, 0x2c);
+REG32(NPCM7XX_PWM_CNR3, 0x30);
+REG32(NPCM7XX_PWM_CMR3, 0x34);
+REG32(NPCM7XX_PWM_PDR3, 0x38);
+REG32(NPCM7XX_PWM_PIER, 0x3c);
+REG32(NPCM7XX_PWM_PIIR, 0x40);
+REG32(NPCM7XX_PWM_PWDR0, 0x44);
+REG32(NPCM7XX_PWM_PWDR1, 0x48);
+REG32(NPCM7XX_PWM_PWDR2, 0x4c);
+REG32(NPCM7XX_PWM_PWDR3, 0x50);
+
+/* Register field definitions. */
+#define NPCM7XX_PPR(rv, index)      extract32((rv), npcm7xx_ppr_base[index], 8)
+#define NPCM7XX_CSR(rv, index)      extract32((rv), npcm7xx_csr_base[index], 3)
+#define NPCM7XX_CH(rv, index)       extract32((rv), npcm7xx_ch_base[index], 4)
+#define NPCM7XX_CH_EN               BIT(0)
+#define NPCM7XX_CH_INV              BIT(2)
+#define NPCM7XX_CH_MOD              BIT(3)
+
+/* Offset of each PWM channel's prescaler in the PPR register. */
+static const int npcm7xx_ppr_base[] = { 0, 0, 8, 8 };
+/* Offset of each PWM channel's clock selector in the CSR register. */
+static const int npcm7xx_csr_base[] = { 0, 4, 8, 12 };
+/* Offset of each PWM channel's control variable in the PCR register. */
+static const int npcm7xx_ch_base[] = { 0, 8, 12, 16 };
+
+static uint32_t npcm7xx_pwm_calculate_freq(NPCM7xxPWM *p)
+{
+    uint32_t ppr;
+    uint32_t csr;
+    uint32_t freq;
+
+    if (!p->running) {
+        return 0;
+    }
+
+    csr = NPCM7XX_CSR(p->module->csr, p->index);
+    ppr = NPCM7XX_PPR(p->module->ppr, p->index);
+    freq = clock_get_hz(p->module->clock);
+    freq /= ppr + 1;
+    /* csr can only be 0~4 */
+    if (csr > 4) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: invalid csr value %u\n",
+                      __func__, csr);
+        csr = 4;
+    }
+    /* freq won't be changed if csr == 4. */
+    if (csr < 4) {
+        freq >>= csr + 1;
+    }
+
+    return freq / (p->cnr + 1);
+}
+
+static uint32_t npcm7xx_pwm_calculate_duty(NPCM7xxPWM *p)
+{
+    uint64_t duty;
+
+    if (p->running) {
+        if (p->cnr == 0) {
+            duty = 0;
+        } else if (p->cmr >= p->cnr) {
+            duty = NPCM7XX_PWM_MAX_DUTY;
+        } else {
+            duty = NPCM7XX_PWM_MAX_DUTY * (p->cmr + 1) / (p->cnr + 1);
+        }
+    } else {
+        duty = 0;
+    }
+
+    if (p->inverted) {
+        duty = NPCM7XX_PWM_MAX_DUTY - duty;
+    }
+
+    return duty;
+}
+
+static void npcm7xx_pwm_update_freq(NPCM7xxPWM *p)
+{
+    uint32_t freq = npcm7xx_pwm_calculate_freq(p);
+
+    if (freq != p->freq) {
+        trace_npcm7xx_pwm_update_freq(DEVICE(p->module)->canonical_path,
+                                      p->index, p->freq, freq);
+        p->freq = freq;
+    }
+}
+
+static void npcm7xx_pwm_update_duty(NPCM7xxPWM *p)
+{
+    uint32_t duty = npcm7xx_pwm_calculate_duty(p);
+
+    if (duty != p->duty) {
+        trace_npcm7xx_pwm_update_duty(DEVICE(p->module)->canonical_path,
+                                      p->index, p->duty, duty);
+        p->duty = duty;
+    }
+}
+
+static void npcm7xx_pwm_update_output(NPCM7xxPWM *p)
+{
+    npcm7xx_pwm_update_freq(p);
+    npcm7xx_pwm_update_duty(p);
+}
+
+static void npcm7xx_pwm_write_ppr(NPCM7xxPWMState *s, uint32_t new_ppr)
+{
+    int i;
+    uint32_t old_ppr = s->ppr;
+
+    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_ppr_base) != NPCM7XX_PWM_PER_MODULE);
+    s->ppr = new_ppr;
+    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
+        if (NPCM7XX_PPR(old_ppr, i) != NPCM7XX_PPR(new_ppr, i)) {
+            npcm7xx_pwm_update_freq(&s->pwm[i]);
+        }
+    }
+}
+
+static void npcm7xx_pwm_write_csr(NPCM7xxPWMState *s, uint32_t new_csr)
+{
+    int i;
+    uint32_t old_csr = s->csr;
+
+    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_csr_base) != NPCM7XX_PWM_PER_MODULE);
+    s->csr = new_csr;
+    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
+        if (NPCM7XX_CSR(old_csr, i) != NPCM7XX_CSR(new_csr, i)) {
+            npcm7xx_pwm_update_freq(&s->pwm[i]);
+        }
+    }
+}
+
+static void npcm7xx_pwm_write_pcr(NPCM7xxPWMState *s, uint32_t new_pcr)
+{
+    int i;
+    bool inverted;
+    uint32_t pcr;
+    NPCM7xxPWM *p;
+
+    s->pcr = new_pcr;
+    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_ch_base) != NPCM7XX_PWM_PER_MODULE);
+    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
+        p = &s->pwm[i];
+        pcr = NPCM7XX_CH(new_pcr, i);
+        inverted = pcr & NPCM7XX_CH_INV;
+
+        /*
+         * We only run a PWM channel with toggle mode. Single-shot mode does not
+         * generate frequency and duty-cycle values.
+         */
+        if ((pcr & NPCM7XX_CH_EN) && (pcr & NPCM7XX_CH_MOD)) {
+            if (p->running) {
+                /* Re-run this PWM channel if inverted changed. */
+                if (p->inverted ^ inverted) {
+                    p->inverted = inverted;
+                    npcm7xx_pwm_update_duty(p);
+                }
+            } else {
+                /* Run this PWM channel. */
+                p->running = true;
+                p->inverted = inverted;
+                npcm7xx_pwm_update_output(p);
+            }
+        } else {
+            /* Clear this PWM channel. */
+            p->running = false;
+            p->inverted = inverted;
+            npcm7xx_pwm_update_output(p);
+        }
+    }
+
+}
+
+static hwaddr npcm7xx_cnr_index(hwaddr offset)
+{
+    switch (offset) {
+    case A_NPCM7XX_PWM_CNR0:
+        return 0;
+    case A_NPCM7XX_PWM_CNR1:
+        return 1;
+    case A_NPCM7XX_PWM_CNR2:
+        return 2;
+    case A_NPCM7XX_PWM_CNR3:
+        return 3;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static hwaddr npcm7xx_cmr_index(hwaddr offset)
+{
+    switch (offset) {
+    case A_NPCM7XX_PWM_CMR0:
+        return 0;
+    case A_NPCM7XX_PWM_CMR1:
+        return 1;
+    case A_NPCM7XX_PWM_CMR2:
+        return 2;
+    case A_NPCM7XX_PWM_CMR3:
+        return 3;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static hwaddr npcm7xx_pdr_index(hwaddr offset)
+{
+    switch (offset) {
+    case A_NPCM7XX_PWM_PDR0:
+        return 0;
+    case A_NPCM7XX_PWM_PDR1:
+        return 1;
+    case A_NPCM7XX_PWM_PDR2:
+        return 2;
+    case A_NPCM7XX_PWM_PDR3:
+        return 3;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static hwaddr npcm7xx_pwdr_index(hwaddr offset)
+{
+    switch (offset) {
+    case A_NPCM7XX_PWM_PWDR0:
+        return 0;
+    case A_NPCM7XX_PWM_PWDR1:
+        return 1;
+    case A_NPCM7XX_PWM_PWDR2:
+        return 2;
+    case A_NPCM7XX_PWM_PWDR3:
+        return 3;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static uint64_t npcm7xx_pwm_read(void *opaque, hwaddr offset, unsigned size)
+{
+    NPCM7xxPWMState *s = opaque;
+    uint64_t value = 0;
+
+    switch (offset) {
+    case A_NPCM7XX_PWM_CNR0:
+    case A_NPCM7XX_PWM_CNR1:
+    case A_NPCM7XX_PWM_CNR2:
+    case A_NPCM7XX_PWM_CNR3:
+        value = s->pwm[npcm7xx_cnr_index(offset)].cnr;
+        break;
+
+    case A_NPCM7XX_PWM_CMR0:
+    case A_NPCM7XX_PWM_CMR1:
+    case A_NPCM7XX_PWM_CMR2:
+    case A_NPCM7XX_PWM_CMR3:
+        value = s->pwm[npcm7xx_cmr_index(offset)].cmr;
+        break;
+
+    case A_NPCM7XX_PWM_PDR0:
+    case A_NPCM7XX_PWM_PDR1:
+    case A_NPCM7XX_PWM_PDR2:
+    case A_NPCM7XX_PWM_PDR3:
+        value = s->pwm[npcm7xx_pdr_index(offset)].pdr;
+        break;
+
+    case A_NPCM7XX_PWM_PWDR0:
+    case A_NPCM7XX_PWM_PWDR1:
+    case A_NPCM7XX_PWM_PWDR2:
+    case A_NPCM7XX_PWM_PWDR3:
+        value = s->pwm[npcm7xx_pwdr_index(offset)].pwdr;
+        break;
+
+    case A_NPCM7XX_PWM_PPR:
+        value = s->ppr;
+        break;
+
+    case A_NPCM7XX_PWM_CSR:
+        value = s->csr;
+        break;
+
+    case A_NPCM7XX_PWM_PCR:
+        value = s->pcr;
+        break;
+
+    case A_NPCM7XX_PWM_PIER:
+        value = s->pier;
+        break;
+
+    case A_NPCM7XX_PWM_PIIR:
+        value = s->piir;
+        break;
+
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
+                      __func__, offset);
+        break;
+    }
+
+    trace_npcm7xx_pwm_read(DEVICE(s)->canonical_path, offset, value);
+    return value;
+}
+
+static void npcm7xx_pwm_write(void *opaque, hwaddr offset,
+                                uint64_t v, unsigned size)
+{
+    NPCM7xxPWMState *s = opaque;
+    NPCM7xxPWM *p;
+    uint32_t value = v;
+
+    trace_npcm7xx_pwm_write(DEVICE(s)->canonical_path, offset, value);
+    switch (offset) {
+    case A_NPCM7XX_PWM_CNR0:
+    case A_NPCM7XX_PWM_CNR1:
+    case A_NPCM7XX_PWM_CNR2:
+    case A_NPCM7XX_PWM_CNR3:
+        p = &s->pwm[npcm7xx_cnr_index(offset)];
+        p->cnr = value;
+        npcm7xx_pwm_update_output(p);
+        break;
+
+    case A_NPCM7XX_PWM_CMR0:
+    case A_NPCM7XX_PWM_CMR1:
+    case A_NPCM7XX_PWM_CMR2:
+    case A_NPCM7XX_PWM_CMR3:
+        p = &s->pwm[npcm7xx_cmr_index(offset)];
+        p->cmr = value;
+        npcm7xx_pwm_update_output(p);
+        break;
+
+    case A_NPCM7XX_PWM_PDR0:
+    case A_NPCM7XX_PWM_PDR1:
+    case A_NPCM7XX_PWM_PDR2:
+    case A_NPCM7XX_PWM_PDR3:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
+                      __func__, offset);
+        break;
+
+    case A_NPCM7XX_PWM_PWDR0:
+    case A_NPCM7XX_PWM_PWDR1:
+    case A_NPCM7XX_PWM_PWDR2:
+    case A_NPCM7XX_PWM_PWDR3:
+        qemu_log_mask(LOG_UNIMP,
+                     "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n",
+                     __func__, offset);
+        break;
+
+    case A_NPCM7XX_PWM_PPR:
+        npcm7xx_pwm_write_ppr(s, value);
+        break;
+
+    case A_NPCM7XX_PWM_CSR:
+        npcm7xx_pwm_write_csr(s, value);
+        break;
+
+    case A_NPCM7XX_PWM_PCR:
+        npcm7xx_pwm_write_pcr(s, value);
+        break;
+
+    case A_NPCM7XX_PWM_PIER:
+        qemu_log_mask(LOG_UNIMP,
+                     "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n",
+                     __func__, offset);
+        break;
+
+    case A_NPCM7XX_PWM_PIIR:
+        qemu_log_mask(LOG_UNIMP,
+                     "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n",
+                     __func__, offset);
+        break;
+
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
+                      __func__, offset);
+        break;
+    }
+}
+
+static const struct MemoryRegionOps npcm7xx_pwm_ops = {
+    .read       = npcm7xx_pwm_read,
+    .write      = npcm7xx_pwm_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .valid      = {
+        .min_access_size        = 4,
+        .max_access_size        = 4,
+        .unaligned              = false,
+    },
+};
+
+static void npcm7xx_pwm_enter_reset(Object *obj, ResetType type)
+{
+    NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
+    int i;
+
+    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
+        NPCM7xxPWM *p = &s->pwm[i];
+
+        p->cnr = 0x00000000;
+        p->cmr = 0x00000000;
+        p->pdr = 0x00000000;
+        p->pwdr = 0x00000000;
+    }
+
+    s->ppr = 0x00000000;
+    s->csr = 0x00000000;
+    s->pcr = 0x00000000;
+    s->pier = 0x00000000;
+    s->piir = 0x00000000;
+}
+
+static void npcm7xx_pwm_hold_reset(Object *obj)
+{
+    NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
+    int i;
+
+    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
+        qemu_irq_lower(s->pwm[i].irq);
+    }
+}
+
+static void npcm7xx_pwm_init(Object *obj)
+{
+    NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+    int i;
+
+    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
+        NPCM7xxPWM *p = &s->pwm[i];
+        p->module = s;
+        p->index = i;
+        sysbus_init_irq(sbd, &p->irq);
+    }
+
+    memory_region_init_io(&s->iomem, obj, &npcm7xx_pwm_ops, s,
+                          TYPE_NPCM7XX_PWM, 4 * KiB);
+    sysbus_init_mmio(sbd, &s->iomem);
+    s->clock = qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL);
+
+    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
+        object_property_add_uint32_ptr(obj, "freq[*]",
+                &s->pwm[i].freq, OBJ_PROP_FLAG_READ);
+        object_property_add_uint32_ptr(obj, "duty[*]",
+                &s->pwm[i].duty, OBJ_PROP_FLAG_READ);
+    }
+}
+
+static const VMStateDescription vmstate_npcm7xx_pwm = {
+    .name = "npcm7xx-pwm",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_BOOL(running, NPCM7xxPWM),
+        VMSTATE_BOOL(inverted, NPCM7xxPWM),
+        VMSTATE_UINT8(index, NPCM7xxPWM),
+        VMSTATE_UINT32(cnr, NPCM7xxPWM),
+        VMSTATE_UINT32(cmr, NPCM7xxPWM),
+        VMSTATE_UINT32(pdr, NPCM7xxPWM),
+        VMSTATE_UINT32(pwdr, NPCM7xxPWM),
+        VMSTATE_UINT32(freq, NPCM7xxPWM),
+        VMSTATE_UINT32(duty, NPCM7xxPWM),
+        VMSTATE_END_OF_LIST(),
+    },
+};
+
+static const VMStateDescription vmstate_npcm7xx_pwm_module = {
+    .name = "npcm7xx-pwm-module",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_CLOCK(clock, NPCM7xxPWMState),
+        VMSTATE_STRUCT_ARRAY(pwm, NPCM7xxPWMState,
+                             NPCM7XX_PWM_PER_MODULE, 0, vmstate_npcm7xx_pwm,
+                             NPCM7xxPWM),
+        VMSTATE_UINT32(ppr, NPCM7xxPWMState),
+        VMSTATE_UINT32(csr, NPCM7xxPWMState),
+        VMSTATE_UINT32(pcr, NPCM7xxPWMState),
+        VMSTATE_UINT32(pier, NPCM7xxPWMState),
+        VMSTATE_UINT32(piir, NPCM7xxPWMState),
+        VMSTATE_END_OF_LIST(),
+    },
+};
+
+static void npcm7xx_pwm_class_init(ObjectClass *klass, void *data)
+{
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->desc = "NPCM7xx PWM Controller";
+    dc->vmsd = &vmstate_npcm7xx_pwm_module;
+    rc->phases.enter = npcm7xx_pwm_enter_reset;
+    rc->phases.hold = npcm7xx_pwm_hold_reset;
+}
+
+static const TypeInfo npcm7xx_pwm_info = {
+    .name               = TYPE_NPCM7XX_PWM,
+    .parent             = TYPE_SYS_BUS_DEVICE,
+    .instance_size      = sizeof(NPCM7xxPWMState),
+    .class_init         = npcm7xx_pwm_class_init,
+    .instance_init      = npcm7xx_pwm_init,
+};
+
+static void npcm7xx_pwm_register_type(void)
+{
+    type_register_static(&npcm7xx_pwm_info);
+}
+type_init(npcm7xx_pwm_register_type);
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mst_fpga.c'))
 softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files(
   'npcm7xx_clk.c',
   'npcm7xx_gcr.c',
+  'npcm7xx_pwm.c',
   'npcm7xx_rng.c',
 ))
 softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files(
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -XXX,XX +XXX,XX @@ npcm7xx_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " valu
 npcm7xx_rng_read(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
 npcm7xx_rng_write(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
 
+# npcm7xx_pwm.c
+npcm7xx_pwm_read(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
+npcm7xx_pwm_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
+npcm7xx_pwm_update_freq(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Freq: old_freq: %u, new_freq: %u"
+npcm7xx_pwm_update_duty(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Duty: old_duty: %u, new_duty: %u"
+
 # stm32f4xx_syscfg.c
 stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interupt: GPIO: %d, Line: %d; Level: %d"
 stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d"
-- 
2.20.1

From: Hao Wu <wuhaotsh@google.com>

We add a qtest for the PWM in the previous patch. It proves it works as
expected.

Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210108190945.949196-6-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/npcm7xx_pwm-test.c | 490 +++++++++++++++++++++++++++++++++
 tests/qtest/meson.build        |   1 +
 2 files changed, 491 insertions(+)
 create mode 100644 tests/qtest/npcm7xx_pwm-test.c

diff --git a/tests/qtest/npcm7xx_pwm-test.c b/tests/qtest/npcm7xx_pwm-test.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tests/qtest/npcm7xx_pwm-test.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * QTests for Nuvoton NPCM7xx PWM Modules.
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bitops.h"
+#include "libqos/libqtest.h"
+#include "qapi/qmp/qdict.h"
+#include "qapi/qmp/qnum.h"
+
+#define REF_HZ          25000000
+
+/* Register field definitions. */
+#define CH_EN           BIT(0)
+#define CH_INV          BIT(2)
+#define CH_MOD          BIT(3)
+
+/* Registers shared between all PWMs in a module */
+#define PPR             0x00
+#define CSR             0x04
+#define PCR             0x08
+#define PIER            0x3c
+#define PIIR            0x40
+
+/* CLK module related */
+#define CLK_BA          0xf0801000
+#define CLKSEL          0x04
+#define CLKDIV1         0x08
+#define CLKDIV2         0x2c
+#define PLLCON0         0x0c
+#define PLLCON1         0x10
+#define PLL_INDV(rv)    extract32((rv), 0, 6)
+#define PLL_FBDV(rv)    extract32((rv), 16, 12)
+#define PLL_OTDV1(rv)   extract32((rv), 8, 3)
+#define PLL_OTDV2(rv)   extract32((rv), 13, 3)
+#define APB3CKDIV(rv)   extract32((rv), 28, 2)
+#define CLK2CKDIV(rv)   extract32((rv), 0, 1)
+#define CLK4CKDIV(rv)   extract32((rv), 26, 2)
+#define CPUCKSEL(rv)    extract32((rv), 0, 2)
+
+#define MAX_DUTY        1000000
+
+typedef struct PWMModule {
+    int irq;
+    uint64_t base_addr;
+} PWMModule;
+
+typedef struct PWM {
+    uint32_t cnr_offset;
+    uint32_t cmr_offset;
+    uint32_t pdr_offset;
+    uint32_t pwdr_offset;
+} PWM;
+
+typedef struct TestData {
+    const PWMModule *module;
+    const PWM *pwm;
+} TestData;
+
+static const PWMModule pwm_module_list[] = {
+    {
+        .irq        = 93,
+        .base_addr  = 0xf0103000
+    },
+    {
+        .irq        = 94,
+        .base_addr  = 0xf0104000
+    }
+};
+
+static const PWM pwm_list[] = {
+    {
+        .cnr_offset     = 0x0c,
+        .cmr_offset     = 0x10,
+        .pdr_offset     = 0x14,
+        .pwdr_offset    = 0x44,
+    },
+    {
+        .cnr_offset     = 0x18,
+        .cmr_offset     = 0x1c,
+        .pdr_offset     = 0x20,
+        .pwdr_offset    = 0x48,
+    },
+    {
+        .cnr_offset     = 0x24,
+        .cmr_offset     = 0x28,
+        .pdr_offset     = 0x2c,
+        .pwdr_offset    = 0x4c,
+    },
+    {
+        .cnr_offset     = 0x30,
+        .cmr_offset     = 0x34,
+        .pdr_offset     = 0x38,
+        .pwdr_offset    = 0x50,
+    },
+};
+
+static const int ppr_base[] = { 0, 0, 8, 8 };
+static const int csr_base[] = { 0, 4, 8, 12 };
+static const int pcr_base[] = { 0, 8, 12, 16 };
+
+static const uint32_t ppr_list[] = {
+    0,
+    1,
+    10,
+    100,
+    255, /* Max possible value. */
+};
+
+static const uint32_t csr_list[] = {
+    0,
+    1,
+    2,
+    3,
+    4, /* Max possible value. */
+};
+
+static const uint32_t cnr_list[] = {
+    0,
+    1,
+    50,
+    100,
+    150,
+    200,
+    1000,
+    10000,
+    65535, /* Max possible value. */
+};
+
+static const uint32_t cmr_list[] = {
+    0,
+    1,
+    10,
+    50,
+    100,
+    150,
+    200,
+    1000,
+    10000,
+    65535, /* Max possible value. */
+};
+
+/* Returns the index of the PWM module. */
+static int pwm_module_index(const PWMModule *module)
+{
+    ptrdiff_t diff = module - pwm_module_list;
+
+    g_assert_true(diff >= 0 && diff < ARRAY_SIZE(pwm_module_list));
+
+    return diff;
+}
+
+/* Returns the index of the PWM entry. */
+static int pwm_index(const PWM *pwm)
+{
+    ptrdiff_t diff = pwm - pwm_list;
+
+    g_assert_true(diff >= 0 && diff < ARRAY_SIZE(pwm_list));
+
+    return diff;
+}
+
+static uint64_t pwm_qom_get(QTestState *qts, const char *path, const char *name)
+{
+    QDict *response;
+
+    g_test_message("Getting properties %s from %s", name, path);
+    response = qtest_qmp(qts, "{ 'execute': 'qom-get',"
+            " 'arguments': { 'path': %s, 'property': %s}}",
+            path, name);
+    /* The qom set message returns successfully. */
+    g_assert_true(qdict_haskey(response, "return"));
+    return qnum_get_uint(qobject_to(QNum, qdict_get(response, "return")));
+}
+
+static uint64_t pwm_get_freq(QTestState *qts, int module_index, int pwm_index)
+{
+    char path[100];
+    char name[100];
+
+    sprintf(path, "/machine/soc/pwm[%d]", module_index);
+    sprintf(name, "freq[%d]", pwm_index);
+
+    return pwm_qom_get(qts, path, name);
+}
+
+static uint64_t pwm_get_duty(QTestState *qts, int module_index, int pwm_index)
+{
+    char path[100];
+    char name[100];
+
+    sprintf(path, "/machine/soc/pwm[%d]", module_index);
+    sprintf(name, "duty[%d]", pwm_index);
+
+    return pwm_qom_get(qts, path, name);
+}
+
+static uint32_t get_pll(uint32_t con)
+{
+    return REF_HZ * PLL_FBDV(con) / (PLL_INDV(con) * PLL_OTDV1(con)
+            * PLL_OTDV2(con));
+}
+
+static uint64_t read_pclk(QTestState *qts)
+{
+    uint64_t freq = REF_HZ;
+    uint32_t clksel = qtest_readl(qts, CLK_BA + CLKSEL);
+    uint32_t pllcon;
+    uint32_t clkdiv1 = qtest_readl(qts, CLK_BA + CLKDIV1);
+    uint32_t clkdiv2 = qtest_readl(qts, CLK_BA + CLKDIV2);
+
+    switch (CPUCKSEL(clksel)) {
+    case 0:
+        pllcon = qtest_readl(qts, CLK_BA + PLLCON0);
+        freq = get_pll(pllcon);
+        break;
+    case 1:
+        pllcon = qtest_readl(qts, CLK_BA + PLLCON1);
+        freq = get_pll(pllcon);
+        break;
+    case 2:
+        break;
+    case 3:
+        break;
+    default:
+        g_assert_not_reached();
+    }
+
+    freq >>= (CLK2CKDIV(clkdiv1) + CLK4CKDIV(clkdiv1) + APB3CKDIV(clkdiv2));
+
+    return freq;
+}
+
+static uint32_t pwm_selector(uint32_t csr)
+{
+    switch (csr) {
+    case 0:
+        return 2;
+    case 1:
+        return 4;
+    case 2:
+        return 8;
+    case 3:
+        return 16;
+    case 4:
+        return 1;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static uint64_t pwm_compute_freq(QTestState *qts, uint32_t ppr, uint32_t csr,
+        uint32_t cnr)
+{
+    return read_pclk(qts) / ((ppr + 1) * pwm_selector(csr) * (cnr + 1));
+}
+
+static uint64_t pwm_compute_duty(uint32_t cnr, uint32_t cmr, bool inverted)
+{
+    uint64_t duty;
+
+    if (cnr == 0) {
+        /* PWM is stopped. */
+        duty = 0;
+    } else if (cmr >= cnr) {
+        duty = MAX_DUTY;
+    } else {
+        duty = MAX_DUTY * (cmr + 1) / (cnr + 1);
+    }
+
+    if (inverted) {
+        duty = MAX_DUTY - duty;
+    }
+
+    return duty;
+}
+
+static uint32_t pwm_read(QTestState *qts, const TestData *td, unsigned offset)
+{
+    return qtest_readl(qts, td->module->base_addr + offset);
+}
+
+static void pwm_write(QTestState *qts, const TestData *td, unsigned offset,
+        uint32_t value)
+{
+    qtest_writel(qts, td->module->base_addr + offset, value);
+}
+
+static uint32_t pwm_read_ppr(QTestState *qts, const TestData *td)
+{
+    return extract32(pwm_read(qts, td, PPR), ppr_base[pwm_index(td->pwm)], 8);
+}
+
+static void pwm_write_ppr(QTestState *qts, const TestData *td, uint32_t value)
+{
+    pwm_write(qts, td, PPR, value << ppr_base[pwm_index(td->pwm)]);
+}
+
+static uint32_t pwm_read_csr(QTestState *qts, const TestData *td)
+{
+    return extract32(pwm_read(qts, td, CSR), csr_base[pwm_index(td->pwm)], 3);
+}
+
+static void pwm_write_csr(QTestState *qts, const TestData *td, uint32_t value)
+{
+    pwm_write(qts, td, CSR, value << csr_base[pwm_index(td->pwm)]);
+}
+
+static uint32_t pwm_read_pcr(QTestState *qts, const TestData *td)
+{
+    return extract32(pwm_read(qts, td, PCR), pcr_base[pwm_index(td->pwm)], 4);
+}
+
+static void pwm_write_pcr(QTestState *qts, const TestData *td, uint32_t value)
+{
+    pwm_write(qts, td, PCR, value << pcr_base[pwm_index(td->pwm)]);
+}
+
+static uint32_t pwm_read_cnr(QTestState *qts, const TestData *td)
+{
+    return pwm_read(qts, td, td->pwm->cnr_offset);
+}
+
+static void pwm_write_cnr(QTestState *qts, const TestData *td, uint32_t value)
+{
+    pwm_write(qts, td, td->pwm->cnr_offset, value);
+}
+
+static uint32_t pwm_read_cmr(QTestState *qts, const TestData *td)
+{
+    return pwm_read(qts, td, td->pwm->cmr_offset);
+}
+
+static void pwm_write_cmr(QTestState *qts, const TestData *td, uint32_t value)
+{
+    pwm_write(qts, td, td->pwm->cmr_offset, value);
+}
+
+/* Check pwm registers can be reset to default value */
+static void test_init(gconstpointer test_data)
+{
+    const TestData *td = test_data;
+    QTestState *qts = qtest_init("-machine quanta-gsj");
+    int module = pwm_module_index(td->module);
+    int pwm = pwm_index(td->pwm);
+
+    g_assert_cmpuint(pwm_get_freq(qts, module, pwm), ==, 0);
+    g_assert_cmpuint(pwm_get_duty(qts, module, pwm), ==, 0);
+
+    qtest_quit(qts);
+}
+
+/* One-shot mode should not change frequency and duty cycle. */
+static void test_oneshot(gconstpointer test_data)
+{
+    const TestData *td = test_data;
+    QTestState *qts = qtest_init("-machine quanta-gsj");
+    int module = pwm_module_index(td->module);
+    int pwm = pwm_index(td->pwm);
+    uint32_t ppr, csr, pcr;
+    int i, j;
+
+    pcr = CH_EN;
+    for (i = 0; i < ARRAY_SIZE(ppr_list); ++i) {
+        ppr = ppr_list[i];
+        pwm_write_ppr(qts, td, ppr);
+
+        for (j = 0; j < ARRAY_SIZE(csr_list); ++j) {
+            csr = csr_list[j];
+            pwm_write_csr(qts, td, csr);
+            pwm_write_pcr(qts, td, pcr);
+
+            g_assert_cmpuint(pwm_read_ppr(qts, td), ==, ppr);
+            g_assert_cmpuint(pwm_read_csr(qts, td), ==, csr);
+            g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr);
+            g_assert_cmpuint(pwm_get_freq(qts, module, pwm), ==, 0);
+            g_assert_cmpuint(pwm_get_duty(qts, module, pwm), ==, 0);
+        }
+    }
+
+    qtest_quit(qts);
+}
+
+/* In toggle mode, the PWM generates correct outputs. */
+static void test_toggle(gconstpointer test_data)
+{
+    const TestData *td = test_data;
+    QTestState *qts = qtest_init("-machine quanta-gsj");
+    int module = pwm_module_index(td->module);
+    int pwm = pwm_index(td->pwm);
+    uint32_t ppr, csr, pcr, cnr, cmr;
+    int i, j, k, l;
+    uint64_t expected_freq, expected_duty;
+
+    pcr = CH_EN | CH_MOD;
+    for (i = 0; i < ARRAY_SIZE(ppr_list); ++i) {
+        ppr = ppr_list[i];
+        pwm_write_ppr(qts, td, ppr);
+
+        for (j = 0; j < ARRAY_SIZE(csr_list); ++j) {
+            csr = csr_list[j];
+            pwm_write_csr(qts, td, csr);
+
+            for (k = 0; k < ARRAY_SIZE(cnr_list); ++k) {
+                cnr = cnr_list[k];
+                pwm_write_cnr(qts, td, cnr);
+
+                for (l = 0; l < ARRAY_SIZE(cmr_list); ++l) {
+                    cmr = cmr_list[l];
+                    pwm_write_cmr(qts, td, cmr);
+                    expected_freq = pwm_compute_freq(qts, ppr, csr, cnr);
+                    expected_duty = pwm_compute_duty(cnr, cmr, false);
+
+                    pwm_write_pcr(qts, td, pcr);
+                    g_assert_cmpuint(pwm_read_ppr(qts, td), ==, ppr);
+                    g_assert_cmpuint(pwm_read_csr(qts, td), ==, csr);
+                    g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr);
+                    g_assert_cmpuint(pwm_read_cnr(qts, td), ==, cnr);
+                    g_assert_cmpuint(pwm_read_cmr(qts, td), ==, cmr);
+                    g_assert_cmpuint(pwm_get_duty(qts, module, pwm),
+                            ==, expected_duty);
+                    if (expected_duty != 0 && expected_duty != 100) {
+                        /* Duty cycle with 0 or 100 doesn't need frequency. */
+                        g_assert_cmpuint(pwm_get_freq(qts, module, pwm),
+                                ==, expected_freq);
+                    }
+
+                    /* Test inverted mode */
+                    expected_duty = pwm_compute_duty(cnr, cmr, true);
+                    pwm_write_pcr(qts, td, pcr | CH_INV);
+                    g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr | CH_INV);
+                    g_assert_cmpuint(pwm_get_duty(qts, module, pwm),
+                            ==, expected_duty);
+                    if (expected_duty != 0 && expected_duty != 100) {
+                        /* Duty cycle with 0 or 100 doesn't need frequency. */
+                        g_assert_cmpuint(pwm_get_freq(qts, module, pwm),
+                                ==, expected_freq);
+                    }
+
+                }
+            }
+        }
+    }
+
+    qtest_quit(qts);
+}
+
+static void pwm_add_test(const char *name, const TestData* td,
+        GTestDataFunc fn)
+{
+    g_autofree char *full_name = g_strdup_printf(
+            "npcm7xx_pwm/module[%d]/pwm[%d]/%s", pwm_module_index(td->module),
+            pwm_index(td->pwm), name);
+    qtest_add_data_func(full_name, td, fn);
+}
+#define add_test(name, td) pwm_add_test(#name, td, test_##name)
+
+int main(int argc, char **argv)
+{
+    TestData test_data_list[ARRAY_SIZE(pwm_module_list) * ARRAY_SIZE(pwm_list)];
+
+    g_test_init(&argc, &argv, NULL);
+
+    for (int i = 0; i < ARRAY_SIZE(pwm_module_list); ++i) {
+        for (int j = 0; j < ARRAY_SIZE(pwm_list); ++j) {
+            TestData *td = &test_data_list[i * ARRAY_SIZE(pwm_list) + j];
+
+            td->module = &pwm_module_list[i];
+            td->pwm = &pwm_list[j];
+
+            add_test(init, td);
+            add_test(oneshot, td);
+            add_test(toggle, td);
+        }
+    }
+
+    return g_test_run();
+}
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -XXX,XX +XXX,XX @@ qtests_sparc64 = \
 qtests_npcm7xx = \
   ['npcm7xx_adc-test',
    'npcm7xx_gpio-test',
+   'npcm7xx_pwm-test',
    'npcm7xx_rng-test',
    'npcm7xx_timer-test',
    'npcm7xx_watchdog_timer-test']
-- 
2.20.1

From: Hao Wu <wuhaotsh@google.com>

A device shouldn't access its parent object which is QOM internal.
Instead it should use type cast for this purporse. This patch fixes this
issue for all NPCM7XX Devices.

Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210108190945.949196-7-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/npcm7xx_boards.c | 2 +-
 hw/mem/npcm7xx_mc.c     | 2 +-
 hw/misc/npcm7xx_clk.c   | 2 +-
 hw/misc/npcm7xx_gcr.c   | 2 +-
 hw/misc/npcm7xx_rng.c   | 2 +-
 hw/nvram/npcm7xx_otp.c  | 2 +-
 hw/ssi/npcm7xx_fiu.c    | 2 +-
 7 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/npcm7xx_boards.c
+++ b/hw/arm/npcm7xx_boards.c
@@ -XXX,XX +XXX,XX @@ static NPCM7xxState *npcm7xx_create_soc(MachineState *machine,
                                         uint32_t hw_straps)
 {
     NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_GET_CLASS(machine);
-    MachineClass *mc = &nmc->parent;
+    MachineClass *mc = MACHINE_CLASS(nmc);
     Object *obj;
 
     if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
diff --git a/hw/mem/npcm7xx_mc.c b/hw/mem/npcm7xx_mc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/mem/npcm7xx_mc.c
+++ b/hw/mem/npcm7xx_mc.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_mc_realize(DeviceState *dev, Error **errp)
 
     memory_region_init_io(&s->mmio, OBJECT(s), &npcm7xx_mc_ops, s, "regs",
                           NPCM7XX_MC_REGS_SIZE);
-    sysbus_init_mmio(&s->parent, &s->mmio);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
 }
 
 static void npcm7xx_mc_class_init(ObjectClass *klass, void *data)
diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/npcm7xx_clk.c
+++ b/hw/misc/npcm7xx_clk.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_init(Object *obj)
 
     memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s,
                           TYPE_NPCM7XX_CLK, 4 * KiB);
-    sysbus_init_mmio(&s->parent, &s->iomem);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
 }
 
 static int npcm7xx_clk_post_load(void *opaque, int version_id)
diff --git a/hw/misc/npcm7xx_gcr.c b/hw/misc/npcm7xx_gcr.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/npcm7xx_gcr.c
+++ b/hw/misc/npcm7xx_gcr.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_gcr_init(Object *obj)
 
     memory_region_init_io(&s->iomem, obj, &npcm7xx_gcr_ops, s,
                           TYPE_NPCM7XX_GCR, 4 * KiB);
-    sysbus_init_mmio(&s->parent, &s->iomem);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
 }
 
 static const VMStateDescription vmstate_npcm7xx_gcr = {
diff --git a/hw/misc/npcm7xx_rng.c b/hw/misc/npcm7xx_rng.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/npcm7xx_rng.c
+++ b/hw/misc/npcm7xx_rng.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_rng_init(Object *obj)
 
     memory_region_init_io(&s->iomem, obj, &npcm7xx_rng_ops, s, "regs",
                           NPCM7XX_RNG_REGS_SIZE);
-    sysbus_init_mmio(&s->parent, &s->iomem);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
 }
 
 static const VMStateDescription vmstate_npcm7xx_rng = {
diff --git a/hw/nvram/npcm7xx_otp.c b/hw/nvram/npcm7xx_otp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/nvram/npcm7xx_otp.c
+++ b/hw/nvram/npcm7xx_otp.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_otp_realize(DeviceState *dev, Error **errp)
 {
     NPCM7xxOTPClass *oc = NPCM7XX_OTP_GET_CLASS(dev);
     NPCM7xxOTPState *s = NPCM7XX_OTP(dev);
-    SysBusDevice *sbd = &s->parent;
+    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 
     memset(s->array, 0, sizeof(s->array));
 
diff --git a/hw/ssi/npcm7xx_fiu.c b/hw/ssi/npcm7xx_fiu.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/npcm7xx_fiu.c
+++ b/hw/ssi/npcm7xx_fiu.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_fiu_hold_reset(Object *obj)
 static void npcm7xx_fiu_realize(DeviceState *dev, Error **errp)
 {
     NPCM7xxFIUState *s = NPCM7XX_FIU(dev);
-    SysBusDevice *sbd = &s->parent;
+    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
     int i;
 
     if (s->cs_count <= 0) {
-- 
2.20.1

From: Roman Bolshakov <r.bolshakov@yadro.com>

ui/cocoa.m:1188:44: warning: 'openFile:' is deprecated: first deprecated in macOS 11.0 - Use -[NSWorkspace openURL:] instead.
      [-Wdeprecated-declarations]
        if ([[NSWorkspace sharedWorkspace] openFile: full_file_path] == YES) {
                                           ^
/Library/Developer/CommandLineTools/SDKs/MacOSX.sdk/System/Library/Frameworks/AppKit.framework/Headers/NSWorkspace.h:350:1: note:
      'openFile:' has been explicitly marked deprecated here
- (BOOL)openFile:(NSString *)fullPath API_DEPRECATED("Use -[NSWorkspace openURL:] instead.", macos(10.0, 11.0));
^

Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210102150718.47618-1-r.bolshakov@yadro.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 ui/cocoa.m | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/ui/cocoa.m b/ui/cocoa.m
index XXXXXXX..XXXXXXX 100644
--- a/ui/cocoa.m
+++ b/ui/cocoa.m
@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
     /* Where to look for local files */
     NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"docs/"};
     NSString *full_file_path;
+    NSURL *full_file_url;
 
     /* iterate thru the possible paths until the file is found */
     int index;
@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
         full_file_path = [full_file_path stringByDeletingLastPathComponent];
         full_file_path = [NSString stringWithFormat: @"%@/%@%@", full_file_path,
                           path_array[index], filename];
-        if ([[NSWorkspace sharedWorkspace] openFile: full_file_path] == YES) {
+        full_file_url = [NSURL fileURLWithPath: full_file_path
+                                   isDirectory: false];
+        if ([[NSWorkspace sharedWorkspace] openURL: full_file_url] == YES) {
             return;
         }
     }
-- 
2.20.1