target-arm queue:

* mostly my latest v8M stuff, plus a couple of minor patches

The following changes since commit a0b261db8c030813e30a39eae47359ac2a37f7e2:

Merge remote-tracking branch 'remotes/ehabkost/tags/python-next-pull-request' into staging (2017-10-12 10:02:09 +0100)

are available in the git repository at:

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20171012

for you to fetch changes up to cf5f7937b05c84d5565134f058c00cd48304a117:

nvic: Fix miscalculation of offsets into ITNS array (2017-10-12 16:33:16 +0100)

* v8M: SG, BLXNS, secure-return

* v8M: fixes for coverity issues in previous patches

* arm: fix armv7m_init() declaration to match definition

* watchdog/aspeed: fix variable type to store reload value

Cédric Le Goater (1):

watchdog/aspeed: fix variable type to store reload value

Igor Mammedov (1):

arm: fix armv7m_init() declaration to match definition

Peter Maydell (11):

target/arm: Add M profile secure MMU index values to get_a32_user_mem_index()

target/arm: Implement SG instruction

target/arm: Implement BLXNS

target/arm: Implement secure function return

target-arm: Don't check for "Thumb2 or M profile" for not-Thumb1

target/arm: Pull Thumb insn word loads up to top level

target-arm: Simplify insn_crosses_page()

target/arm: Support some Thumb insns being always unconditional

target/arm: Implement SG instruction corner cases

nvic: Add missing 'break'

nvic: Fix miscalculation of offsets into ITNS array

include/hw/arm/arm.h | 2 +-

target/arm/helper.h | 1 +

target/arm/internals.h | 8 ++

hw/intc/armv7m_nvic.c | 5 +-

hw/watchdog/wdt_aspeed.c | 4 +-

target/arm/helper.c | 306 ++++++++++++++++++++++++++++++++++++++++++++--

target/arm/translate.c | 310 ++++++++++++++++++++++++++++++++---------------

7 files changed, 521 insertions(+), 115 deletions(-)

Coverity points out that we forgot the 'break' for

the SAU_CTRL write case (CID1381683). This has

no actual visible consequences because it happens

that the following case is effectively a no-op.

hw/intc/armv7m_nvic.c | 1 +

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c

--- a/hw/intc/armv7m_nvic.c

+++ b/hw/intc/armv7m_nvic.c

@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,

return;

}

cpu->env.sau.ctrl = value & 3;

+ break;

case 0xdd4: /* SAU_TYPE */

if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {

goto bad_offset;

2.7.4

Refactor the Thumb decode to do the loads of the instruction words at

the top level rather than only loading the second half of a 32-bit

Thumb insn in the middle of the decode.

This is simple apart from the awkward case of Thumb1, where the

BL/BLX prefix and suffix instructions live in what in Thumb2 is the

32-bit insn space. To handle these we decode enough to identify

whether we're looking at a prefix/suffix that we handle as a 16 bit

insn, or a prefix that we're going to merge with the following suffix

to consider as a 32 bit insn. The translation of the 16 bit cases

then moves from disas_thumb2_insn() to disas_thumb_insn().

The refactoring has the benefit that we don't need to pass the

CPUARMState* down into the decoder code any more, but the major

reason for doing this is that some Thumb instructions must be always

unconditional regardless of the IT state bits, so we need to know the

whole insn before we emit the "skip this insn if the IT bits and cond

state tell us to" code. (The always unconditional insns are BKPT,

HLT and SG; the last of these is 32 bits.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 1507556919-24992-7-git-send-email-peter.maydell@linaro.org

---

target/arm/translate.c | 178 ++++++++++++++++++++++++++++++-------------------

1 file changed, 108 insertions(+), 70 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c

--- a/target/arm/translate.c

+++ b/target/arm/translate.c

@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)

+static bool thumb_insn_is_16bit(DisasContext *s, uint32_t insn)

+{

+ /* Return true if this is a 16 bit instruction. We must be precise

+ * about this (matching the decode). We assume that s->pc still

+ * points to the first 16 bits of the insn.

+ */

+ if ((insn >> 11) < 0x1d) {

+ /* Definitely a 16-bit instruction */

+ return true;

+ }

+

+ /* Top five bits 0b11101 / 0b11110 / 0b11111 : this is the

+ * first half of a 32-bit Thumb insn. Thumb-1 cores might

+ * end up actually treating this as two 16-bit insns, though,

+ * if it's half of a bl/blx pair that might span a page boundary.

+ */

+ if (arm_dc_feature(s, ARM_FEATURE_THUMB2)) {

+ /* Thumb2 cores (including all M profile ones) always treat

+ * 32-bit insns as 32-bit.

+ */

+ return false;

+ }

+

+ if ((insn >> 11) == 0x1e && (s->pc < s->next_page_start - 3)) {

+ /* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix, and the suffix

+ * is not on the next page; we merge this into a 32-bit

+ * insn.

+ */

+ return false;

+ }

+ /* 0b1110_1xxx_xxxx_xxxx : BLX suffix (or UNDEF);

+ * 0b1111_1xxx_xxxx_xxxx : BL suffix;

+ * 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix on the end of a page

+ * -- handle as single 16 bit insn

+ */

+ return true;

+}

+

/* Return true if this is a Thumb-2 logical op. */

static int

thumb2_logic_op(int op)

@@ -XXX,XX +XXX,XX @@ gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out,

/* Translate a 32-bit thumb instruction. Returns nonzero if the instruction

is not legal. */

-static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw1)

+static int disas_thumb2_insn(DisasContext *s, uint32_t insn)

{

- uint32_t insn, imm, shift, offset;

+ uint32_t imm, shift, offset;

uint32_t rd, rn, rm, rs;

TCGv_i32 tmp;

TCGv_i32 tmp2;

@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw

int conds;

int logic_cc;

- if (!arm_dc_feature(s, ARM_FEATURE_THUMB2)) {

- /* Thumb-1 cores may need to treat bl and blx as a pair of

- 16-bit instructions to get correct prefetch abort behavior. */

- insn = insn_hw1;

- if ((insn & (1 << 12)) == 0) {

- ARCH(5);

- /* Second half of blx. */

- offset = ((insn & 0x7ff) << 1);

- tmp = load_reg(s, 14);

- tcg_gen_addi_i32(tmp, tmp, offset);

- tcg_gen_andi_i32(tmp, tmp, 0xfffffffc);

-

- tmp2 = tcg_temp_new_i32();

- tcg_gen_movi_i32(tmp2, s->pc | 1);

- store_reg(s, 14, tmp2);

- gen_bx(s, tmp);

- return 0;

- }

- if (insn & (1 << 11)) {

- /* Second half of bl. */

- offset = ((insn & 0x7ff) << 1) | 1;

- tmp = load_reg(s, 14);

- tcg_gen_addi_i32(tmp, tmp, offset);

-

- tmp2 = tcg_temp_new_i32();

- tcg_gen_movi_i32(tmp2, s->pc | 1);

- store_reg(s, 14, tmp2);

- gen_bx(s, tmp);

- return 0;

- }

- if ((s->pc & ~TARGET_PAGE_MASK) == 0) {

- /* Instruction spans a page boundary. Implement it as two

- 16-bit instructions in case the second half causes an

- prefetch abort. */

- offset = ((int32_t)insn << 21) >> 9;

- tcg_gen_movi_i32(cpu_R[14], s->pc + 2 + offset);

- return 0;

- }

- /* Fall through to 32-bit decode. */

- }

-

- insn = arm_lduw_code(env, s->pc, s->sctlr_b);

- s->pc += 2;

- insn |= (uint32_t)insn_hw1 << 16;

-

+ /* The only 32 bit insn that's allowed for Thumb1 is the combined

+ * BL/BLX prefix and suffix.

+ */

if ((insn & 0xf800e800) != 0xf000e800) {

ARCH(6T2);

-static void disas_thumb_insn(CPUARMState *env, DisasContext *s)

+static void disas_thumb_insn(DisasContext *s, uint32_t insn)

{

- uint32_t val, insn, op, rm, rn, rd, shift, cond;

+ uint32_t val, op, rm, rn, rd, shift, cond;

int32_t offset;

int i;

TCGv_i32 tmp;

TCGv_i32 tmp2;

TCGv_i32 addr;

- if (s->condexec_mask) {

- cond = s->condexec_cond;

- if (cond != 0x0e) { /* Skip conditional when condition is AL. */

- s->condlabel = gen_new_label();

- arm_gen_test_cc(cond ^ 1, s->condlabel);

- s->condjmp = 1;

- }

- }

-

- insn = arm_lduw_code(env, s->pc, s->sctlr_b);

- s->pc += 2;

-

switch (insn >> 12) {

case 0: case 1:

@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)

case 14:

if (insn & (1 << 11)) {

- if (disas_thumb2_insn(env, s, insn))

- goto undef32;

+ /* thumb_insn_is_16bit() ensures we can't get here for

+ * a Thumb2 CPU, so this must be a thumb1 split BL/BLX:

+ * 0b1110_1xxx_xxxx_xxxx : BLX suffix (or UNDEF)

+ */

+ assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2));

+ ARCH(5);

+ offset = ((insn & 0x7ff) << 1);

+ tmp = load_reg(s, 14);

+ tcg_gen_addi_i32(tmp, tmp, offset);

+ tcg_gen_andi_i32(tmp, tmp, 0xfffffffc);

+

+ tmp2 = tcg_temp_new_i32();

+ tcg_gen_movi_i32(tmp2, s->pc | 1);

+ store_reg(s, 14, tmp2);

+ gen_bx(s, tmp);

break;

}

/* unconditional branch */

@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)

break;

case 15:

- if (disas_thumb2_insn(env, s, insn))

- goto undef32;

+ /* thumb_insn_is_16bit() ensures we can't get here for

+ * a Thumb2 CPU, so this must be a thumb1 split BL/BLX.

+ */

+ assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2));

+

+ if (insn & (1 << 11)) {

+ /* 0b1111_1xxx_xxxx_xxxx : BL suffix */

+ offset = ((insn & 0x7ff) << 1) | 1;

+ tmp = load_reg(s, 14);

+ tcg_gen_addi_i32(tmp, tmp, offset);

+

+ tmp2 = tcg_temp_new_i32();

+ tcg_gen_movi_i32(tmp2, s->pc | 1);

+ store_reg(s, 14, tmp2);

+ gen_bx(s, tmp);

+ } else {

+ /* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix */

+ uint32_t uoffset = ((int32_t)insn << 21) >> 9;

+

+ tcg_gen_movi_i32(cpu_R[14], s->pc + 2 + uoffset);

+ }

break;

return;

-undef32:

- gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),

- default_exception_el(s));

- return;

illegal_op:

undef:

gen_exception_insn(s, 2, EXCP_UDEF, syn_uncategorized(),

@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)

{

DisasContext *dc = container_of(dcbase, DisasContext, base);

CPUARMState *env = cpu->env_ptr;

+ uint32_t insn;

+ bool is_16bit;

if (arm_pre_translate_insn(dc)) {

return;

- disas_thumb_insn(env, dc);

+ insn = arm_lduw_code(env, dc->pc, dc->sctlr_b);

+ is_16bit = thumb_insn_is_16bit(dc, insn);

+ dc->pc += 2;

+ if (!is_16bit) {

+ uint32_t insn2 = arm_lduw_code(env, dc->pc, dc->sctlr_b);

+

+ insn = insn << 16 | insn2;

+ dc->pc += 2;

+ }

+

+ if (dc->condexec_mask) {

+ uint32_t cond = dc->condexec_cond;

+

+ if (cond != 0x0e) { /* Skip conditional when condition is AL. */

+ dc->condlabel = gen_new_label();

+ arm_gen_test_cc(cond ^ 1, dc->condlabel);

+ dc->condjmp = 1;

+ }

+ }

+

+ if (is_16bit) {

+ disas_thumb_insn(dc, insn);

+ } else {

+ disas_thumb2_insn(dc, insn);

+ }

/* Advance the Thumb condexec condition. */

if (dc->condexec_mask) {

2.7.4

This calculation of the first exception vector in

the ITNS<n> register being accessed:

int startvec = 32 * (offset - 0x380) + NVIC_FIRST_IRQ;

is incorrect, because offset is in bytes, so we only want

to multiply by 8.

Spotted by Coverity (CID 1381484, CID 1381488), though it is

not correct that it actually overflows the buffer, because

we have a 'startvec + i < s->num_irq' guard.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 1507650856-11718-1-git-send-email-peter.maydell@linaro.org

hw/intc/armv7m_nvic.c | 4 ++--

1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c

--- a/hw/intc/armv7m_nvic.c

+++ b/hw/intc/armv7m_nvic.c

@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)

return ((s->num_irq - NVIC_FIRST_IRQ) / 32) - 1;

case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */

{

- int startvec = 32 * (offset - 0x380) + NVIC_FIRST_IRQ;

+ int startvec = 8 * (offset - 0x380) + NVIC_FIRST_IRQ;

int i;

if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {

@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,

switch (offset) {

case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */

{

- int startvec = 32 * (offset - 0x380) + NVIC_FIRST_IRQ;

+ int startvec = 8 * (offset - 0x380) + NVIC_FIRST_IRQ;

int i;

if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {

2.7.4

The common situation of the SG instruction is that it is

executed from S&NSC memory by a CPU in NS state. That case

is handled by v7m_handle_execute_nsc(). However the instruction

also has defined behaviour in a couple of other cases:

* SG instruction in NS memory (behaves as a NOP)

* SG in S memory but CPU already secure (clears IT bits and

does nothing else)

* SG instruction in v8M without Security Extension (NOP)

These can be implemented in translate.c.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 1507556919-24992-10-git-send-email-peter.maydell@linaro.org

target/arm/translate.c | 23 ++++++++++++++++++++++-

1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c

--- a/target/arm/translate.c

+++ b/target/arm/translate.c

@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(DisasContext *s, uint32_t insn)

* - load/store doubleword, load/store exclusive, ldacq/strel,

* table branch.

*/

- if (insn & 0x01200000) {

+ if (insn == 0xe97fe97f && arm_dc_feature(s, ARM_FEATURE_M) &&

+ arm_dc_feature(s, ARM_FEATURE_V8)) {

+ /* 0b1110_1001_0111_1111_1110_1001_0111_111

+ * - SG (v8M only)

+ * The bulk of the behaviour for this instruction is implemented

+ * in v7m_handle_execute_nsc(), which deals with the insn when

+ * it is executed by a CPU in non-secure state from memory

+ * which is Secure & NonSecure-Callable.

+ * Here we only need to handle the remaining cases:

+ * * in NS memory (including the "security extension not

+ * implemented" case) : NOP

+ * * in S memory but CPU already secure (clear IT bits)

+ * We know that the attribute for the memory this insn is

+ * in must match the current CPU state, because otherwise

+ * get_phys_addr_pmsav8 would have generated an exception.

+ */

+ if (s->v8m_secure) {

+ /* Like the IT insn, we don't need to generate any code */

+ s->condexec_cond = 0;

+ s->condexec_mask = 0;

+ }

+ } else if (insn & 0x01200000) {

/* 0b1110_1000_x11x_xxxx_xxxx_xxxx_xxxx_xxxx

* - load/store dual (post-indexed)

* 0b1111_1001_x10x_xxxx_xxxx_xxxx_xxxx_xxxx

2.7.4

From: Igor Mammedov <imammedo@redhat.com>

s/cpu_model/cpu_type/ that has been forgotten during

conversion (ba1ba5cc), while touching the line also

fixup alignment.

Signed-off-by: Igor Mammedov <imammedo@redhat.com>

Message-id: 1507710805-221721-1-git-send-email-imammedo@redhat.com

include/hw/arm/arm.h | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h

--- a/include/hw/arm/arm.h

+++ b/include/hw/arm/arm.h

@@ -XXX,XX +XXX,XX @@ typedef enum {

/* armv7m.c */

DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,

- const char *kernel_filename, const char *cpu_model);

+ const char *kernel_filename, const char *cpu_type);

/**

* armv7m_load_kernel:

* @cpu: CPU

2.7.4

From: Cédric Le Goater <clg@kaod.org>

Initially from Anton D. Kachalov" <mouse@yandex-team.ru> but the SoB was

missing.

Signed-off-by: Cédric Le Goater <clg@kaod.org>

Acked-by: Andrew Jeffery <andrew@aj.id.au>

Message-id: 20170920064915.30027-1-clg@kaod.org

[clg: change commit log and subject

replace UL suffix by ULL ]

Signed-off-by: Cédric Le Goater <clg@kaod.org>

hw/watchdog/wdt_aspeed.c | 4 ++--

1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c

--- a/hw/watchdog/wdt_aspeed.c

+++ b/hw/watchdog/wdt_aspeed.c

@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size)

static void aspeed_wdt_reload(AspeedWDTState *s, bool pclk)

{

- uint32_t reload;

+ uint64_t reload;

if (pclk) {

reload = muldiv64(s->regs[WDT_RELOAD_VALUE], NANOSECONDS_PER_SECOND,

s->pclk_freq);

} else {

- reload = s->regs[WDT_RELOAD_VALUE] * 1000;

+ reload = s->regs[WDT_RELOAD_VALUE] * 1000ULL;

if (aspeed_wdt_is_enabled(s)) {

2.7.4

A few Thumb instructions are always unconditional even inside an

IT block (as opposed to being UNPREDICTABLE if used inside an

IT block): BKPT, the v8M SG instruction, and the A profile

HLT (debug halt) instruction.

This means we need to suppress the jump-over-instruction-on-condfail

code generation (though the IT state still advances as usual and

subsequent insns in the IT block may be conditional).

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 1507556919-24992-9-git-send-email-peter.maydell@linaro.org

target/arm/translate.c | 48 +++++++++++++++++++++++++++++++++++++++++++++++-

1 file changed, 47 insertions(+), 1 deletion(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate.c

+++ b/target/arm/translate.c

@@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)

in init_disas_context by adjusting max_insns. */

}

+static bool thumb_insn_is_unconditional(DisasContext *s, uint32_t insn)

+ /* Return true if this Thumb insn is always unconditional,

+ * even inside an IT block. This is true of only a very few

+ * instructions: BKPT, HLT, and SG.

+ *

+ * A larger class of instructions are UNPREDICTABLE if used

+ * inside an IT block; we do not need to detect those here, because

+ * what we do by default (perform the cc check and update the IT

+ * bits state machine) is a permitted CONSTRAINED UNPREDICTABLE

+ * choice for those situations.

+ *

+ * insn is either a 16-bit or a 32-bit instruction; the two are

+ * distinguishable because for the 16-bit case the top 16 bits

+ * are zeroes, and that isn't a valid 32-bit encoding.

+ */

+ if ((insn & 0xffffff00) == 0xbe00) {

+ /* BKPT */

+ return true;

+ }

+

+ if ((insn & 0xffffffc0) == 0xba80 && arm_dc_feature(s, ARM_FEATURE_V8) &&

+ !arm_dc_feature(s, ARM_FEATURE_M)) {

+ /* HLT: v8A only. This is unconditional even when it is going to

+ * UNDEF; see the v8A ARM ARM DDI0487B.a H3.3.

+ * For v7 cores this was a plain old undefined encoding and so

+ * honours its cc check. (We might be using the encoding as

+ * a semihosting trap, but we don't change the cc check behaviour

+ * on that account, because a debugger connected to a real v7A

+ * core and emulating semihosting traps by catching the UNDEF

+ * exception would also only see cases where the cc check passed.

+ * No guest code should be trying to do a HLT semihosting trap

+ * in an IT block anyway.

+ */

+ return true;

+ }

+

+ if (insn == 0xe97fe97f && arm_dc_feature(s, ARM_FEATURE_V8) &&

+ arm_dc_feature(s, ARM_FEATURE_M)) {

+ /* SG: v8M only */

+ return true;

+ }

+

+ return false;

+

static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)

{

DisasContext *dc = container_of(dcbase, DisasContext, base);

@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)

dc->pc += 2;

}

- if (dc->condexec_mask) {

+ if (dc->condexec_mask && !thumb_insn_is_unconditional(dc, insn)) {

uint32_t cond = dc->condexec_cond;

if (cond != 0x0e) { /* Skip conditional when condition is AL. */

2.7.4

Recent changes have left insn_crosses_page() more complicated

than it needed to be:

* it's only called from thumb_tr_translate_insn() so we know

for certain that we're looking at a Thumb insn

* the caller's check for dc->pc >= dc->next_page_start - 3

means that dc->pc can't possibly be 4 aligned, so there's

no need to check that (the check was partly there to ensure

that we didn't treat an ARM insn as Thumb, I think)

* we now have thumb_insn_is_16bit() which lets us do a precise

check of the length of the next insn, rather than opencoding

an inaccurate check

Simplify it down to just loading the first half of the insn

and calling thumb_insn_is_16bit() on it.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 1507556919-24992-8-git-send-email-peter.maydell@linaro.org

target/arm/translate.c | 27 ++++++---------------------

1 file changed, 6 insertions(+), 21 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c

--- a/target/arm/translate.c

+++ b/target/arm/translate.c

@@ -XXX,XX +XXX,XX @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s)

{

/* Return true if the insn at dc->pc might cross a page boundary.

* (False positives are OK, false negatives are not.)

+ * We know this is a Thumb insn, and our caller ensures we are

+ * only called if dc->pc is less than 4 bytes from the page

+ * boundary, so we cross the page if the first 16 bits indicate

+ * that this is a 32 bit insn.

*/

- uint16_t insn;

+ uint16_t insn = arm_lduw_code(env, s->pc, s->sctlr_b);

- if ((s->pc & 3) == 0) {

- /* At a 4-aligned address we can't be crossing a page */

- return false;

- }

-

- /* This must be a Thumb insn */

- insn = arm_lduw_code(env, s->pc, s->sctlr_b);

-

- if ((insn >> 11) >= 0x1d) {

- /* Top five bits 0b11101 / 0b11110 / 0b11111 : this is the

- * First half of a 32-bit Thumb insn. Thumb-1 cores might

- * end up actually treating this as two 16-bit insns (see the

- * code at the start of disas_thumb2_insn()) but we don't bother

- * to check for that as it is unlikely, and false positives here

- * are harmless.

- */

- return true;

- }

- /* Definitely a 16-bit insn, can't be crossing a page. */

- return false;

+ return !thumb_insn_is_16bit(s, insn);

2.7.4

Implement the BLXNS instruction, which allows secure code to

call non-secure code.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 1507556919-24992-4-git-send-email-peter.maydell@linaro.org

target/arm/helper.h | 1 +

target/arm/internals.h | 1 +

target/arm/helper.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++

target/arm/translate.c | 17 +++++++++++++--

4 files changed, 76 insertions(+), 2 deletions(-)

diff --git a/target/arm/helper.h b/target/arm/helper.h

--- a/target/arm/helper.h

+++ b/target/arm/helper.h

@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(v7m_msr, void, env, i32, i32)

DEF_HELPER_2(v7m_mrs, i32, env, i32)

DEF_HELPER_2(v7m_bxns, void, env, i32)

+DEF_HELPER_2(v7m_blxns, void, env, i32)

DEF_HELPER_4(access_check_cp_reg, void, env, ptr, i32, i32)

DEF_HELPER_3(set_cp_reg, void, env, ptr, i32)

diff --git a/target/arm/internals.h b/target/arm/internals.h

--- a/target/arm/internals.h

+++ b/target/arm/internals.h

@@ -XXX,XX +XXX,XX @@ static inline bool excp_is_internal(int excp)

FIELD(V7M_CONTROL, NPRIV, 0, 1)

FIELD(V7M_CONTROL, SPSEL, 1, 1)

FIELD(V7M_CONTROL, FPCA, 2, 1)

+FIELD(V7M_CONTROL, SFPA, 3, 1)

/* Bit definitions for v7M exception return payload */

FIELD(V7M_EXCRET, ES, 0, 1)

diff --git a/target/arm/helper.c b/target/arm/helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/helper.c

+++ b/target/arm/helper.c

@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)

g_assert_not_reached();

+void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)

+ /* translate.c should never generate calls here in user-only mode */

+ g_assert_not_reached();

void switch_mode(CPUARMState *env, int mode)

{

ARMCPU *cpu = arm_env_get_cpu(env);

@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)

env->regs[15] = dest & ~1;

}

+void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)

+{

+ /* Handle v7M BLXNS:

+ * - bit 0 of the destination address is the target security state

+ */

+ /* At this point regs[15] is the address just after the BLXNS */

+ uint32_t nextinst = env->regs[15] | 1;

+ uint32_t sp = env->regs[13] - 8;

+ uint32_t saved_psr;

+

+ /* translate.c will have made BLXNS UNDEF unless we're secure */

+ assert(env->v7m.secure);

+

+ if (dest & 1) {

+ /* target is Secure, so this is just a normal BLX,

+ * except that the low bit doesn't indicate Thumb/not.

+ */

+ env->regs[14] = nextinst;

+ env->thumb = 1;

+ env->regs[15] = dest & ~1;

+ return;

+ }

+

+ /* Target is non-secure: first push a stack frame */

+ if (!QEMU_IS_ALIGNED(sp, 8)) {

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "BLXNS with misaligned SP is UNPREDICTABLE\n");

+ }

+

+ saved_psr = env->v7m.exception;

+ if (env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK) {

+ saved_psr |= XPSR_SFPA;

+ }

+

+ /* Note that these stores can throw exceptions on MPU faults */

+ cpu_stl_data(env, sp, nextinst);

+ cpu_stl_data(env, sp + 4, saved_psr);

+

+ env->regs[13] = sp;

+ env->regs[14] = 0xfeffffff;

+ if (arm_v7m_is_handler_mode(env)) {

+ /* Write a dummy value to IPSR, to avoid leaking the current secure

+ * exception number to non-secure code. This is guaranteed not

+ * to cause write_v7m_exception() to actually change stacks.

+ */

+ write_v7m_exception(env, 1);

+ }

+ switch_v7m_security_state(env, 0);

+ env->thumb = 1;

+ env->regs[15] = dest;

+}

+

static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode,

bool spsel)

{

diff --git a/target/arm/translate.c b/target/arm/translate.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate.c

+++ b/target/arm/translate.c

@@ -XXX,XX +XXX,XX @@ static inline void gen_bxns(DisasContext *s, int rm)

s->base.is_jmp = DISAS_EXIT;

}

+static inline void gen_blxns(DisasContext *s, int rm)

+{

+ TCGv_i32 var = load_reg(s, rm);

+

+ /* We don't need to sync condexec state, for the same reason as bxns.

+ * We do however need to set the PC, because the blxns helper reads it.

+ * The blxns helper may throw an exception.

+ */

+ gen_set_pc_im(s, s->pc);

+ gen_helper_v7m_blxns(cpu_env, var);

+ tcg_temp_free_i32(var);

+ s->base.is_jmp = DISAS_EXIT;

+}

+

/* Variant of store_reg which uses branch&exchange logic when storing

to r15 in ARM architecture v7 and above. The source must be a temporary

and will be marked as dead. */

@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)

goto undef;

}

if (link) {

- /* BLXNS: not yet implemented */

- goto undef;

+ gen_blxns(s, rm);

} else {

gen_bxns(s, rm);

}

2.7.4