Series comparison

-[Qemu-devel] [PULL 00/13] target-arm queue
+[Qemu-devel] [PULL 00/25] target-arm queue
-target-arm queue:
+target-arm queue. This has the "plumb txattrs through various
- * mostly my latest v8M stuff, plus a couple of minor patches
+bits of exec.c" patches, and a collection of bug fixes from
 various people.
-The following changes since commit a0b261db8c030813e30a39eae47359ac2a37f7e2:
+thanks
 -- PMM
-  Merge remote-tracking branch 'remotes/ehabkost/tags/python-next-pull-request' into staging (2017-10-12 10:02:09 +0100)
-are available in the git repository at:
-  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20171012
+The following changes since commit a3ac12fba028df90f7b3dbec924995c126c41022:
-for you to fetch changes up to cf5f7937b05c84d5565134f058c00cd48304a117:
+  Merge remote-tracking branch 'remotes/ehabkost/tags/numa-next-pull-request' into staging (2018-05-31 11:12:36 +0100)
-  nvic: Fix miscalculation of offsets into ITNS array (2017-10-12 16:33:16 +0100)
+are available in the Git repository at:
   git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180531
 for you to fetch changes up to 49d1dca0520ea71bc21867fab6647f474fcf857b:
   KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice (2018-05-31 14:52:53 +0100)
 ----------------------------------------------------------------
 target-arm queue:
- * v8M: SG, BLXNS, secure-return
+ * target/arm: Honour FPCR.FZ in FRECPX
- * v8M: fixes for coverity issues in previous patches
+ * MAINTAINERS: Add entries for newer MPS2 boards and devices
- * arm: fix armv7m_init() declaration to match definition
+ * hw/intc/arm_gicv3: Fix APxR<n> register dispatching
- * watchdog/aspeed: fix variable type to store reload value
+ * arm_gicv3_kvm: fix bug in writing zero bits back to the in-kernel
    GIC state
  * tcg: Fix helper function vs host abi for float16
  * arm: fix qemu crash on startup with -bios option
  * arm: fix malloc type mismatch
  * xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors
  * Correct CPACR reset value for v7 cores
  * memory.h: Improve IOMMU related documentation
  * exec: Plumb transaction attributes through various functions in
    preparation for allowing IOMMUs to see them
  * vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY
  * ARM: ACPI: Fix use-after-free due to memory realloc
  * KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice
 ----------------------------------------------------------------
-Cédric Le Goater (1):
+Francisco Iglesias (1):
-      watchdog/aspeed: fix variable type to store reload value
+      xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors
 Igor Mammedov (1):
-      arm: fix armv7m_init() declaration to match definition
+      arm: fix qemu crash on startup with -bios option
-Peter Maydell (11):
+Jan Kiszka (1):
-      target/arm: Add M profile secure MMU index values to get_a32_user_mem_index()
+      hw/intc/arm_gicv3: Fix APxR<n> register dispatching
       target/arm: Implement SG instruction
       target/arm: Implement BLXNS
       target/arm: Implement secure function return
       target-arm: Don't check for "Thumb2 or M profile" for not-Thumb1
       target/arm: Pull Thumb insn word loads up to top level
       target-arm: Simplify insn_crosses_page()
       target/arm: Support some Thumb insns being always unconditional
       target/arm: Implement SG instruction corner cases
       nvic: Add missing 'break'
       nvic: Fix miscalculation of offsets into ITNS array
- include/hw/arm/arm.h     |   2 +-
+Paolo Bonzini (1):
- target/arm/helper.h      |   1 +
+      arm: fix malloc type mismatch
  target/arm/internals.h   |   8 ++
  hw/intc/armv7m_nvic.c    |   5 +-
  hw/watchdog/wdt_aspeed.c |   4 +-
  target/arm/helper.c      | 306 ++++++++++++++++++++++++++++++++++++++++++++--
  target/arm/translate.c   | 310 ++++++++++++++++++++++++++++++++---------------
 files changed, 521 insertions(+), 115 deletions(-)
+Peter Maydell (17):
+      target/arm: Honour FPCR.FZ in FRECPX
+      MAINTAINERS: Add entries for newer MPS2 boards and devices
+      Correct CPACR reset value for v7 cores
+      memory.h: Improve IOMMU related documentation
+      Make tb_invalidate_phys_addr() take a MemTxAttrs argument
+      Make address_space_translate{, _cached}() take a MemTxAttrs argument
+      Make address_space_map() take a MemTxAttrs argument
+      Make address_space_access_valid() take a MemTxAttrs argument
+      Make flatview_extend_translation() take a MemTxAttrs argument
+      Make memory_region_access_valid() take a MemTxAttrs argument
+      Make MemoryRegion valid.accepts callback take a MemTxAttrs argument
+      Make flatview_access_valid() take a MemTxAttrs argument
+      Make flatview_translate() take a MemTxAttrs argument
+      Make address_space_get_iotlb_entry() take a MemTxAttrs argument
+      Make flatview_do_translate() take a MemTxAttrs argument
+      Make address_space_translate_iommu take a MemTxAttrs argument
+      vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY
+Richard Henderson (1):
+      tcg: Fix helper function vs host abi for float16
+Shannon Zhao (3):
+      arm_gicv3_kvm: increase clroffset accordingly
+      ARM: ACPI: Fix use-after-free due to memory realloc
+      KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice
+ include/exec/exec-all.h        |   5 +-
+ include/exec/helper-head.h     |   2 +-
+ include/exec/memory-internal.h |   3 +-
+ include/exec/memory.h          | 128 +++++++++++++++++++++++++++++++++++------
+ include/migration/vmstate.h    |   3 +
+ include/sysemu/dma.h           |   6 +-
+ accel/tcg/translate-all.c      |   4 +-
+ exec.c                         |  95 ++++++++++++++++++------------
+ hw/arm/boot.c                  |  18 +++---
+ hw/arm/virt-acpi-build.c       |  20 +++++--
+ hw/dma/xlnx-zdma.c             |  10 +++-
+ hw/hppa/dino.c                 |   3 +-
+ hw/intc/arm_gic_kvm.c          |   1 -
+ hw/intc/arm_gicv3_cpuif.c      |  12 ++--
+ hw/intc/arm_gicv3_kvm.c        |   2 +-
+ hw/nvram/fw_cfg.c              |  12 ++--
+ hw/s390x/s390-pci-inst.c       |   3 +-
+ hw/scsi/esp.c                  |   3 +-
+ hw/vfio/common.c               |   3 +-
+ hw/virtio/vhost.c              |   3 +-
+ hw/xen/xen_pt_msi.c            |   3 +-
+ memory.c                       |  12 ++--
+ memory_ldst.inc.c              |  18 +++---
+ target/arm/gdbstub.c           |   3 +-
+ target/arm/helper-a64.c        |  41 +++++++------
+ target/arm/helper.c            |  90 ++++++++++++++++-------------
+ target/ppc/mmu-hash64.c        |   3 +-
+ target/riscv/helper.c          |   2 +-
+ target/s390x/diag.c            |   6 +-
+ target/s390x/excp_helper.c     |   3 +-
+ target/s390x/mmu_helper.c      |   3 +-
+ target/s390x/sigp.c            |   3 +-
+ target/xtensa/op_helper.c      |   3 +-
+ MAINTAINERS                    |   9 ++-
+files changed, 353 insertions(+), 182 deletions(-)

-[Qemu-devel] [PULL 13/13] nvic: Fix miscalculation of offsets into ITNS array
+[Qemu-devel] [PULL 01/25] target/arm: Honour FPCR.FZ in FRECPX
-This calculation of the first exception vector in
+The FRECPX instructions should (like most other floating point operations)
-the ITNS<n> register being accessed:
+honour the FPCR.FZ bit which specifies whether input denormals should
-        int startvec = 32 * (offset - 0x380) + NVIC_FIRST_IRQ;
+be flushed to zero (or FZ16 for the half-precision version).
+We forgot to implement this, which doesn't affect the results (since
-is incorrect, because offset is in bytes, so we only want
+the calculation doesn't actually care about the mantissa bits) but did
-to multiply by 8.
+mean we were failing to set the FPSR.IDC bit.
 Spotted by Coverity (CID 1381484, CID 1381488), though it is
 not correct that it actually overflows the buffer, because
 we have a 'startvec + i < s->num_irq' guard.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 1507650856-11718-1-git-send-email-peter.maydell@linaro.org
+Message-id: 20180521172712.19930-1-peter.maydell@linaro.org
 ---
- hw/intc/armv7m_nvic.c | 4 ++--
+ target/arm/helper-a64.c | 6 ++++++
-file changed, 2 insertions(+), 2 deletions(-)
+file changed, 6 insertions(+)
-diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
+diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/armv7m_nvic.c
+--- a/target/arm/helper-a64.c
-+++ b/hw/intc/armv7m_nvic.c
++++ b/target/arm/helper-a64.c
-@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
+@@ -XXX,XX +XXX,XX @@ float16 HELPER(frecpx_f16)(float16 a, void *fpstp)
-         return ((s->num_irq - NVIC_FIRST_IRQ) / 32) - 1;
+         return nan;
-     case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */
+     }
-     {
--        int startvec = 32 * (offset - 0x380) + NVIC_FIRST_IRQ;
++    a = float16_squash_input_denormal(a, fpst);
-+        int startvec = 8 * (offset - 0x380) + NVIC_FIRST_IRQ;
++
-         int i;
+     val16 = float16_val(a);
+     sbit = 0x8000 & val16;
-         if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
+     exp = extract32(val16, 10, 5);
-@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
+@@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
-     switch (offset) {
+         return nan;
-     case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */
+     }
-     {
--        int startvec = 32 * (offset - 0x380) + NVIC_FIRST_IRQ;
++    a = float32_squash_input_denormal(a, fpst);
-+        int startvec = 8 * (offset - 0x380) + NVIC_FIRST_IRQ;
++
-         int i;
+     val32 = float32_val(a);
+     sbit = 0x80000000ULL & val32;
-         if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
+     exp = extract32(val32, 23, 8);
@@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
          return nan;
      }
 +    a = float64_squash_input_denormal(a, fpst);
 +
      val64 = float64_val(a);
      sbit = 0x8000000000000000ULL & val64;
      exp = extract64(float64_val(a), 52, 11);
 --
-.7.4
+.17.1

-New patch
+[Qemu-devel] [PULL 02/25] MAINTAINERS: Add entries for newer MPS2 boards and devices
+Add entries to MAINTAINERS to cover the newer MPS2 boards and
+the new devices they use.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20180518153157.14899-1-peter.maydell@linaro.org
+---
+ MAINTAINERS | 9 +++++++--
+file changed, 7 insertions(+), 2 deletions(-)
+diff --git a/MAINTAINERS b/MAINTAINERS
+index XXXXXXX..XXXXXXX 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -XXX,XX +XXX,XX @@ F: hw/timer/cmsdk-apb-timer.c
+ F: include/hw/timer/cmsdk-apb-timer.h
+ F: hw/char/cmsdk-apb-uart.c
+ F: include/hw/char/cmsdk-apb-uart.h
++F: hw/misc/tz-ppc.c
++F: include/hw/misc/tz-ppc.h
+ ARM cores
+ M: Peter Maydell <peter.maydell@linaro.org>
+@@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org>
+ L: qemu-arm@nongnu.org
+ S: Maintained
+ F: hw/arm/mps2.c
+-F: hw/misc/mps2-scc.c
+-F: include/hw/misc/mps2-scc.h
++F: hw/arm/mps2-tz.c
++F: hw/misc/mps2-*.c
++F: include/hw/misc/mps2-*.h
++F: hw/arm/iotkit.c
++F: include/hw/arm/iotkit.h
+ Musicpal
+ M: Jan Kiszka <jan.kiszka@web.de>
+--
+.17.1

-New patch
+[Qemu-devel] [PULL 03/25] hw/intc/arm_gicv3: Fix APxR<n> register dispatching
+From: Jan Kiszka <jan.kiszka@siemens.com>
+There was a nasty flip in identifying which register group an access is
+targeting. The issue caused spuriously raised priorities of the guest
+when handing CPUs over in the Jailhouse hypervisor.
+Cc: qemu-stable@nongnu.org
+Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
+Message-id: 28b927d3-da58-bce4-cc13-bfec7f9b1cb9@siemens.com
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/intc/arm_gicv3_cpuif.c | 12 ++++++------
+file changed, 6 insertions(+), 6 deletions(-)
+diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/intc/arm_gicv3_cpuif.c
++++ b/hw/intc/arm_gicv3_cpuif.c
+@@ -XXX,XX +XXX,XX @@ static uint64_t icv_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
+ {
+     GICv3CPUState *cs = icc_cs_from_env(env);
+     int regno = ri->opc2 & 3;
+-    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
++    int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
+     uint64_t value = cs->ich_apr[grp][regno];
+     trace_gicv3_icv_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
+@@ -XXX,XX +XXX,XX @@ static void icv_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ {
+     GICv3CPUState *cs = icc_cs_from_env(env);
+     int regno = ri->opc2 & 3;
+-    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
++    int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
+     trace_gicv3_icv_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
+@@ -XXX,XX +XXX,XX @@ static uint64_t icc_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
+     uint64_t value;
+     int regno = ri->opc2 & 3;
+-    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;
++    int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0;
+     if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
+         return icv_ap_read(env, ri);
+@@ -XXX,XX +XXX,XX @@ static void icc_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
+     GICv3CPUState *cs = icc_cs_from_env(env);
+     int regno = ri->opc2 & 3;
+-    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;
++    int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0;
+     if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
+         icv_ap_write(env, ri, value);
+@@ -XXX,XX +XXX,XX @@ static uint64_t ich_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
+ {
+     GICv3CPUState *cs = icc_cs_from_env(env);
+     int regno = ri->opc2 & 3;
+-    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
++    int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
+     uint64_t value;
+     value = cs->ich_apr[grp][regno];
+@@ -XXX,XX +XXX,XX @@ static void ich_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ {
+     GICv3CPUState *cs = icc_cs_from_env(env);
+     int regno = ri->opc2 & 3;
+-    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
++    int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
+     trace_gicv3_ich_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
+--
+.17.1

-New patch
+[Qemu-devel] [PULL 04/25] arm_gicv3_kvm: increase clroffset accordingly
+From: Shannon Zhao <zhaoshenglong@huawei.com>
+It forgot to increase clroffset during the loop. So it only clear the
+first 4 bytes.
+Fixes: 367b9f527becdd20ddf116e17a3c0c2bbc486920
+Cc: qemu-stable@nongnu.org
+Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
+Message-id: 1527047633-12368-1-git-send-email-zhaoshenglong@huawei.com
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/intc/arm_gicv3_kvm.c | 1 +
+file changed, 1 insertion(+)
+diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/intc/arm_gicv3_kvm.c
++++ b/hw/intc/arm_gicv3_kvm.c
+@@ -XXX,XX +XXX,XX @@ static void kvm_dist_putbmp(GICv3State *s, uint32_t offset,
+         if (clroffset != 0) {
+             reg = 0;
+             kvm_gicd_access(s, clroffset, &reg, true);
++            clroffset += 4;
+         }
+         reg = *gic_bmp_ptr32(bmp, irq);
+         kvm_gicd_access(s, offset, &reg, true);
+--
+.17.1

-New patch
+[Qemu-devel] [PULL 05/25] tcg: Fix helper function vs host abi for float16
+From: Richard Henderson <richard.henderson@linaro.org>
 Depending on the host abi, float16, aka uint16_t, values are
 passed and returned either zero-extended in the host register
 or with garbage at the top of the host register.
 The tcg code generator has so far been assuming garbage, as that
 matches the x86 abi, but this is incorrect for other host abis.
 Further, target/arm has so far been assuming zero-extended results,
 so that it may store the 16-bit value into a 32-bit slot with the
 high 16-bits already clear.
 Rectify both problems by mapping "f16" in the helper definition
 to uint32_t instead of (a typedef for) uint16_t.  This forces
 the host compiler to assume garbage in the upper 16 bits on input
 and to zero-extend the result on output.
 Cc: qemu-stable@nongnu.org
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
 Message-id: 20180522175629.24932-1-richard.henderson@linaro.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  include/exec/helper-head.h |  2 +-
  target/arm/helper-a64.c    | 35 +++++++++--------
  target/arm/helper.c        | 80 +++++++++++++++++++-------------------
 files changed, 59 insertions(+), 58 deletions(-)
 diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/exec/helper-head.h
 +++ b/include/exec/helper-head.h
@@ -XXX,XX +XXX,XX @@
  #define dh_ctype_int int
  #define dh_ctype_i64 uint64_t
  #define dh_ctype_s64 int64_t
 -#define dh_ctype_f16 float16
 +#define dh_ctype_f16 uint32_t
  #define dh_ctype_f32 float32
  #define dh_ctype_f64 float64
  #define dh_ctype_ptr void *
 diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper-a64.c
 +++ b/target/arm/helper-a64.c
@@ -XXX,XX +XXX,XX @@ static inline uint32_t float_rel_to_flags(int res)
      return flags;
  }
 -uint64_t HELPER(vfp_cmph_a64)(float16 x, float16 y, void *fp_status)
 +uint64_t HELPER(vfp_cmph_a64)(uint32_t x, uint32_t y, void *fp_status)
  {
      return float_rel_to_flags(float16_compare_quiet(x, y, fp_status));
  }
 -uint64_t HELPER(vfp_cmpeh_a64)(float16 x, float16 y, void *fp_status)
 +uint64_t HELPER(vfp_cmpeh_a64)(uint32_t x, uint32_t y, void *fp_status)
  {
      return float_rel_to_flags(float16_compare(x, y, fp_status));
  }
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
  #define float64_three make_float64(0x4008000000000000ULL)
  #define float64_one_point_five make_float64(0x3FF8000000000000ULL)
 -float16 HELPER(recpsf_f16)(float16 a, float16 b, void *fpstp)
 +uint32_t HELPER(recpsf_f16)(uint32_t a, uint32_t b, void *fpstp)
  {
      float_status *fpst = fpstp;
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp)
      return float64_muladd(a, b, float64_two, 0, fpst);
  }
 -float16 HELPER(rsqrtsf_f16)(float16 a, float16 b, void *fpstp)
 +uint32_t HELPER(rsqrtsf_f16)(uint32_t a, uint32_t b, void *fpstp)
  {
      float_status *fpst = fpstp;
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_addlp_u16)(uint64_t a)
  }
  /* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */
 -float16 HELPER(frecpx_f16)(float16 a, void *fpstp)
 +uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
  {
      float_status *fpst = fpstp;
      uint16_t val16, sbit;
@@ -XXX,XX +XXX,XX @@ void HELPER(casp_be_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr,
  #define ADVSIMD_HELPER(name, suffix) HELPER(glue(glue(advsimd_, name), suffix))
  #define ADVSIMD_HALFOP(name) \
 -float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \
 +uint32_t ADVSIMD_HELPER(name, h)(uint32_t a, uint32_t b, void *fpstp) \
  { \
      float_status *fpst = fpstp; \
      return float16_ ## name(a, b, fpst);    \
@@ -XXX,XX +XXX,XX @@ ADVSIMD_HALFOP(mulx)
  ADVSIMD_TWOHALFOP(mulx)
  /* fused multiply-accumulate */
 -float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp)
 +uint32_t HELPER(advsimd_muladdh)(uint32_t a, uint32_t b, uint32_t c,
 +                                 void *fpstp)
  {
      float_status *fpst = fpstp;
      return float16_muladd(a, b, c, 0, fpst);
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_muladd2h)(uint32_t two_a, uint32_t two_b,
  #define ADVSIMD_CMPRES(test) (test) ? 0xffff : 0
 -uint32_t HELPER(advsimd_ceq_f16)(float16 a, float16 b, void *fpstp)
 +uint32_t HELPER(advsimd_ceq_f16)(uint32_t a, uint32_t b, void *fpstp)
  {
      float_status *fpst = fpstp;
      int compare = float16_compare_quiet(a, b, fpst);
      return ADVSIMD_CMPRES(compare == float_relation_equal);
  }
 -uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp)
 +uint32_t HELPER(advsimd_cge_f16)(uint32_t a, uint32_t b, void *fpstp)
  {
      float_status *fpst = fpstp;
      int compare = float16_compare(a, b, fpst);
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp)
                            compare == float_relation_equal);
  }
 -uint32_t HELPER(advsimd_cgt_f16)(float16 a, float16 b, void *fpstp)
 +uint32_t HELPER(advsimd_cgt_f16)(uint32_t a, uint32_t b, void *fpstp)
  {
      float_status *fpst = fpstp;
      int compare = float16_compare(a, b, fpst);
      return ADVSIMD_CMPRES(compare == float_relation_greater);
  }
 -uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp)
 +uint32_t HELPER(advsimd_acge_f16)(uint32_t a, uint32_t b, void *fpstp)
  {
      float_status *fpst = fpstp;
      float16 f0 = float16_abs(a);
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp)
                            compare == float_relation_equal);
  }
 -uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
 +uint32_t HELPER(advsimd_acgt_f16)(uint32_t a, uint32_t b, void *fpstp)
  {
      float_status *fpst = fpstp;
      float16 f0 = float16_abs(a);
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
  }
  /* round to integral */
 -float16 HELPER(advsimd_rinth_exact)(float16 x, void *fp_status)
 +uint32_t HELPER(advsimd_rinth_exact)(uint32_t x, void *fp_status)
  {
      return float16_round_to_int(x, fp_status);
  }
 -float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)
 +uint32_t HELPER(advsimd_rinth)(uint32_t x, void *fp_status)
  {
      int old_flags = get_float_exception_flags(fp_status), new_flags;
      float16 ret;
@@ -XXX,XX +XXX,XX @@ float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)
   * setting the mode appropriately before calling the helper.
   */
 -uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp)
 +uint32_t HELPER(advsimd_f16tosinth)(uint32_t a, void *fpstp)
  {
      float_status *fpst = fpstp;
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp)
      return float16_to_int16(a, fpst);
  }
 -uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
 +uint32_t HELPER(advsimd_f16touinth)(uint32_t a, void *fpstp)
  {
      float_status *fpst = fpstp;
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
   * Square Root and Reciprocal square root
   */
 -float16 HELPER(sqrt_f16)(float16 a, void *fpstp)
 +uint32_t HELPER(sqrt_f16)(uint32_t a, void *fpstp)
  {
      float_status *s = fpstp;
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ DO_VFP_cmp(d, float64)
  /* Integer to float and float to integer conversions */
 -#define CONV_ITOF(name, fsz, sign) \
 -    float##fsz HELPER(name)(uint32_t x, void *fpstp) \
 -{ \
 -    float_status *fpst = fpstp; \
 -    return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
 +#define CONV_ITOF(name, ftype, fsz, sign)                           \
 +ftype HELPER(name)(uint32_t x, void *fpstp)                         \
 +{                                                                   \
 +    float_status *fpst = fpstp;                                     \
 +    return sign##int32_to_##float##fsz((sign##int32_t)x, fpst);     \
  }
 -#define CONV_FTOI(name, fsz, sign, round) \
 -uint32_t HELPER(name)(float##fsz x, void *fpstp) \
 -{ \
 -    float_status *fpst = fpstp; \
 -    if (float##fsz##_is_any_nan(x)) { \
 -        float_raise(float_flag_invalid, fpst); \
 -        return 0; \
 -    } \
 -    return float##fsz##_to_##sign##int32##round(x, fpst); \
 +#define CONV_FTOI(name, ftype, fsz, sign, round)                \
 +uint32_t HELPER(name)(ftype x, void *fpstp)                     \
 +{                                                               \
 +    float_status *fpst = fpstp;                                 \
 +    if (float##fsz##_is_any_nan(x)) {                           \
 +        float_raise(float_flag_invalid, fpst);                  \
 +        return 0;                                               \
 +    }                                                           \
 +    return float##fsz##_to_##sign##int32##round(x, fpst);       \
  }
 -#define FLOAT_CONVS(name, p, fsz, sign) \
 -CONV_ITOF(vfp_##name##to##p, fsz, sign) \
 -CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
 -CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
 +#define FLOAT_CONVS(name, p, ftype, fsz, sign)            \
 +    CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign)        \
 +    CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, )        \
 +    CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero)
 -FLOAT_CONVS(si, h, 16, )
 -FLOAT_CONVS(si, s, 32, )
 -FLOAT_CONVS(si, d, 64, )
 -FLOAT_CONVS(ui, h, 16, u)
 -FLOAT_CONVS(ui, s, 32, u)
 -FLOAT_CONVS(ui, d, 64, u)
 +FLOAT_CONVS(si, h, uint32_t, 16, )
 +FLOAT_CONVS(si, s, float32, 32, )
 +FLOAT_CONVS(si, d, float64, 64, )
 +FLOAT_CONVS(ui, h, uint32_t, 16, u)
 +FLOAT_CONVS(ui, s, float32, 32, u)
 +FLOAT_CONVS(ui, d, float64, 64, u)
  #undef CONV_ITOF
  #undef CONV_FTOI
@@ -XXX,XX +XXX,XX @@ static float16 do_postscale_fp16(float64 f, int shift, float_status *fpst)
      return float64_to_float16(float64_scalbn(f, -shift, fpst), true, fpst);
  }
 -float16 HELPER(vfp_sltoh)(uint32_t x, uint32_t shift, void *fpst)
 +uint32_t HELPER(vfp_sltoh)(uint32_t x, uint32_t shift, void *fpst)
  {
      return do_postscale_fp16(int32_to_float64(x, fpst), shift, fpst);
  }
 -float16 HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
 +uint32_t HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
  {
      return do_postscale_fp16(uint32_to_float64(x, fpst), shift, fpst);
  }
 -float16 HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
 +uint32_t HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
  {
      return do_postscale_fp16(int64_to_float64(x, fpst), shift, fpst);
  }
 -float16 HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
 +uint32_t HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
  {
      return do_postscale_fp16(uint64_to_float64(x, fpst), shift, fpst);
  }
@@ -XXX,XX +XXX,XX @@ static float64 do_prescale_fp16(float16 f, int shift, float_status *fpst)
      }
  }
 -uint32_t HELPER(vfp_toshh)(float16 x, uint32_t shift, void *fpst)
 +uint32_t HELPER(vfp_toshh)(uint32_t x, uint32_t shift, void *fpst)
  {
      return float64_to_int16(do_prescale_fp16(x, shift, fpst), fpst);
  }
 -uint32_t HELPER(vfp_touhh)(float16 x, uint32_t shift, void *fpst)
 +uint32_t HELPER(vfp_touhh)(uint32_t x, uint32_t shift, void *fpst)
  {
      return float64_to_uint16(do_prescale_fp16(x, shift, fpst), fpst);
  }
 -uint32_t HELPER(vfp_toslh)(float16 x, uint32_t shift, void *fpst)
 +uint32_t HELPER(vfp_toslh)(uint32_t x, uint32_t shift, void *fpst)
  {
      return float64_to_int32(do_prescale_fp16(x, shift, fpst), fpst);
  }
 -uint32_t HELPER(vfp_toulh)(float16 x, uint32_t shift, void *fpst)
 +uint32_t HELPER(vfp_toulh)(uint32_t x, uint32_t shift, void *fpst)
  {
      return float64_to_uint32(do_prescale_fp16(x, shift, fpst), fpst);
  }
 -uint64_t HELPER(vfp_tosqh)(float16 x, uint32_t shift, void *fpst)
 +uint64_t HELPER(vfp_tosqh)(uint32_t x, uint32_t shift, void *fpst)
  {
      return float64_to_int64(do_prescale_fp16(x, shift, fpst), fpst);
  }
 -uint64_t HELPER(vfp_touqh)(float16 x, uint32_t shift, void *fpst)
 +uint64_t HELPER(vfp_touqh)(uint32_t x, uint32_t shift, void *fpst)
  {
      return float64_to_uint64(do_prescale_fp16(x, shift, fpst), fpst);
  }
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
  }
  /* Half precision conversions.  */
 -float32 HELPER(vfp_fcvt_f16_to_f32)(float16 a, void *fpstp, uint32_t ahp_mode)
 +float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode)
  {
      /* Squash FZ16 to 0 for the duration of conversion.  In this case,
       * it would affect flushing input denormals.
@@ -XXX,XX +XXX,XX @@ float32 HELPER(vfp_fcvt_f16_to_f32)(float16 a, void *fpstp, uint32_t ahp_mode)
      return r;
  }
 -float16 HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
 +uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
  {
      /* Squash FZ16 to 0 for the duration of conversion.  In this case,
       * it would affect flushing output denormals.
@@ -XXX,XX +XXX,XX @@ float16 HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
      return r;
  }
 -float64 HELPER(vfp_fcvt_f16_to_f64)(float16 a, void *fpstp, uint32_t ahp_mode)
 +float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode)
  {
      /* Squash FZ16 to 0 for the duration of conversion.  In this case,
       * it would affect flushing input denormals.
@@ -XXX,XX +XXX,XX @@ float64 HELPER(vfp_fcvt_f16_to_f64)(float16 a, void *fpstp, uint32_t ahp_mode)
      return r;
  }
 -float16 HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)
 +uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)
  {
      /* Squash FZ16 to 0 for the duration of conversion.  In this case,
       * it would affect flushing output denormals.
@@ -XXX,XX +XXX,XX @@ static bool round_to_inf(float_status *fpst, bool sign_bit)
      g_assert_not_reached();
  }
 -float16 HELPER(recpe_f16)(float16 input, void *fpstp)
 +uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
  {
      float_status *fpst = fpstp;
      float16 f16 = float16_squash_input_denormal(input, fpst);
@@ -XXX,XX +XXX,XX @@ static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac)
      return extract64(estimate, 0, 8) << 44;
  }
 -float16 HELPER(rsqrte_f16)(float16 input, void *fpstp)
 +uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
  {
      float_status *s = fpstp;
      float16 f16 = float16_squash_input_denormal(input, s);
 --
 .17.1

-[Qemu-devel] [PULL 02/13] arm: fix armv7m_init() declaration to match definition
+[Qemu-devel] [PULL 06/25] arm: fix qemu crash on startup with -bios option
 From: Igor Mammedov <imammedo@redhat.com>
-s/cpu_model/cpu_type/ that has been forgotten during
+When QEMU is started with following CLI
-conversion (ba1ba5cc), while touching the line also
+ -machine virt,gic-version=3,accel=kvm -cpu host -bios AAVMF_CODE.fd
-fixup alignment.
+it crashes with abort at
  accel/kvm/kvm-all.c:2164:
  KVM_SET_DEVICE_ATTR failed: Group 6 attr 0x000000000000c665: Invalid argument
+Which is caused by implicit dependency of kvm_arm_gicv3_reset() on
+arm_gicv3_icc_reset() where the later is called by CPU reset
+reset callback.
+However commit:
+b77f6c arm/boot: split load_dtb() from arm_load_kernel()
+broke CPU reset callback registration in case
+  arm_load_kernel()
+      ...
+      if (!info->kernel_filename || info->firmware_loaded)
+branch is taken, i.e. it's sufficient to provide a firmware
+or do not provide kernel on CLI to skip cpu reset callback
+registration, where before offending commit the callback
+has been registered unconditionally.
+Fix it by registering the callback right at the beginning of
+arm_load_kernel() unconditionally instead of doing it at the end.
+NOTE:
+ we probably should eliminate that dependency anyways as well as
+ separate arch CPU reset parts from arm_load_kernel() into CPU
+ itself, but that refactoring that I probably would have to do
+ anyways later for CPU hotplug to work.
+Reported-by: Auger Eric <eric.auger@redhat.com>
 Signed-off-by: Igor Mammedov <imammedo@redhat.com>
-Message-id: 1507710805-221721-1-git-send-email-imammedo@redhat.com
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
 Tested-by: Eric Auger <eric.auger@redhat.com>
 Message-id: 1527070950-208350-1-git-send-email-imammedo@redhat.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/arm/arm.h | 2 +-
+ hw/arm/boot.c | 18 +++++++++---------
-file changed, 1 insertion(+), 1 deletion(-)
+file changed, 9 insertions(+), 9 deletions(-)
-diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h
+diff --git a/hw/arm/boot.c b/hw/arm/boot.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/arm.h
+--- a/hw/arm/boot.c
-+++ b/include/hw/arm/arm.h
++++ b/hw/arm/boot.c
-@@ -XXX,XX +XXX,XX @@ typedef enum {
+@@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
+     static const ARMInsnFixup *primary_loader;
- /* armv7m.c */
+     AddressSpace *as = arm_boot_address_space(cpu, info);
- DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
--                      const char *kernel_filename, const char *cpu_model);
++    /* CPU objects (unlike devices) are not automatically reset on system
-+                         const char *kernel_filename, const char *cpu_type);
++     * reset, so we must always register a handler to do so. If we're
- /**
++     * actually loading a kernel, the handler is also responsible for
-  * armv7m_load_kernel:
++     * arranging that we start it correctly.
-  * @cpu: CPU
++     */
 +    for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
 +        qemu_register_reset(do_cpu_reset, ARM_CPU(cs));
 +    }
 +
      /* The board code is not supposed to set secure_board_setup unless
       * running its code in secure mode is actually possible, and KVM
       * doesn't support secure.
@@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
          ARM_CPU(cs)->env.boot_info = info;
      }
 -    /* CPU objects (unlike devices) are not automatically reset on system
 -     * reset, so we must always register a handler to do so. If we're
 -     * actually loading a kernel, the handler is also responsible for
 -     * arranging that we start it correctly.
 -     */
 -    for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
 -        qemu_register_reset(do_cpu_reset, ARM_CPU(cs));
 -    }
 -
      if (!info->skip_dtb_autoload && have_dtb(info)) {
          if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as) < 0) {
              exit(1);
 --
-.7.4
+.17.1

-New patch
+[Qemu-devel] [PULL 07/25] arm: fix malloc type mismatch
+From: Paolo Bonzini <pbonzini@redhat.com>
+cpregs_keys is an uint32_t* so the allocation should use uint32_t.
+g_new is even better because it is type-safe.
+Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/gdbstub.c | 3 +--
+file changed, 1 insertion(+), 2 deletions(-)
+diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/gdbstub.c
++++ b/target/arm/gdbstub.c
+@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_xml(CPUState *cs)
+     RegisterSysregXmlParam param = {cs, s};
+     cpu->dyn_xml.num_cpregs = 0;
+-    cpu->dyn_xml.cpregs_keys = g_malloc(sizeof(uint32_t *) *
+-                                        g_hash_table_size(cpu->cp_regs));
++    cpu->dyn_xml.cpregs_keys = g_new(uint32_t, g_hash_table_size(cpu->cp_regs));
+     g_string_printf(s, "<?xml version=\"1.0\"?>");
+     g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
+     g_string_append_printf(s, "<feature name=\"org.qemu.gdb.arm.sys.regs\">");
+--
+.17.1

-New patch
+[Qemu-devel] [PULL 08/25] xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors
+From: Francisco Iglesias <frasse.iglesias@gmail.com>
+Coverity found that the string return by 'object_get_canonical_path' was not
+being freed at two locations in the model (CID 1391294 and CID 1391293) and
+also that a memset was being called with a value greater than the max of a byte
+on the second argument (CID 1391286). This patch corrects this by adding the
+freeing of the strings and also changing to memset to zero instead on
+descriptor unaligned errors.
+Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
+Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-id: 20180528184859.3530-1-frasse.iglesias@gmail.com
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/dma/xlnx-zdma.c | 10 +++++++---
+file changed, 7 insertions(+), 3 deletions(-)
+diff --git a/hw/dma/xlnx-zdma.c b/hw/dma/xlnx-zdma.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/dma/xlnx-zdma.c
++++ b/hw/dma/xlnx-zdma.c
+@@ -XXX,XX +XXX,XX @@ static bool zdma_load_descriptor(XlnxZDMA *s, uint64_t addr, void *buf)
+         qemu_log_mask(LOG_GUEST_ERROR,
+                       "zdma: unaligned descriptor at %" PRIx64,
+                       addr);
+-        memset(buf, 0xdeadbeef, sizeof(XlnxZDMADescr));
++        memset(buf, 0x0, sizeof(XlnxZDMADescr));
+         s->error = true;
+         return false;
+     }
+@@ -XXX,XX +XXX,XX @@ static uint64_t zdma_read(void *opaque, hwaddr addr, unsigned size)
+     RegisterInfo *r = &s->regs_info[addr / 4];
+     if (!r->data) {
++        gchar *path = object_get_canonical_path(OBJECT(s));
+         qemu_log("%s: Decode error: read from %" HWADDR_PRIx "\n",
+-                 object_get_canonical_path(OBJECT(s)),
++                 path,
+                  addr);
++        g_free(path);
+         ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true);
+         zdma_ch_imr_update_irq(s);
+         return 0;
+@@ -XXX,XX +XXX,XX @@ static void zdma_write(void *opaque, hwaddr addr, uint64_t value,
+     RegisterInfo *r = &s->regs_info[addr / 4];
+     if (!r->data) {
++        gchar *path = object_get_canonical_path(OBJECT(s));
+         qemu_log("%s: Decode error: write to %" HWADDR_PRIx "=%" PRIx64 "\n",
+-                 object_get_canonical_path(OBJECT(s)),
++                 path,
+                  addr, value);
++        g_free(path);
+         ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true);
+         zdma_ch_imr_update_irq(s);
+         return;
+--
+.17.1

-[Qemu-devel] [PULL 04/13] target/arm: Implement SG instruction
+[Qemu-devel] [PULL 09/25] Correct CPACR reset value for v7 cores
-Implement the SG instruction, which we emulate 'by hand' in the
+In commit f0aff255700 we made cpacr_write() enforce that some CPACR
-exception handling code path.
+bits are RAZ/WI and some are RAO/WI for ARMv7 cores. Unfortunately
 we forgot to also update the register's reset value. The effect
 was that (a) a guest that read CPACR on reset would not see ones in
 the RAO bits, and (b) if you did a migration before the guest did
 a write to the CPACR then the migration would fail because the
 destination would enforce the RAO bits and then complain that they
 didn't match the zero value from the source.
+Implement reset for the CPACR using a custom reset function
+that just calls cpacr_write(), to avoid having to duplicate
+the logic for which bits are RAO.
+This bug would affect migration for TCG CPUs which are ARMv7
+with VFP but without one of Neon or VFPv3.
+Reported-by: Cédric Le Goater <clg@kaod.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Tested-by: Cédric Le Goater <clg@kaod.org>
-Message-id: 1507556919-24992-3-git-send-email-peter.maydell@linaro.org
+Message-id: 20180522173713.26282-1-peter.maydell@linaro.org
 ---
- target/arm/helper.c | 132 ++++++++++++++++++++++++++++++++++++++++++++++++++--
+ target/arm/helper.c | 10 +++++++++-
-file changed, 127 insertions(+), 5 deletions(-)
+file changed, 9 insertions(+), 1 deletion(-)
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ typedef struct V8M_SAttributes {
+@@ -XXX,XX +XXX,XX @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
-     bool irvalid;
+     env->cp15.cpacr_el1 = value;
  } V8M_SAttributes;
 +static void v8m_security_lookup(CPUARMState *env, uint32_t address,
 +                                MMUAccessType access_type, ARMMMUIdx mmu_idx,
 +                                V8M_SAttributes *sattrs);
 +
  /* Definitions for the PMCCNTR and PMCR registers */
  #define PMCRD   0x8
  #define PMCRC   0x4
@@ -XXX,XX +XXX,XX @@ static void arm_log_exception(int idx)
      }
  }
-+static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
++static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
 +                               uint32_t addr, uint16_t *insn)
 +{
-+    /* Load a 16-bit portion of a v7M instruction, returning true on success,
++    /* Call cpacr_write() so that we reset with the correct RAO bits set
-+     * or false on failure (in which case we will have pended the appropriate
++     * for our CPU features.
 +     * exception).
 +     * We need to do the instruction fetch's MPU and SAU checks
 +     * like this because there is no MMU index that would allow
 +     * doing the load with a single function call. Instead we must
 +     * first check that the security attributes permit the load
 +     * and that they don't mismatch on the two halves of the instruction,
 +     * and then we do the load as a secure load (ie using the security
 +     * attributes of the address, not the CPU, as architecturally required).
 +     */
-+    CPUState *cs = CPU(cpu);
++    cpacr_write(env, ri, 0);
 +    CPUARMState *env = &cpu->env;
 +    V8M_SAttributes sattrs = {};
 +    MemTxAttrs attrs = {};
 +    ARMMMUFaultInfo fi = {};
 +    MemTxResult txres;
 +    target_ulong page_size;
 +    hwaddr physaddr;
 +    int prot;
 +    uint32_t fsr;
 +
 +    v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, &sattrs);
 +    if (!sattrs.nsc || sattrs.ns) {
 +        /* This must be the second half of the insn, and it straddles a
 +         * region boundary with the second half not being S&NSC.
 +         */
 +        env->v7m.sfsr |= R_V7M_SFSR_INVEP_MASK;
 +        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false);
 +        qemu_log_mask(CPU_LOG_INT,
 +                      "...really SecureFault with SFSR.INVEP\n");
 +        return false;
 +    }
 +    if (get_phys_addr(env, addr, MMU_INST_FETCH, mmu_idx,
 +                      &physaddr, &attrs, &prot, &page_size, &fsr, &fi)) {
 +        /* the MPU lookup failed */
 +        env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_IACCVIOL_MASK;
 +        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, env->v7m.secure);
 +        qemu_log_mask(CPU_LOG_INT, "...really MemManage with CFSR.IACCVIOL\n");
 +        return false;
 +    }
 +    *insn = address_space_lduw_le(arm_addressspace(cs, attrs), physaddr,
 +                                 attrs, &txres);
 +    if (txres != MEMTX_OK) {
 +        env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_IBUSERR_MASK;
 +        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false);
 +        qemu_log_mask(CPU_LOG_INT, "...really BusFault with CFSR.IBUSERR\n");
 +        return false;
 +    }
 +    return true;
 +}
 +
-+static bool v7m_handle_execute_nsc(ARMCPU *cpu)
+ static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
-+{
+                                    bool isread)
 +    /* Check whether this attempt to execute code in a Secure & NS-Callable
 +     * memory region is for an SG instruction; if so, then emulate the
 +     * effect of the SG instruction and return true. Otherwise pend
 +     * the correct kind of exception and return false.
 +     */
 +    CPUARMState *env = &cpu->env;
 +    ARMMMUIdx mmu_idx;
 +    uint16_t insn;
 +
 +    /* We should never get here unless get_phys_addr_pmsav8() caused
 +     * an exception for NS executing in S&NSC memory.
 +     */
 +    assert(!env->v7m.secure);
 +    assert(arm_feature(env, ARM_FEATURE_M_SECURITY));
 +
 +    /* We want to do the MPU lookup as secure; work out what mmu_idx that is */
 +    mmu_idx = arm_v7m_mmu_idx_for_secstate(env, true);
 +
 +    if (!v7m_read_half_insn(cpu, mmu_idx, env->regs[15], &insn)) {
 +        return false;
 +    }
 +
 +    if (!env->thumb) {
 +        goto gen_invep;
 +    }
 +
 +    if (insn != 0xe97f) {
 +        /* Not an SG instruction first half (we choose the IMPDEF
 +         * early-SG-check option).
 +         */
 +        goto gen_invep;
 +    }
 +
 +    if (!v7m_read_half_insn(cpu, mmu_idx, env->regs[15] + 2, &insn)) {
 +        return false;
 +    }
 +
 +    if (insn != 0xe97f) {
 +        /* Not an SG instruction second half (yes, both halves of the SG
 +         * insn have the same hex value)
 +         */
 +        goto gen_invep;
 +    }
 +
 +    /* OK, we have confirmed that we really have an SG instruction.
 +     * We know we're NS in S memory so don't need to repeat those checks.
 +     */
 +    qemu_log_mask(CPU_LOG_INT, "...really an SG instruction at 0x%08" PRIx32
 +                  ", executing it\n", env->regs[15]);
 +    env->regs[14] &= ~1;
 +    switch_v7m_security_state(env, true);
 +    xpsr_write(env, 0, XPSR_IT);
 +    env->regs[15] += 4;
 +    return true;
 +
 +gen_invep:
 +    env->v7m.sfsr |= R_V7M_SFSR_INVEP_MASK;
 +    armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false);
 +    qemu_log_mask(CPU_LOG_INT,
 +                  "...really SecureFault with SFSR.INVEP\n");
 +    return false;
 +}
 +
  void arm_v7m_cpu_do_interrupt(CPUState *cs)
  {
-     ARMCPU *cpu = ARM_CPU(cs);
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
-@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
+     { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
-              * the SG instruction have the same security attributes.)
+       .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
-              * Everything else must generate an INVEP SecureFault, so we
+       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
-              * emulate the SG instruction here.
+-      .resetvalue = 0, .writefn = cpacr_write },
--             * TODO: actually emulate SG.
++      .resetfn = cpacr_reset, .writefn = cpacr_write },
-              */
+     REGINFO_SENTINEL
--            env->v7m.sfsr |= R_V7M_SFSR_INVEP_MASK;
+ };
--            armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false);
 -            qemu_log_mask(CPU_LOG_INT,
 -                          "...really SecureFault with SFSR.INVEP\n");
 +            if (v7m_handle_execute_nsc(cpu)) {
 +                return;
 +            }
              break;
          case M_FAKE_FSR_SFAULT:
              /* Various flavours of SecureFault for attempts to execute or
 --
-.7.4
+.17.1

-[Qemu-devel] [PULL 11/13] target/arm: Implement SG instruction corner cases
+[Qemu-devel] [PULL 10/25] memory.h: Improve IOMMU related documentation
-The common situation of the SG instruction is that it is
+Add more detail to the documentation for memory_region_init_iommu()
-executed from S&NSC memory by a CPU in NS state. That case
+and other IOMMU-related functions and data structures.
 is handled by v7m_handle_execute_nsc(). However the instruction
 also has defined behaviour in a couple of other cases:
  * SG instruction in NS memory (behaves as a NOP)
  * SG in S memory but CPU already secure (clears IT bits and
    does nothing else)
  * SG instruction in v8M without Security Extension (NOP)
 These can be implemented in translate.c.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 1507556919-24992-10-git-send-email-peter.maydell@linaro.org
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Eric Auger <eric.auger@redhat.com>
 Message-id: 20180521140402.23318-2-peter.maydell@linaro.org
 ---
- target/arm/translate.c | 23 ++++++++++++++++++++++-
+ include/exec/memory.h | 105 ++++++++++++++++++++++++++++++++++++++----
-file changed, 22 insertions(+), 1 deletion(-)
+file changed, 95 insertions(+), 10 deletions(-)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
+diff --git a/include/exec/memory.h b/include/exec/memory.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
+--- a/include/exec/memory.h
-+++ b/target/arm/translate.c
++++ b/include/exec/memory.h
-@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(DisasContext *s, uint32_t insn)
+@@ -XXX,XX +XXX,XX @@ enum IOMMUMemoryRegionAttr {
-              * - load/store doubleword, load/store exclusive, ldacq/strel,
+     IOMMU_ATTR_SPAPR_TCE_FD
-              *   table branch.
+ };
-              */
--            if (insn & 0x01200000) {
++/**
-+            if (insn == 0xe97fe97f && arm_dc_feature(s, ARM_FEATURE_M) &&
++ * IOMMUMemoryRegionClass:
-+                arm_dc_feature(s, ARM_FEATURE_V8)) {
++ *
-+                /* 0b1110_1001_0111_1111_1110_1001_0111_111
++ * All IOMMU implementations need to subclass TYPE_IOMMU_MEMORY_REGION
-+                 *  - SG (v8M only)
++ * and provide an implementation of at least the @translate method here
-+                 * The bulk of the behaviour for this instruction is implemented
++ * to handle requests to the memory region. Other methods are optional.
-+                 * in v7m_handle_execute_nsc(), which deals with the insn when
++ *
-+                 * it is executed by a CPU in non-secure state from memory
++ * The IOMMU implementation must use the IOMMU notifier infrastructure
-+                 * which is Secure & NonSecure-Callable.
++ * to report whenever mappings are changed, by calling
-+                 * Here we only need to handle the remaining cases:
++ * memory_region_notify_iommu() (or, if necessary, by calling
-+                 *  * in NS memory (including the "security extension not
++ * memory_region_notify_one() for each registered notifier).
-+                 *    implemented" case) : NOP
++ */
-+                 *  * in S memory but CPU already secure (clear IT bits)
+ typedef struct IOMMUMemoryRegionClass {
-+                 * We know that the attribute for the memory this insn is
+     /* private */
-+                 * in must match the current CPU state, because otherwise
+     struct DeviceClass parent_class;
-+                 * get_phys_addr_pmsav8 would have generated an exception.
-+                 */
+     /*
-+                if (s->v8m_secure) {
+-     * Return a TLB entry that contains a given address. Flag should
-+                    /* Like the IT insn, we don't need to generate any code */
+-     * be the access permission of this translation operation. We can
-+                    s->condexec_cond = 0;
+-     * set flag to IOMMU_NONE to mean that we don't need any
-+                    s->condexec_mask = 0;
+-     * read/write permission checks, like, when for region replay.
-+                }
++     * Return a TLB entry that contains a given address.
-+            } else if (insn & 0x01200000) {
++     *
-                 /* 0b1110_1000_x11x_xxxx_xxxx_xxxx_xxxx_xxxx
++     * The IOMMUAccessFlags indicated via @flag are optional and may
-                  *  - load/store dual (post-indexed)
++     * be specified as IOMMU_NONE to indicate that the caller needs
-                  * 0b1111_1001_x10x_xxxx_xxxx_xxxx_xxxx_xxxx
++     * the full translation information for both reads and writes. If
 +     * the access flags are specified then the IOMMU implementation
 +     * may use this as an optimization, to stop doing a page table
 +     * walk as soon as it knows that the requested permissions are not
 +     * allowed. If IOMMU_NONE is passed then the IOMMU must do the
 +     * full page table walk and report the permissions in the returned
 +     * IOMMUTLBEntry. (Note that this implies that an IOMMU may not
 +     * return different mappings for reads and writes.)
 +     *
 +     * The returned information remains valid while the caller is
 +     * holding the big QEMU lock or is inside an RCU critical section;
 +     * if the caller wishes to cache the mapping beyond that it must
 +     * register an IOMMU notifier so it can invalidate its cached
 +     * information when the IOMMU mapping changes.
 +     *
 +     * @iommu: the IOMMUMemoryRegion
 +     * @hwaddr: address to be translated within the memory region
 +     * @flag: requested access permissions
       */
      IOMMUTLBEntry (*translate)(IOMMUMemoryRegion *iommu, hwaddr addr,
                                 IOMMUAccessFlags flag);
 -    /* Returns minimum supported page size */
 +    /* Returns minimum supported page size in bytes.
 +     * If this method is not provided then the minimum is assumed to
 +     * be TARGET_PAGE_SIZE.
 +     *
 +     * @iommu: the IOMMUMemoryRegion
 +     */
      uint64_t (*get_min_page_size)(IOMMUMemoryRegion *iommu);
 -    /* Called when IOMMU Notifier flag changed */
 +    /* Called when IOMMU Notifier flag changes (ie when the set of
 +     * events which IOMMU users are requesting notification for changes).
 +     * Optional method -- need not be provided if the IOMMU does not
 +     * need to know exactly which events must be notified.
 +     *
 +     * @iommu: the IOMMUMemoryRegion
 +     * @old_flags: events which previously needed to be notified
 +     * @new_flags: events which now need to be notified
 +     */
      void (*notify_flag_changed)(IOMMUMemoryRegion *iommu,
                                  IOMMUNotifierFlag old_flags,
                                  IOMMUNotifierFlag new_flags);
 -    /* Set this up to provide customized IOMMU replay function */
 +    /* Called to handle memory_region_iommu_replay().
 +     *
 +     * The default implementation of memory_region_iommu_replay() is to
 +     * call the IOMMU translate method for every page in the address space
 +     * with flag == IOMMU_NONE and then call the notifier if translate
 +     * returns a valid mapping. If this method is implemented then it
 +     * overrides the default behaviour, and must provide the full semantics
 +     * of memory_region_iommu_replay(), by calling @notifier for every
 +     * translation present in the IOMMU.
 +     *
 +     * Optional method -- an IOMMU only needs to provide this method
 +     * if the default is inefficient or produces undesirable side effects.
 +     *
 +     * Note: this is not related to record-and-replay functionality.
 +     */
      void (*replay)(IOMMUMemoryRegion *iommu, IOMMUNotifier *notifier);
 -    /* Get IOMMU misc attributes */
 -    int (*get_attr)(IOMMUMemoryRegion *iommu, enum IOMMUMemoryRegionAttr,
 +    /* Get IOMMU misc attributes. This is an optional method that
 +     * can be used to allow users of the IOMMU to get implementation-specific
 +     * information. The IOMMU implements this method to handle calls
 +     * by IOMMU users to memory_region_iommu_get_attr() by filling in
 +     * the arbitrary data pointer for any IOMMUMemoryRegionAttr values that
 +     * the IOMMU supports. If the method is unimplemented then
 +     * memory_region_iommu_get_attr() will always return -EINVAL.
 +     *
 +     * @iommu: the IOMMUMemoryRegion
 +     * @attr: attribute being queried
 +     * @data: memory to fill in with the attribute data
 +     *
 +     * Returns 0 on success, or a negative errno; in particular
 +     * returns -EINVAL for unrecognized or unimplemented attribute types.
 +     */
 +    int (*get_attr)(IOMMUMemoryRegion *iommu, enum IOMMUMemoryRegionAttr attr,
                      void *data);
  } IOMMUMemoryRegionClass;
@@ -XXX,XX +XXX,XX @@ static inline void memory_region_init_reservation(MemoryRegion *mr,
   * An IOMMU region translates addresses and forwards accesses to a target
   * memory region.
   *
 + * The IOMMU implementation must define a subclass of TYPE_IOMMU_MEMORY_REGION.
 + * @_iommu_mr should be a pointer to enough memory for an instance of
 + * that subclass, @instance_size is the size of that subclass, and
 + * @mrtypename is its name. This function will initialize @_iommu_mr as an
 + * instance of the subclass, and its methods will then be called to handle
 + * accesses to the memory region. See the documentation of
 + * #IOMMUMemoryRegionClass for further details.
 + *
   * @_iommu_mr: the #IOMMUMemoryRegion to be initialized
   * @instance_size: the IOMMUMemoryRegion subclass instance size
   * @mrtypename: the type name of the #IOMMUMemoryRegion
@@ -XXX,XX +XXX,XX @@ void memory_region_register_iommu_notifier(MemoryRegion *mr,
   * a notifier with the minimum page granularity returned by
   * mr->iommu_ops->get_page_size().
   *
 + * Note: this is not related to record-and-replay functionality.
 + *
   * @iommu_mr: the memory region to observe
   * @n: the notifier to which to replay iommu mappings
   */
@@ -XXX,XX +XXX,XX @@ void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n);
   * memory_region_iommu_replay_all: replay existing IOMMU translations
   * to all the notifiers registered.
   *
 + * Note: this is not related to record-and-replay functionality.
 + *
   * @iommu_mr: the memory region to observe
   */
  void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr);
@@ -XXX,XX +XXX,XX @@ void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
   * memory_region_iommu_get_attr: return an IOMMU attr if get_attr() is
   * defined on the IOMMU.
   *
 - * Returns 0 if succeded, error code otherwise.
 + * Returns 0 on success, or a negative errno otherwise. In particular,
 + * -EINVAL indicates that the IOMMU does not support the requested
 + * attribute.
   *
   * @iommu_mr: the memory region
   * @attr: the requested attribute
 --
-.7.4
+.17.1

-[Qemu-devel] [PULL 08/13] target/arm: Pull Thumb insn word loads up to top level
+[Qemu-devel] [PULL 11/25] Make tb_invalidate_phys_addr() take a MemTxAttrs argument
-Refactor the Thumb decode to do the loads of the instruction words at
+As part of plumbing MemTxAttrs down to the IOMMU translate method,
-the top level rather than only loading the second half of a 32-bit
+add MemTxAttrs as an argument to tb_invalidate_phys_addr().
-Thumb insn in the middle of the decode.
+Its callers either have an attrs value to hand, or don't care
+and can use MEMTXATTRS_UNSPECIFIED.
 This is simple apart from the awkward case of Thumb1, where the
 BL/BLX prefix and suffix instructions live in what in Thumb2 is the
 -bit insn space.  To handle these we decode enough to identify
 whether we're looking at a prefix/suffix that we handle as a 16 bit
 insn, or a prefix that we're going to merge with the following suffix
 to consider as a 32 bit insn.  The translation of the 16 bit cases
 then moves from disas_thumb2_insn() to disas_thumb_insn().
 The refactoring has the benefit that we don't need to pass the
 CPUARMState* down into the decoder code any more, but the major
 reason for doing this is that some Thumb instructions must be always
 unconditional regardless of the IT state bits, so we need to know the
 whole insn before we emit the "skip this insn if the IT bits and cond
 state tell us to" code.  (The always unconditional insns are BKPT,
 HLT and SG; the last of these is 32 bits.)
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 1507556919-24992-7-git-send-email-peter.maydell@linaro.org
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Message-id: 20180521140402.23318-3-peter.maydell@linaro.org
 ---
- target/arm/translate.c | 178 ++++++++++++++++++++++++++++++-------------------
+ include/exec/exec-all.h   | 5 +++--
-file changed, 108 insertions(+), 70 deletions(-)
+ accel/tcg/translate-all.c | 2 +-
  exec.c                    | 2 +-
  target/xtensa/op_helper.c | 3 ++-
 files changed, 7 insertions(+), 5 deletions(-)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
+diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
+--- a/include/exec/exec-all.h
-+++ b/target/arm/translate.c
++++ b/include/exec/exec-all.h
-@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
+@@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
  void tlb_set_page(CPUState *cpu, target_ulong vaddr,
                    hwaddr paddr, int prot,
                    int mmu_idx, target_ulong size);
 -void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);
 +void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs);
  void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx,
                   uintptr_t retaddr);
  #else
@@ -XXX,XX +XXX,XX @@ static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
                                                         uint16_t idxmap)
  {
  }
 -static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr)
 +static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr,
 +                                           MemTxAttrs attrs)
  {
  }
  #endif
 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
 index XXXXXXX..XXXXXXX 100644
 --- a/accel/tcg/translate-all.c
 +++ b/accel/tcg/translate-all.c
@@ -XXX,XX +XXX,XX @@ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr)
  }
  #if !defined(CONFIG_USER_ONLY)
 -void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr)
 +void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
  {
      ram_addr_t ram_addr;
      MemoryRegion *mr;
 diff --git a/exec.c b/exec.c
 index XXXXXXX..XXXXXXX 100644
 --- a/exec.c
 +++ b/exec.c
@@ -XXX,XX +XXX,XX @@ static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
      if (phys != -1) {
          /* Locks grabbed by tb_invalidate_phys_addr */
          tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as,
 -                                phys | (pc & ~TARGET_PAGE_MASK));
 +                                phys | (pc & ~TARGET_PAGE_MASK), attrs);
      }
  }
+ #endif
-+static bool thumb_insn_is_16bit(DisasContext *s, uint32_t insn)
+diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c
-+{
+index XXXXXXX..XXXXXXX 100644
-+    /* Return true if this is a 16 bit instruction. We must be precise
+--- a/target/xtensa/op_helper.c
-+     * about this (matching the decode).  We assume that s->pc still
++++ b/target/xtensa/op_helper.c
-+     * points to the first 16 bits of the insn.
+@@ -XXX,XX +XXX,XX @@ static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)
-+     */
+     int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0,
-+    if ((insn >> 11) < 0x1d) {
+             &paddr, &page_size, &access);
-+        /* Definitely a 16-bit instruction */
+     if (ret == 0) {
-+        return true;
+-        tb_invalidate_phys_addr(&address_space_memory, paddr);
-+    }
++        tb_invalidate_phys_addr(&address_space_memory, paddr,
-+
++                                MEMTXATTRS_UNSPECIFIED);
 +    /* Top five bits 0b11101 / 0b11110 / 0b11111 : this is the
 +     * first half of a 32-bit Thumb insn. Thumb-1 cores might
 +     * end up actually treating this as two 16-bit insns, though,
 +     * if it's half of a bl/blx pair that might span a page boundary.
 +     */
 +    if (arm_dc_feature(s, ARM_FEATURE_THUMB2)) {
 +        /* Thumb2 cores (including all M profile ones) always treat
 +         * 32-bit insns as 32-bit.
 +         */
 +        return false;
 +    }
 +
 +    if ((insn >> 11) == 0x1e && (s->pc < s->next_page_start - 3)) {
 +        /* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix, and the suffix
 +         * is not on the next page; we merge this into a 32-bit
 +         * insn.
 +         */
 +        return false;
 +    }
 +    /* 0b1110_1xxx_xxxx_xxxx : BLX suffix (or UNDEF);
 +     * 0b1111_1xxx_xxxx_xxxx : BL suffix;
 +     * 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix on the end of a page
 +     *  -- handle as single 16 bit insn
 +     */
 +    return true;
 +}
 +
  /* Return true if this is a Thumb-2 logical op.  */
  static int
  thumb2_logic_op(int op)
@@ -XXX,XX +XXX,XX @@ gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out,
  /* Translate a 32-bit thumb instruction.  Returns nonzero if the instruction
     is not legal.  */
 -static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw1)
 +static int disas_thumb2_insn(DisasContext *s, uint32_t insn)
  {
 -    uint32_t insn, imm, shift, offset;
 +    uint32_t imm, shift, offset;
      uint32_t rd, rn, rm, rs;
      TCGv_i32 tmp;
      TCGv_i32 tmp2;
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
      int conds;
      int logic_cc;
 -    if (!arm_dc_feature(s, ARM_FEATURE_THUMB2)) {
 -        /* Thumb-1 cores may need to treat bl and blx as a pair of
 -           16-bit instructions to get correct prefetch abort behavior.  */
 -        insn = insn_hw1;
 -        if ((insn & (1 << 12)) == 0) {
 -            ARCH(5);
 -            /* Second half of blx.  */
 -            offset = ((insn & 0x7ff) << 1);
 -            tmp = load_reg(s, 14);
 -            tcg_gen_addi_i32(tmp, tmp, offset);
 -            tcg_gen_andi_i32(tmp, tmp, 0xfffffffc);
 -
 -            tmp2 = tcg_temp_new_i32();
 -            tcg_gen_movi_i32(tmp2, s->pc | 1);
 -            store_reg(s, 14, tmp2);
 -            gen_bx(s, tmp);
 -            return 0;
 -        }
 -        if (insn & (1 << 11)) {
 -            /* Second half of bl.  */
 -            offset = ((insn & 0x7ff) << 1) | 1;
 -            tmp = load_reg(s, 14);
 -            tcg_gen_addi_i32(tmp, tmp, offset);
 -
 -            tmp2 = tcg_temp_new_i32();
 -            tcg_gen_movi_i32(tmp2, s->pc | 1);
 -            store_reg(s, 14, tmp2);
 -            gen_bx(s, tmp);
 -            return 0;
 -        }
 -        if ((s->pc & ~TARGET_PAGE_MASK) == 0) {
 -            /* Instruction spans a page boundary.  Implement it as two
 -               16-bit instructions in case the second half causes an
 -               prefetch abort.  */
 -            offset = ((int32_t)insn << 21) >> 9;
 -            tcg_gen_movi_i32(cpu_R[14], s->pc + 2 + offset);
 -            return 0;
 -        }
 -        /* Fall through to 32-bit decode.  */
 -    }
 -
 -    insn = arm_lduw_code(env, s->pc, s->sctlr_b);
 -    s->pc += 2;
 -    insn |= (uint32_t)insn_hw1 << 16;
 -
 +    /* The only 32 bit insn that's allowed for Thumb1 is the combined
 +     * BL/BLX prefix and suffix.
 +     */
      if ((insn & 0xf800e800) != 0xf000e800) {
          ARCH(6T2);
      }
-@@ -XXX,XX +XXX,XX @@ illegal_op:
-     return 1;
  }
--static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
-+static void disas_thumb_insn(DisasContext *s, uint32_t insn)
- {
--    uint32_t val, insn, op, rm, rn, rd, shift, cond;
-+    uint32_t val, op, rm, rn, rd, shift, cond;
-     int32_t offset;
-     int i;
-     TCGv_i32 tmp;
-     TCGv_i32 tmp2;
-     TCGv_i32 addr;
--    if (s->condexec_mask) {
--        cond = s->condexec_cond;
--        if (cond != 0x0e) {     /* Skip conditional when condition is AL. */
--          s->condlabel = gen_new_label();
--          arm_gen_test_cc(cond ^ 1, s->condlabel);
--          s->condjmp = 1;
--        }
--    }
--
--    insn = arm_lduw_code(env, s->pc, s->sctlr_b);
--    s->pc += 2;
--
-     switch (insn >> 12) {
-     case 0: case 1:
-@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
-     case 14:
-         if (insn & (1 << 11)) {
--            if (disas_thumb2_insn(env, s, insn))
--              goto undef32;
-+            /* thumb_insn_is_16bit() ensures we can't get here for
-+             * a Thumb2 CPU, so this must be a thumb1 split BL/BLX:
-+             * 0b1110_1xxx_xxxx_xxxx : BLX suffix (or UNDEF)
-+             */
-+            assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2));
-+            ARCH(5);
-+            offset = ((insn & 0x7ff) << 1);
-+            tmp = load_reg(s, 14);
-+            tcg_gen_addi_i32(tmp, tmp, offset);
-+            tcg_gen_andi_i32(tmp, tmp, 0xfffffffc);
-+
-+            tmp2 = tcg_temp_new_i32();
-+            tcg_gen_movi_i32(tmp2, s->pc | 1);
-+            store_reg(s, 14, tmp2);
-+            gen_bx(s, tmp);
-             break;
-         }
-         /* unconditional branch */
-@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
-         break;
-     case 15:
--        if (disas_thumb2_insn(env, s, insn))
--            goto undef32;
-+        /* thumb_insn_is_16bit() ensures we can't get here for
-+         * a Thumb2 CPU, so this must be a thumb1 split BL/BLX.
-+         */
-+        assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2));
-+
-+        if (insn & (1 << 11)) {
-+            /* 0b1111_1xxx_xxxx_xxxx : BL suffix */
-+            offset = ((insn & 0x7ff) << 1) | 1;
-+            tmp = load_reg(s, 14);
-+            tcg_gen_addi_i32(tmp, tmp, offset);
-+
-+            tmp2 = tcg_temp_new_i32();
-+            tcg_gen_movi_i32(tmp2, s->pc | 1);
-+            store_reg(s, 14, tmp2);
-+            gen_bx(s, tmp);
-+        } else {
-+            /* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix */
-+            uint32_t uoffset = ((int32_t)insn << 21) >> 9;
-+
-+            tcg_gen_movi_i32(cpu_R[14], s->pc + 2 + uoffset);
-+        }
-         break;
-     }
-     return;
--undef32:
--    gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
--                       default_exception_el(s));
--    return;
- illegal_op:
- undef:
-     gen_exception_insn(s, 2, EXCP_UDEF, syn_uncategorized(),
-@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
- {
-     DisasContext *dc = container_of(dcbase, DisasContext, base);
-     CPUARMState *env = cpu->env_ptr;
-+    uint32_t insn;
-+    bool is_16bit;
-     if (arm_pre_translate_insn(dc)) {
-         return;
-     }
--    disas_thumb_insn(env, dc);
-+    insn = arm_lduw_code(env, dc->pc, dc->sctlr_b);
-+    is_16bit = thumb_insn_is_16bit(dc, insn);
-+    dc->pc += 2;
-+    if (!is_16bit) {
-+        uint32_t insn2 = arm_lduw_code(env, dc->pc, dc->sctlr_b);
-+
-+        insn = insn << 16 | insn2;
-+        dc->pc += 2;
-+    }
-+
-+    if (dc->condexec_mask) {
-+        uint32_t cond = dc->condexec_cond;
-+
-+        if (cond != 0x0e) {     /* Skip conditional when condition is AL. */
-+            dc->condlabel = gen_new_label();
-+            arm_gen_test_cc(cond ^ 1, dc->condlabel);
-+            dc->condjmp = 1;
-+        }
-+    }
-+
-+    if (is_16bit) {
-+        disas_thumb_insn(dc, insn);
-+    } else {
-+        disas_thumb2_insn(dc, insn);
-+    }
-     /* Advance the Thumb condexec condition.  */
-     if (dc->condexec_mask) {
 --
-.7.4
+.17.1

-New patch
+[Qemu-devel] [PULL 12/25] Make address_space_translate{, _cached}() take a MemTxAttrs argument
+As part of plumbing MemTxAttrs down to the IOMMU translate method,
 add MemTxAttrs as an argument to address_space_translate()
 and address_space_translate_cached(). Callers either have an
 attrs value to hand, or don't care and can use MEMTXATTRS_UNSPECIFIED.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20180521140402.23318-4-peter.maydell@linaro.org
 ---
  include/exec/memory.h     |  4 +++-
  accel/tcg/translate-all.c |  2 +-
  exec.c                    | 14 +++++++++-----
  hw/vfio/common.c          |  3 ++-
  memory_ldst.inc.c         | 18 +++++++++---------
  target/riscv/helper.c     |  2 +-
 files changed, 25 insertions(+), 18 deletions(-)
 diff --git a/include/exec/memory.h b/include/exec/memory.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/exec/memory.h
 +++ b/include/exec/memory.h
@@ -XXX,XX +XXX,XX @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
   * #MemoryRegion.
   * @len: pointer to length
   * @is_write: indicates the transfer direction
 + * @attrs: memory attributes
   */
  MemoryRegion *flatview_translate(FlatView *fv,
                                   hwaddr addr, hwaddr *xlat,
@@ -XXX,XX +XXX,XX @@ MemoryRegion *flatview_translate(FlatView *fv,
  static inline MemoryRegion *address_space_translate(AddressSpace *as,
                                                      hwaddr addr, hwaddr *xlat,
 -                                                    hwaddr *len, bool is_write)
 +                                                    hwaddr *len, bool is_write,
 +                                                    MemTxAttrs attrs)
  {
      return flatview_translate(address_space_to_flatview(as),
                                addr, xlat, len, is_write);
 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
 index XXXXXXX..XXXXXXX 100644
 --- a/accel/tcg/translate-all.c
 +++ b/accel/tcg/translate-all.c
@@ -XXX,XX +XXX,XX @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
      hwaddr l = 1;
      rcu_read_lock();
 -    mr = address_space_translate(as, addr, &addr, &l, false);
 +    mr = address_space_translate(as, addr, &addr, &l, false, attrs);
      if (!(memory_region_is_ram(mr)
            || memory_region_is_romd(mr))) {
          rcu_read_unlock();
 diff --git a/exec.c b/exec.c
 index XXXXXXX..XXXXXXX 100644
 --- a/exec.c
 +++ b/exec.c
@@ -XXX,XX +XXX,XX @@ static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as,
      rcu_read_lock();
      while (len > 0) {
          l = len;
 -        mr = address_space_translate(as, addr, &addr1, &l, true);
 +        mr = address_space_translate(as, addr, &addr1, &l, true,
 +                                     MEMTXATTRS_UNSPECIFIED);
          if (!(memory_region_is_ram(mr) ||
                memory_region_is_romd(mr))) {
@@ -XXX,XX +XXX,XX @@ void address_space_cache_destroy(MemoryRegionCache *cache)
   */
  static inline MemoryRegion *address_space_translate_cached(
      MemoryRegionCache *cache, hwaddr addr, hwaddr *xlat,
 -    hwaddr *plen, bool is_write)
 +    hwaddr *plen, bool is_write, MemTxAttrs attrs)
  {
      MemoryRegionSection section;
      MemoryRegion *mr;
@@ -XXX,XX +XXX,XX @@ address_space_read_cached_slow(MemoryRegionCache *cache, hwaddr addr,
      MemoryRegion *mr;
      l = len;
 -    mr = address_space_translate_cached(cache, addr, &addr1, &l, false);
 +    mr = address_space_translate_cached(cache, addr, &addr1, &l, false,
 +                                        MEMTXATTRS_UNSPECIFIED);
      flatview_read_continue(cache->fv,
                             addr, MEMTXATTRS_UNSPECIFIED, buf, len,
                             addr1, l, mr);
@@ -XXX,XX +XXX,XX @@ address_space_write_cached_slow(MemoryRegionCache *cache, hwaddr addr,
      MemoryRegion *mr;
      l = len;
 -    mr = address_space_translate_cached(cache, addr, &addr1, &l, true);
 +    mr = address_space_translate_cached(cache, addr, &addr1, &l, true,
 +                                        MEMTXATTRS_UNSPECIFIED);
      flatview_write_continue(cache->fv,
                              addr, MEMTXATTRS_UNSPECIFIED, buf, len,
                              addr1, l, mr);
@@ -XXX,XX +XXX,XX @@ bool cpu_physical_memory_is_io(hwaddr phys_addr)
      rcu_read_lock();
      mr = address_space_translate(&address_space_memory,
 -                                 phys_addr, &phys_addr, &l, false);
 +                                 phys_addr, &phys_addr, &l, false,
 +                                 MEMTXATTRS_UNSPECIFIED);
      res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr));
      rcu_read_unlock();
 diff --git a/hw/vfio/common.c b/hw/vfio/common.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/vfio/common.c
 +++ b/hw/vfio/common.c
@@ -XXX,XX +XXX,XX @@ static bool vfio_get_vaddr(IOMMUTLBEntry *iotlb, void **vaddr,
       */
      mr = address_space_translate(&address_space_memory,
                                   iotlb->translated_addr,
 -                                 &xlat, &len, writable);
 +                                 &xlat, &len, writable,
 +                                 MEMTXATTRS_UNSPECIFIED);
      if (!memory_region_is_ram(mr)) {
          error_report("iommu map to non memory area %"HWADDR_PRIx"",
                       xlat);
 diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/memory_ldst.inc.c
 +++ b/memory_ldst.inc.c
@@ -XXX,XX +XXX,XX @@ static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL,
      bool release_lock = false;
      RCU_READ_LOCK();
 -    mr = TRANSLATE(addr, &addr1, &l, false);
 +    mr = TRANSLATE(addr, &addr1, &l, false, attrs);
      if (l < 4 || !IS_DIRECT(mr, false)) {
          release_lock |= prepare_mmio_access(mr);
@@ -XXX,XX +XXX,XX @@ static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL,
      bool release_lock = false;
      RCU_READ_LOCK();
 -    mr = TRANSLATE(addr, &addr1, &l, false);
 +    mr = TRANSLATE(addr, &addr1, &l, false, attrs);
      if (l < 8 || !IS_DIRECT(mr, false)) {
          release_lock |= prepare_mmio_access(mr);
@@ -XXX,XX +XXX,XX @@ uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
      bool release_lock = false;
      RCU_READ_LOCK();
 -    mr = TRANSLATE(addr, &addr1, &l, false);
 +    mr = TRANSLATE(addr, &addr1, &l, false, attrs);
      if (!IS_DIRECT(mr, false)) {
          release_lock |= prepare_mmio_access(mr);
@@ -XXX,XX +XXX,XX @@ static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,
      bool release_lock = false;
      RCU_READ_LOCK();
 -    mr = TRANSLATE(addr, &addr1, &l, false);
 +    mr = TRANSLATE(addr, &addr1, &l, false, attrs);
      if (l < 2 || !IS_DIRECT(mr, false)) {
          release_lock |= prepare_mmio_access(mr);
@@ -XXX,XX +XXX,XX @@ void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL,
      bool release_lock = false;
      RCU_READ_LOCK();
 -    mr = TRANSLATE(addr, &addr1, &l, true);
 +    mr = TRANSLATE(addr, &addr1, &l, true, attrs);
      if (l < 4 || !IS_DIRECT(mr, true)) {
          release_lock |= prepare_mmio_access(mr);
@@ -XXX,XX +XXX,XX @@ static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL,
      bool release_lock = false;
      RCU_READ_LOCK();
 -    mr = TRANSLATE(addr, &addr1, &l, true);
 +    mr = TRANSLATE(addr, &addr1, &l, true, attrs);
      if (l < 4 || !IS_DIRECT(mr, true)) {
          release_lock |= prepare_mmio_access(mr);
@@ -XXX,XX +XXX,XX @@ void glue(address_space_stb, SUFFIX)(ARG1_DECL,
      bool release_lock = false;
      RCU_READ_LOCK();
 -    mr = TRANSLATE(addr, &addr1, &l, true);
 +    mr = TRANSLATE(addr, &addr1, &l, true, attrs);
      if (!IS_DIRECT(mr, true)) {
          release_lock |= prepare_mmio_access(mr);
          r = memory_region_dispatch_write(mr, addr1, val, 1, attrs);
@@ -XXX,XX +XXX,XX @@ static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL,
      bool release_lock = false;
      RCU_READ_LOCK();
 -    mr = TRANSLATE(addr, &addr1, &l, true);
 +    mr = TRANSLATE(addr, &addr1, &l, true, attrs);
      if (l < 2 || !IS_DIRECT(mr, true)) {
          release_lock |= prepare_mmio_access(mr);
@@ -XXX,XX +XXX,XX @@ static void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL,
      bool release_lock = false;
      RCU_READ_LOCK();
 -    mr = TRANSLATE(addr, &addr1, &l, true);
 +    mr = TRANSLATE(addr, &addr1, &l, true, attrs);
      if (l < 8 || !IS_DIRECT(mr, true)) {
          release_lock |= prepare_mmio_access(mr);
 diff --git a/target/riscv/helper.c b/target/riscv/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/helper.c
 +++ b/target/riscv/helper.c
@@ -XXX,XX +XXX,XX @@ restart:
                  MemoryRegion *mr;
                  hwaddr l = sizeof(target_ulong), addr1;
                  mr = address_space_translate(cs->as, pte_addr,
 -                    &addr1, &l, false);
 +                    &addr1, &l, false, MEMTXATTRS_UNSPECIFIED);
                  if (memory_access_is_direct(mr, true)) {
                      target_ulong *pte_pa =
                          qemu_map_ram_ptr(mr->ram_block, addr1);
 --
 .17.1

-New patch
+[Qemu-devel] [PULL 13/25] Make address_space_map() take a MemTxAttrs argument
+As part of plumbing MemTxAttrs down to the IOMMU translate method,
+add MemTxAttrs as an argument to address_space_map().
+Its callers either have an attrs value to hand, or don't care
+and can use MEMTXATTRS_UNSPECIFIED.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20180521140402.23318-5-peter.maydell@linaro.org
+---
+ include/exec/memory.h   | 3 ++-
+ include/sysemu/dma.h    | 3 ++-
+ exec.c                  | 6 ++++--
+ target/ppc/mmu-hash64.c | 3 ++-
+files changed, 10 insertions(+), 5 deletions(-)
+diff --git a/include/exec/memory.h b/include/exec/memory.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/exec/memory.h
++++ b/include/exec/memory.h
+@@ -XXX,XX +XXX,XX @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_
+  * @addr: address within that address space
+  * @plen: pointer to length of buffer; updated on return
+  * @is_write: indicates the transfer direction
++ * @attrs: memory attributes
+  */
+ void *address_space_map(AddressSpace *as, hwaddr addr,
+-                        hwaddr *plen, bool is_write);
++                        hwaddr *plen, bool is_write, MemTxAttrs attrs);
+ /* address_space_unmap: Unmaps a memory region previously mapped by address_space_map()
+  *
+diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/sysemu/dma.h
++++ b/include/sysemu/dma.h
+@@ -XXX,XX +XXX,XX @@ static inline void *dma_memory_map(AddressSpace *as,
+     hwaddr xlen = *len;
+     void *p;
+-    p = address_space_map(as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE);
++    p = address_space_map(as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE,
++                          MEMTXATTRS_UNSPECIFIED);
+     *len = xlen;
+     return p;
+ }
+diff --git a/exec.c b/exec.c
+index XXXXXXX..XXXXXXX 100644
+--- a/exec.c
++++ b/exec.c
+@@ -XXX,XX +XXX,XX @@ flatview_extend_translation(FlatView *fv, hwaddr addr,
+ void *address_space_map(AddressSpace *as,
+                         hwaddr addr,
+                         hwaddr *plen,
+-                        bool is_write)
++                        bool is_write,
++                        MemTxAttrs attrs)
+ {
+     hwaddr len = *plen;
+     hwaddr l, xlat;
+@@ -XXX,XX +XXX,XX @@ void *cpu_physical_memory_map(hwaddr addr,
+                               hwaddr *plen,
+                               int is_write)
+ {
+-    return address_space_map(&address_space_memory, addr, plen, is_write);
++    return address_space_map(&address_space_memory, addr, plen, is_write,
++                             MEMTXATTRS_UNSPECIFIED);
+ }
+ void cpu_physical_memory_unmap(void *buffer, hwaddr len,
+diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/ppc/mmu-hash64.c
++++ b/target/ppc/mmu-hash64.c
+@@ -XXX,XX +XXX,XX @@ const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU *cpu,
+         return NULL;
+     }
+-    hptes = address_space_map(CPU(cpu)->as, base + pte_offset, &plen, false);
++    hptes = address_space_map(CPU(cpu)->as, base + pte_offset, &plen, false,
++                              MEMTXATTRS_UNSPECIFIED);
+     if (plen < (n * HASH_PTE_SIZE_64)) {
+         hw_error("%s: Unable to map all requested HPTEs\n", __func__);
+     }
+--
+.17.1

-[Qemu-devel] [PULL 12/13] nvic: Add missing 'break'
+[Qemu-devel] [PULL 14/25] Make address_space_access_valid() take a MemTxAttrs argument
-Coverity points out that we forgot the 'break' for
+As part of plumbing MemTxAttrs down to the IOMMU translate method,
-the SAU_CTRL write case (CID1381683). This has
+add MemTxAttrs as an argument to address_space_access_valid().
-no actual visible consequences because it happens
+Its callers either have an attrs value to hand, or don't care
-that the following case is effectively a no-op.
+and can use MEMTXATTRS_UNSPECIFIED.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Message-id: 1507742676-9908-1-git-send-email-peter.maydell@linaro.org
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20180521140402.23318-6-peter.maydell@linaro.org
 ---
- hw/intc/armv7m_nvic.c | 1 +
+ include/exec/memory.h      | 4 +++-
-file changed, 1 insertion(+)
+ include/sysemu/dma.h       | 3 ++-
  exec.c                     | 3 ++-
  target/s390x/diag.c        | 6 ++++--
  target/s390x/excp_helper.c | 3 ++-
  target/s390x/mmu_helper.c  | 3 ++-
  target/s390x/sigp.c        | 3 ++-
 files changed, 17 insertions(+), 8 deletions(-)
-diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
+diff --git a/include/exec/memory.h b/include/exec/memory.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/armv7m_nvic.c
+--- a/include/exec/memory.h
-+++ b/hw/intc/armv7m_nvic.c
++++ b/include/exec/memory.h
-@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
+@@ -XXX,XX +XXX,XX @@ static inline MemoryRegion *address_space_translate(AddressSpace *as,
   * @addr: address within that address space
   * @len: length of the area to be checked
   * @is_write: indicates the transfer direction
 + * @attrs: memory attributes
   */
 -bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_write);
 +bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len,
 +                                bool is_write, MemTxAttrs attrs);
  /* address_space_map: map a physical memory region into a host virtual address
   *
 diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/sysemu/dma.h
 +++ b/include/sysemu/dma.h
@@ -XXX,XX +XXX,XX @@ static inline bool dma_memory_valid(AddressSpace *as,
                                      DMADirection dir)
  {
      return address_space_access_valid(as, addr, len,
 -                                      dir == DMA_DIRECTION_FROM_DEVICE);
 +                                      dir == DMA_DIRECTION_FROM_DEVICE,
 +                                      MEMTXATTRS_UNSPECIFIED);
  }
  static inline int dma_memory_rw_relaxed(AddressSpace *as, dma_addr_t addr,
 diff --git a/exec.c b/exec.c
 index XXXXXXX..XXXXXXX 100644
 --- a/exec.c
 +++ b/exec.c
@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
  }
  bool address_space_access_valid(AddressSpace *as, hwaddr addr,
 -                                int len, bool is_write)
 +                                int len, bool is_write,
 +                                MemTxAttrs attrs)
  {
      FlatView *fv;
      bool result;
 diff --git a/target/s390x/diag.c b/target/s390x/diag.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/s390x/diag.c
 +++ b/target/s390x/diag.c
@@ -XXX,XX +XXX,XX @@ void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3, uintptr_t ra)
              return;
          }
-         cpu->env.sau.ctrl = value & 3;
+         if (!address_space_access_valid(&address_space_memory, addr,
-+        break;
+-                                        sizeof(IplParameterBlock), false)) {
-     case 0xdd4: /* SAU_TYPE */
++                                        sizeof(IplParameterBlock), false,
-         if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
++                                        MEMTXATTRS_UNSPECIFIED)) {
-             goto bad_offset;
+             s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra);
              return;
          }
@@ -XXX,XX +XXX,XX @@ out:
              return;
          }
          if (!address_space_access_valid(&address_space_memory, addr,
 -                                        sizeof(IplParameterBlock), true)) {
 +                                        sizeof(IplParameterBlock), true,
 +                                        MEMTXATTRS_UNSPECIFIED)) {
              s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra);
              return;
          }
 diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/s390x/excp_helper.c
 +++ b/target/s390x/excp_helper.c
@@ -XXX,XX +XXX,XX @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr, int size,
      /* check out of RAM access */
      if (!address_space_access_valid(&address_space_memory, raddr,
 -                                    TARGET_PAGE_SIZE, rw)) {
 +                                    TARGET_PAGE_SIZE, rw,
 +                                    MEMTXATTRS_UNSPECIFIED)) {
          DPRINTF("%s: raddr %" PRIx64 " > ram_size %" PRIx64 "\n", __func__,
                  (uint64_t)raddr, (uint64_t)ram_size);
          trigger_pgm_exception(env, PGM_ADDRESSING, ILEN_AUTO);
 diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/s390x/mmu_helper.c
 +++ b/target/s390x/mmu_helper.c
@@ -XXX,XX +XXX,XX @@ static int translate_pages(S390CPU *cpu, vaddr addr, int nr_pages,
              return ret;
          }
          if (!address_space_access_valid(&address_space_memory, pages[i],
 -                                        TARGET_PAGE_SIZE, is_write)) {
 +                                        TARGET_PAGE_SIZE, is_write,
 +                                        MEMTXATTRS_UNSPECIFIED)) {
              trigger_access_exception(env, PGM_ADDRESSING, ILEN_AUTO, 0);
              return -EFAULT;
          }
 diff --git a/target/s390x/sigp.c b/target/s390x/sigp.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/s390x/sigp.c
 +++ b/target/s390x/sigp.c
@@ -XXX,XX +XXX,XX @@ static void sigp_set_prefix(CPUState *cs, run_on_cpu_data arg)
      cpu_synchronize_state(cs);
      if (!address_space_access_valid(&address_space_memory, addr,
 -                                    sizeof(struct LowCore), false)) {
 +                                    sizeof(struct LowCore), false,
 +                                    MEMTXATTRS_UNSPECIFIED)) {
          set_sigp_status(si, SIGP_STAT_INVALID_PARAMETER);
          return;
      }
 --
-.7.4
+.17.1

-New patch
+[Qemu-devel] [PULL 15/25] Make flatview_extend_translation() take a MemTxAttrs argument
+As part of plumbing MemTxAttrs down to the IOMMU translate method,
+add MemTxAttrs as an argument to flatview_extend_translation().
+Its callers either have an attrs value to hand, or don't care
+and can use MEMTXATTRS_UNSPECIFIED.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20180521140402.23318-7-peter.maydell@linaro.org
+---
+ exec.c | 15 ++++++++++-----
+file changed, 10 insertions(+), 5 deletions(-)
+diff --git a/exec.c b/exec.c
+index XXXXXXX..XXXXXXX 100644
+--- a/exec.c
++++ b/exec.c
+@@ -XXX,XX +XXX,XX @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr,
+ static hwaddr
+ flatview_extend_translation(FlatView *fv, hwaddr addr,
+-                                 hwaddr target_len,
+-                                 MemoryRegion *mr, hwaddr base, hwaddr len,
+-                                 bool is_write)
++                            hwaddr target_len,
++                            MemoryRegion *mr, hwaddr base, hwaddr len,
++                            bool is_write, MemTxAttrs attrs)
+ {
+     hwaddr done = 0;
+     hwaddr xlat;
+@@ -XXX,XX +XXX,XX @@ void *address_space_map(AddressSpace *as,
+     memory_region_ref(mr);
+     *plen = flatview_extend_translation(fv, addr, len, mr, xlat,
+-                                             l, is_write);
++                                        l, is_write, attrs);
+     ptr = qemu_ram_ptr_length(mr->ram_block, xlat, plen, true);
+     rcu_read_unlock();
+@@ -XXX,XX +XXX,XX @@ int64_t address_space_cache_init(MemoryRegionCache *cache,
+     mr = cache->mrs.mr;
+     memory_region_ref(mr);
+     if (memory_access_is_direct(mr, is_write)) {
++        /* We don't care about the memory attributes here as we're only
++         * doing this if we found actual RAM, which behaves the same
++         * regardless of attributes; so UNSPECIFIED is fine.
++         */
+         l = flatview_extend_translation(cache->fv, addr, len, mr,
+-                                        cache->xlat, l, is_write);
++                                        cache->xlat, l, is_write,
++                                        MEMTXATTRS_UNSPECIFIED);
+         cache->ptr = qemu_ram_ptr_length(mr->ram_block, cache->xlat, &l, true);
+     } else {
+         cache->ptr = NULL;
+--
+.17.1

-New patch
+[Qemu-devel] [PULL 16/25] Make memory_region_access_valid() take a MemTxAttrs argument
+As part of plumbing MemTxAttrs down to the IOMMU translate method,
+add MemTxAttrs as an argument to memory_region_access_valid().
+Its callers either have an attrs value to hand, or don't care
+and can use MEMTXATTRS_UNSPECIFIED.
+The callsite in flatview_access_valid() is part of a recursive
+loop flatview_access_valid() -> memory_region_access_valid() ->
+ subpage_accepts() -> flatview_access_valid(); we make it pass
+MEMTXATTRS_UNSPECIFIED for now, until the next several commits
+have plumbed an attrs parameter through the rest of the loop
+and we can add an attrs parameter to flatview_access_valid().
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20180521140402.23318-8-peter.maydell@linaro.org
+---
+ include/exec/memory-internal.h | 3 ++-
+ exec.c                         | 4 +++-
+ hw/s390x/s390-pci-inst.c       | 3 ++-
+ memory.c                       | 7 ++++---
+files changed, 11 insertions(+), 6 deletions(-)
+diff --git a/include/exec/memory-internal.h b/include/exec/memory-internal.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/exec/memory-internal.h
++++ b/include/exec/memory-internal.h
+@@ -XXX,XX +XXX,XX @@ void flatview_unref(FlatView *view);
+ extern const MemoryRegionOps unassigned_mem_ops;
+ bool memory_region_access_valid(MemoryRegion *mr, hwaddr addr,
+-                                unsigned size, bool is_write);
++                                unsigned size, bool is_write,
++                                MemTxAttrs attrs);
+ void flatview_add_to_dispatch(FlatView *fv, MemoryRegionSection *section);
+ AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv);
+diff --git a/exec.c b/exec.c
+index XXXXXXX..XXXXXXX 100644
+--- a/exec.c
++++ b/exec.c
+@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
+         mr = flatview_translate(fv, addr, &xlat, &l, is_write);
+         if (!memory_access_is_direct(mr, is_write)) {
+             l = memory_access_size(mr, l, addr);
+-            if (!memory_region_access_valid(mr, xlat, l, is_write)) {
++            /* When our callers all have attrs we'll pass them through here */
++            if (!memory_region_access_valid(mr, xlat, l, is_write,
++                                            MEMTXATTRS_UNSPECIFIED)) {
+                 return false;
+             }
+         }
+diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/s390x/s390-pci-inst.c
++++ b/hw/s390x/s390-pci-inst.c
+@@ -XXX,XX +XXX,XX @@ int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr,
+     mr = s390_get_subregion(mr, offset, len);
+     offset -= mr->addr;
+-    if (!memory_region_access_valid(mr, offset, len, true)) {
++    if (!memory_region_access_valid(mr, offset, len, true,
++                                    MEMTXATTRS_UNSPECIFIED)) {
+         s390_program_interrupt(env, PGM_OPERAND, 6, ra);
+         return 0;
+     }
+diff --git a/memory.c b/memory.c
+index XXXXXXX..XXXXXXX 100644
+--- a/memory.c
++++ b/memory.c
+@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps ram_device_mem_ops = {
+ bool memory_region_access_valid(MemoryRegion *mr,
+                                 hwaddr addr,
+                                 unsigned size,
+-                                bool is_write)
++                                bool is_write,
++                                MemTxAttrs attrs)
+ {
+     int access_size_min, access_size_max;
+     int access_size, i;
+@@ -XXX,XX +XXX,XX @@ MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
+ {
+     MemTxResult r;
+-    if (!memory_region_access_valid(mr, addr, size, false)) {
++    if (!memory_region_access_valid(mr, addr, size, false, attrs)) {
+         *pval = unassigned_mem_read(mr, addr, size);
+         return MEMTX_DECODE_ERROR;
+     }
+@@ -XXX,XX +XXX,XX @@ MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
+                                          unsigned size,
+                                          MemTxAttrs attrs)
+ {
+-    if (!memory_region_access_valid(mr, addr, size, true)) {
++    if (!memory_region_access_valid(mr, addr, size, true, attrs)) {
+         unassigned_mem_write(mr, addr, data, size);
+         return MEMTX_DECODE_ERROR;
+     }
+--
+.17.1

-[Qemu-devel] [PULL 05/13] target/arm: Implement BLXNS
+[Qemu-devel] [PULL 17/25] Make MemoryRegion valid.accepts callback take a MemTxAttrs argument
-Implement the BLXNS instruction, which allows secure code to
+As part of plumbing MemTxAttrs down to the IOMMU translate method,
-call non-secure code.
+add MemTxAttrs as an argument to the MemoryRegion valid.accepts
 callback. We'll need this for subpage_accepts().
 We could take the approach we used with the read and write
 callbacks and add new a new _with_attrs version, but since there
 are so few implementations of the accepts hook we just change
 them all.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 1507556919-24992-4-git-send-email-peter.maydell@linaro.org
+Message-id: 20180521140402.23318-9-peter.maydell@linaro.org
 ---
- target/arm/helper.h    |  1 +
+ include/exec/memory.h |  3 ++-
- target/arm/internals.h |  1 +
+ exec.c                |  9 ++++++---
- target/arm/helper.c    | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++
+ hw/hppa/dino.c        |  3 ++-
- target/arm/translate.c | 17 +++++++++++++--
+ hw/nvram/fw_cfg.c     | 12 ++++++++----
-files changed, 76 insertions(+), 2 deletions(-)
+ hw/scsi/esp.c         |  3 ++-
  hw/xen/xen_pt_msi.c   |  3 ++-
  memory.c              |  5 +++--
 files changed, 25 insertions(+), 13 deletions(-)
-diff --git a/target/arm/helper.h b/target/arm/helper.h
+diff --git a/include/exec/memory.h b/include/exec/memory.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.h
+--- a/include/exec/memory.h
-+++ b/target/arm/helper.h
++++ b/include/exec/memory.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(v7m_msr, void, env, i32, i32)
+@@ -XXX,XX +XXX,XX @@ struct MemoryRegionOps {
- DEF_HELPER_2(v7m_mrs, i32, env, i32)
+          * as a machine check exception).
+          */
- DEF_HELPER_2(v7m_bxns, void, env, i32)
+         bool (*accepts)(void *opaque, hwaddr addr,
-+DEF_HELPER_2(v7m_blxns, void, env, i32)
+-                        unsigned size, bool is_write);
++                        unsigned size, bool is_write,
- DEF_HELPER_4(access_check_cp_reg, void, env, ptr, i32, i32)
++                        MemTxAttrs attrs);
- DEF_HELPER_3(set_cp_reg, void, env, ptr, i32)
+     } valid;
-diff --git a/target/arm/internals.h b/target/arm/internals.h
+     /* Internal implementation constraints: */
      struct {
 diff --git a/exec.c b/exec.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/internals.h
+--- a/exec.c
-+++ b/target/arm/internals.h
++++ b/exec.c
-@@ -XXX,XX +XXX,XX @@ static inline bool excp_is_internal(int excp)
+@@ -XXX,XX +XXX,XX @@ static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
- FIELD(V7M_CONTROL, NPRIV, 0, 1)
+ }
- FIELD(V7M_CONTROL, SPSEL, 1, 1)
- FIELD(V7M_CONTROL, FPCA, 2, 1)
+ static bool notdirty_mem_accepts(void *opaque, hwaddr addr,
-+FIELD(V7M_CONTROL, SFPA, 3, 1)
+-                                 unsigned size, bool is_write)
++                                 unsigned size, bool is_write,
- /* Bit definitions for v7M exception return payload */
++                                 MemTxAttrs attrs)
- FIELD(V7M_EXCRET, ES, 0, 1)
+ {
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+     return is_write;
  }
@@ -XXX,XX +XXX,XX @@ static MemTxResult subpage_write(void *opaque, hwaddr addr,
  }
  static bool subpage_accepts(void *opaque, hwaddr addr,
 -                            unsigned len, bool is_write)
 +                            unsigned len, bool is_write,
 +                            MemTxAttrs attrs)
  {
      subpage_t *subpage = opaque;
  #if defined(DEBUG_SUBPAGE)
@@ -XXX,XX +XXX,XX @@ static void readonly_mem_write(void *opaque, hwaddr addr,
  }
  static bool readonly_mem_accepts(void *opaque, hwaddr addr,
 -                                 unsigned size, bool is_write)
 +                                 unsigned size, bool is_write,
 +                                 MemTxAttrs attrs)
  {
      return is_write;
  }
 diff --git a/hw/hppa/dino.c b/hw/hppa/dino.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/hw/hppa/dino.c
-+++ b/target/arm/helper.c
++++ b/hw/hppa/dino.c
-@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)
+@@ -XXX,XX +XXX,XX @@ static void gsc_to_pci_forwarding(DinoState *s)
      g_assert_not_reached();
  }
-+void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
+ static bool dino_chip_mem_valid(void *opaque, hwaddr addr,
-+{
+-                                unsigned size, bool is_write)
-+    /* translate.c should never generate calls here in user-only mode */
++                                unsigned size, bool is_write,
-+    g_assert_not_reached();
++                                MemTxAttrs attrs)
 +}
 +
  void switch_mode(CPUARMState *env, int mode)
  {
-     ARMCPU *cpu = arm_env_get_cpu(env);
+     switch (addr) {
-@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)
+     case DINO_IAR0:
-     env->regs[15] = dest & ~1;
+diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/nvram/fw_cfg.c
 +++ b/hw/nvram/fw_cfg.c
@@ -XXX,XX +XXX,XX @@ static void fw_cfg_dma_mem_write(void *opaque, hwaddr addr,
  }
-+void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
+ static bool fw_cfg_dma_mem_valid(void *opaque, hwaddr addr,
-+{
+-                                  unsigned size, bool is_write)
-+    /* Handle v7M BLXNS:
++                                 unsigned size, bool is_write,
-+     *  - bit 0 of the destination address is the target security state
++                                 MemTxAttrs attrs)
 +     */
 +
 +    /* At this point regs[15] is the address just after the BLXNS */
 +    uint32_t nextinst = env->regs[15] | 1;
 +    uint32_t sp = env->regs[13] - 8;
 +    uint32_t saved_psr;
 +
 +    /* translate.c will have made BLXNS UNDEF unless we're secure */
 +    assert(env->v7m.secure);
 +
 +    if (dest & 1) {
 +        /* target is Secure, so this is just a normal BLX,
 +         * except that the low bit doesn't indicate Thumb/not.
 +         */
 +        env->regs[14] = nextinst;
 +        env->thumb = 1;
 +        env->regs[15] = dest & ~1;
 +        return;
 +    }
 +
 +    /* Target is non-secure: first push a stack frame */
 +    if (!QEMU_IS_ALIGNED(sp, 8)) {
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "BLXNS with misaligned SP is UNPREDICTABLE\n");
 +    }
 +
 +    saved_psr = env->v7m.exception;
 +    if (env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK) {
 +        saved_psr |= XPSR_SFPA;
 +    }
 +
 +    /* Note that these stores can throw exceptions on MPU faults */
 +    cpu_stl_data(env, sp, nextinst);
 +    cpu_stl_data(env, sp + 4, saved_psr);
 +
 +    env->regs[13] = sp;
 +    env->regs[14] = 0xfeffffff;
 +    if (arm_v7m_is_handler_mode(env)) {
 +        /* Write a dummy value to IPSR, to avoid leaking the current secure
 +         * exception number to non-secure code. This is guaranteed not
 +         * to cause write_v7m_exception() to actually change stacks.
 +         */
 +        write_v7m_exception(env, 1);
 +    }
 +    switch_v7m_security_state(env, 0);
 +    env->thumb = 1;
 +    env->regs[15] = dest;
 +}
 +
  static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode,
                                  bool spsel)
  {
-diff --git a/target/arm/translate.c b/target/arm/translate.c
+     return !is_write || ((size == 4 && (addr == 0 || addr == 4)) ||
                           (size == 8 && addr == 0));
  }
  static bool fw_cfg_data_mem_valid(void *opaque, hwaddr addr,
 -                                  unsigned size, bool is_write)
 +                                  unsigned size, bool is_write,
 +                                  MemTxAttrs attrs)
  {
      return addr == 0;
  }
@@ -XXX,XX +XXX,XX @@ static void fw_cfg_ctl_mem_write(void *opaque, hwaddr addr,
  }
  static bool fw_cfg_ctl_mem_valid(void *opaque, hwaddr addr,
 -                                 unsigned size, bool is_write)
 +                                 unsigned size, bool is_write,
 +                                 MemTxAttrs attrs)
  {
      return is_write && size == 2;
  }
@@ -XXX,XX +XXX,XX @@ static void fw_cfg_comb_write(void *opaque, hwaddr addr,
  }
  static bool fw_cfg_comb_valid(void *opaque, hwaddr addr,
 -                                  unsigned size, bool is_write)
 +                              unsigned size, bool is_write,
 +                              MemTxAttrs attrs)
  {
      return (size == 1) || (is_write && size == 2);
  }
 diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
+--- a/hw/scsi/esp.c
-+++ b/target/arm/translate.c
++++ b/hw/scsi/esp.c
-@@ -XXX,XX +XXX,XX @@ static inline void gen_bxns(DisasContext *s, int rm)
+@@ -XXX,XX +XXX,XX @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
      s->base.is_jmp = DISAS_EXIT;
  }
-+static inline void gen_blxns(DisasContext *s, int rm)
+ static bool esp_mem_accepts(void *opaque, hwaddr addr,
-+{
+-                            unsigned size, bool is_write)
-+    TCGv_i32 var = load_reg(s, rm);
++                            unsigned size, bool is_write,
-+
++                            MemTxAttrs attrs)
-+    /* We don't need to sync condexec state, for the same reason as bxns.
+ {
-+     * We do however need to set the PC, because the blxns helper reads it.
+     return (size == 1) || (is_write && size == 4);
-+     * The blxns helper may throw an exception.
+ }
-+     */
+diff --git a/hw/xen/xen_pt_msi.c b/hw/xen/xen_pt_msi.c
-+    gen_set_pc_im(s, s->pc);
+index XXXXXXX..XXXXXXX 100644
-+    gen_helper_v7m_blxns(cpu_env, var);
+--- a/hw/xen/xen_pt_msi.c
-+    tcg_temp_free_i32(var);
++++ b/hw/xen/xen_pt_msi.c
-+    s->base.is_jmp = DISAS_EXIT;
+@@ -XXX,XX +XXX,XX @@ static uint64_t pci_msix_read(void *opaque, hwaddr addr,
-+}
+ }
-+
- /* Variant of store_reg which uses branch&exchange logic when storing
+ static bool pci_msix_accepts(void *opaque, hwaddr addr,
-    to r15 in ARM architecture v7 and above. The source must be a temporary
+-                             unsigned size, bool is_write)
-    and will be marked as dead. */
++                             unsigned size, bool is_write,
-@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
++                             MemTxAttrs attrs)
-                         goto undef;
+ {
-                     }
+     return !(addr & (size - 1));
-                     if (link) {
+ }
--                        /* BLXNS: not yet implemented */
+diff --git a/memory.c b/memory.c
--                        goto undef;
+index XXXXXXX..XXXXXXX 100644
-+                        gen_blxns(s, rm);
+--- a/memory.c
-                     } else {
++++ b/memory.c
-                         gen_bxns(s, rm);
+@@ -XXX,XX +XXX,XX @@ static void unassigned_mem_write(void *opaque, hwaddr addr,
-                     }
+ }
  static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
 -                                   unsigned size, bool is_write)
 +                                   unsigned size, bool is_write,
 +                                   MemTxAttrs attrs)
  {
      return false;
  }
@@ -XXX,XX +XXX,XX @@ bool memory_region_access_valid(MemoryRegion *mr,
      access_size = MAX(MIN(size, access_size_max), access_size_min);
      for (i = 0; i < size; i += access_size) {
          if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
 -                                    is_write)) {
 +                                    is_write, attrs)) {
              return false;
          }
      }
 --
-.7.4
+.17.1

-[Qemu-devel] [PULL 06/13] target/arm: Implement secure function return
+[Qemu-devel] [PULL 18/25] Make flatview_access_valid() take a MemTxAttrs argument
-Secure function return happens when a non-secure function has been
+As part of plumbing MemTxAttrs down to the IOMMU translate method,
-called using BLXNS and so has a particular magic LR value (either
+add MemTxAttrs as an argument to flatview_access_valid().
-xfefffffe or 0xfeffffff). The function return via BX behaves
+Its callers now all have an attrs value to hand, so we can
-specially when the new PC value is this magic value, in the same
+correct our earlier temporary use of MEMTXATTRS_UNSPECIFIED.
 way that exception returns are handled.
 Adjust our BX excret guards so that they recognize the function
 return magic number as well, and perform the function-return
 unstacking in do_v7m_exception_exit().
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 1507556919-24992-5-git-send-email-peter.maydell@linaro.org
+Message-id: 20180521140402.23318-10-peter.maydell@linaro.org
 ---
- target/arm/internals.h |   7 +++
+ exec.c | 12 +++++-------
- target/arm/helper.c    | 115 +++++++++++++++++++++++++++++++++++++++++++++----
+file changed, 5 insertions(+), 7 deletions(-)
  target/arm/translate.c |  14 +++++-
 files changed, 126 insertions(+), 10 deletions(-)
-diff --git a/target/arm/internals.h b/target/arm/internals.h
+diff --git a/exec.c b/exec.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/internals.h
+--- a/exec.c
-+++ b/target/arm/internals.h
++++ b/exec.c
-@@ -XXX,XX +XXX,XX @@ FIELD(V7M_EXCRET, DCRS, 5, 1)
+@@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
- FIELD(V7M_EXCRET, S, 6, 1)
+ static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
- FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */
+                                   const uint8_t *buf, int len);
+ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
-+/* Minimum value which is a magic number for exception return */
+-                                  bool is_write);
-+#define EXC_RETURN_MIN_MAGIC 0xff000000
++                                  bool is_write, MemTxAttrs attrs);
-+/* Minimum number which is a magic number for function or exception return
-+ * when using v8M security extension
+ static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data,
-+ */
+                                 unsigned len, MemTxAttrs attrs)
-+#define FNC_RETURN_MIN_MAGIC 0xfefffffe
+@@ -XXX,XX +XXX,XX @@ static bool subpage_accepts(void *opaque, hwaddr addr,
-+
+ #endif
- /* We use a few fake FSR values for internal purposes in M profile.
-  * M profile cores don't have A/R format FSRs, but currently our
+     return flatview_access_valid(subpage->fv, addr + subpage->base,
-  * get_phys_addr() code assumes A/R profile and reports failures via
+-                                 len, is_write);
-diff --git a/target/arm/helper.c b/target/arm/helper.c
++                                 len, is_write, attrs);
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)
       *  - if the return value is a magic value, do exception return (like BX)
       *  - otherwise bit 0 of the return value is the target security state
       */
 -    if (dest >= 0xff000000) {
 +    uint32_t min_magic;
 +
 +    if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
 +        /* Covers FNC_RETURN and EXC_RETURN magic */
 +        min_magic = FNC_RETURN_MIN_MAGIC;
 +    } else {
 +        /* EXC_RETURN magic only */
 +        min_magic = EXC_RETURN_MIN_MAGIC;
 +    }
 +
 +    if (dest >= min_magic) {
          /* This is an exception return magic value; put it where
           * do_v7m_exception_exit() expects and raise EXCEPTION_EXIT.
           * Note that if we ever add gen_ss_advance() singlestep support to
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
      bool exc_secure = false;
      bool return_to_secure;
 -    /* We can only get here from an EXCP_EXCEPTION_EXIT, and
 -     * gen_bx_excret() enforces the architectural rule
 -     * that jumps to magic addresses don't have magic behaviour unless
 -     * we're in Handler mode (compare pseudocode BXWritePC()).
 +    /* If we're not in Handler mode then jumps to magic exception-exit
 +     * addresses don't have magic behaviour. However for the v8M
 +     * security extensions the magic secure-function-return has to
 +     * work in thread mode too, so to avoid doing an extra check in
 +     * the generated code we allow exception-exit magic to also cause the
 +     * internal exception and bring us here in thread mode. Correct code
 +     * will never try to do this (the following insn fetch will always
 +     * fault) so we the overhead of having taken an unnecessary exception
 +     * doesn't matter.
       */
 -    assert(arm_v7m_is_handler_mode(env));
 +    if (!arm_v7m_is_handler_mode(env)) {
 +        return;
 +    }
      /* In the spec pseudocode ExceptionReturn() is called directly
       * from BXWritePC() and gets the full target PC value including
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
      qemu_log_mask(CPU_LOG_INT, "...successful exception return\n");
  }
-+static bool do_v7m_function_return(ARMCPU *cpu)
+ static const MemoryRegionOps subpage_ops = {
-+{
+@@ -XXX,XX +XXX,XX @@ static void cpu_notify_map_clients(void)
-+    /* v8M security extensions magic function return.
+ }
-+     * We may either:
-+     *  (1) throw an exception (longjump)
+ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
-+     *  (2) return true if we successfully handled the function return
+-                                  bool is_write)
-+     *  (3) return false if we failed a consistency check and have
++                                  bool is_write, MemTxAttrs attrs)
 +     *      pended a UsageFault that needs to be taken now
 +     *
 +     * At this point the magic return value is split between env->regs[15]
 +     * and env->thumb. We don't bother to reconstitute it because we don't
 +     * need it (all values are handled the same way).
 +     */
 +    CPUARMState *env = &cpu->env;
 +    uint32_t newpc, newpsr, newpsr_exc;
 +
 +    qemu_log_mask(CPU_LOG_INT, "...really v7M secure function return\n");
 +
 +    {
 +        bool threadmode, spsel;
 +        TCGMemOpIdx oi;
 +        ARMMMUIdx mmu_idx;
 +        uint32_t *frame_sp_p;
 +        uint32_t frameptr;
 +
 +        /* Pull the return address and IPSR from the Secure stack */
 +        threadmode = !arm_v7m_is_handler_mode(env);
 +        spsel = env->v7m.control[M_REG_S] & R_V7M_CONTROL_SPSEL_MASK;
 +
 +        frame_sp_p = get_v7m_sp_ptr(env, true, threadmode, spsel);
 +        frameptr = *frame_sp_p;
 +
 +        /* These loads may throw an exception (for MPU faults). We want to
 +         * do them as secure, so work out what MMU index that is.
 +         */
 +        mmu_idx = arm_v7m_mmu_idx_for_secstate(env, true);
 +        oi = make_memop_idx(MO_LE, arm_to_core_mmu_idx(mmu_idx));
 +        newpc = helper_le_ldul_mmu(env, frameptr, oi, 0);
 +        newpsr = helper_le_ldul_mmu(env, frameptr + 4, oi, 0);
 +
 +        /* Consistency checks on new IPSR */
 +        newpsr_exc = newpsr & XPSR_EXCP;
 +        if (!((env->v7m.exception == 0 && newpsr_exc == 0) ||
 +              (env->v7m.exception == 1 && newpsr_exc != 0))) {
 +            /* Pend the fault and tell our caller to take it */
 +            env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;
 +            armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE,
 +                                    env->v7m.secure);
 +            qemu_log_mask(CPU_LOG_INT,
 +                          "...taking INVPC UsageFault: "
 +                          "IPSR consistency check failed\n");
 +            return false;
 +        }
 +
 +        *frame_sp_p = frameptr + 8;
 +    }
 +
 +    /* This invalidates frame_sp_p */
 +    switch_v7m_security_state(env, true);
 +    env->v7m.exception = newpsr_exc;
 +    env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK;
 +    if (newpsr & XPSR_SFPA) {
 +        env->v7m.control[M_REG_S] |= R_V7M_CONTROL_SFPA_MASK;
 +    }
 +    xpsr_write(env, 0, XPSR_IT);
 +    env->thumb = newpc & 1;
 +    env->regs[15] = newpc & ~1;
 +
 +    qemu_log_mask(CPU_LOG_INT, "...function return successful\n");
 +    return true;
 +}
 +
  static void arm_log_exception(int idx)
  {
-     if (qemu_loglevel_mask(CPU_LOG_INT)) {
+     MemoryRegion *mr;
-@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
+     hwaddr l, xlat;
-     case EXCP_IRQ:
+@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
-         break;
+         mr = flatview_translate(fv, addr, &xlat, &l, is_write);
-     case EXCP_EXCEPTION_EXIT:
+         if (!memory_access_is_direct(mr, is_write)) {
--        do_v7m_exception_exit(cpu);
+             l = memory_access_size(mr, l, addr);
--        return;
+-            /* When our callers all have attrs we'll pass them through here */
-+        if (env->regs[15] < EXC_RETURN_MIN_MAGIC) {
+-            if (!memory_region_access_valid(mr, xlat, l, is_write,
-+            /* Must be v8M security extension function return */
+-                                            MEMTXATTRS_UNSPECIFIED)) {
-+            assert(env->regs[15] >= FNC_RETURN_MIN_MAGIC);
++            if (!memory_region_access_valid(mr, xlat, l, is_write, attrs)) {
-+            assert(arm_feature(env, ARM_FEATURE_M_SECURITY));
+                 return false;
-+            if (do_v7m_function_return(cpu)) {
+             }
-+                return;
+         }
-+            }
+@@ -XXX,XX +XXX,XX @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr,
-+        } else {
-+            do_v7m_exception_exit(cpu);
+     rcu_read_lock();
-+            return;
+     fv = address_space_to_flatview(as);
-+        }
+-    result = flatview_access_valid(fv, addr, len, is_write);
-+        break;
++    result = flatview_access_valid(fv, addr, len, is_write, attrs);
-     default:
+     rcu_read_unlock();
-         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
+     return result;
          return; /* Never happens.  Keep compiler happy.  */
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static inline void gen_bx_excret(DisasContext *s, TCGv_i32 var)
       * s->base.is_jmp that we need to do the rest of the work later.
       */
      gen_bx(s, var);
 -    if (s->v7m_handler_mode && arm_dc_feature(s, ARM_FEATURE_M)) {
 +    if (arm_dc_feature(s, ARM_FEATURE_M_SECURITY) ||
 +        (s->v7m_handler_mode && arm_dc_feature(s, ARM_FEATURE_M))) {
          s->base.is_jmp = DISAS_BX_EXCRET;
      }
  }
-@@ -XXX,XX +XXX,XX @@ static inline void gen_bx_excret_final_code(DisasContext *s)
- {
-     /* Generate the code to finish possible exception return and end the TB */
-     TCGLabel *excret_label = gen_new_label();
-+    uint32_t min_magic;
-+
-+    if (arm_dc_feature(s, ARM_FEATURE_M_SECURITY)) {
-+        /* Covers FNC_RETURN and EXC_RETURN magic */
-+        min_magic = FNC_RETURN_MIN_MAGIC;
-+    } else {
-+        /* EXC_RETURN magic only */
-+        min_magic = EXC_RETURN_MIN_MAGIC;
-+    }
-     /* Is the new PC value in the magic range indicating exception return? */
--    tcg_gen_brcondi_i32(TCG_COND_GEU, cpu_R[15], 0xff000000, excret_label);
-+    tcg_gen_brcondi_i32(TCG_COND_GEU, cpu_R[15], min_magic, excret_label);
-     /* No: end the TB as we would for a DISAS_JMP */
-     if (is_singlestepping(s)) {
-         gen_singlestep_exception(s);
 --
-.7.4
+.17.1

-[Qemu-devel] [PULL 10/13] target/arm: Support some Thumb insns being always unconditional
+[Qemu-devel] [PULL 19/25] Make flatview_translate() take a MemTxAttrs argument
-A few Thumb instructions are always unconditional even inside an
+As part of plumbing MemTxAttrs down to the IOMMU translate method,
-IT block (as opposed to being UNPREDICTABLE if used inside an
+add MemTxAttrs as an argument to flatview_translate(); all its
-IT block): BKPT, the v8M SG instruction, and the A profile
+callers now have attrs available.
 HLT (debug halt) instruction.
 This means we need to suppress the jump-over-instruction-on-condfail
 code generation (though the IT state still advances as usual and
 subsequent insns in the IT block may be conditional).
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 1507556919-24992-9-git-send-email-peter.maydell@linaro.org
+Message-id: 20180521140402.23318-11-peter.maydell@linaro.org
 ---
- target/arm/translate.c | 48 +++++++++++++++++++++++++++++++++++++++++++++++-
+ include/exec/memory.h |  7 ++++---
-file changed, 47 insertions(+), 1 deletion(-)
+ exec.c                | 17 +++++++++--------
 files changed, 13 insertions(+), 11 deletions(-)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
+diff --git a/include/exec/memory.h b/include/exec/memory.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
+--- a/include/exec/memory.h
-+++ b/target/arm/translate.c
++++ b/include/exec/memory.h
-@@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
+@@ -XXX,XX +XXX,XX @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
-        in init_disas_context by adjusting max_insns.  */
+  */
  MemoryRegion *flatview_translate(FlatView *fv,
                                   hwaddr addr, hwaddr *xlat,
 -                                 hwaddr *len, bool is_write);
 +                                 hwaddr *len, bool is_write,
 +                                 MemTxAttrs attrs);
  static inline MemoryRegion *address_space_translate(AddressSpace *as,
                                                      hwaddr addr, hwaddr *xlat,
@@ -XXX,XX +XXX,XX @@ static inline MemoryRegion *address_space_translate(AddressSpace *as,
                                                      MemTxAttrs attrs)
  {
      return flatview_translate(address_space_to_flatview(as),
 -                              addr, xlat, len, is_write);
 +                              addr, xlat, len, is_write, attrs);
  }
-+static bool thumb_insn_is_unconditional(DisasContext *s, uint32_t insn)
+ /* address_space_access_valid: check for validity of accessing an address
-+{
+@@ -XXX,XX +XXX,XX @@ MemTxResult address_space_read(AddressSpace *as, hwaddr addr,
-+    /* Return true if this Thumb insn is always unconditional,
+             rcu_read_lock();
-+     * even inside an IT block. This is true of only a very few
+             fv = address_space_to_flatview(as);
-+     * instructions: BKPT, HLT, and SG.
+             l = len;
-+     *
+-            mr = flatview_translate(fv, addr, &addr1, &l, false);
-+     * A larger class of instructions are UNPREDICTABLE if used
++            mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
-+     * inside an IT block; we do not need to detect those here, because
+             if (len == l && memory_access_is_direct(mr, false)) {
-+     * what we do by default (perform the cc check and update the IT
+                 ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
-+     * bits state machine) is a permitted CONSTRAINED UNPREDICTABLE
+                 memcpy(buf, ptr, len);
-+     * choice for those situations.
+diff --git a/exec.c b/exec.c
-+     *
+index XXXXXXX..XXXXXXX 100644
-+     * insn is either a 16-bit or a 32-bit instruction; the two are
+--- a/exec.c
-+     * distinguishable because for the 16-bit case the top 16 bits
++++ b/exec.c
-+     * are zeroes, and that isn't a valid 32-bit encoding.
+@@ -XXX,XX +XXX,XX @@ iotlb_fail:
-+     */
-+    if ((insn & 0xffffff00) == 0xbe00) {
+ /* Called from RCU critical section */
-+        /* BKPT */
+ MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat,
-+        return true;
+-                                 hwaddr *plen, bool is_write)
-+    }
++                                 hwaddr *plen, bool is_write,
-+
++                                 MemTxAttrs attrs)
 +    if ((insn & 0xffffffc0) == 0xba80 && arm_dc_feature(s, ARM_FEATURE_V8) &&
 +        !arm_dc_feature(s, ARM_FEATURE_M)) {
 +        /* HLT: v8A only. This is unconditional even when it is going to
 +         * UNDEF; see the v8A ARM ARM DDI0487B.a H3.3.
 +         * For v7 cores this was a plain old undefined encoding and so
 +         * honours its cc check. (We might be using the encoding as
 +         * a semihosting trap, but we don't change the cc check behaviour
 +         * on that account, because a debugger connected to a real v7A
 +         * core and emulating semihosting traps by catching the UNDEF
 +         * exception would also only see cases where the cc check passed.
 +         * No guest code should be trying to do a HLT semihosting trap
 +         * in an IT block anyway.
 +         */
 +        return true;
 +    }
 +
 +    if (insn == 0xe97fe97f && arm_dc_feature(s, ARM_FEATURE_V8) &&
 +        arm_dc_feature(s, ARM_FEATURE_M)) {
 +        /* SG: v8M only */
 +        return true;
 +    }
 +
 +    return false;
 +}
 +
  static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
  {
-     DisasContext *dc = container_of(dcbase, DisasContext, base);
+     MemoryRegion *mr;
-@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
+     MemoryRegionSection section;
-         dc->pc += 2;
+@@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr,
          }
          l = len;
 -        mr = flatview_translate(fv, addr, &addr1, &l, true);
 +        mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
      }
--    if (dc->condexec_mask) {
+     return result;
-+    if (dc->condexec_mask && !thumb_insn_is_unconditional(dc, insn)) {
+@@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
-         uint32_t cond = dc->condexec_cond;
+     MemTxResult result = MEMTX_OK;
-         if (cond != 0x0e) {     /* Skip conditional when condition is AL. */
+     l = len;
 -    mr = flatview_translate(fv, addr, &addr1, &l, true);
 +    mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
      result = flatview_write_continue(fv, addr, attrs, buf, len,
                                       addr1, l, mr);
@@ -XXX,XX +XXX,XX @@ MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr,
          }
          l = len;
 -        mr = flatview_translate(fv, addr, &addr1, &l, false);
 +        mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
      }
      return result;
@@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
      MemoryRegion *mr;
      l = len;
 -    mr = flatview_translate(fv, addr, &addr1, &l, false);
 +    mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
      return flatview_read_continue(fv, addr, attrs, buf, len,
                                    addr1, l, mr);
  }
@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
      while (len > 0) {
          l = len;
 -        mr = flatview_translate(fv, addr, &xlat, &l, is_write);
 +        mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs);
          if (!memory_access_is_direct(mr, is_write)) {
              l = memory_access_size(mr, l, addr);
              if (!memory_region_access_valid(mr, xlat, l, is_write, attrs)) {
@@ -XXX,XX +XXX,XX @@ flatview_extend_translation(FlatView *fv, hwaddr addr,
          len = target_len;
          this_mr = flatview_translate(fv, addr, &xlat,
 -                                                   &len, is_write);
 +                                     &len, is_write, attrs);
          if (this_mr != mr || xlat != base + done) {
              return done;
          }
@@ -XXX,XX +XXX,XX @@ void *address_space_map(AddressSpace *as,
      l = len;
      rcu_read_lock();
      fv = address_space_to_flatview(as);
 -    mr = flatview_translate(fv, addr, &xlat, &l, is_write);
 +    mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs);
      if (!memory_access_is_direct(mr, is_write)) {
          if (atomic_xchg(&bounce.in_use, true)) {
 --
-.7.4
+.17.1

-New patch
+[Qemu-devel] [PULL 20/25] Make address_space_get_iotlb_entry() take a MemTxAttrs argument
+As part of plumbing MemTxAttrs down to the IOMMU translate method,
+add MemTxAttrs as an argument to address_space_get_iotlb_entry().
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20180521140402.23318-12-peter.maydell@linaro.org
+---
+ include/exec/memory.h | 2 +-
+ exec.c                | 2 +-
+ hw/virtio/vhost.c     | 3 ++-
+files changed, 4 insertions(+), 3 deletions(-)
+diff --git a/include/exec/memory.h b/include/exec/memory.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/exec/memory.h
++++ b/include/exec/memory.h
+@@ -XXX,XX +XXX,XX @@ void address_space_cache_destroy(MemoryRegionCache *cache);
+  * entry. Should be called from an RCU critical section.
+  */
+ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
+-                                            bool is_write);
++                                            bool is_write, MemTxAttrs attrs);
+ /* address_space_translate: translate an address range into an address space
+  * into a MemoryRegion and an address range into that section.  Should be
+diff --git a/exec.c b/exec.c
+index XXXXXXX..XXXXXXX 100644
+--- a/exec.c
++++ b/exec.c
+@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,
+ /* Called from RCU critical section */
+ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
+-                                            bool is_write)
++                                            bool is_write, MemTxAttrs attrs)
+ {
+     MemoryRegionSection section;
+     hwaddr xlat, page_mask;
+diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/virtio/vhost.c
++++ b/hw/virtio/vhost.c
+@@ -XXX,XX +XXX,XX @@ int vhost_device_iotlb_miss(struct vhost_dev *dev, uint64_t iova, int write)
+     trace_vhost_iotlb_miss(dev, 1);
+     iotlb = address_space_get_iotlb_entry(dev->vdev->dma_as,
+-                                          iova, write);
++                                          iova, write,
++                                          MEMTXATTRS_UNSPECIFIED);
+     if (iotlb.target_as != NULL) {
+         ret = vhost_memory_region_lookup(dev, iotlb.translated_addr,
+                                          &uaddr, &len);
+--
+.17.1

-[Qemu-devel] [PULL 07/13] target-arm: Don't check for "Thumb2 or M profile" for not-Thumb1
+[Qemu-devel] [PULL 21/25] Make flatview_do_translate() take a MemTxAttrs argument
-The code which implements the Thumb1 split BL/BLX instructions
+As part of plumbing MemTxAttrs down to the IOMMU translate method,
-is guarded by a check on "not M or THUMB2". All we really need
+add MemTxAttrs as an argument to flatview_do_translate().
 to check here is "not THUMB2" (and we assume that elsewhere too,
 eg in the ARCH(6T2) test that UNDEFs the Thumb2 insns).
 This doesn't change behaviour because all M profile cores
 have Thumb2 and so ARM_FEATURE_M implies ARM_FEATURE_THUMB2.
 (v6M implements a very restricted subset of Thumb2, but we
 can cross that bridge when we get to it with appropriate
 feature bits.)
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 1507556919-24992-6-git-send-email-peter.maydell@linaro.org
+Message-id: 20180521140402.23318-13-peter.maydell@linaro.org
 ---
- target/arm/translate.c | 3 +--
+ exec.c | 9 ++++++---
-file changed, 1 insertion(+), 2 deletions(-)
+file changed, 6 insertions(+), 3 deletions(-)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
+diff --git a/exec.c b/exec.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
+--- a/exec.c
-+++ b/target/arm/translate.c
++++ b/exec.c
-@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
+@@ -XXX,XX +XXX,XX @@ unassigned:
-     int conds;
+  * @is_write: whether the translation operation is for write
-     int logic_cc;
+  * @is_mmio: whether this can be MMIO, set true if it can
+  * @target_as: the address space targeted by the IOMMU
--    if (!(arm_dc_feature(s, ARM_FEATURE_THUMB2)
++ * @attrs: memory transaction attributes
--          || arm_dc_feature(s, ARM_FEATURE_M))) {
+  *
-+    if (!arm_dc_feature(s, ARM_FEATURE_THUMB2)) {
+  * This function is called from RCU critical section
-         /* Thumb-1 cores may need to treat bl and blx as a pair of
+  */
--bit instructions to get correct prefetch abort behavior.  */
+@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,
-         insn = insn_hw1;
+                                                  hwaddr *page_mask_out,
                                                   bool is_write,
                                                   bool is_mmio,
 -                                                 AddressSpace **target_as)
 +                                                 AddressSpace **target_as,
 +                                                 MemTxAttrs attrs)
  {
      MemoryRegionSection *section;
      IOMMUMemoryRegion *iommu_mr;
@@ -XXX,XX +XXX,XX @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
       * but page mask.
       */
      section = flatview_do_translate(address_space_to_flatview(as), addr, &xlat,
 -                                    NULL, &page_mask, is_write, false, &as);
 +                                    NULL, &page_mask, is_write, false, &as,
 +                                    attrs);
      /* Illegal translation */
      if (section.mr == &io_mem_unassigned) {
@@ -XXX,XX +XXX,XX @@ MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat,
      /* This can be MMIO, so setup MMIO bit. */
      section = flatview_do_translate(fv, addr, xlat, plen, NULL,
 -                                    is_write, true, &as);
 +                                    is_write, true, &as, attrs);
      mr = section.mr;
      if (xen_enabled() && memory_access_is_direct(mr, is_write)) {
 --
-.7.4
+.17.1

-[Qemu-devel] [PULL 09/13] target-arm: Simplify insn_crosses_page()
+[Qemu-devel] [PULL 22/25] Make address_space_translate_iommu take a MemTxAttrs argument
-Recent changes have left insn_crosses_page() more complicated
+As part of plumbing MemTxAttrs down to the IOMMU translate method,
-than it needed to be:
+add MemTxAttrs as an argument to address_space_translate_iommu().
  * it's only called from thumb_tr_translate_insn() so we know
    for certain that we're looking at a Thumb insn
  * the caller's check for dc->pc >= dc->next_page_start - 3
    means that dc->pc can't possibly be 4 aligned, so there's
    no need to check that (the check was partly there to ensure
    that we didn't treat an ARM insn as Thumb, I think)
  * we now have thumb_insn_is_16bit() which lets us do a precise
    check of the length of the next insn, rather than opencoding
    an inaccurate check
 Simplify it down to just loading the first half of the insn
 and calling thumb_insn_is_16bit() on it.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 1507556919-24992-8-git-send-email-peter.maydell@linaro.org
+Message-id: 20180521140402.23318-14-peter.maydell@linaro.org
 ---
- target/arm/translate.c | 27 ++++++---------------------
+ exec.c | 8 +++++---
-file changed, 6 insertions(+), 21 deletions(-)
+file changed, 5 insertions(+), 3 deletions(-)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
+diff --git a/exec.c b/exec.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
+--- a/exec.c
-+++ b/target/arm/translate.c
++++ b/exec.c
-@@ -XXX,XX +XXX,XX @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
+@@ -XXX,XX +XXX,XX @@ address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *x
   * @is_write: whether the translation operation is for write
   * @is_mmio: whether this can be MMIO, set true if it can
   * @target_as: the address space targeted by the IOMMU
 + * @attrs: transaction attributes
   *
   * This function is called from RCU critical section.  It is the common
   * part of flatview_do_translate and address_space_translate_cached.
@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection address_space_translate_iommu(IOMMUMemoryRegion *iomm
                                                           hwaddr *page_mask_out,
                                                           bool is_write,
                                                           bool is_mmio,
 -                                                         AddressSpace **target_as)
 +                                                         AddressSpace **target_as,
 +                                                         MemTxAttrs attrs)
  {
-     /* Return true if the insn at dc->pc might cross a page boundary.
+     MemoryRegionSection *section;
-      * (False positives are OK, false negatives are not.)
+     hwaddr page_mask = (hwaddr)-1;
-+     * We know this is a Thumb insn, and our caller ensures we are
+@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,
-+     * only called if dc->pc is less than 4 bytes from the page
+         return address_space_translate_iommu(iommu_mr, xlat,
-+     * boundary, so we cross the page if the first 16 bits indicate
+                                              plen_out, page_mask_out,
-+     * that this is a 32 bit insn.
+                                              is_write, is_mmio,
-      */
+-                                             target_as);
--    uint16_t insn;
++                                             target_as, attrs);
-+    uint16_t insn = arm_lduw_code(env, s->pc, s->sctlr_b);
+     }
+     if (page_mask_out) {
--    if ((s->pc & 3) == 0) {
+         /* Not behind an IOMMU, use default page size. */
--        /* At a 4-aligned address we can't be crossing a page */
+@@ -XXX,XX +XXX,XX @@ static inline MemoryRegion *address_space_translate_cached(
--        return false;
--    }
+     section = address_space_translate_iommu(iommu_mr, xlat, plen,
--
+                                             NULL, is_write, true,
--    /* This must be a Thumb insn */
+-                                            &target_as);
--    insn = arm_lduw_code(env, s->pc, s->sctlr_b);
++                                            &target_as, attrs);
--
+     return section.mr;
 -    if ((insn >> 11) >= 0x1d) {
 -        /* Top five bits 0b11101 / 0b11110 / 0b11111 : this is the
 -         * First half of a 32-bit Thumb insn. Thumb-1 cores might
 -         * end up actually treating this as two 16-bit insns (see the
 -         * code at the start of disas_thumb2_insn()) but we don't bother
 -         * to check for that as it is unlikely, and false positives here
 -         * are harmless.
 -         */
 -        return true;
 -    }
 -    /* Definitely a 16-bit insn, can't be crossing a page. */
 -    return false;
 +    return !thumb_insn_is_16bit(s, insn);
  }
- static int arm_tr_init_disas_context(DisasContextBase *dcbase,
 --
-.7.4
+.17.1

-[Qemu-devel] [PULL 03/13] target/arm: Add M profile secure MMU index values to get_a32_user_mem_index()
+[Qemu-devel] [PULL 23/25] vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY
-Add the M profile secure MMU index values to the switch in
+Provide a VMSTATE_BOOL_SUB_ARRAY to go with VMSTATE_UINT8_SUB_ARRAY
-get_a32_user_mem_index() so that LDRT/STRT work correctly
+and friends.
 rather than asserting at translate time.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Message-id: 1507556919-24992-2-git-send-email-peter.maydell@linaro.org
+Message-id: 20180521140402.23318-23-peter.maydell@linaro.org
 ---
- target/arm/translate.c | 4 ++++
+ include/migration/vmstate.h | 3 +++
-file changed, 4 insertions(+)
+file changed, 3 insertions(+)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
+diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
+--- a/include/migration/vmstate.h
-+++ b/target/arm/translate.c
++++ b/include/migration/vmstate.h
-@@ -XXX,XX +XXX,XX @@ static inline int get_a32_user_mem_index(DisasContext *s)
+@@ -XXX,XX +XXX,XX @@ extern const VMStateInfo vmstate_info_qtailq;
-     case ARMMMUIdx_MPriv:
+ #define VMSTATE_BOOL_ARRAY(_f, _s, _n)                               \
-     case ARMMMUIdx_MNegPri:
+     VMSTATE_BOOL_ARRAY_V(_f, _s, _n, 0)
-         return arm_to_core_mmu_idx(ARMMMUIdx_MUser);
-+    case ARMMMUIdx_MSUser:
++#define VMSTATE_BOOL_SUB_ARRAY(_f, _s, _start, _num)                \
-+    case ARMMMUIdx_MSPriv:
++    VMSTATE_SUB_ARRAY(_f, _s, _start, _num, 0, vmstate_info_bool, bool)
-+    case ARMMMUIdx_MSNegPri:
++
-+        return arm_to_core_mmu_idx(ARMMMUIdx_MSUser);
+ #define VMSTATE_UINT16_ARRAY_V(_f, _s, _n, _v)                         \
-     case ARMMMUIdx_S2NS:
+     VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_uint16, uint16_t)
-     default:
          g_assert_not_reached();
 --
-.7.4
+.17.1

-[Qemu-devel] [PULL 01/13] watchdog/aspeed: fix variable type to store reload value
+[Qemu-devel] [PULL 24/25] ARM: ACPI: Fix use-after-free due to memory realloc
-From: Cédric Le Goater <clg@kaod.org>
+From: Shannon Zhao <zhaoshenglong@huawei.com>
-Initially from Anton D. Kachalov" <mouse@yandex-team.ru> but the SoB was
+acpi_data_push uses g_array_set_size to resize the memory size. If there
-missing.
+is no enough contiguous memory, the address will be changed. So previous
 pointer could not be used any more. It must update the pointer and use
 the new one.
-Signed-off-by: Cédric Le Goater <clg@kaod.org>
+Also, previous codes wrongly use le32 conversion of iort->node_offset
-Acked-by: Andrew Jeffery <andrew@aj.id.au>
+for subsequent computations that will result incorrect value if host is
-Message-id: 20170920064915.30027-1-clg@kaod.org
+not litlle endian. So use the non-converted one instead.
-[clg: change commit log and subject
-      replace UL suffix by ULL ]
+Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
-Signed-off-by: Cédric Le Goater <clg@kaod.org>
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 1527663951-14552-1-git-send-email-zhaoshenglong@huawei.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/watchdog/wdt_aspeed.c | 4 ++--
+ hw/arm/virt-acpi-build.c | 20 +++++++++++++++-----
-file changed, 2 insertions(+), 2 deletions(-)
+file changed, 15 insertions(+), 5 deletions(-)
-diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c
+diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/watchdog/wdt_aspeed.c
+--- a/hw/arm/virt-acpi-build.c
-+++ b/hw/watchdog/wdt_aspeed.c
++++ b/hw/arm/virt-acpi-build.c
-@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size)
+@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
+     AcpiIortItsGroup *its;
- static void aspeed_wdt_reload(AspeedWDTState *s, bool pclk)
+     AcpiIortTable *iort;
- {
+     AcpiIortSmmu3 *smmu;
--    uint32_t reload;
+-    size_t node_size, iort_length, smmu_offset = 0;
-+    uint64_t reload;
++    size_t node_size, iort_node_offset, iort_length, smmu_offset = 0;
+     AcpiIortRC *rc;
-     if (pclk) {
-         reload = muldiv64(s->regs[WDT_RELOAD_VALUE], NANOSECONDS_PER_SECOND,
+     iort = acpi_data_push(table_data, sizeof(*iort));
-                           s->pclk_freq);
+@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
      iort_length = sizeof(*iort);
      iort->node_count = cpu_to_le32(nb_nodes);
 -    iort->node_offset = cpu_to_le32(sizeof(*iort));
 +    /*
 +     * Use a copy in case table_data->data moves during acpi_data_push
 +     * operations.
 +     */
 +    iort_node_offset = sizeof(*iort);
 +    iort->node_offset = cpu_to_le32(iort_node_offset);
      /* ITS group node */
      node_size =  sizeof(*its) + sizeof(uint32_t);
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
          int irq =  vms->irqmap[VIRT_SMMU];
          /* SMMUv3 node */
 -        smmu_offset = iort->node_offset + node_size;
 +        smmu_offset = iort_node_offset + node_size;
          node_size = sizeof(*smmu) + sizeof(*idmap);
          iort_length += node_size;
          smmu = acpi_data_push(table_data, node_size);
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
          idmap->id_count = cpu_to_le32(0xFFFF);
          idmap->output_base = 0;
          /* output IORT node is the ITS group node (the first node) */
 -        idmap->output_reference = cpu_to_le32(iort->node_offset);
 +        idmap->output_reference = cpu_to_le32(iort_node_offset);
      }
      /* Root Complex Node */
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
          idmap->output_reference = cpu_to_le32(smmu_offset);
      } else {
--        reload = s->regs[WDT_RELOAD_VALUE] * 1000;
+         /* output IORT node is the ITS group node (the first node) */
-+        reload = s->regs[WDT_RELOAD_VALUE] * 1000ULL;
+-        idmap->output_reference = cpu_to_le32(iort->node_offset);
 +        idmap->output_reference = cpu_to_le32(iort_node_offset);
      }
-     if (aspeed_wdt_is_enabled(s)) {
++    /*
 +     * Update the pointer address in case table_data->data moves during above
 +     * acpi_data_push operations.
 +     */
 +    iort = (AcpiIortTable *)(table_data->data + iort_start);
      iort->length = cpu_to_le32(iort_length);
      build_header(linker, table_data, (void *)(table_data->data + iort_start),
 --
-.7.4
+.17.1

-New patch
+[Qemu-devel] [PULL 25/25] KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice
+From: Shannon Zhao <zhaoshenglong@huawei.com>
+kvm_irqchip_create called by kvm_init will call kvm_init_irq_routing to
+initialize global capability variables. If we call kvm_init_irq_routing in
+GIC realize function, previous allocated memory will leak.
+Fix this by deleting the unnecessary call.
+Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
+Message-id: 1527750994-14360-1-git-send-email-zhaoshenglong@huawei.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/intc/arm_gic_kvm.c   | 1 -
+ hw/intc/arm_gicv3_kvm.c | 1 -
+files changed, 2 deletions(-)
+diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/intc/arm_gic_kvm.c
++++ b/hw/intc/arm_gic_kvm.c
+@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
+     if (kvm_has_gsi_routing()) {
+         /* set up irq routing */
+-        kvm_init_irq_routing(kvm_state);
+         for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) {
+             kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
+         }
+diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/intc/arm_gicv3_kvm.c
++++ b/hw/intc/arm_gicv3_kvm.c
+@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
+     if (kvm_has_gsi_routing()) {
+         /* set up irq routing */
+-        kvm_init_irq_routing(kvm_state);
+         for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) {
+             kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
+         }
+--
+.17.1

target-arm queue:
 * mostly my latest v8M stuff, plus a couple of minor patches

The following changes since commit a0b261db8c030813e30a39eae47359ac2a37f7e2:

Merge remote-tracking branch 'remotes/ehabkost/tags/python-next-pull-request' into staging (2017-10-12 10:02:09 +0100)

are available in the git repository at:

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20171012

for you to fetch changes up to cf5f7937b05c84d5565134f058c00cd48304a117:

nvic: Fix miscalculation of offsets into ITNS array (2017-10-12 16:33:16 +0100)

----------------------------------------------------------------
target-arm queue:
 * v8M: SG, BLXNS, secure-return
 * v8M: fixes for coverity issues in previous patches
 * arm: fix armv7m_init() declaration to match definition
 * watchdog/aspeed: fix variable type to store reload value

----------------------------------------------------------------
Cédric Le Goater (1):
      watchdog/aspeed: fix variable type to store reload value

Igor Mammedov (1):
      arm: fix armv7m_init() declaration to match definition

Peter Maydell (11):
      target/arm: Add M profile secure MMU index values to get_a32_user_mem_index()
      target/arm: Implement SG instruction
      target/arm: Implement BLXNS
      target/arm: Implement secure function return
      target-arm: Don't check for "Thumb2 or M profile" for not-Thumb1
      target/arm: Pull Thumb insn word loads up to top level
      target-arm: Simplify insn_crosses_page()
      target/arm: Support some Thumb insns being always unconditional
      target/arm: Implement SG instruction corner cases
      nvic: Add missing 'break'
      nvic: Fix miscalculation of offsets into ITNS array

include/hw/arm/arm.h     |   2 +-
 target/arm/helper.h      |   1 +
 target/arm/internals.h   |   8 ++
 hw/intc/armv7m_nvic.c    |   5 +-
 hw/watchdog/wdt_aspeed.c |   4 +-
 target/arm/helper.c      | 306 ++++++++++++++++++++++++++++++++++++++++++++--
 target/arm/translate.c   | 310 ++++++++++++++++++++++++++++++++---------------
 7 files changed, 521 insertions(+), 115 deletions(-)

From: Cédric Le Goater <clg@kaod.org>

Initially from Anton D. Kachalov" <mouse@yandex-team.ru> but the SoB was
missing.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Message-id: 20170920064915.30027-1-clg@kaod.org
[clg: change commit log and subject
      replace UL suffix by ULL ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/watchdog/wdt_aspeed.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/watchdog/wdt_aspeed.c
+++ b/hw/watchdog/wdt_aspeed.c
@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size)
 
 static void aspeed_wdt_reload(AspeedWDTState *s, bool pclk)
 {
-    uint32_t reload;
+    uint64_t reload;
 
     if (pclk) {
         reload = muldiv64(s->regs[WDT_RELOAD_VALUE], NANOSECONDS_PER_SECOND,
                           s->pclk_freq);
     } else {
-        reload = s->regs[WDT_RELOAD_VALUE] * 1000;
+        reload = s->regs[WDT_RELOAD_VALUE] * 1000ULL;
     }
 
     if (aspeed_wdt_is_enabled(s)) {
-- 
2.7.4

Implement the SG instruction, which we emulate 'by hand' in the
exception handling code path.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1507556919-24992-3-git-send-email-peter.maydell@linaro.org
---
 target/arm/helper.c | 132 ++++++++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 127 insertions(+), 5 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ typedef struct V8M_SAttributes {
     bool irvalid;
 } V8M_SAttributes;
 
+static void v8m_security_lookup(CPUARMState *env, uint32_t address,
+                                MMUAccessType access_type, ARMMMUIdx mmu_idx,
+                                V8M_SAttributes *sattrs);
+
 /* Definitions for the PMCCNTR and PMCR registers */
 #define PMCRD   0x8
 #define PMCRC   0x4
@@ -XXX,XX +XXX,XX @@ static void arm_log_exception(int idx)
     }
 }
 
+static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
+                               uint32_t addr, uint16_t *insn)
+{
+    /* Load a 16-bit portion of a v7M instruction, returning true on success,
+     * or false on failure (in which case we will have pended the appropriate
+     * exception).
+     * We need to do the instruction fetch's MPU and SAU checks
+     * like this because there is no MMU index that would allow
+     * doing the load with a single function call. Instead we must
+     * first check that the security attributes permit the load
+     * and that they don't mismatch on the two halves of the instruction,
+     * and then we do the load as a secure load (ie using the security
+     * attributes of the address, not the CPU, as architecturally required).
+     */
+    CPUState *cs = CPU(cpu);
+    CPUARMState *env = &cpu->env;
+    V8M_SAttributes sattrs = {};
+    MemTxAttrs attrs = {};
+    ARMMMUFaultInfo fi = {};
+    MemTxResult txres;
+    target_ulong page_size;
+    hwaddr physaddr;
+    int prot;
+    uint32_t fsr;
+
+    v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, &sattrs);
+    if (!sattrs.nsc || sattrs.ns) {
+        /* This must be the second half of the insn, and it straddles a
+         * region boundary with the second half not being S&NSC.
+         */
+        env->v7m.sfsr |= R_V7M_SFSR_INVEP_MASK;
+        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false);
+        qemu_log_mask(CPU_LOG_INT,
+                      "...really SecureFault with SFSR.INVEP\n");
+        return false;
+    }
+    if (get_phys_addr(env, addr, MMU_INST_FETCH, mmu_idx,
+                      &physaddr, &attrs, &prot, &page_size, &fsr, &fi)) {
+        /* the MPU lookup failed */
+        env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_IACCVIOL_MASK;
+        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, env->v7m.secure);
+        qemu_log_mask(CPU_LOG_INT, "...really MemManage with CFSR.IACCVIOL\n");
+        return false;
+    }
+    *insn = address_space_lduw_le(arm_addressspace(cs, attrs), physaddr,
+                                 attrs, &txres);
+    if (txres != MEMTX_OK) {
+        env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_IBUSERR_MASK;
+        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false);
+        qemu_log_mask(CPU_LOG_INT, "...really BusFault with CFSR.IBUSERR\n");
+        return false;
+    }
+    return true;
+}
+
+static bool v7m_handle_execute_nsc(ARMCPU *cpu)
+{
+    /* Check whether this attempt to execute code in a Secure & NS-Callable
+     * memory region is for an SG instruction; if so, then emulate the
+     * effect of the SG instruction and return true. Otherwise pend
+     * the correct kind of exception and return false.
+     */
+    CPUARMState *env = &cpu->env;
+    ARMMMUIdx mmu_idx;
+    uint16_t insn;
+
+    /* We should never get here unless get_phys_addr_pmsav8() caused
+     * an exception for NS executing in S&NSC memory.
+     */
+    assert(!env->v7m.secure);
+    assert(arm_feature(env, ARM_FEATURE_M_SECURITY));
+
+    /* We want to do the MPU lookup as secure; work out what mmu_idx that is */
+    mmu_idx = arm_v7m_mmu_idx_for_secstate(env, true);
+
+    if (!v7m_read_half_insn(cpu, mmu_idx, env->regs[15], &insn)) {
+        return false;
+    }
+
+    if (!env->thumb) {
+        goto gen_invep;
+    }
+
+    if (insn != 0xe97f) {
+        /* Not an SG instruction first half (we choose the IMPDEF
+         * early-SG-check option).
+         */
+        goto gen_invep;
+    }
+
+    if (!v7m_read_half_insn(cpu, mmu_idx, env->regs[15] + 2, &insn)) {
+        return false;
+    }
+
+    if (insn != 0xe97f) {
+        /* Not an SG instruction second half (yes, both halves of the SG
+         * insn have the same hex value)
+         */
+        goto gen_invep;
+    }
+
+    /* OK, we have confirmed that we really have an SG instruction.
+     * We know we're NS in S memory so don't need to repeat those checks.
+     */
+    qemu_log_mask(CPU_LOG_INT, "...really an SG instruction at 0x%08" PRIx32
+                  ", executing it\n", env->regs[15]);
+    env->regs[14] &= ~1;
+    switch_v7m_security_state(env, true);
+    xpsr_write(env, 0, XPSR_IT);
+    env->regs[15] += 4;
+    return true;
+
+gen_invep:
+    env->v7m.sfsr |= R_V7M_SFSR_INVEP_MASK;
+    armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false);
+    qemu_log_mask(CPU_LOG_INT,
+                  "...really SecureFault with SFSR.INVEP\n");
+    return false;
+}
+
 void arm_v7m_cpu_do_interrupt(CPUState *cs)
 {
     ARMCPU *cpu = ARM_CPU(cs);
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
              * the SG instruction have the same security attributes.)
              * Everything else must generate an INVEP SecureFault, so we
              * emulate the SG instruction here.
-             * TODO: actually emulate SG.
              */
-            env->v7m.sfsr |= R_V7M_SFSR_INVEP_MASK;
-            armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false);
-            qemu_log_mask(CPU_LOG_INT,
-                          "...really SecureFault with SFSR.INVEP\n");
+            if (v7m_handle_execute_nsc(cpu)) {
+                return;
+            }
             break;
         case M_FAKE_FSR_SFAULT:
             /* Various flavours of SecureFault for attempts to execute or
-- 
2.7.4

Implement the BLXNS instruction, which allows secure code to
call non-secure code.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1507556919-24992-4-git-send-email-peter.maydell@linaro.org
---
 target/arm/helper.h    |  1 +
 target/arm/internals.h |  1 +
 target/arm/helper.c    | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++
 target/arm/translate.c | 17 +++++++++++++--
 4 files changed, 76 insertions(+), 2 deletions(-)

diff --git a/target/arm/helper.h b/target/arm/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(v7m_msr, void, env, i32, i32)
 DEF_HELPER_2(v7m_mrs, i32, env, i32)
 
 DEF_HELPER_2(v7m_bxns, void, env, i32)
+DEF_HELPER_2(v7m_blxns, void, env, i32)
 
 DEF_HELPER_4(access_check_cp_reg, void, env, ptr, i32, i32)
 DEF_HELPER_3(set_cp_reg, void, env, ptr, i32)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ static inline bool excp_is_internal(int excp)
 FIELD(V7M_CONTROL, NPRIV, 0, 1)
 FIELD(V7M_CONTROL, SPSEL, 1, 1)
 FIELD(V7M_CONTROL, FPCA, 2, 1)
+FIELD(V7M_CONTROL, SFPA, 3, 1)
 
 /* Bit definitions for v7M exception return payload */
 FIELD(V7M_EXCRET, ES, 0, 1)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)
     g_assert_not_reached();
 }
 
+void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
+{
+    /* translate.c should never generate calls here in user-only mode */
+    g_assert_not_reached();
+}
+
 void switch_mode(CPUARMState *env, int mode)
 {
     ARMCPU *cpu = arm_env_get_cpu(env);
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)
     env->regs[15] = dest & ~1;
 }
 
+void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
+{
+    /* Handle v7M BLXNS:
+     *  - bit 0 of the destination address is the target security state
+     */
+
+    /* At this point regs[15] is the address just after the BLXNS */
+    uint32_t nextinst = env->regs[15] | 1;
+    uint32_t sp = env->regs[13] - 8;
+    uint32_t saved_psr;
+
+    /* translate.c will have made BLXNS UNDEF unless we're secure */
+    assert(env->v7m.secure);
+
+    if (dest & 1) {
+        /* target is Secure, so this is just a normal BLX,
+         * except that the low bit doesn't indicate Thumb/not.
+         */
+        env->regs[14] = nextinst;
+        env->thumb = 1;
+        env->regs[15] = dest & ~1;
+        return;
+    }
+
+    /* Target is non-secure: first push a stack frame */
+    if (!QEMU_IS_ALIGNED(sp, 8)) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "BLXNS with misaligned SP is UNPREDICTABLE\n");
+    }
+
+    saved_psr = env->v7m.exception;
+    if (env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK) {
+        saved_psr |= XPSR_SFPA;
+    }
+
+    /* Note that these stores can throw exceptions on MPU faults */
+    cpu_stl_data(env, sp, nextinst);
+    cpu_stl_data(env, sp + 4, saved_psr);
+
+    env->regs[13] = sp;
+    env->regs[14] = 0xfeffffff;
+    if (arm_v7m_is_handler_mode(env)) {
+        /* Write a dummy value to IPSR, to avoid leaking the current secure
+         * exception number to non-secure code. This is guaranteed not
+         * to cause write_v7m_exception() to actually change stacks.
+         */
+        write_v7m_exception(env, 1);
+    }
+    switch_v7m_security_state(env, 0);
+    env->thumb = 1;
+    env->regs[15] = dest;
+}
+
 static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode,
                                 bool spsel)
 {
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static inline void gen_bxns(DisasContext *s, int rm)
     s->base.is_jmp = DISAS_EXIT;
 }
 
+static inline void gen_blxns(DisasContext *s, int rm)
+{
+    TCGv_i32 var = load_reg(s, rm);
+
+    /* We don't need to sync condexec state, for the same reason as bxns.
+     * We do however need to set the PC, because the blxns helper reads it.
+     * The blxns helper may throw an exception.
+     */
+    gen_set_pc_im(s, s->pc);
+    gen_helper_v7m_blxns(cpu_env, var);
+    tcg_temp_free_i32(var);
+    s->base.is_jmp = DISAS_EXIT;
+}
+
 /* Variant of store_reg which uses branch&exchange logic when storing
    to r15 in ARM architecture v7 and above. The source must be a temporary
    and will be marked as dead. */
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
                         goto undef;
                     }
                     if (link) {
-                        /* BLXNS: not yet implemented */
-                        goto undef;
+                        gen_blxns(s, rm);
                     } else {
                         gen_bxns(s, rm);
                     }
-- 
2.7.4

Secure function return happens when a non-secure function has been
called using BLXNS and so has a particular magic LR value (either
0xfefffffe or 0xfeffffff). The function return via BX behaves
specially when the new PC value is this magic value, in the same
way that exception returns are handled.

Adjust our BX excret guards so that they recognize the function
return magic number as well, and perform the function-return
unstacking in do_v7m_exception_exit().

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1507556919-24992-5-git-send-email-peter.maydell@linaro.org
---
 target/arm/internals.h |   7 +++
 target/arm/helper.c    | 115 +++++++++++++++++++++++++++++++++++++++++++++----
 target/arm/translate.c |  14 +++++-
 3 files changed, 126 insertions(+), 10 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ FIELD(V7M_EXCRET, DCRS, 5, 1)
 FIELD(V7M_EXCRET, S, 6, 1)
 FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */
 
+/* Minimum value which is a magic number for exception return */
+#define EXC_RETURN_MIN_MAGIC 0xff000000
+/* Minimum number which is a magic number for function or exception return
+ * when using v8M security extension
+ */
+#define FNC_RETURN_MIN_MAGIC 0xfefffffe
+
 /* We use a few fake FSR values for internal purposes in M profile.
  * M profile cores don't have A/R format FSRs, but currently our
  * get_phys_addr() code assumes A/R profile and reports failures via
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)
      *  - if the return value is a magic value, do exception return (like BX)
      *  - otherwise bit 0 of the return value is the target security state
      */
-    if (dest >= 0xff000000) {
+    uint32_t min_magic;
+
+    if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
+        /* Covers FNC_RETURN and EXC_RETURN magic */
+        min_magic = FNC_RETURN_MIN_MAGIC;
+    } else {
+        /* EXC_RETURN magic only */
+        min_magic = EXC_RETURN_MIN_MAGIC;
+    }
+
+    if (dest >= min_magic) {
         /* This is an exception return magic value; put it where
          * do_v7m_exception_exit() expects and raise EXCEPTION_EXIT.
          * Note that if we ever add gen_ss_advance() singlestep support to
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
     bool exc_secure = false;
     bool return_to_secure;
 
-    /* We can only get here from an EXCP_EXCEPTION_EXIT, and
-     * gen_bx_excret() enforces the architectural rule
-     * that jumps to magic addresses don't have magic behaviour unless
-     * we're in Handler mode (compare pseudocode BXWritePC()).
+    /* If we're not in Handler mode then jumps to magic exception-exit
+     * addresses don't have magic behaviour. However for the v8M
+     * security extensions the magic secure-function-return has to
+     * work in thread mode too, so to avoid doing an extra check in
+     * the generated code we allow exception-exit magic to also cause the
+     * internal exception and bring us here in thread mode. Correct code
+     * will never try to do this (the following insn fetch will always
+     * fault) so we the overhead of having taken an unnecessary exception
+     * doesn't matter.
      */
-    assert(arm_v7m_is_handler_mode(env));
+    if (!arm_v7m_is_handler_mode(env)) {
+        return;
+    }
 
     /* In the spec pseudocode ExceptionReturn() is called directly
      * from BXWritePC() and gets the full target PC value including
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
     qemu_log_mask(CPU_LOG_INT, "...successful exception return\n");
 }
 
+static bool do_v7m_function_return(ARMCPU *cpu)
+{
+    /* v8M security extensions magic function return.
+     * We may either:
+     *  (1) throw an exception (longjump)
+     *  (2) return true if we successfully handled the function return
+     *  (3) return false if we failed a consistency check and have
+     *      pended a UsageFault that needs to be taken now
+     *
+     * At this point the magic return value is split between env->regs[15]
+     * and env->thumb. We don't bother to reconstitute it because we don't
+     * need it (all values are handled the same way).
+     */
+    CPUARMState *env = &cpu->env;
+    uint32_t newpc, newpsr, newpsr_exc;
+
+    qemu_log_mask(CPU_LOG_INT, "...really v7M secure function return\n");
+
+    {
+        bool threadmode, spsel;
+        TCGMemOpIdx oi;
+        ARMMMUIdx mmu_idx;
+        uint32_t *frame_sp_p;
+        uint32_t frameptr;
+
+        /* Pull the return address and IPSR from the Secure stack */
+        threadmode = !arm_v7m_is_handler_mode(env);
+        spsel = env->v7m.control[M_REG_S] & R_V7M_CONTROL_SPSEL_MASK;
+
+        frame_sp_p = get_v7m_sp_ptr(env, true, threadmode, spsel);
+        frameptr = *frame_sp_p;
+
+        /* These loads may throw an exception (for MPU faults). We want to
+         * do them as secure, so work out what MMU index that is.
+         */
+        mmu_idx = arm_v7m_mmu_idx_for_secstate(env, true);
+        oi = make_memop_idx(MO_LE, arm_to_core_mmu_idx(mmu_idx));
+        newpc = helper_le_ldul_mmu(env, frameptr, oi, 0);
+        newpsr = helper_le_ldul_mmu(env, frameptr + 4, oi, 0);
+
+        /* Consistency checks on new IPSR */
+        newpsr_exc = newpsr & XPSR_EXCP;
+        if (!((env->v7m.exception == 0 && newpsr_exc == 0) ||
+              (env->v7m.exception == 1 && newpsr_exc != 0))) {
+            /* Pend the fault and tell our caller to take it */
+            env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;
+            armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE,
+                                    env->v7m.secure);
+            qemu_log_mask(CPU_LOG_INT,
+                          "...taking INVPC UsageFault: "
+                          "IPSR consistency check failed\n");
+            return false;
+        }
+
+        *frame_sp_p = frameptr + 8;
+    }
+
+    /* This invalidates frame_sp_p */
+    switch_v7m_security_state(env, true);
+    env->v7m.exception = newpsr_exc;
+    env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK;
+    if (newpsr & XPSR_SFPA) {
+        env->v7m.control[M_REG_S] |= R_V7M_CONTROL_SFPA_MASK;
+    }
+    xpsr_write(env, 0, XPSR_IT);
+    env->thumb = newpc & 1;
+    env->regs[15] = newpc & ~1;
+
+    qemu_log_mask(CPU_LOG_INT, "...function return successful\n");
+    return true;
+}
+
 static void arm_log_exception(int idx)
 {
     if (qemu_loglevel_mask(CPU_LOG_INT)) {
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
     case EXCP_IRQ:
         break;
     case EXCP_EXCEPTION_EXIT:
-        do_v7m_exception_exit(cpu);
-        return;
+        if (env->regs[15] < EXC_RETURN_MIN_MAGIC) {
+            /* Must be v8M security extension function return */
+            assert(env->regs[15] >= FNC_RETURN_MIN_MAGIC);
+            assert(arm_feature(env, ARM_FEATURE_M_SECURITY));
+            if (do_v7m_function_return(cpu)) {
+                return;
+            }
+        } else {
+            do_v7m_exception_exit(cpu);
+            return;
+        }
+        break;
     default:
         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
         return; /* Never happens.  Keep compiler happy.  */
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static inline void gen_bx_excret(DisasContext *s, TCGv_i32 var)
      * s->base.is_jmp that we need to do the rest of the work later.
      */
     gen_bx(s, var);
-    if (s->v7m_handler_mode && arm_dc_feature(s, ARM_FEATURE_M)) {
+    if (arm_dc_feature(s, ARM_FEATURE_M_SECURITY) ||
+        (s->v7m_handler_mode && arm_dc_feature(s, ARM_FEATURE_M))) {
         s->base.is_jmp = DISAS_BX_EXCRET;
     }
 }
@@ -XXX,XX +XXX,XX @@ static inline void gen_bx_excret_final_code(DisasContext *s)
 {
     /* Generate the code to finish possible exception return and end the TB */
     TCGLabel *excret_label = gen_new_label();
+    uint32_t min_magic;
+
+    if (arm_dc_feature(s, ARM_FEATURE_M_SECURITY)) {
+        /* Covers FNC_RETURN and EXC_RETURN magic */
+        min_magic = FNC_RETURN_MIN_MAGIC;
+    } else {
+        /* EXC_RETURN magic only */
+        min_magic = EXC_RETURN_MIN_MAGIC;
+    }
 
     /* Is the new PC value in the magic range indicating exception return? */
-    tcg_gen_brcondi_i32(TCG_COND_GEU, cpu_R[15], 0xff000000, excret_label);
+    tcg_gen_brcondi_i32(TCG_COND_GEU, cpu_R[15], min_magic, excret_label);
     /* No: end the TB as we would for a DISAS_JMP */
     if (is_singlestepping(s)) {
         gen_singlestep_exception(s);
-- 
2.7.4

The code which implements the Thumb1 split BL/BLX instructions
is guarded by a check on "not M or THUMB2". All we really need
to check here is "not THUMB2" (and we assume that elsewhere too,
eg in the ARCH(6T2) test that UNDEFs the Thumb2 insns).

This doesn't change behaviour because all M profile cores
have Thumb2 and so ARM_FEATURE_M implies ARM_FEATURE_THUMB2.
(v6M implements a very restricted subset of Thumb2, but we
can cross that bridge when we get to it with appropriate
feature bits.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1507556919-24992-6-git-send-email-peter.maydell@linaro.org
---
 target/arm/translate.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
     int conds;
     int logic_cc;
 
-    if (!(arm_dc_feature(s, ARM_FEATURE_THUMB2)
-          || arm_dc_feature(s, ARM_FEATURE_M))) {
+    if (!arm_dc_feature(s, ARM_FEATURE_THUMB2)) {
         /* Thumb-1 cores may need to treat bl and blx as a pair of
            16-bit instructions to get correct prefetch abort behavior.  */
         insn = insn_hw1;
-- 
2.7.4

Refactor the Thumb decode to do the loads of the instruction words at
the top level rather than only loading the second half of a 32-bit
Thumb insn in the middle of the decode.

This is simple apart from the awkward case of Thumb1, where the
BL/BLX prefix and suffix instructions live in what in Thumb2 is the
32-bit insn space.  To handle these we decode enough to identify
whether we're looking at a prefix/suffix that we handle as a 16 bit
insn, or a prefix that we're going to merge with the following suffix
to consider as a 32 bit insn.  The translation of the 16 bit cases
then moves from disas_thumb2_insn() to disas_thumb_insn().

The refactoring has the benefit that we don't need to pass the
CPUARMState* down into the decoder code any more, but the major
reason for doing this is that some Thumb instructions must be always
unconditional regardless of the IT state bits, so we need to know the
whole insn before we emit the "skip this insn if the IT bits and cond
state tell us to" code.  (The always unconditional insns are BKPT,
HLT and SG; the last of these is 32 bits.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1507556919-24992-7-git-send-email-peter.maydell@linaro.org
---
 target/arm/translate.c | 178 ++++++++++++++++++++++++++++++-------------------
 1 file changed, 108 insertions(+), 70 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
     }
 }
 
+static bool thumb_insn_is_16bit(DisasContext *s, uint32_t insn)
+{
+    /* Return true if this is a 16 bit instruction. We must be precise
+     * about this (matching the decode).  We assume that s->pc still
+     * points to the first 16 bits of the insn.
+     */
+    if ((insn >> 11) < 0x1d) {
+        /* Definitely a 16-bit instruction */
+        return true;
+    }
+
+    /* Top five bits 0b11101 / 0b11110 / 0b11111 : this is the
+     * first half of a 32-bit Thumb insn. Thumb-1 cores might
+     * end up actually treating this as two 16-bit insns, though,
+     * if it's half of a bl/blx pair that might span a page boundary.
+     */
+    if (arm_dc_feature(s, ARM_FEATURE_THUMB2)) {
+        /* Thumb2 cores (including all M profile ones) always treat
+         * 32-bit insns as 32-bit.
+         */
+        return false;
+    }
+
+    if ((insn >> 11) == 0x1e && (s->pc < s->next_page_start - 3)) {
+        /* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix, and the suffix
+         * is not on the next page; we merge this into a 32-bit
+         * insn.
+         */
+        return false;
+    }
+    /* 0b1110_1xxx_xxxx_xxxx : BLX suffix (or UNDEF);
+     * 0b1111_1xxx_xxxx_xxxx : BL suffix;
+     * 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix on the end of a page
+     *  -- handle as single 16 bit insn
+     */
+    return true;
+}
+
 /* Return true if this is a Thumb-2 logical op.  */
 static int
 thumb2_logic_op(int op)
@@ -XXX,XX +XXX,XX @@ gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out,
 
 /* Translate a 32-bit thumb instruction.  Returns nonzero if the instruction
    is not legal.  */
-static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw1)
+static int disas_thumb2_insn(DisasContext *s, uint32_t insn)
 {
-    uint32_t insn, imm, shift, offset;
+    uint32_t imm, shift, offset;
     uint32_t rd, rn, rm, rs;
     TCGv_i32 tmp;
     TCGv_i32 tmp2;
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
     int conds;
     int logic_cc;
 
-    if (!arm_dc_feature(s, ARM_FEATURE_THUMB2)) {
-        /* Thumb-1 cores may need to treat bl and blx as a pair of
-           16-bit instructions to get correct prefetch abort behavior.  */
-        insn = insn_hw1;
-        if ((insn & (1 << 12)) == 0) {
-            ARCH(5);
-            /* Second half of blx.  */
-            offset = ((insn & 0x7ff) << 1);
-            tmp = load_reg(s, 14);
-            tcg_gen_addi_i32(tmp, tmp, offset);
-            tcg_gen_andi_i32(tmp, tmp, 0xfffffffc);
-
-            tmp2 = tcg_temp_new_i32();
-            tcg_gen_movi_i32(tmp2, s->pc | 1);
-            store_reg(s, 14, tmp2);
-            gen_bx(s, tmp);
-            return 0;
-        }
-        if (insn & (1 << 11)) {
-            /* Second half of bl.  */
-            offset = ((insn & 0x7ff) << 1) | 1;
-            tmp = load_reg(s, 14);
-            tcg_gen_addi_i32(tmp, tmp, offset);
-
-            tmp2 = tcg_temp_new_i32();
-            tcg_gen_movi_i32(tmp2, s->pc | 1);
-            store_reg(s, 14, tmp2);
-            gen_bx(s, tmp);
-            return 0;
-        }
-        if ((s->pc & ~TARGET_PAGE_MASK) == 0) {
-            /* Instruction spans a page boundary.  Implement it as two
-               16-bit instructions in case the second half causes an
-               prefetch abort.  */
-            offset = ((int32_t)insn << 21) >> 9;
-            tcg_gen_movi_i32(cpu_R[14], s->pc + 2 + offset);
-            return 0;
-        }
-        /* Fall through to 32-bit decode.  */
-    }
-
-    insn = arm_lduw_code(env, s->pc, s->sctlr_b);
-    s->pc += 2;
-    insn |= (uint32_t)insn_hw1 << 16;
-
+    /* The only 32 bit insn that's allowed for Thumb1 is the combined
+     * BL/BLX prefix and suffix.
+     */
     if ((insn & 0xf800e800) != 0xf000e800) {
         ARCH(6T2);
     }
@@ -XXX,XX +XXX,XX @@ illegal_op:
     return 1;
 }
 
-static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
+static void disas_thumb_insn(DisasContext *s, uint32_t insn)
 {
-    uint32_t val, insn, op, rm, rn, rd, shift, cond;
+    uint32_t val, op, rm, rn, rd, shift, cond;
     int32_t offset;
     int i;
     TCGv_i32 tmp;
     TCGv_i32 tmp2;
     TCGv_i32 addr;
 
-    if (s->condexec_mask) {
-        cond = s->condexec_cond;
-        if (cond != 0x0e) {     /* Skip conditional when condition is AL. */
-          s->condlabel = gen_new_label();
-          arm_gen_test_cc(cond ^ 1, s->condlabel);
-          s->condjmp = 1;
-        }
-    }
-
-    insn = arm_lduw_code(env, s->pc, s->sctlr_b);
-    s->pc += 2;
-
     switch (insn >> 12) {
     case 0: case 1:
 
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
 
     case 14:
         if (insn & (1 << 11)) {
-            if (disas_thumb2_insn(env, s, insn))
-              goto undef32;
+            /* thumb_insn_is_16bit() ensures we can't get here for
+             * a Thumb2 CPU, so this must be a thumb1 split BL/BLX:
+             * 0b1110_1xxx_xxxx_xxxx : BLX suffix (or UNDEF)
+             */
+            assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2));
+            ARCH(5);
+            offset = ((insn & 0x7ff) << 1);
+            tmp = load_reg(s, 14);
+            tcg_gen_addi_i32(tmp, tmp, offset);
+            tcg_gen_andi_i32(tmp, tmp, 0xfffffffc);
+
+            tmp2 = tcg_temp_new_i32();
+            tcg_gen_movi_i32(tmp2, s->pc | 1);
+            store_reg(s, 14, tmp2);
+            gen_bx(s, tmp);
             break;
         }
         /* unconditional branch */
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
         break;
 
     case 15:
-        if (disas_thumb2_insn(env, s, insn))
-            goto undef32;
+        /* thumb_insn_is_16bit() ensures we can't get here for
+         * a Thumb2 CPU, so this must be a thumb1 split BL/BLX.
+         */
+        assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2));
+
+        if (insn & (1 << 11)) {
+            /* 0b1111_1xxx_xxxx_xxxx : BL suffix */
+            offset = ((insn & 0x7ff) << 1) | 1;
+            tmp = load_reg(s, 14);
+            tcg_gen_addi_i32(tmp, tmp, offset);
+
+            tmp2 = tcg_temp_new_i32();
+            tcg_gen_movi_i32(tmp2, s->pc | 1);
+            store_reg(s, 14, tmp2);
+            gen_bx(s, tmp);
+        } else {
+            /* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix */
+            uint32_t uoffset = ((int32_t)insn << 21) >> 9;
+
+            tcg_gen_movi_i32(cpu_R[14], s->pc + 2 + uoffset);
+        }
         break;
     }
     return;
-undef32:
-    gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
-                       default_exception_el(s));
-    return;
 illegal_op:
 undef:
     gen_exception_insn(s, 2, EXCP_UDEF, syn_uncategorized(),
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
 {
     DisasContext *dc = container_of(dcbase, DisasContext, base);
     CPUARMState *env = cpu->env_ptr;
+    uint32_t insn;
+    bool is_16bit;
 
     if (arm_pre_translate_insn(dc)) {
         return;
     }
 
-    disas_thumb_insn(env, dc);
+    insn = arm_lduw_code(env, dc->pc, dc->sctlr_b);
+    is_16bit = thumb_insn_is_16bit(dc, insn);
+    dc->pc += 2;
+    if (!is_16bit) {
+        uint32_t insn2 = arm_lduw_code(env, dc->pc, dc->sctlr_b);
+
+        insn = insn << 16 | insn2;
+        dc->pc += 2;
+    }
+
+    if (dc->condexec_mask) {
+        uint32_t cond = dc->condexec_cond;
+
+        if (cond != 0x0e) {     /* Skip conditional when condition is AL. */
+            dc->condlabel = gen_new_label();
+            arm_gen_test_cc(cond ^ 1, dc->condlabel);
+            dc->condjmp = 1;
+        }
+    }
+
+    if (is_16bit) {
+        disas_thumb_insn(dc, insn);
+    } else {
+        disas_thumb2_insn(dc, insn);
+    }
 
     /* Advance the Thumb condexec condition.  */
     if (dc->condexec_mask) {
-- 
2.7.4

Recent changes have left insn_crosses_page() more complicated
than it needed to be:
 * it's only called from thumb_tr_translate_insn() so we know
   for certain that we're looking at a Thumb insn
 * the caller's check for dc->pc >= dc->next_page_start - 3
   means that dc->pc can't possibly be 4 aligned, so there's
   no need to check that (the check was partly there to ensure
   that we didn't treat an ARM insn as Thumb, I think)
 * we now have thumb_insn_is_16bit() which lets us do a precise
   check of the length of the next insn, rather than opencoding
   an inaccurate check

Simplify it down to just loading the first half of the insn
and calling thumb_insn_is_16bit() on it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1507556919-24992-8-git-send-email-peter.maydell@linaro.org
---
 target/arm/translate.c | 27 ++++++---------------------
 1 file changed, 6 insertions(+), 21 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
 {
     /* Return true if the insn at dc->pc might cross a page boundary.
      * (False positives are OK, false negatives are not.)
+     * We know this is a Thumb insn, and our caller ensures we are
+     * only called if dc->pc is less than 4 bytes from the page
+     * boundary, so we cross the page if the first 16 bits indicate
+     * that this is a 32 bit insn.
      */
-    uint16_t insn;
+    uint16_t insn = arm_lduw_code(env, s->pc, s->sctlr_b);
 
-    if ((s->pc & 3) == 0) {
-        /* At a 4-aligned address we can't be crossing a page */
-        return false;
-    }
-
-    /* This must be a Thumb insn */
-    insn = arm_lduw_code(env, s->pc, s->sctlr_b);
-
-    if ((insn >> 11) >= 0x1d) {
-        /* Top five bits 0b11101 / 0b11110 / 0b11111 : this is the
-         * First half of a 32-bit Thumb insn. Thumb-1 cores might
-         * end up actually treating this as two 16-bit insns (see the
-         * code at the start of disas_thumb2_insn()) but we don't bother
-         * to check for that as it is unlikely, and false positives here
-         * are harmless.
-         */
-        return true;
-    }
-    /* Definitely a 16-bit insn, can't be crossing a page. */
-    return false;
+    return !thumb_insn_is_16bit(s, insn);
 }
 
 static int arm_tr_init_disas_context(DisasContextBase *dcbase,
-- 
2.7.4

A few Thumb instructions are always unconditional even inside an
IT block (as opposed to being UNPREDICTABLE if used inside an
IT block): BKPT, the v8M SG instruction, and the A profile
HLT (debug halt) instruction.

This means we need to suppress the jump-over-instruction-on-condfail
code generation (though the IT state still advances as usual and
subsequent insns in the IT block may be conditional).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1507556919-24992-9-git-send-email-peter.maydell@linaro.org
---
 target/arm/translate.c | 48 +++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 47 insertions(+), 1 deletion(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
        in init_disas_context by adjusting max_insns.  */
 }
 
+static bool thumb_insn_is_unconditional(DisasContext *s, uint32_t insn)
+{
+    /* Return true if this Thumb insn is always unconditional,
+     * even inside an IT block. This is true of only a very few
+     * instructions: BKPT, HLT, and SG.
+     *
+     * A larger class of instructions are UNPREDICTABLE if used
+     * inside an IT block; we do not need to detect those here, because
+     * what we do by default (perform the cc check and update the IT
+     * bits state machine) is a permitted CONSTRAINED UNPREDICTABLE
+     * choice for those situations.
+     *
+     * insn is either a 16-bit or a 32-bit instruction; the two are
+     * distinguishable because for the 16-bit case the top 16 bits
+     * are zeroes, and that isn't a valid 32-bit encoding.
+     */
+    if ((insn & 0xffffff00) == 0xbe00) {
+        /* BKPT */
+        return true;
+    }
+
+    if ((insn & 0xffffffc0) == 0xba80 && arm_dc_feature(s, ARM_FEATURE_V8) &&
+        !arm_dc_feature(s, ARM_FEATURE_M)) {
+        /* HLT: v8A only. This is unconditional even when it is going to
+         * UNDEF; see the v8A ARM ARM DDI0487B.a H3.3.
+         * For v7 cores this was a plain old undefined encoding and so
+         * honours its cc check. (We might be using the encoding as
+         * a semihosting trap, but we don't change the cc check behaviour
+         * on that account, because a debugger connected to a real v7A
+         * core and emulating semihosting traps by catching the UNDEF
+         * exception would also only see cases where the cc check passed.
+         * No guest code should be trying to do a HLT semihosting trap
+         * in an IT block anyway.
+         */
+        return true;
+    }
+
+    if (insn == 0xe97fe97f && arm_dc_feature(s, ARM_FEATURE_V8) &&
+        arm_dc_feature(s, ARM_FEATURE_M)) {
+        /* SG: v8M only */
+        return true;
+    }
+
+    return false;
+}
+
 static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
 {
     DisasContext *dc = container_of(dcbase, DisasContext, base);
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
         dc->pc += 2;
     }
 
-    if (dc->condexec_mask) {
+    if (dc->condexec_mask && !thumb_insn_is_unconditional(dc, insn)) {
         uint32_t cond = dc->condexec_cond;
 
         if (cond != 0x0e) {     /* Skip conditional when condition is AL. */
-- 
2.7.4

The common situation of the SG instruction is that it is
executed from S&NSC memory by a CPU in NS state. That case
is handled by v7m_handle_execute_nsc(). However the instruction
also has defined behaviour in a couple of other cases:
 * SG instruction in NS memory (behaves as a NOP)
 * SG in S memory but CPU already secure (clears IT bits and
   does nothing else)
 * SG instruction in v8M without Security Extension (NOP)

These can be implemented in translate.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1507556919-24992-10-git-send-email-peter.maydell@linaro.org
---
 target/arm/translate.c | 23 ++++++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(DisasContext *s, uint32_t insn)
              * - load/store doubleword, load/store exclusive, ldacq/strel,
              *   table branch.
              */
-            if (insn & 0x01200000) {
+            if (insn == 0xe97fe97f && arm_dc_feature(s, ARM_FEATURE_M) &&
+                arm_dc_feature(s, ARM_FEATURE_V8)) {
+                /* 0b1110_1001_0111_1111_1110_1001_0111_111
+                 *  - SG (v8M only)
+                 * The bulk of the behaviour for this instruction is implemented
+                 * in v7m_handle_execute_nsc(), which deals with the insn when
+                 * it is executed by a CPU in non-secure state from memory
+                 * which is Secure & NonSecure-Callable.
+                 * Here we only need to handle the remaining cases:
+                 *  * in NS memory (including the "security extension not
+                 *    implemented" case) : NOP
+                 *  * in S memory but CPU already secure (clear IT bits)
+                 * We know that the attribute for the memory this insn is
+                 * in must match the current CPU state, because otherwise
+                 * get_phys_addr_pmsav8 would have generated an exception.
+                 */
+                if (s->v8m_secure) {
+                    /* Like the IT insn, we don't need to generate any code */
+                    s->condexec_cond = 0;
+                    s->condexec_mask = 0;
+                }
+            } else if (insn & 0x01200000) {
                 /* 0b1110_1000_x11x_xxxx_xxxx_xxxx_xxxx_xxxx
                  *  - load/store dual (post-indexed)
                  * 0b1111_1001_x10x_xxxx_xxxx_xxxx_xxxx_xxxx
-- 
2.7.4

This calculation of the first exception vector in
the ITNS<n> register being accessed:
        int startvec = 32 * (offset - 0x380) + NVIC_FIRST_IRQ;

is incorrect, because offset is in bytes, so we only want
to multiply by 8.

Spotted by Coverity (CID 1381484, CID 1381488), though it is
not correct that it actually overflows the buffer, because
we have a 'startvec + i < s->num_irq' guard.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1507650856-11718-1-git-send-email-peter.maydell@linaro.org
---
 hw/intc/armv7m_nvic.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
         return ((s->num_irq - NVIC_FIRST_IRQ) / 32) - 1;
     case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */
     {
-        int startvec = 32 * (offset - 0x380) + NVIC_FIRST_IRQ;
+        int startvec = 8 * (offset - 0x380) + NVIC_FIRST_IRQ;
         int i;
 
         if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
     switch (offset) {
     case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */
     {
-        int startvec = 32 * (offset - 0x380) + NVIC_FIRST_IRQ;
+        int startvec = 8 * (offset - 0x380) + NVIC_FIRST_IRQ;
         int i;
 
         if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
-- 
2.7.4

target-arm queue. This has the "plumb txattrs through various
bits of exec.c" patches, and a collection of bug fixes from
various people.

thanks
-- PMM

The following changes since commit a3ac12fba028df90f7b3dbec924995c126c41022:

Merge remote-tracking branch 'remotes/ehabkost/tags/numa-next-pull-request' into staging (2018-05-31 11:12:36 +0100)

are available in the Git repository at:

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180531

for you to fetch changes up to 49d1dca0520ea71bc21867fab6647f474fcf857b:

KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice (2018-05-31 14:52:53 +0100)

----------------------------------------------------------------
target-arm queue:
 * target/arm: Honour FPCR.FZ in FRECPX
 * MAINTAINERS: Add entries for newer MPS2 boards and devices
 * hw/intc/arm_gicv3: Fix APxR<n> register dispatching
 * arm_gicv3_kvm: fix bug in writing zero bits back to the in-kernel
   GIC state
 * tcg: Fix helper function vs host abi for float16
 * arm: fix qemu crash on startup with -bios option
 * arm: fix malloc type mismatch
 * xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors
 * Correct CPACR reset value for v7 cores
 * memory.h: Improve IOMMU related documentation
 * exec: Plumb transaction attributes through various functions in
   preparation for allowing IOMMUs to see them
 * vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY
 * ARM: ACPI: Fix use-after-free due to memory realloc
 * KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice

----------------------------------------------------------------
Francisco Iglesias (1):
      xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors

Igor Mammedov (1):
      arm: fix qemu crash on startup with -bios option

Jan Kiszka (1):
      hw/intc/arm_gicv3: Fix APxR<n> register dispatching

Paolo Bonzini (1):
      arm: fix malloc type mismatch

Peter Maydell (17):
      target/arm: Honour FPCR.FZ in FRECPX
      MAINTAINERS: Add entries for newer MPS2 boards and devices
      Correct CPACR reset value for v7 cores
      memory.h: Improve IOMMU related documentation
      Make tb_invalidate_phys_addr() take a MemTxAttrs argument
      Make address_space_translate{, _cached}() take a MemTxAttrs argument
      Make address_space_map() take a MemTxAttrs argument
      Make address_space_access_valid() take a MemTxAttrs argument
      Make flatview_extend_translation() take a MemTxAttrs argument
      Make memory_region_access_valid() take a MemTxAttrs argument
      Make MemoryRegion valid.accepts callback take a MemTxAttrs argument
      Make flatview_access_valid() take a MemTxAttrs argument
      Make flatview_translate() take a MemTxAttrs argument
      Make address_space_get_iotlb_entry() take a MemTxAttrs argument
      Make flatview_do_translate() take a MemTxAttrs argument
      Make address_space_translate_iommu take a MemTxAttrs argument
      vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY

Richard Henderson (1):
      tcg: Fix helper function vs host abi for float16

Shannon Zhao (3):
      arm_gicv3_kvm: increase clroffset accordingly
      ARM: ACPI: Fix use-after-free due to memory realloc
      KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice

The FRECPX instructions should (like most other floating point operations)
honour the FPCR.FZ bit which specifies whether input denormals should
be flushed to zero (or FZ16 for the half-precision version).
We forgot to implement this, which doesn't affect the results (since
the calculation doesn't actually care about the mantissa bits) but did
mean we were failing to set the FPSR.IDC bit.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180521172712.19930-1-peter.maydell@linaro.org
---
 target/arm/helper-a64.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -XXX,XX +XXX,XX @@ float16 HELPER(frecpx_f16)(float16 a, void *fpstp)
         return nan;
     }
 
+    a = float16_squash_input_denormal(a, fpst);
+
     val16 = float16_val(a);
     sbit = 0x8000 & val16;
     exp = extract32(val16, 10, 5);
@@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
         return nan;
     }
 
+    a = float32_squash_input_denormal(a, fpst);
+
     val32 = float32_val(a);
     sbit = 0x80000000ULL & val32;
     exp = extract32(val32, 23, 8);
@@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
         return nan;
     }
 
+    a = float64_squash_input_denormal(a, fpst);
+
     val64 = float64_val(a);
     sbit = 0x8000000000000000ULL & val64;
     exp = extract64(float64_val(a), 52, 11);
-- 
2.17.1

Add entries to MAINTAINERS to cover the newer MPS2 boards and
the new devices they use.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20180518153157.14899-1-peter.maydell@linaro.org
---
 MAINTAINERS | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: hw/timer/cmsdk-apb-timer.c
 F: include/hw/timer/cmsdk-apb-timer.h
 F: hw/char/cmsdk-apb-uart.c
 F: include/hw/char/cmsdk-apb-uart.h
+F: hw/misc/tz-ppc.c
+F: include/hw/misc/tz-ppc.h
 
 ARM cores
 M: Peter Maydell <peter.maydell@linaro.org>
@@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
 S: Maintained
 F: hw/arm/mps2.c
-F: hw/misc/mps2-scc.c
-F: include/hw/misc/mps2-scc.h
+F: hw/arm/mps2-tz.c
+F: hw/misc/mps2-*.c
+F: include/hw/misc/mps2-*.h
+F: hw/arm/iotkit.c
+F: include/hw/arm/iotkit.h
 
 Musicpal
 M: Jan Kiszka <jan.kiszka@web.de>
-- 
2.17.1

From: Jan Kiszka <jan.kiszka@siemens.com>

There was a nasty flip in identifying which register group an access is
targeting. The issue caused spuriously raised priorities of the guest
when handing CPUs over in the Jailhouse hypervisor.

Cc: qemu-stable@nongnu.org
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Message-id: 28b927d3-da58-bce4-cc13-bfec7f9b1cb9@siemens.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/arm_gicv3_cpuif.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -XXX,XX +XXX,XX @@ static uint64_t icv_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
 {
     GICv3CPUState *cs = icc_cs_from_env(env);
     int regno = ri->opc2 & 3;
-    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
+    int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
     uint64_t value = cs->ich_apr[grp][regno];
 
     trace_gicv3_icv_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
@@ -XXX,XX +XXX,XX @@ static void icv_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
 {
     GICv3CPUState *cs = icc_cs_from_env(env);
     int regno = ri->opc2 & 3;
-    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
+    int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
 
     trace_gicv3_icv_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
 
@@ -XXX,XX +XXX,XX @@ static uint64_t icc_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
     uint64_t value;
 
     int regno = ri->opc2 & 3;
-    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;
+    int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0;
 
     if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
         return icv_ap_read(env, ri);
@@ -XXX,XX +XXX,XX @@ static void icc_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
     GICv3CPUState *cs = icc_cs_from_env(env);
 
     int regno = ri->opc2 & 3;
-    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;
+    int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0;
 
     if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
         icv_ap_write(env, ri, value);
@@ -XXX,XX +XXX,XX @@ static uint64_t ich_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
 {
     GICv3CPUState *cs = icc_cs_from_env(env);
     int regno = ri->opc2 & 3;
-    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
+    int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
     uint64_t value;
 
     value = cs->ich_apr[grp][regno];
@@ -XXX,XX +XXX,XX @@ static void ich_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
 {
     GICv3CPUState *cs = icc_cs_from_env(env);
     int regno = ri->opc2 & 3;
-    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
+    int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
 
     trace_gicv3_ich_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
 
-- 
2.17.1

From: Shannon Zhao <zhaoshenglong@huawei.com>

It forgot to increase clroffset during the loop. So it only clear the
first 4 bytes.

Fixes: 367b9f527becdd20ddf116e17a3c0c2bbc486920
Cc: qemu-stable@nongnu.org
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1527047633-12368-1-git-send-email-zhaoshenglong@huawei.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/arm_gicv3_kvm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_kvm.c
+++ b/hw/intc/arm_gicv3_kvm.c
@@ -XXX,XX +XXX,XX @@ static void kvm_dist_putbmp(GICv3State *s, uint32_t offset,
         if (clroffset != 0) {
             reg = 0;
             kvm_gicd_access(s, clroffset, &reg, true);
+            clroffset += 4;
         }
         reg = *gic_bmp_ptr32(bmp, irq);
         kvm_gicd_access(s, offset, &reg, true);
-- 
2.17.1

From: Richard Henderson <richard.henderson@linaro.org>

Depending on the host abi, float16, aka uint16_t, values are
passed and returned either zero-extended in the host register
or with garbage at the top of the host register.

The tcg code generator has so far been assuming garbage, as that
matches the x86 abi, but this is incorrect for other host abis.
Further, target/arm has so far been assuming zero-extended results,
so that it may store the 16-bit value into a 32-bit slot with the
high 16-bits already clear.

Rectify both problems by mapping "f16" in the helper definition
to uint32_t instead of (a typedef for) uint16_t.  This forces
the host compiler to assume garbage in the upper 16 bits on input
and to zero-extend the result on output.

Cc: qemu-stable@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20180522175629.24932-1-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/exec/helper-head.h |  2 +-
 target/arm/helper-a64.c    | 35 +++++++++--------
 target/arm/helper.c        | 80 +++++++++++++++++++-------------------
 3 files changed, 59 insertions(+), 58 deletions(-)

diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/helper-head.h
+++ b/include/exec/helper-head.h
@@ -XXX,XX +XXX,XX @@
 #define dh_ctype_int int
 #define dh_ctype_i64 uint64_t
 #define dh_ctype_s64 int64_t
-#define dh_ctype_f16 float16
+#define dh_ctype_f16 uint32_t
 #define dh_ctype_f32 float32
 #define dh_ctype_f64 float64
 #define dh_ctype_ptr void *
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -XXX,XX +XXX,XX @@ static inline uint32_t float_rel_to_flags(int res)
     return flags;
 }
 
-uint64_t HELPER(vfp_cmph_a64)(float16 x, float16 y, void *fp_status)
+uint64_t HELPER(vfp_cmph_a64)(uint32_t x, uint32_t y, void *fp_status)
 {
     return float_rel_to_flags(float16_compare_quiet(x, y, fp_status));
 }
 
-uint64_t HELPER(vfp_cmpeh_a64)(float16 x, float16 y, void *fp_status)
+uint64_t HELPER(vfp_cmpeh_a64)(uint32_t x, uint32_t y, void *fp_status)
 {
     return float_rel_to_flags(float16_compare(x, y, fp_status));
 }
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
 #define float64_three make_float64(0x4008000000000000ULL)
 #define float64_one_point_five make_float64(0x3FF8000000000000ULL)
 
-float16 HELPER(recpsf_f16)(float16 a, float16 b, void *fpstp)
+uint32_t HELPER(recpsf_f16)(uint32_t a, uint32_t b, void *fpstp)
 {
     float_status *fpst = fpstp;
 
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp)
     return float64_muladd(a, b, float64_two, 0, fpst);
 }
 
-float16 HELPER(rsqrtsf_f16)(float16 a, float16 b, void *fpstp)
+uint32_t HELPER(rsqrtsf_f16)(uint32_t a, uint32_t b, void *fpstp)
 {
     float_status *fpst = fpstp;
 
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_addlp_u16)(uint64_t a)
 }
 
 /* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */
-float16 HELPER(frecpx_f16)(float16 a, void *fpstp)
+uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
 {
     float_status *fpst = fpstp;
     uint16_t val16, sbit;
@@ -XXX,XX +XXX,XX @@ void HELPER(casp_be_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr,
 #define ADVSIMD_HELPER(name, suffix) HELPER(glue(glue(advsimd_, name), suffix))
 
 #define ADVSIMD_HALFOP(name) \
-float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \
+uint32_t ADVSIMD_HELPER(name, h)(uint32_t a, uint32_t b, void *fpstp) \
 { \
     float_status *fpst = fpstp; \
     return float16_ ## name(a, b, fpst);    \
@@ -XXX,XX +XXX,XX @@ ADVSIMD_HALFOP(mulx)
 ADVSIMD_TWOHALFOP(mulx)
 
 /* fused multiply-accumulate */
-float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp)
+uint32_t HELPER(advsimd_muladdh)(uint32_t a, uint32_t b, uint32_t c,
+                                 void *fpstp)
 {
     float_status *fpst = fpstp;
     return float16_muladd(a, b, c, 0, fpst);
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_muladd2h)(uint32_t two_a, uint32_t two_b,
 
 #define ADVSIMD_CMPRES(test) (test) ? 0xffff : 0
 
-uint32_t HELPER(advsimd_ceq_f16)(float16 a, float16 b, void *fpstp)
+uint32_t HELPER(advsimd_ceq_f16)(uint32_t a, uint32_t b, void *fpstp)
 {
     float_status *fpst = fpstp;
     int compare = float16_compare_quiet(a, b, fpst);
     return ADVSIMD_CMPRES(compare == float_relation_equal);
 }
 
-uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp)
+uint32_t HELPER(advsimd_cge_f16)(uint32_t a, uint32_t b, void *fpstp)
 {
     float_status *fpst = fpstp;
     int compare = float16_compare(a, b, fpst);
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp)
                           compare == float_relation_equal);
 }
 
-uint32_t HELPER(advsimd_cgt_f16)(float16 a, float16 b, void *fpstp)
+uint32_t HELPER(advsimd_cgt_f16)(uint32_t a, uint32_t b, void *fpstp)
 {
     float_status *fpst = fpstp;
     int compare = float16_compare(a, b, fpst);
     return ADVSIMD_CMPRES(compare == float_relation_greater);
 }
 
-uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp)
+uint32_t HELPER(advsimd_acge_f16)(uint32_t a, uint32_t b, void *fpstp)
 {
     float_status *fpst = fpstp;
     float16 f0 = float16_abs(a);
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp)
                           compare == float_relation_equal);
 }
 
-uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
+uint32_t HELPER(advsimd_acgt_f16)(uint32_t a, uint32_t b, void *fpstp)
 {
     float_status *fpst = fpstp;
     float16 f0 = float16_abs(a);
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
 }
 
 /* round to integral */
-float16 HELPER(advsimd_rinth_exact)(float16 x, void *fp_status)
+uint32_t HELPER(advsimd_rinth_exact)(uint32_t x, void *fp_status)
 {
     return float16_round_to_int(x, fp_status);
 }
 
-float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)
+uint32_t HELPER(advsimd_rinth)(uint32_t x, void *fp_status)
 {
     int old_flags = get_float_exception_flags(fp_status), new_flags;
     float16 ret;
@@ -XXX,XX +XXX,XX @@ float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)
  * setting the mode appropriately before calling the helper.
  */
 
-uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp)
+uint32_t HELPER(advsimd_f16tosinth)(uint32_t a, void *fpstp)
 {
     float_status *fpst = fpstp;
 
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp)
     return float16_to_int16(a, fpst);
 }
 
-uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
+uint32_t HELPER(advsimd_f16touinth)(uint32_t a, void *fpstp)
 {
     float_status *fpst = fpstp;
 
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
  * Square Root and Reciprocal square root
  */
 
-float16 HELPER(sqrt_f16)(float16 a, void *fpstp)
+uint32_t HELPER(sqrt_f16)(uint32_t a, void *fpstp)
 {
     float_status *s = fpstp;
 
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ DO_VFP_cmp(d, float64)
 
 /* Integer to float and float to integer conversions */
 
-#define CONV_ITOF(name, fsz, sign) \
-    float##fsz HELPER(name)(uint32_t x, void *fpstp) \
-{ \
-    float_status *fpst = fpstp; \
-    return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
+#define CONV_ITOF(name, ftype, fsz, sign)                           \
+ftype HELPER(name)(uint32_t x, void *fpstp)                         \
+{                                                                   \
+    float_status *fpst = fpstp;                                     \
+    return sign##int32_to_##float##fsz((sign##int32_t)x, fpst);     \
 }
 
-#define CONV_FTOI(name, fsz, sign, round) \
-uint32_t HELPER(name)(float##fsz x, void *fpstp) \
-{ \
-    float_status *fpst = fpstp; \
-    if (float##fsz##_is_any_nan(x)) { \
-        float_raise(float_flag_invalid, fpst); \
-        return 0; \
-    } \
-    return float##fsz##_to_##sign##int32##round(x, fpst); \
+#define CONV_FTOI(name, ftype, fsz, sign, round)                \
+uint32_t HELPER(name)(ftype x, void *fpstp)                     \
+{                                                               \
+    float_status *fpst = fpstp;                                 \
+    if (float##fsz##_is_any_nan(x)) {                           \
+        float_raise(float_flag_invalid, fpst);                  \
+        return 0;                                               \
+    }                                                           \
+    return float##fsz##_to_##sign##int32##round(x, fpst);       \
 }
 
-#define FLOAT_CONVS(name, p, fsz, sign) \
-CONV_ITOF(vfp_##name##to##p, fsz, sign) \
-CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
-CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
+#define FLOAT_CONVS(name, p, ftype, fsz, sign)            \
+    CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign)        \
+    CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, )        \
+    CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero)
 
-FLOAT_CONVS(si, h, 16, )
-FLOAT_CONVS(si, s, 32, )
-FLOAT_CONVS(si, d, 64, )
-FLOAT_CONVS(ui, h, 16, u)
-FLOAT_CONVS(ui, s, 32, u)
-FLOAT_CONVS(ui, d, 64, u)
+FLOAT_CONVS(si, h, uint32_t, 16, )
+FLOAT_CONVS(si, s, float32, 32, )
+FLOAT_CONVS(si, d, float64, 64, )
+FLOAT_CONVS(ui, h, uint32_t, 16, u)
+FLOAT_CONVS(ui, s, float32, 32, u)
+FLOAT_CONVS(ui, d, float64, 64, u)
 
 #undef CONV_ITOF
 #undef CONV_FTOI
@@ -XXX,XX +XXX,XX @@ static float16 do_postscale_fp16(float64 f, int shift, float_status *fpst)
     return float64_to_float16(float64_scalbn(f, -shift, fpst), true, fpst);
 }
 
-float16 HELPER(vfp_sltoh)(uint32_t x, uint32_t shift, void *fpst)
+uint32_t HELPER(vfp_sltoh)(uint32_t x, uint32_t shift, void *fpst)
 {
     return do_postscale_fp16(int32_to_float64(x, fpst), shift, fpst);
 }
 
-float16 HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
+uint32_t HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
 {
     return do_postscale_fp16(uint32_to_float64(x, fpst), shift, fpst);
 }
 
-float16 HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
+uint32_t HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
 {
     return do_postscale_fp16(int64_to_float64(x, fpst), shift, fpst);
 }
 
-float16 HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
+uint32_t HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
 {
     return do_postscale_fp16(uint64_to_float64(x, fpst), shift, fpst);
 }
@@ -XXX,XX +XXX,XX @@ static float64 do_prescale_fp16(float16 f, int shift, float_status *fpst)
     }
 }
 
-uint32_t HELPER(vfp_toshh)(float16 x, uint32_t shift, void *fpst)
+uint32_t HELPER(vfp_toshh)(uint32_t x, uint32_t shift, void *fpst)
 {
     return float64_to_int16(do_prescale_fp16(x, shift, fpst), fpst);
 }
 
-uint32_t HELPER(vfp_touhh)(float16 x, uint32_t shift, void *fpst)
+uint32_t HELPER(vfp_touhh)(uint32_t x, uint32_t shift, void *fpst)
 {
     return float64_to_uint16(do_prescale_fp16(x, shift, fpst), fpst);
 }
 
-uint32_t HELPER(vfp_toslh)(float16 x, uint32_t shift, void *fpst)
+uint32_t HELPER(vfp_toslh)(uint32_t x, uint32_t shift, void *fpst)
 {
     return float64_to_int32(do_prescale_fp16(x, shift, fpst), fpst);
 }
 
-uint32_t HELPER(vfp_toulh)(float16 x, uint32_t shift, void *fpst)
+uint32_t HELPER(vfp_toulh)(uint32_t x, uint32_t shift, void *fpst)
 {
     return float64_to_uint32(do_prescale_fp16(x, shift, fpst), fpst);
 }
 
-uint64_t HELPER(vfp_tosqh)(float16 x, uint32_t shift, void *fpst)
+uint64_t HELPER(vfp_tosqh)(uint32_t x, uint32_t shift, void *fpst)
 {
     return float64_to_int64(do_prescale_fp16(x, shift, fpst), fpst);
 }
 
-uint64_t HELPER(vfp_touqh)(float16 x, uint32_t shift, void *fpst)
+uint64_t HELPER(vfp_touqh)(uint32_t x, uint32_t shift, void *fpst)
 {
     return float64_to_uint64(do_prescale_fp16(x, shift, fpst), fpst);
 }
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
 }
 
 /* Half precision conversions.  */
-float32 HELPER(vfp_fcvt_f16_to_f32)(float16 a, void *fpstp, uint32_t ahp_mode)
+float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode)
 {
     /* Squash FZ16 to 0 for the duration of conversion.  In this case,
      * it would affect flushing input denormals.
@@ -XXX,XX +XXX,XX @@ float32 HELPER(vfp_fcvt_f16_to_f32)(float16 a, void *fpstp, uint32_t ahp_mode)
     return r;
 }
 
-float16 HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
+uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
 {
     /* Squash FZ16 to 0 for the duration of conversion.  In this case,
      * it would affect flushing output denormals.
@@ -XXX,XX +XXX,XX @@ float16 HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
     return r;
 }
 
-float64 HELPER(vfp_fcvt_f16_to_f64)(float16 a, void *fpstp, uint32_t ahp_mode)
+float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode)
 {
     /* Squash FZ16 to 0 for the duration of conversion.  In this case,
      * it would affect flushing input denormals.
@@ -XXX,XX +XXX,XX @@ float64 HELPER(vfp_fcvt_f16_to_f64)(float16 a, void *fpstp, uint32_t ahp_mode)
     return r;
 }
 
-float16 HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)
+uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)
 {
     /* Squash FZ16 to 0 for the duration of conversion.  In this case,
      * it would affect flushing output denormals.
@@ -XXX,XX +XXX,XX @@ static bool round_to_inf(float_status *fpst, bool sign_bit)
     g_assert_not_reached();
 }
 
-float16 HELPER(recpe_f16)(float16 input, void *fpstp)
+uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
 {
     float_status *fpst = fpstp;
     float16 f16 = float16_squash_input_denormal(input, fpst);
@@ -XXX,XX +XXX,XX @@ static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac)
     return extract64(estimate, 0, 8) << 44;
 }
 
-float16 HELPER(rsqrte_f16)(float16 input, void *fpstp)
+uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
 {
     float_status *s = fpstp;
     float16 f16 = float16_squash_input_denormal(input, s);
-- 
2.17.1

From: Igor Mammedov <imammedo@redhat.com>

When QEMU is started with following CLI
 -machine virt,gic-version=3,accel=kvm -cpu host -bios AAVMF_CODE.fd
it crashes with abort at
 accel/kvm/kvm-all.c:2164:
 KVM_SET_DEVICE_ATTR failed: Group 6 attr 0x000000000000c665: Invalid argument

Which is caused by implicit dependency of kvm_arm_gicv3_reset() on
arm_gicv3_icc_reset() where the later is called by CPU reset
reset callback.

However commit:
 3b77f6c arm/boot: split load_dtb() from arm_load_kernel()
broke CPU reset callback registration in case

arm_load_kernel()
      ...
      if (!info->kernel_filename || info->firmware_loaded)

branch is taken, i.e. it's sufficient to provide a firmware
or do not provide kernel on CLI to skip cpu reset callback
registration, where before offending commit the callback
has been registered unconditionally.

Fix it by registering the callback right at the beginning of
arm_load_kernel() unconditionally instead of doing it at the end.

NOTE:
 we probably should eliminate that dependency anyways as well as
 separate arch CPU reset parts from arm_load_kernel() into CPU
 itself, but that refactoring that I probably would have to do
 anyways later for CPU hotplug to work.

Reported-by: Auger Eric <eric.auger@redhat.com>
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1527070950-208350-1-git-send-email-imammedo@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/boot.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
     static const ARMInsnFixup *primary_loader;
     AddressSpace *as = arm_boot_address_space(cpu, info);
 
+    /* CPU objects (unlike devices) are not automatically reset on system
+     * reset, so we must always register a handler to do so. If we're
+     * actually loading a kernel, the handler is also responsible for
+     * arranging that we start it correctly.
+     */
+    for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
+        qemu_register_reset(do_cpu_reset, ARM_CPU(cs));
+    }
+
     /* The board code is not supposed to set secure_board_setup unless
      * running its code in secure mode is actually possible, and KVM
      * doesn't support secure.
@@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
         ARM_CPU(cs)->env.boot_info = info;
     }
 
-    /* CPU objects (unlike devices) are not automatically reset on system
-     * reset, so we must always register a handler to do so. If we're
-     * actually loading a kernel, the handler is also responsible for
-     * arranging that we start it correctly.
-     */
-    for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
-        qemu_register_reset(do_cpu_reset, ARM_CPU(cs));
-    }
-
     if (!info->skip_dtb_autoload && have_dtb(info)) {
         if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as) < 0) {
             exit(1);
-- 
2.17.1

From: Paolo Bonzini <pbonzini@redhat.com>

cpregs_keys is an uint32_t* so the allocation should use uint32_t.
g_new is even better because it is type-safe.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/gdbstub.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_xml(CPUState *cs)
     RegisterSysregXmlParam param = {cs, s};
 
     cpu->dyn_xml.num_cpregs = 0;
-    cpu->dyn_xml.cpregs_keys = g_malloc(sizeof(uint32_t *) *
-                                        g_hash_table_size(cpu->cp_regs));
+    cpu->dyn_xml.cpregs_keys = g_new(uint32_t, g_hash_table_size(cpu->cp_regs));
     g_string_printf(s, "<?xml version=\"1.0\"?>");
     g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
     g_string_append_printf(s, "<feature name=\"org.qemu.gdb.arm.sys.regs\">");
-- 
2.17.1

From: Francisco Iglesias <frasse.iglesias@gmail.com>

Coverity found that the string return by 'object_get_canonical_path' was not
being freed at two locations in the model (CID 1391294 and CID 1391293) and
also that a memset was being called with a value greater than the max of a byte
on the second argument (CID 1391286). This patch corrects this by adding the
freeing of the strings and also changing to memset to zero instead on
descriptor unaligned errors.

Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180528184859.3530-1-frasse.iglesias@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/dma/xlnx-zdma.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/hw/dma/xlnx-zdma.c b/hw/dma/xlnx-zdma.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/dma/xlnx-zdma.c
+++ b/hw/dma/xlnx-zdma.c
@@ -XXX,XX +XXX,XX @@ static bool zdma_load_descriptor(XlnxZDMA *s, uint64_t addr, void *buf)
         qemu_log_mask(LOG_GUEST_ERROR,
                       "zdma: unaligned descriptor at %" PRIx64,
                       addr);
-        memset(buf, 0xdeadbeef, sizeof(XlnxZDMADescr));
+        memset(buf, 0x0, sizeof(XlnxZDMADescr));
         s->error = true;
         return false;
     }
@@ -XXX,XX +XXX,XX @@ static uint64_t zdma_read(void *opaque, hwaddr addr, unsigned size)
     RegisterInfo *r = &s->regs_info[addr / 4];
 
     if (!r->data) {
+        gchar *path = object_get_canonical_path(OBJECT(s));
         qemu_log("%s: Decode error: read from %" HWADDR_PRIx "\n",
-                 object_get_canonical_path(OBJECT(s)),
+                 path,
                  addr);
+        g_free(path);
         ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true);
         zdma_ch_imr_update_irq(s);
         return 0;
@@ -XXX,XX +XXX,XX @@ static void zdma_write(void *opaque, hwaddr addr, uint64_t value,
     RegisterInfo *r = &s->regs_info[addr / 4];
 
     if (!r->data) {
+        gchar *path = object_get_canonical_path(OBJECT(s));
         qemu_log("%s: Decode error: write to %" HWADDR_PRIx "=%" PRIx64 "\n",
-                 object_get_canonical_path(OBJECT(s)),
+                 path,
                  addr, value);
+        g_free(path);
         ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true);
         zdma_ch_imr_update_irq(s);
         return;
-- 
2.17.1

In commit f0aff255700 we made cpacr_write() enforce that some CPACR
bits are RAZ/WI and some are RAO/WI for ARMv7 cores. Unfortunately
we forgot to also update the register's reset value. The effect
was that (a) a guest that read CPACR on reset would not see ones in
the RAO bits, and (b) if you did a migration before the guest did
a write to the CPACR then the migration would fail because the
destination would enforce the RAO bits and then complain that they
didn't match the zero value from the source.

Implement reset for the CPACR using a custom reset function
that just calls cpacr_write(), to avoid having to duplicate
the logic for which bits are RAO.

This bug would affect migration for TCG CPUs which are ARMv7
with VFP but without one of Neon or VFPv3.

Reported-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20180522173713.26282-1-peter.maydell@linaro.org
---
 target/arm/helper.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
     env->cp15.cpacr_el1 = value;
 }
 
+static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+    /* Call cpacr_write() so that we reset with the correct RAO bits set
+     * for our CPU features.
+     */
+    cpacr_write(env, ri, 0);
+}
+
 static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
                                    bool isread)
 {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
     { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
       .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
-      .resetvalue = 0, .writefn = cpacr_write },
+      .resetfn = cpacr_reset, .writefn = cpacr_write },
     REGINFO_SENTINEL
 };
 
-- 
2.17.1

Add more detail to the documentation for memory_region_init_iommu()
and other IOMMU-related functions and data structures.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20180521140402.23318-2-peter.maydell@linaro.org
---
 include/exec/memory.h | 105 ++++++++++++++++++++++++++++++++++++++----
 1 file changed, 95 insertions(+), 10 deletions(-)

diff --git a/include/exec/memory.h b/include/exec/memory.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -XXX,XX +XXX,XX @@ enum IOMMUMemoryRegionAttr {
     IOMMU_ATTR_SPAPR_TCE_FD
 };
 
+/**
+ * IOMMUMemoryRegionClass:
+ *
+ * All IOMMU implementations need to subclass TYPE_IOMMU_MEMORY_REGION
+ * and provide an implementation of at least the @translate method here
+ * to handle requests to the memory region. Other methods are optional.
+ *
+ * The IOMMU implementation must use the IOMMU notifier infrastructure
+ * to report whenever mappings are changed, by calling
+ * memory_region_notify_iommu() (or, if necessary, by calling
+ * memory_region_notify_one() for each registered notifier).
+ */
 typedef struct IOMMUMemoryRegionClass {
     /* private */
     struct DeviceClass parent_class;
 
     /*
-     * Return a TLB entry that contains a given address. Flag should
-     * be the access permission of this translation operation. We can
-     * set flag to IOMMU_NONE to mean that we don't need any
-     * read/write permission checks, like, when for region replay.
+     * Return a TLB entry that contains a given address.
+     *
+     * The IOMMUAccessFlags indicated via @flag are optional and may
+     * be specified as IOMMU_NONE to indicate that the caller needs
+     * the full translation information for both reads and writes. If
+     * the access flags are specified then the IOMMU implementation
+     * may use this as an optimization, to stop doing a page table
+     * walk as soon as it knows that the requested permissions are not
+     * allowed. If IOMMU_NONE is passed then the IOMMU must do the
+     * full page table walk and report the permissions in the returned
+     * IOMMUTLBEntry. (Note that this implies that an IOMMU may not
+     * return different mappings for reads and writes.)
+     *
+     * The returned information remains valid while the caller is
+     * holding the big QEMU lock or is inside an RCU critical section;
+     * if the caller wishes to cache the mapping beyond that it must
+     * register an IOMMU notifier so it can invalidate its cached
+     * information when the IOMMU mapping changes.
+     *
+     * @iommu: the IOMMUMemoryRegion
+     * @hwaddr: address to be translated within the memory region
+     * @flag: requested access permissions
      */
     IOMMUTLBEntry (*translate)(IOMMUMemoryRegion *iommu, hwaddr addr,
                                IOMMUAccessFlags flag);
-    /* Returns minimum supported page size */
+    /* Returns minimum supported page size in bytes.
+     * If this method is not provided then the minimum is assumed to
+     * be TARGET_PAGE_SIZE.
+     *
+     * @iommu: the IOMMUMemoryRegion
+     */
     uint64_t (*get_min_page_size)(IOMMUMemoryRegion *iommu);
-    /* Called when IOMMU Notifier flag changed */
+    /* Called when IOMMU Notifier flag changes (ie when the set of
+     * events which IOMMU users are requesting notification for changes).
+     * Optional method -- need not be provided if the IOMMU does not
+     * need to know exactly which events must be notified.
+     *
+     * @iommu: the IOMMUMemoryRegion
+     * @old_flags: events which previously needed to be notified
+     * @new_flags: events which now need to be notified
+     */
     void (*notify_flag_changed)(IOMMUMemoryRegion *iommu,
                                 IOMMUNotifierFlag old_flags,
                                 IOMMUNotifierFlag new_flags);
-    /* Set this up to provide customized IOMMU replay function */
+    /* Called to handle memory_region_iommu_replay().
+     *
+     * The default implementation of memory_region_iommu_replay() is to
+     * call the IOMMU translate method for every page in the address space
+     * with flag == IOMMU_NONE and then call the notifier if translate
+     * returns a valid mapping. If this method is implemented then it
+     * overrides the default behaviour, and must provide the full semantics
+     * of memory_region_iommu_replay(), by calling @notifier for every
+     * translation present in the IOMMU.
+     *
+     * Optional method -- an IOMMU only needs to provide this method
+     * if the default is inefficient or produces undesirable side effects.
+     *
+     * Note: this is not related to record-and-replay functionality.
+     */
     void (*replay)(IOMMUMemoryRegion *iommu, IOMMUNotifier *notifier);
 
-    /* Get IOMMU misc attributes */
-    int (*get_attr)(IOMMUMemoryRegion *iommu, enum IOMMUMemoryRegionAttr,
+    /* Get IOMMU misc attributes. This is an optional method that
+     * can be used to allow users of the IOMMU to get implementation-specific
+     * information. The IOMMU implements this method to handle calls
+     * by IOMMU users to memory_region_iommu_get_attr() by filling in
+     * the arbitrary data pointer for any IOMMUMemoryRegionAttr values that
+     * the IOMMU supports. If the method is unimplemented then
+     * memory_region_iommu_get_attr() will always return -EINVAL.
+     *
+     * @iommu: the IOMMUMemoryRegion
+     * @attr: attribute being queried
+     * @data: memory to fill in with the attribute data
+     *
+     * Returns 0 on success, or a negative errno; in particular
+     * returns -EINVAL for unrecognized or unimplemented attribute types.
+     */
+    int (*get_attr)(IOMMUMemoryRegion *iommu, enum IOMMUMemoryRegionAttr attr,
                     void *data);
 } IOMMUMemoryRegionClass;
 
@@ -XXX,XX +XXX,XX @@ static inline void memory_region_init_reservation(MemoryRegion *mr,
  * An IOMMU region translates addresses and forwards accesses to a target
  * memory region.
  *
+ * The IOMMU implementation must define a subclass of TYPE_IOMMU_MEMORY_REGION.
+ * @_iommu_mr should be a pointer to enough memory for an instance of
+ * that subclass, @instance_size is the size of that subclass, and
+ * @mrtypename is its name. This function will initialize @_iommu_mr as an
+ * instance of the subclass, and its methods will then be called to handle
+ * accesses to the memory region. See the documentation of
+ * #IOMMUMemoryRegionClass for further details.
+ *
  * @_iommu_mr: the #IOMMUMemoryRegion to be initialized
  * @instance_size: the IOMMUMemoryRegion subclass instance size
  * @mrtypename: the type name of the #IOMMUMemoryRegion
@@ -XXX,XX +XXX,XX @@ void memory_region_register_iommu_notifier(MemoryRegion *mr,
  * a notifier with the minimum page granularity returned by
  * mr->iommu_ops->get_page_size().
  *
+ * Note: this is not related to record-and-replay functionality.
+ *
  * @iommu_mr: the memory region to observe
  * @n: the notifier to which to replay iommu mappings
  */
@@ -XXX,XX +XXX,XX @@ void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n);
  * memory_region_iommu_replay_all: replay existing IOMMU translations
  * to all the notifiers registered.
  *
+ * Note: this is not related to record-and-replay functionality.
+ *
  * @iommu_mr: the memory region to observe
  */
 void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr);
@@ -XXX,XX +XXX,XX @@ void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
  * memory_region_iommu_get_attr: return an IOMMU attr if get_attr() is
  * defined on the IOMMU.
  *
- * Returns 0 if succeded, error code otherwise.
+ * Returns 0 on success, or a negative errno otherwise. In particular,
+ * -EINVAL indicates that the IOMMU does not support the requested
+ * attribute.
  *
  * @iommu_mr: the memory region
  * @attr: the requested attribute
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to tb_invalidate_phys_addr().
Its callers either have an attrs value to hand, or don't care
and can use MEMTXATTRS_UNSPECIFIED.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20180521140402.23318-3-peter.maydell@linaro.org
---
 include/exec/exec-all.h   | 5 +++--
 accel/tcg/translate-all.c | 2 +-
 exec.c                    | 2 +-
 target/xtensa/op_helper.c | 3 ++-
 4 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
 void tlb_set_page(CPUState *cpu, target_ulong vaddr,
                   hwaddr paddr, int prot,
                   int mmu_idx, target_ulong size);
-void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);
+void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs);
 void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx,
                  uintptr_t retaddr);
 #else
@@ -XXX,XX +XXX,XX @@ static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
                                                        uint16_t idxmap)
 {
 }
-static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr)
+static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr,
+                                           MemTxAttrs attrs)
 {
 }
 #endif
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -XXX,XX +XXX,XX @@ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr)
 }
 
 #if !defined(CONFIG_USER_ONLY)
-void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr)
+void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
 {
     ram_addr_t ram_addr;
     MemoryRegion *mr;
diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
     if (phys != -1) {
         /* Locks grabbed by tb_invalidate_phys_addr */
         tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as,
-                                phys | (pc & ~TARGET_PAGE_MASK));
+                                phys | (pc & ~TARGET_PAGE_MASK), attrs);
     }
 }
 #endif
diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/xtensa/op_helper.c
+++ b/target/xtensa/op_helper.c
@@ -XXX,XX +XXX,XX @@ static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)
     int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0,
             &paddr, &page_size, &access);
     if (ret == 0) {
-        tb_invalidate_phys_addr(&address_space_memory, paddr);
+        tb_invalidate_phys_addr(&address_space_memory, paddr,
+                                MEMTXATTRS_UNSPECIFIED);
     }
 }
 
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to address_space_translate()
and address_space_translate_cached(). Callers either have an
attrs value to hand, or don't care and can use MEMTXATTRS_UNSPECIFIED.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180521140402.23318-4-peter.maydell@linaro.org
---
 include/exec/memory.h     |  4 +++-
 accel/tcg/translate-all.c |  2 +-
 exec.c                    | 14 +++++++++-----
 hw/vfio/common.c          |  3 ++-
 memory_ldst.inc.c         | 18 +++++++++---------
 target/riscv/helper.c     |  2 +-
 6 files changed, 25 insertions(+), 18 deletions(-)

diff --git a/include/exec/memory.h b/include/exec/memory.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -XXX,XX +XXX,XX @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
  * #MemoryRegion.
  * @len: pointer to length
  * @is_write: indicates the transfer direction
+ * @attrs: memory attributes
  */
 MemoryRegion *flatview_translate(FlatView *fv,
                                  hwaddr addr, hwaddr *xlat,
@@ -XXX,XX +XXX,XX @@ MemoryRegion *flatview_translate(FlatView *fv,
 
 static inline MemoryRegion *address_space_translate(AddressSpace *as,
                                                     hwaddr addr, hwaddr *xlat,
-                                                    hwaddr *len, bool is_write)
+                                                    hwaddr *len, bool is_write,
+                                                    MemTxAttrs attrs)
 {
     return flatview_translate(address_space_to_flatview(as),
                               addr, xlat, len, is_write);
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -XXX,XX +XXX,XX @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
     hwaddr l = 1;
 
     rcu_read_lock();
-    mr = address_space_translate(as, addr, &addr, &l, false);
+    mr = address_space_translate(as, addr, &addr, &l, false, attrs);
     if (!(memory_region_is_ram(mr)
           || memory_region_is_romd(mr))) {
         rcu_read_unlock();
diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as,
     rcu_read_lock();
     while (len > 0) {
         l = len;
-        mr = address_space_translate(as, addr, &addr1, &l, true);
+        mr = address_space_translate(as, addr, &addr1, &l, true,
+                                     MEMTXATTRS_UNSPECIFIED);
 
         if (!(memory_region_is_ram(mr) ||
               memory_region_is_romd(mr))) {
@@ -XXX,XX +XXX,XX @@ void address_space_cache_destroy(MemoryRegionCache *cache)
  */
 static inline MemoryRegion *address_space_translate_cached(
     MemoryRegionCache *cache, hwaddr addr, hwaddr *xlat,
-    hwaddr *plen, bool is_write)
+    hwaddr *plen, bool is_write, MemTxAttrs attrs)
 {
     MemoryRegionSection section;
     MemoryRegion *mr;
@@ -XXX,XX +XXX,XX @@ address_space_read_cached_slow(MemoryRegionCache *cache, hwaddr addr,
     MemoryRegion *mr;
 
     l = len;
-    mr = address_space_translate_cached(cache, addr, &addr1, &l, false);
+    mr = address_space_translate_cached(cache, addr, &addr1, &l, false,
+                                        MEMTXATTRS_UNSPECIFIED);
     flatview_read_continue(cache->fv,
                            addr, MEMTXATTRS_UNSPECIFIED, buf, len,
                            addr1, l, mr);
@@ -XXX,XX +XXX,XX @@ address_space_write_cached_slow(MemoryRegionCache *cache, hwaddr addr,
     MemoryRegion *mr;
 
     l = len;
-    mr = address_space_translate_cached(cache, addr, &addr1, &l, true);
+    mr = address_space_translate_cached(cache, addr, &addr1, &l, true,
+                                        MEMTXATTRS_UNSPECIFIED);
     flatview_write_continue(cache->fv,
                             addr, MEMTXATTRS_UNSPECIFIED, buf, len,
                             addr1, l, mr);
@@ -XXX,XX +XXX,XX @@ bool cpu_physical_memory_is_io(hwaddr phys_addr)
 
     rcu_read_lock();
     mr = address_space_translate(&address_space_memory,
-                                 phys_addr, &phys_addr, &l, false);
+                                 phys_addr, &phys_addr, &l, false,
+                                 MEMTXATTRS_UNSPECIFIED);
 
     res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr));
     rcu_read_unlock();
diff --git a/hw/vfio/common.c b/hw/vfio/common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/vfio/common.c
+++ b/hw/vfio/common.c
@@ -XXX,XX +XXX,XX @@ static bool vfio_get_vaddr(IOMMUTLBEntry *iotlb, void **vaddr,
      */
     mr = address_space_translate(&address_space_memory,
                                  iotlb->translated_addr,
-                                 &xlat, &len, writable);
+                                 &xlat, &len, writable,
+                                 MEMTXATTRS_UNSPECIFIED);
     if (!memory_region_is_ram(mr)) {
         error_report("iommu map to non memory area %"HWADDR_PRIx"",
                      xlat);
diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/memory_ldst.inc.c
+++ b/memory_ldst.inc.c
@@ -XXX,XX +XXX,XX @@ static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL,
     bool release_lock = false;
 
     RCU_READ_LOCK();
-    mr = TRANSLATE(addr, &addr1, &l, false);
+    mr = TRANSLATE(addr, &addr1, &l, false, attrs);
     if (l < 4 || !IS_DIRECT(mr, false)) {
         release_lock |= prepare_mmio_access(mr);
 
@@ -XXX,XX +XXX,XX @@ static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL,
     bool release_lock = false;
 
     RCU_READ_LOCK();
-    mr = TRANSLATE(addr, &addr1, &l, false);
+    mr = TRANSLATE(addr, &addr1, &l, false, attrs);
     if (l < 8 || !IS_DIRECT(mr, false)) {
         release_lock |= prepare_mmio_access(mr);
 
@@ -XXX,XX +XXX,XX @@ uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
     bool release_lock = false;
 
     RCU_READ_LOCK();
-    mr = TRANSLATE(addr, &addr1, &l, false);
+    mr = TRANSLATE(addr, &addr1, &l, false, attrs);
     if (!IS_DIRECT(mr, false)) {
         release_lock |= prepare_mmio_access(mr);
 
@@ -XXX,XX +XXX,XX @@ static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,
     bool release_lock = false;
 
     RCU_READ_LOCK();
-    mr = TRANSLATE(addr, &addr1, &l, false);
+    mr = TRANSLATE(addr, &addr1, &l, false, attrs);
     if (l < 2 || !IS_DIRECT(mr, false)) {
         release_lock |= prepare_mmio_access(mr);
 
@@ -XXX,XX +XXX,XX @@ void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL,
     bool release_lock = false;
 
     RCU_READ_LOCK();
-    mr = TRANSLATE(addr, &addr1, &l, true);
+    mr = TRANSLATE(addr, &addr1, &l, true, attrs);
     if (l < 4 || !IS_DIRECT(mr, true)) {
         release_lock |= prepare_mmio_access(mr);
 
@@ -XXX,XX +XXX,XX @@ static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL,
     bool release_lock = false;
 
     RCU_READ_LOCK();
-    mr = TRANSLATE(addr, &addr1, &l, true);
+    mr = TRANSLATE(addr, &addr1, &l, true, attrs);
     if (l < 4 || !IS_DIRECT(mr, true)) {
         release_lock |= prepare_mmio_access(mr);
 
@@ -XXX,XX +XXX,XX @@ void glue(address_space_stb, SUFFIX)(ARG1_DECL,
     bool release_lock = false;
 
     RCU_READ_LOCK();
-    mr = TRANSLATE(addr, &addr1, &l, true);
+    mr = TRANSLATE(addr, &addr1, &l, true, attrs);
     if (!IS_DIRECT(mr, true)) {
         release_lock |= prepare_mmio_access(mr);
         r = memory_region_dispatch_write(mr, addr1, val, 1, attrs);
@@ -XXX,XX +XXX,XX @@ static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL,
     bool release_lock = false;
 
     RCU_READ_LOCK();
-    mr = TRANSLATE(addr, &addr1, &l, true);
+    mr = TRANSLATE(addr, &addr1, &l, true, attrs);
     if (l < 2 || !IS_DIRECT(mr, true)) {
         release_lock |= prepare_mmio_access(mr);
 
@@ -XXX,XX +XXX,XX @@ static void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL,
     bool release_lock = false;
 
     RCU_READ_LOCK();
-    mr = TRANSLATE(addr, &addr1, &l, true);
+    mr = TRANSLATE(addr, &addr1, &l, true, attrs);
     if (l < 8 || !IS_DIRECT(mr, true)) {
         release_lock |= prepare_mmio_access(mr);
 
diff --git a/target/riscv/helper.c b/target/riscv/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/helper.c
+++ b/target/riscv/helper.c
@@ -XXX,XX +XXX,XX @@ restart:
                 MemoryRegion *mr;
                 hwaddr l = sizeof(target_ulong), addr1;
                 mr = address_space_translate(cs->as, pte_addr,
-                    &addr1, &l, false);
+                    &addr1, &l, false, MEMTXATTRS_UNSPECIFIED);
                 if (memory_access_is_direct(mr, true)) {
                     target_ulong *pte_pa =
                         qemu_map_ram_ptr(mr->ram_block, addr1);
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to address_space_map().
Its callers either have an attrs value to hand, or don't care
and can use MEMTXATTRS_UNSPECIFIED.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180521140402.23318-5-peter.maydell@linaro.org
---
 include/exec/memory.h   | 3 ++-
 include/sysemu/dma.h    | 3 ++-
 exec.c                  | 6 ++++--
 target/ppc/mmu-hash64.c | 3 ++-
 4 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/include/exec/memory.h b/include/exec/memory.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -XXX,XX +XXX,XX @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_
  * @addr: address within that address space
  * @plen: pointer to length of buffer; updated on return
  * @is_write: indicates the transfer direction
+ * @attrs: memory attributes
  */
 void *address_space_map(AddressSpace *as, hwaddr addr,
-                        hwaddr *plen, bool is_write);
+                        hwaddr *plen, bool is_write, MemTxAttrs attrs);
 
 /* address_space_unmap: Unmaps a memory region previously mapped by address_space_map()
  *
diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h
index XXXXXXX..XXXXXXX 100644
--- a/include/sysemu/dma.h
+++ b/include/sysemu/dma.h
@@ -XXX,XX +XXX,XX @@ static inline void *dma_memory_map(AddressSpace *as,
     hwaddr xlen = *len;
     void *p;
 
-    p = address_space_map(as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE);
+    p = address_space_map(as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE,
+                          MEMTXATTRS_UNSPECIFIED);
     *len = xlen;
     return p;
 }
diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ flatview_extend_translation(FlatView *fv, hwaddr addr,
 void *address_space_map(AddressSpace *as,
                         hwaddr addr,
                         hwaddr *plen,
-                        bool is_write)
+                        bool is_write,
+                        MemTxAttrs attrs)
 {
     hwaddr len = *plen;
     hwaddr l, xlat;
@@ -XXX,XX +XXX,XX @@ void *cpu_physical_memory_map(hwaddr addr,
                               hwaddr *plen,
                               int is_write)
 {
-    return address_space_map(&address_space_memory, addr, plen, is_write);
+    return address_space_map(&address_space_memory, addr, plen, is_write,
+                             MEMTXATTRS_UNSPECIFIED);
 }
 
 void cpu_physical_memory_unmap(void *buffer, hwaddr len,
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -XXX,XX +XXX,XX @@ const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU *cpu,
         return NULL;
     }
 
-    hptes = address_space_map(CPU(cpu)->as, base + pte_offset, &plen, false);
+    hptes = address_space_map(CPU(cpu)->as, base + pte_offset, &plen, false,
+                              MEMTXATTRS_UNSPECIFIED);
     if (plen < (n * HASH_PTE_SIZE_64)) {
         hw_error("%s: Unable to map all requested HPTEs\n", __func__);
     }
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to address_space_access_valid().
Its callers either have an attrs value to hand, or don't care
and can use MEMTXATTRS_UNSPECIFIED.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180521140402.23318-6-peter.maydell@linaro.org
---
 include/exec/memory.h      | 4 +++-
 include/sysemu/dma.h       | 3 ++-
 exec.c                     | 3 ++-
 target/s390x/diag.c        | 6 ++++--
 target/s390x/excp_helper.c | 3 ++-
 target/s390x/mmu_helper.c  | 3 ++-
 target/s390x/sigp.c        | 3 ++-
 7 files changed, 17 insertions(+), 8 deletions(-)

diff --git a/include/exec/memory.h b/include/exec/memory.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -XXX,XX +XXX,XX @@ static inline MemoryRegion *address_space_translate(AddressSpace *as,
  * @addr: address within that address space
  * @len: length of the area to be checked
  * @is_write: indicates the transfer direction
+ * @attrs: memory attributes
  */
-bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_write);
+bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len,
+                                bool is_write, MemTxAttrs attrs);
 
 /* address_space_map: map a physical memory region into a host virtual address
  *
diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h
index XXXXXXX..XXXXXXX 100644
--- a/include/sysemu/dma.h
+++ b/include/sysemu/dma.h
@@ -XXX,XX +XXX,XX @@ static inline bool dma_memory_valid(AddressSpace *as,
                                     DMADirection dir)
 {
     return address_space_access_valid(as, addr, len,
-                                      dir == DMA_DIRECTION_FROM_DEVICE);
+                                      dir == DMA_DIRECTION_FROM_DEVICE,
+                                      MEMTXATTRS_UNSPECIFIED);
 }
 
 static inline int dma_memory_rw_relaxed(AddressSpace *as, dma_addr_t addr,
diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
 }
 
 bool address_space_access_valid(AddressSpace *as, hwaddr addr,
-                                int len, bool is_write)
+                                int len, bool is_write,
+                                MemTxAttrs attrs)
 {
     FlatView *fv;
     bool result;
diff --git a/target/s390x/diag.c b/target/s390x/diag.c
index XXXXXXX..XXXXXXX 100644
--- a/target/s390x/diag.c
+++ b/target/s390x/diag.c
@@ -XXX,XX +XXX,XX @@ void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3, uintptr_t ra)
             return;
         }
         if (!address_space_access_valid(&address_space_memory, addr,
-                                        sizeof(IplParameterBlock), false)) {
+                                        sizeof(IplParameterBlock), false,
+                                        MEMTXATTRS_UNSPECIFIED)) {
             s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra);
             return;
         }
@@ -XXX,XX +XXX,XX @@ out:
             return;
         }
         if (!address_space_access_valid(&address_space_memory, addr,
-                                        sizeof(IplParameterBlock), true)) {
+                                        sizeof(IplParameterBlock), true,
+                                        MEMTXATTRS_UNSPECIFIED)) {
             s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra);
             return;
         }
diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/s390x/excp_helper.c
+++ b/target/s390x/excp_helper.c
@@ -XXX,XX +XXX,XX @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr, int size,
 
     /* check out of RAM access */
     if (!address_space_access_valid(&address_space_memory, raddr,
-                                    TARGET_PAGE_SIZE, rw)) {
+                                    TARGET_PAGE_SIZE, rw,
+                                    MEMTXATTRS_UNSPECIFIED)) {
         DPRINTF("%s: raddr %" PRIx64 " > ram_size %" PRIx64 "\n", __func__,
                 (uint64_t)raddr, (uint64_t)ram_size);
         trigger_pgm_exception(env, PGM_ADDRESSING, ILEN_AUTO);
diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/s390x/mmu_helper.c
+++ b/target/s390x/mmu_helper.c
@@ -XXX,XX +XXX,XX @@ static int translate_pages(S390CPU *cpu, vaddr addr, int nr_pages,
             return ret;
         }
         if (!address_space_access_valid(&address_space_memory, pages[i],
-                                        TARGET_PAGE_SIZE, is_write)) {
+                                        TARGET_PAGE_SIZE, is_write,
+                                        MEMTXATTRS_UNSPECIFIED)) {
             trigger_access_exception(env, PGM_ADDRESSING, ILEN_AUTO, 0);
             return -EFAULT;
         }
diff --git a/target/s390x/sigp.c b/target/s390x/sigp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/s390x/sigp.c
+++ b/target/s390x/sigp.c
@@ -XXX,XX +XXX,XX @@ static void sigp_set_prefix(CPUState *cs, run_on_cpu_data arg)
     cpu_synchronize_state(cs);
 
     if (!address_space_access_valid(&address_space_memory, addr,
-                                    sizeof(struct LowCore), false)) {
+                                    sizeof(struct LowCore), false,
+                                    MEMTXATTRS_UNSPECIFIED)) {
         set_sigp_status(si, SIGP_STAT_INVALID_PARAMETER);
         return;
     }
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to flatview_extend_translation().
Its callers either have an attrs value to hand, or don't care
and can use MEMTXATTRS_UNSPECIFIED.

diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr,
 
 static hwaddr
 flatview_extend_translation(FlatView *fv, hwaddr addr,
-                                 hwaddr target_len,
-                                 MemoryRegion *mr, hwaddr base, hwaddr len,
-                                 bool is_write)
+                            hwaddr target_len,
+                            MemoryRegion *mr, hwaddr base, hwaddr len,
+                            bool is_write, MemTxAttrs attrs)
 {
     hwaddr done = 0;
     hwaddr xlat;
@@ -XXX,XX +XXX,XX @@ void *address_space_map(AddressSpace *as,
 
     memory_region_ref(mr);
     *plen = flatview_extend_translation(fv, addr, len, mr, xlat,
-                                             l, is_write);
+                                        l, is_write, attrs);
     ptr = qemu_ram_ptr_length(mr->ram_block, xlat, plen, true);
     rcu_read_unlock();
 
@@ -XXX,XX +XXX,XX @@ int64_t address_space_cache_init(MemoryRegionCache *cache,
     mr = cache->mrs.mr;
     memory_region_ref(mr);
     if (memory_access_is_direct(mr, is_write)) {
+        /* We don't care about the memory attributes here as we're only
+         * doing this if we found actual RAM, which behaves the same
+         * regardless of attributes; so UNSPECIFIED is fine.
+         */
         l = flatview_extend_translation(cache->fv, addr, len, mr,
-                                        cache->xlat, l, is_write);
+                                        cache->xlat, l, is_write,
+                                        MEMTXATTRS_UNSPECIFIED);
         cache->ptr = qemu_ram_ptr_length(mr->ram_block, cache->xlat, &l, true);
     } else {
         cache->ptr = NULL;
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to memory_region_access_valid().
Its callers either have an attrs value to hand, or don't care
and can use MEMTXATTRS_UNSPECIFIED.

The callsite in flatview_access_valid() is part of a recursive
loop flatview_access_valid() -> memory_region_access_valid() ->
 subpage_accepts() -> flatview_access_valid(); we make it pass
MEMTXATTRS_UNSPECIFIED for now, until the next several commits
have plumbed an attrs parameter through the rest of the loop
and we can add an attrs parameter to flatview_access_valid().

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180521140402.23318-8-peter.maydell@linaro.org
---
 include/exec/memory-internal.h | 3 ++-
 exec.c                         | 4 +++-
 hw/s390x/s390-pci-inst.c       | 3 ++-
 memory.c                       | 7 ++++---
 4 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/include/exec/memory-internal.h b/include/exec/memory-internal.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/memory-internal.h
+++ b/include/exec/memory-internal.h
@@ -XXX,XX +XXX,XX @@ void flatview_unref(FlatView *view);
 extern const MemoryRegionOps unassigned_mem_ops;
 
 bool memory_region_access_valid(MemoryRegion *mr, hwaddr addr,
-                                unsigned size, bool is_write);
+                                unsigned size, bool is_write,
+                                MemTxAttrs attrs);
 
 void flatview_add_to_dispatch(FlatView *fv, MemoryRegionSection *section);
 AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv);
diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
         mr = flatview_translate(fv, addr, &xlat, &l, is_write);
         if (!memory_access_is_direct(mr, is_write)) {
             l = memory_access_size(mr, l, addr);
-            if (!memory_region_access_valid(mr, xlat, l, is_write)) {
+            /* When our callers all have attrs we'll pass them through here */
+            if (!memory_region_access_valid(mr, xlat, l, is_write,
+                                            MEMTXATTRS_UNSPECIFIED)) {
                 return false;
             }
         }
diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/s390x/s390-pci-inst.c
+++ b/hw/s390x/s390-pci-inst.c
@@ -XXX,XX +XXX,XX @@ int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr,
     mr = s390_get_subregion(mr, offset, len);
     offset -= mr->addr;
 
-    if (!memory_region_access_valid(mr, offset, len, true)) {
+    if (!memory_region_access_valid(mr, offset, len, true,
+                                    MEMTXATTRS_UNSPECIFIED)) {
         s390_program_interrupt(env, PGM_OPERAND, 6, ra);
         return 0;
     }
diff --git a/memory.c b/memory.c
index XXXXXXX..XXXXXXX 100644
--- a/memory.c
+++ b/memory.c
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps ram_device_mem_ops = {
 bool memory_region_access_valid(MemoryRegion *mr,
                                 hwaddr addr,
                                 unsigned size,
-                                bool is_write)
+                                bool is_write,
+                                MemTxAttrs attrs)
 {
     int access_size_min, access_size_max;
     int access_size, i;
@@ -XXX,XX +XXX,XX @@ MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
 {
     MemTxResult r;
 
-    if (!memory_region_access_valid(mr, addr, size, false)) {
+    if (!memory_region_access_valid(mr, addr, size, false, attrs)) {
         *pval = unassigned_mem_read(mr, addr, size);
         return MEMTX_DECODE_ERROR;
     }
@@ -XXX,XX +XXX,XX @@ MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
                                          unsigned size,
                                          MemTxAttrs attrs)
 {
-    if (!memory_region_access_valid(mr, addr, size, true)) {
+    if (!memory_region_access_valid(mr, addr, size, true, attrs)) {
         unassigned_mem_write(mr, addr, data, size);
         return MEMTX_DECODE_ERROR;
     }
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to the MemoryRegion valid.accepts
callback. We'll need this for subpage_accepts().

We could take the approach we used with the read and write
callbacks and add new a new _with_attrs version, but since there
are so few implementations of the accepts hook we just change
them all.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180521140402.23318-9-peter.maydell@linaro.org
---
 include/exec/memory.h |  3 ++-
 exec.c                |  9 ++++++---
 hw/hppa/dino.c        |  3 ++-
 hw/nvram/fw_cfg.c     | 12 ++++++++----
 hw/scsi/esp.c         |  3 ++-
 hw/xen/xen_pt_msi.c   |  3 ++-
 memory.c              |  5 +++--
 7 files changed, 25 insertions(+), 13 deletions(-)

diff --git a/include/exec/memory.h b/include/exec/memory.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -XXX,XX +XXX,XX @@ struct MemoryRegionOps {
          * as a machine check exception).
          */
         bool (*accepts)(void *opaque, hwaddr addr,
-                        unsigned size, bool is_write);
+                        unsigned size, bool is_write,
+                        MemTxAttrs attrs);
     } valid;
     /* Internal implementation constraints: */
     struct {
diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
 }
 
 static bool notdirty_mem_accepts(void *opaque, hwaddr addr,
-                                 unsigned size, bool is_write)
+                                 unsigned size, bool is_write,
+                                 MemTxAttrs attrs)
 {
     return is_write;
 }
@@ -XXX,XX +XXX,XX @@ static MemTxResult subpage_write(void *opaque, hwaddr addr,
 }
 
 static bool subpage_accepts(void *opaque, hwaddr addr,
-                            unsigned len, bool is_write)
+                            unsigned len, bool is_write,
+                            MemTxAttrs attrs)
 {
     subpage_t *subpage = opaque;
 #if defined(DEBUG_SUBPAGE)
@@ -XXX,XX +XXX,XX @@ static void readonly_mem_write(void *opaque, hwaddr addr,
 }
 
 static bool readonly_mem_accepts(void *opaque, hwaddr addr,
-                                 unsigned size, bool is_write)
+                                 unsigned size, bool is_write,
+                                 MemTxAttrs attrs)
 {
     return is_write;
 }
diff --git a/hw/hppa/dino.c b/hw/hppa/dino.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/hppa/dino.c
+++ b/hw/hppa/dino.c
@@ -XXX,XX +XXX,XX @@ static void gsc_to_pci_forwarding(DinoState *s)
 }
 
 static bool dino_chip_mem_valid(void *opaque, hwaddr addr,
-                                unsigned size, bool is_write)
+                                unsigned size, bool is_write,
+                                MemTxAttrs attrs)
 {
     switch (addr) {
     case DINO_IAR0:
diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/nvram/fw_cfg.c
+++ b/hw/nvram/fw_cfg.c
@@ -XXX,XX +XXX,XX @@ static void fw_cfg_dma_mem_write(void *opaque, hwaddr addr,
 }
 
 static bool fw_cfg_dma_mem_valid(void *opaque, hwaddr addr,
-                                  unsigned size, bool is_write)
+                                 unsigned size, bool is_write,
+                                 MemTxAttrs attrs)
 {
     return !is_write || ((size == 4 && (addr == 0 || addr == 4)) ||
                          (size == 8 && addr == 0));
 }
 
 static bool fw_cfg_data_mem_valid(void *opaque, hwaddr addr,
-                                  unsigned size, bool is_write)
+                                  unsigned size, bool is_write,
+                                  MemTxAttrs attrs)
 {
     return addr == 0;
 }
@@ -XXX,XX +XXX,XX @@ static void fw_cfg_ctl_mem_write(void *opaque, hwaddr addr,
 }
 
 static bool fw_cfg_ctl_mem_valid(void *opaque, hwaddr addr,
-                                 unsigned size, bool is_write)
+                                 unsigned size, bool is_write,
+                                 MemTxAttrs attrs)
 {
     return is_write && size == 2;
 }
@@ -XXX,XX +XXX,XX @@ static void fw_cfg_comb_write(void *opaque, hwaddr addr,
 }
 
 static bool fw_cfg_comb_valid(void *opaque, hwaddr addr,
-                                  unsigned size, bool is_write)
+                              unsigned size, bool is_write,
+                              MemTxAttrs attrs)
 {
     return (size == 1) || (is_write && size == 2);
 }
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/scsi/esp.c
+++ b/hw/scsi/esp.c
@@ -XXX,XX +XXX,XX @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
 }
 
 static bool esp_mem_accepts(void *opaque, hwaddr addr,
-                            unsigned size, bool is_write)
+                            unsigned size, bool is_write,
+                            MemTxAttrs attrs)
 {
     return (size == 1) || (is_write && size == 4);
 }
diff --git a/hw/xen/xen_pt_msi.c b/hw/xen/xen_pt_msi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/xen/xen_pt_msi.c
+++ b/hw/xen/xen_pt_msi.c
@@ -XXX,XX +XXX,XX @@ static uint64_t pci_msix_read(void *opaque, hwaddr addr,
 }
 
 static bool pci_msix_accepts(void *opaque, hwaddr addr,
-                             unsigned size, bool is_write)
+                             unsigned size, bool is_write,
+                             MemTxAttrs attrs)
 {
     return !(addr & (size - 1));
 }
diff --git a/memory.c b/memory.c
index XXXXXXX..XXXXXXX 100644
--- a/memory.c
+++ b/memory.c
@@ -XXX,XX +XXX,XX @@ static void unassigned_mem_write(void *opaque, hwaddr addr,
 }
 
 static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
-                                   unsigned size, bool is_write)
+                                   unsigned size, bool is_write,
+                                   MemTxAttrs attrs)
 {
     return false;
 }
@@ -XXX,XX +XXX,XX @@ bool memory_region_access_valid(MemoryRegion *mr,
     access_size = MAX(MIN(size, access_size_max), access_size_min);
     for (i = 0; i < size; i += access_size) {
         if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
-                                    is_write)) {
+                                    is_write, attrs)) {
             return false;
         }
     }
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to flatview_access_valid().
Its callers now all have an attrs value to hand, so we can
correct our earlier temporary use of MEMTXATTRS_UNSPECIFIED.

diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
 static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
                                   const uint8_t *buf, int len);
 static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
-                                  bool is_write);
+                                  bool is_write, MemTxAttrs attrs);
 
 static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data,
                                 unsigned len, MemTxAttrs attrs)
@@ -XXX,XX +XXX,XX @@ static bool subpage_accepts(void *opaque, hwaddr addr,
 #endif
 
     return flatview_access_valid(subpage->fv, addr + subpage->base,
-                                 len, is_write);
+                                 len, is_write, attrs);
 }
 
 static const MemoryRegionOps subpage_ops = {
@@ -XXX,XX +XXX,XX @@ static void cpu_notify_map_clients(void)
 }
 
 static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
-                                  bool is_write)
+                                  bool is_write, MemTxAttrs attrs)
 {
     MemoryRegion *mr;
     hwaddr l, xlat;
@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
         mr = flatview_translate(fv, addr, &xlat, &l, is_write);
         if (!memory_access_is_direct(mr, is_write)) {
             l = memory_access_size(mr, l, addr);
-            /* When our callers all have attrs we'll pass them through here */
-            if (!memory_region_access_valid(mr, xlat, l, is_write,
-                                            MEMTXATTRS_UNSPECIFIED)) {
+            if (!memory_region_access_valid(mr, xlat, l, is_write, attrs)) {
                 return false;
             }
         }
@@ -XXX,XX +XXX,XX @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr,
 
     rcu_read_lock();
     fv = address_space_to_flatview(as);
-    result = flatview_access_valid(fv, addr, len, is_write);
+    result = flatview_access_valid(fv, addr, len, is_write, attrs);
     rcu_read_unlock();
     return result;
 }
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to flatview_translate(); all its
callers now have attrs available.

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to address_space_get_iotlb_entry().

diff --git a/include/exec/memory.h b/include/exec/memory.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -XXX,XX +XXX,XX @@ void address_space_cache_destroy(MemoryRegionCache *cache);
  * entry. Should be called from an RCU critical section.
  */
 IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
-                                            bool is_write);
+                                            bool is_write, MemTxAttrs attrs);
 
 /* address_space_translate: translate an address range into an address space
  * into a MemoryRegion and an address range into that section.  Should be
diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,
 
 /* Called from RCU critical section */
 IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
-                                            bool is_write)
+                                            bool is_write, MemTxAttrs attrs)
 {
     MemoryRegionSection section;
     hwaddr xlat, page_mask;
diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/virtio/vhost.c
+++ b/hw/virtio/vhost.c
@@ -XXX,XX +XXX,XX @@ int vhost_device_iotlb_miss(struct vhost_dev *dev, uint64_t iova, int write)
     trace_vhost_iotlb_miss(dev, 1);
 
     iotlb = address_space_get_iotlb_entry(dev->vdev->dma_as,
-                                          iova, write);
+                                          iova, write,
+                                          MEMTXATTRS_UNSPECIFIED);
     if (iotlb.target_as != NULL) {
         ret = vhost_memory_region_lookup(dev, iotlb.translated_addr,
                                          &uaddr, &len);
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to flatview_do_translate().

diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ unassigned:
  * @is_write: whether the translation operation is for write
  * @is_mmio: whether this can be MMIO, set true if it can
  * @target_as: the address space targeted by the IOMMU
+ * @attrs: memory transaction attributes
  *
  * This function is called from RCU critical section
  */
@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,
                                                  hwaddr *page_mask_out,
                                                  bool is_write,
                                                  bool is_mmio,
-                                                 AddressSpace **target_as)
+                                                 AddressSpace **target_as,
+                                                 MemTxAttrs attrs)
 {
     MemoryRegionSection *section;
     IOMMUMemoryRegion *iommu_mr;
@@ -XXX,XX +XXX,XX @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
      * but page mask.
      */
     section = flatview_do_translate(address_space_to_flatview(as), addr, &xlat,
-                                    NULL, &page_mask, is_write, false, &as);
+                                    NULL, &page_mask, is_write, false, &as,
+                                    attrs);
 
     /* Illegal translation */
     if (section.mr == &io_mem_unassigned) {
@@ -XXX,XX +XXX,XX @@ MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat,
 
     /* This can be MMIO, so setup MMIO bit. */
     section = flatview_do_translate(fv, addr, xlat, plen, NULL,
-                                    is_write, true, &as);
+                                    is_write, true, &as, attrs);
     mr = section.mr;
 
     if (xen_enabled() && memory_access_is_direct(mr, is_write)) {
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to address_space_translate_iommu().

diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *x
  * @is_write: whether the translation operation is for write
  * @is_mmio: whether this can be MMIO, set true if it can
  * @target_as: the address space targeted by the IOMMU
+ * @attrs: transaction attributes
  *
  * This function is called from RCU critical section.  It is the common
  * part of flatview_do_translate and address_space_translate_cached.
@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection address_space_translate_iommu(IOMMUMemoryRegion *iomm
                                                          hwaddr *page_mask_out,
                                                          bool is_write,
                                                          bool is_mmio,
-                                                         AddressSpace **target_as)
+                                                         AddressSpace **target_as,
+                                                         MemTxAttrs attrs)
 {
     MemoryRegionSection *section;
     hwaddr page_mask = (hwaddr)-1;
@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,
         return address_space_translate_iommu(iommu_mr, xlat,
                                              plen_out, page_mask_out,
                                              is_write, is_mmio,
-                                             target_as);
+                                             target_as, attrs);
     }
     if (page_mask_out) {
         /* Not behind an IOMMU, use default page size. */
@@ -XXX,XX +XXX,XX @@ static inline MemoryRegion *address_space_translate_cached(
 
     section = address_space_translate_iommu(iommu_mr, xlat, plen,
                                             NULL, is_write, true,
-                                            &target_as);
+                                            &target_as, attrs);
     return section.mr;
 }
 
-- 
2.17.1

From: Shannon Zhao <zhaoshenglong@huawei.com>

acpi_data_push uses g_array_set_size to resize the memory size. If there
is no enough contiguous memory, the address will be changed. So previous
pointer could not be used any more. It must update the pointer and use
the new one.

Also, previous codes wrongly use le32 conversion of iort->node_offset
for subsequent computations that will result incorrect value if host is
not litlle endian. So use the non-converted one instead.

Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1527663951-14552-1-git-send-email-zhaoshenglong@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt-acpi-build.c | 20 +++++++++++++++-----
 1 file changed, 15 insertions(+), 5 deletions(-)

diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
     AcpiIortItsGroup *its;
     AcpiIortTable *iort;
     AcpiIortSmmu3 *smmu;
-    size_t node_size, iort_length, smmu_offset = 0;
+    size_t node_size, iort_node_offset, iort_length, smmu_offset = 0;
     AcpiIortRC *rc;
 
     iort = acpi_data_push(table_data, sizeof(*iort));
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
 
     iort_length = sizeof(*iort);
     iort->node_count = cpu_to_le32(nb_nodes);
-    iort->node_offset = cpu_to_le32(sizeof(*iort));
+    /*
+     * Use a copy in case table_data->data moves during acpi_data_push
+     * operations.
+     */
+    iort_node_offset = sizeof(*iort);
+    iort->node_offset = cpu_to_le32(iort_node_offset);
 
     /* ITS group node */
     node_size =  sizeof(*its) + sizeof(uint32_t);
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
         int irq =  vms->irqmap[VIRT_SMMU];
 
         /* SMMUv3 node */
-        smmu_offset = iort->node_offset + node_size;
+        smmu_offset = iort_node_offset + node_size;
         node_size = sizeof(*smmu) + sizeof(*idmap);
         iort_length += node_size;
         smmu = acpi_data_push(table_data, node_size);
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
         idmap->id_count = cpu_to_le32(0xFFFF);
         idmap->output_base = 0;
         /* output IORT node is the ITS group node (the first node) */
-        idmap->output_reference = cpu_to_le32(iort->node_offset);
+        idmap->output_reference = cpu_to_le32(iort_node_offset);
     }
 
     /* Root Complex Node */
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
         idmap->output_reference = cpu_to_le32(smmu_offset);
     } else {
         /* output IORT node is the ITS group node (the first node) */
-        idmap->output_reference = cpu_to_le32(iort->node_offset);
+        idmap->output_reference = cpu_to_le32(iort_node_offset);
     }
 
+    /*
+     * Update the pointer address in case table_data->data moves during above
+     * acpi_data_push operations.
+     */
+    iort = (AcpiIortTable *)(table_data->data + iort_start);
     iort->length = cpu_to_le32(iort_length);
 
     build_header(linker, table_data, (void *)(table_data->data + iort_start),
-- 
2.17.1

From: Shannon Zhao <zhaoshenglong@huawei.com>

kvm_irqchip_create called by kvm_init will call kvm_init_irq_routing to
initialize global capability variables. If we call kvm_init_irq_routing in
GIC realize function, previous allocated memory will leak.

Fix this by deleting the unnecessary call.

Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1527750994-14360-1-git-send-email-zhaoshenglong@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/arm_gic_kvm.c   | 1 -
 hw/intc/arm_gicv3_kvm.c | 1 -
 2 files changed, 2 deletions(-)

diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gic_kvm.c
+++ b/hw/intc/arm_gic_kvm.c
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
 
     if (kvm_has_gsi_routing()) {
         /* set up irq routing */
-        kvm_init_irq_routing(kvm_state);
         for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) {
             kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
         }
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_kvm.c
+++ b/hw/intc/arm_gicv3_kvm.c
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
 
     if (kvm_has_gsi_routing()) {
         /* set up irq routing */
-        kvm_init_irq_routing(kvm_state);
         for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) {
             kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
         }
-- 
2.17.1