target-arm queue:

* mostly my latest v8M stuff, plus a couple of minor patches

The following changes since commit a0b261db8c030813e30a39eae47359ac2a37f7e2:

Merge remote-tracking branch 'remotes/ehabkost/tags/python-next-pull-request' into staging (2017-10-12 10:02:09 +0100)

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20171012

for you to fetch changes up to cf5f7937b05c84d5565134f058c00cd48304a117:

nvic: Fix miscalculation of offsets into ITNS array (2017-10-12 16:33:16 +0100)

* v8M: SG, BLXNS, secure-return

* v8M: fixes for coverity issues in previous patches

* arm: fix armv7m_init() declaration to match definition

* watchdog/aspeed: fix variable type to store reload value

Cédric Le Goater (1):

watchdog/aspeed: fix variable type to store reload value

Igor Mammedov (1):

arm: fix armv7m_init() declaration to match definition

Peter Maydell (11):

target/arm: Add M profile secure MMU index values to get_a32_user_mem_index()

target/arm: Implement SG instruction

target/arm: Implement BLXNS

target/arm: Implement secure function return

target-arm: Don't check for "Thumb2 or M profile" for not-Thumb1

target/arm: Pull Thumb insn word loads up to top level

target-arm: Simplify insn_crosses_page()

target/arm: Support some Thumb insns being always unconditional

target/arm: Implement SG instruction corner cases

nvic: Add missing 'break'

nvic: Fix miscalculation of offsets into ITNS array

From: Igor Mammedov <imammedo@redhat.com>

s/cpu_model/cpu_type/ that has been forgotten during

conversion (ba1ba5cc), while touching the line also

fixup alignment.

Signed-off-by: Igor Mammedov <imammedo@redhat.com>

Message-id: 1507710805-221721-1-git-send-email-imammedo@redhat.com

include/hw/arm/arm.h | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h

--- a/include/hw/arm/arm.h

+++ b/include/hw/arm/arm.h

@@ -XXX,XX +XXX,XX @@ typedef enum {

/* armv7m.c */

DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,

- const char *kernel_filename, const char *cpu_model);

+ const char *kernel_filename, const char *cpu_type);

/**

* armv7m_load_kernel:

* @cpu: CPU

Secure function return happens when a non-secure function has been

called using BLXNS and so has a particular magic LR value (either

0xfefffffe or 0xfeffffff). The function return via BX behaves

specially when the new PC value is this magic value, in the same

way that exception returns are handled.

Adjust our BX excret guards so that they recognize the function

return magic number as well, and perform the function-return

unstacking in do_v7m_exception_exit().

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 1507556919-24992-5-git-send-email-peter.maydell@linaro.org

---

target/arm/internals.h | 7 +++

target/arm/helper.c | 115 +++++++++++++++++++++++++++++++++++++++++++++----

target/arm/translate.c | 14 +++++-

3 files changed, 126 insertions(+), 10 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/internals.h

+++ b/target/arm/internals.h

@@ -XXX,XX +XXX,XX @@ FIELD(V7M_EXCRET, DCRS, 5, 1)

FIELD(V7M_EXCRET, S, 6, 1)

FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */

+/* Minimum value which is a magic number for exception return */

+#define EXC_RETURN_MIN_MAGIC 0xff000000

+/* Minimum number which is a magic number for function or exception return

+ * when using v8M security extension

+ */

+#define FNC_RETURN_MIN_MAGIC 0xfefffffe

+

/* We use a few fake FSR values for internal purposes in M profile.

* M profile cores don't have A/R format FSRs, but currently our

* get_phys_addr() code assumes A/R profile and reports failures via

diff --git a/target/arm/helper.c b/target/arm/helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/helper.c

+++ b/target/arm/helper.c

@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)

* - if the return value is a magic value, do exception return (like BX)

* - otherwise bit 0 of the return value is the target security state

*/

- if (dest >= 0xff000000) {

+ uint32_t min_magic;

+

+ if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {

+ /* Covers FNC_RETURN and EXC_RETURN magic */

+ min_magic = FNC_RETURN_MIN_MAGIC;

+ } else {

+ /* EXC_RETURN magic only */

+ min_magic = EXC_RETURN_MIN_MAGIC;

+ }

+

+ if (dest >= min_magic) {

/* This is an exception return magic value; put it where

* do_v7m_exception_exit() expects and raise EXCEPTION_EXIT.

* Note that if we ever add gen_ss_advance() singlestep support to

@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)

bool exc_secure = false;

bool return_to_secure;

- /* We can only get here from an EXCP_EXCEPTION_EXIT, and

- * gen_bx_excret() enforces the architectural rule

- * that jumps to magic addresses don't have magic behaviour unless

- * we're in Handler mode (compare pseudocode BXWritePC()).

+ /* If we're not in Handler mode then jumps to magic exception-exit

+ * addresses don't have magic behaviour. However for the v8M

+ * security extensions the magic secure-function-return has to

+ * work in thread mode too, so to avoid doing an extra check in

+ * the generated code we allow exception-exit magic to also cause the

+ * internal exception and bring us here in thread mode. Correct code

+ * will never try to do this (the following insn fetch will always

+ * fault) so we the overhead of having taken an unnecessary exception

+ * doesn't matter.

*/

- assert(arm_v7m_is_handler_mode(env));

+ if (!arm_v7m_is_handler_mode(env)) {

+ return;

+ }

/* In the spec pseudocode ExceptionReturn() is called directly

* from BXWritePC() and gets the full target PC value including

@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)

qemu_log_mask(CPU_LOG_INT, "...successful exception return\n");

}

+static bool do_v7m_function_return(ARMCPU *cpu)

+{

+ /* v8M security extensions magic function return.

+ * We may either:

+ * (1) throw an exception (longjump)

+ * (2) return true if we successfully handled the function return

+ * (3) return false if we failed a consistency check and have

+ * pended a UsageFault that needs to be taken now

+ *

+ * At this point the magic return value is split between env->regs[15]

+ * and env->thumb. We don't bother to reconstitute it because we don't

+ * need it (all values are handled the same way).

+ */

+ CPUARMState *env = &cpu->env;

+ uint32_t newpc, newpsr, newpsr_exc;

+

+ qemu_log_mask(CPU_LOG_INT, "...really v7M secure function return\n");

+

+ {

+ bool threadmode, spsel;

+ TCGMemOpIdx oi;

+ ARMMMUIdx mmu_idx;

+ uint32_t *frame_sp_p;

+ uint32_t frameptr;

+

+ /* Pull the return address and IPSR from the Secure stack */

+ threadmode = !arm_v7m_is_handler_mode(env);

+ spsel = env->v7m.control[M_REG_S] & R_V7M_CONTROL_SPSEL_MASK;

+

+ frame_sp_p = get_v7m_sp_ptr(env, true, threadmode, spsel);

+ frameptr = *frame_sp_p;

+

+ /* These loads may throw an exception (for MPU faults). We want to

+ * do them as secure, so work out what MMU index that is.

+ */

+ mmu_idx = arm_v7m_mmu_idx_for_secstate(env, true);

+ oi = make_memop_idx(MO_LE, arm_to_core_mmu_idx(mmu_idx));

+ newpc = helper_le_ldul_mmu(env, frameptr, oi, 0);

+ newpsr = helper_le_ldul_mmu(env, frameptr + 4, oi, 0);

+

+ /* Consistency checks on new IPSR */

+ newpsr_exc = newpsr & XPSR_EXCP;

+ if (!((env->v7m.exception == 0 && newpsr_exc == 0) ||

+ (env->v7m.exception == 1 && newpsr_exc != 0))) {

+ /* Pend the fault and tell our caller to take it */

+ env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;

+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE,

+ env->v7m.secure);

+ qemu_log_mask(CPU_LOG_INT,

+ "...taking INVPC UsageFault: "

+ "IPSR consistency check failed\n");

+ return false;

+ }

+

+ *frame_sp_p = frameptr + 8;

+ }

+

+ /* This invalidates frame_sp_p */

+ switch_v7m_security_state(env, true);

+ env->v7m.exception = newpsr_exc;

+ env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK;

+ if (newpsr & XPSR_SFPA) {

+ env->v7m.control[M_REG_S] |= R_V7M_CONTROL_SFPA_MASK;

+ }

+ xpsr_write(env, 0, XPSR_IT);

+ env->thumb = newpc & 1;

+ env->regs[15] = newpc & ~1;

+

+ qemu_log_mask(CPU_LOG_INT, "...function return successful\n");

+ return true;

+}

+

static void arm_log_exception(int idx)

{

if (qemu_loglevel_mask(CPU_LOG_INT)) {

@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)

case EXCP_IRQ:

break;

case EXCP_EXCEPTION_EXIT:

- do_v7m_exception_exit(cpu);

- return;

+ if (env->regs[15] < EXC_RETURN_MIN_MAGIC) {

+ /* Must be v8M security extension function return */

+ assert(env->regs[15] >= FNC_RETURN_MIN_MAGIC);

+ assert(arm_feature(env, ARM_FEATURE_M_SECURITY));

+ if (do_v7m_function_return(cpu)) {

+ return;

+ }

+ } else {

+ do_v7m_exception_exit(cpu);

+ return;

+ }

+ break;

default:

cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);

return; /* Never happens. Keep compiler happy. */

diff --git a/target/arm/translate.c b/target/arm/translate.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate.c

+++ b/target/arm/translate.c

@@ -XXX,XX +XXX,XX @@ static inline void gen_bx_excret(DisasContext *s, TCGv_i32 var)

* s->base.is_jmp that we need to do the rest of the work later.

*/

gen_bx(s, var);

- if (s->v7m_handler_mode && arm_dc_feature(s, ARM_FEATURE_M)) {

+ if (arm_dc_feature(s, ARM_FEATURE_M_SECURITY) ||

+ (s->v7m_handler_mode && arm_dc_feature(s, ARM_FEATURE_M))) {

s->base.is_jmp = DISAS_BX_EXCRET;

}

}

@@ -XXX,XX +XXX,XX @@ static inline void gen_bx_excret_final_code(DisasContext *s)

{

/* Generate the code to finish possible exception return and end the TB */

TCGLabel *excret_label = gen_new_label();

+ uint32_t min_magic;

+

+ if (arm_dc_feature(s, ARM_FEATURE_M_SECURITY)) {

+ /* Covers FNC_RETURN and EXC_RETURN magic */

+ min_magic = FNC_RETURN_MIN_MAGIC;

+ } else {

+ /* EXC_RETURN magic only */

+ min_magic = EXC_RETURN_MIN_MAGIC;

+ }

/* Is the new PC value in the magic range indicating exception return? */

- tcg_gen_brcondi_i32(TCG_COND_GEU, cpu_R[15], 0xff000000, excret_label);

+ tcg_gen_brcondi_i32(TCG_COND_GEU, cpu_R[15], min_magic, excret_label);

/* No: end the TB as we would for a DISAS_JMP */

if (is_singlestepping(s)) {

gen_singlestep_exception(s);

--

2.7.4

The code which implements the Thumb1 split BL/BLX instructions

is guarded by a check on "not M or THUMB2". All we really need

to check here is "not THUMB2" (and we assume that elsewhere too,

eg in the ARCH(6T2) test that UNDEFs the Thumb2 insns).

This doesn't change behaviour because all M profile cores

have Thumb2 and so ARM_FEATURE_M implies ARM_FEATURE_THUMB2.

(v6M implements a very restricted subset of Thumb2, but we

can cross that bridge when we get to it with appropriate

feature bits.)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 1507556919-24992-6-git-send-email-peter.maydell@linaro.org

target/arm/translate.c | 3 +--

diff --git a/target/arm/translate.c b/target/arm/translate.c

--- a/target/arm/translate.c

+++ b/target/arm/translate.c

@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw

int conds;

int logic_cc;

- if (!(arm_dc_feature(s, ARM_FEATURE_THUMB2)

- || arm_dc_feature(s, ARM_FEATURE_M))) {

+ if (!arm_dc_feature(s, ARM_FEATURE_THUMB2)) {

/* Thumb-1 cores may need to treat bl and blx as a pair of

16-bit instructions to get correct prefetch abort behavior. */

insn = insn_hw1;

Refactor the Thumb decode to do the loads of the instruction words at

the top level rather than only loading the second half of a 32-bit

Thumb insn in the middle of the decode.

This is simple apart from the awkward case of Thumb1, where the

BL/BLX prefix and suffix instructions live in what in Thumb2 is the

32-bit insn space. To handle these we decode enough to identify

whether we're looking at a prefix/suffix that we handle as a 16 bit

insn, or a prefix that we're going to merge with the following suffix

to consider as a 32 bit insn. The translation of the 16 bit cases

then moves from disas_thumb2_insn() to disas_thumb_insn().

The refactoring has the benefit that we don't need to pass the

CPUARMState* down into the decoder code any more, but the major

reason for doing this is that some Thumb instructions must be always

unconditional regardless of the IT state bits, so we need to know the

whole insn before we emit the "skip this insn if the IT bits and cond

state tell us to" code. (The always unconditional insns are BKPT,

HLT and SG; the last of these is 32 bits.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 1507556919-24992-7-git-send-email-peter.maydell@linaro.org

---

target/arm/translate.c | 178 ++++++++++++++++++++++++++++++-------------------

1 file changed, 108 insertions(+), 70 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate.c

+++ b/target/arm/translate.c

@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)

}

}

+static bool thumb_insn_is_16bit(DisasContext *s, uint32_t insn)

+{

+ /* Return true if this is a 16 bit instruction. We must be precise

+ * about this (matching the decode). We assume that s->pc still

+ * points to the first 16 bits of the insn.

+ */

+ if ((insn >> 11) < 0x1d) {

+ /* Definitely a 16-bit instruction */

+ return true;

+ }

+

+ /* Top five bits 0b11101 / 0b11110 / 0b11111 : this is the

+ * first half of a 32-bit Thumb insn. Thumb-1 cores might

+ * end up actually treating this as two 16-bit insns, though,

+ * if it's half of a bl/blx pair that might span a page boundary.

+ */

+ if (arm_dc_feature(s, ARM_FEATURE_THUMB2)) {

+ /* Thumb2 cores (including all M profile ones) always treat

+ * 32-bit insns as 32-bit.

+ */

+ return false;

+ }

+

+ if ((insn >> 11) == 0x1e && (s->pc < s->next_page_start - 3)) {

+ /* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix, and the suffix

+ * is not on the next page; we merge this into a 32-bit

+ * insn.

+ */

+ return false;

+ }

+ /* 0b1110_1xxx_xxxx_xxxx : BLX suffix (or UNDEF);

+ * 0b1111_1xxx_xxxx_xxxx : BL suffix;

+ * 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix on the end of a page

+ * -- handle as single 16 bit insn

+ */

+ return true;

+}

+

/* Return true if this is a Thumb-2 logical op. */

static int

thumb2_logic_op(int op)

@@ -XXX,XX +XXX,XX @@ gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out,

/* Translate a 32-bit thumb instruction. Returns nonzero if the instruction

is not legal. */

-static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw1)

+static int disas_thumb2_insn(DisasContext *s, uint32_t insn)

{

- uint32_t insn, imm, shift, offset;

+ uint32_t imm, shift, offset;

uint32_t rd, rn, rm, rs;

TCGv_i32 tmp;

TCGv_i32 tmp2;

@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw

int conds;

int logic_cc;

- if (!arm_dc_feature(s, ARM_FEATURE_THUMB2)) {

- /* Thumb-1 cores may need to treat bl and blx as a pair of

- 16-bit instructions to get correct prefetch abort behavior. */

- insn = insn_hw1;

- if ((insn & (1 << 12)) == 0) {

- ARCH(5);

- /* Second half of blx. */

- offset = ((insn & 0x7ff) << 1);

- tmp = load_reg(s, 14);

- tcg_gen_addi_i32(tmp, tmp, offset);

- tcg_gen_andi_i32(tmp, tmp, 0xfffffffc);

-

- tmp2 = tcg_temp_new_i32();

- tcg_gen_movi_i32(tmp2, s->pc | 1);

- store_reg(s, 14, tmp2);

- gen_bx(s, tmp);

- return 0;

- }

- if (insn & (1 << 11)) {

- /* Second half of bl. */

- offset = ((insn & 0x7ff) << 1) | 1;

- tmp = load_reg(s, 14);

- tcg_gen_addi_i32(tmp, tmp, offset);

-

- tmp2 = tcg_temp_new_i32();

- tcg_gen_movi_i32(tmp2, s->pc | 1);

- store_reg(s, 14, tmp2);

- gen_bx(s, tmp);

- return 0;

- }

- if ((s->pc & ~TARGET_PAGE_MASK) == 0) {

- /* Instruction spans a page boundary. Implement it as two

- 16-bit instructions in case the second half causes an

- prefetch abort. */

- offset = ((int32_t)insn << 21) >> 9;

- tcg_gen_movi_i32(cpu_R[14], s->pc + 2 + offset);

- return 0;

- }

- /* Fall through to 32-bit decode. */

- }

-

- insn = arm_lduw_code(env, s->pc, s->sctlr_b);

- s->pc += 2;

- insn |= (uint32_t)insn_hw1 << 16;

-

+ /* The only 32 bit insn that's allowed for Thumb1 is the combined

+ * BL/BLX prefix and suffix.

+ */

if ((insn & 0xf800e800) != 0xf000e800) {

ARCH(6T2);

}

@@ -XXX,XX +XXX,XX @@ illegal_op:

return 1;

}

-static void disas_thumb_insn(CPUARMState *env, DisasContext *s)

+static void disas_thumb_insn(DisasContext *s, uint32_t insn)

{

- uint32_t val, insn, op, rm, rn, rd, shift, cond;

+ uint32_t val, op, rm, rn, rd, shift, cond;

int32_t offset;

int i;

TCGv_i32 tmp;

TCGv_i32 tmp2;

TCGv_i32 addr;

- if (s->condexec_mask) {

- cond = s->condexec_cond;

- if (cond != 0x0e) { /* Skip conditional when condition is AL. */

- s->condlabel = gen_new_label();

- arm_gen_test_cc(cond ^ 1, s->condlabel);

- s->condjmp = 1;

- }

- }

-

- insn = arm_lduw_code(env, s->pc, s->sctlr_b);

- s->pc += 2;

-

switch (insn >> 12) {

case 0: case 1:

@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)

case 14:

if (insn & (1 << 11)) {

- if (disas_thumb2_insn(env, s, insn))

- goto undef32;

+ /* thumb_insn_is_16bit() ensures we can't get here for

+ * a Thumb2 CPU, so this must be a thumb1 split BL/BLX:

+ * 0b1110_1xxx_xxxx_xxxx : BLX suffix (or UNDEF)

+ */

+ assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2));

+ ARCH(5);

+ offset = ((insn & 0x7ff) << 1);

+ tmp = load_reg(s, 14);

+ tcg_gen_addi_i32(tmp, tmp, offset);

+ tcg_gen_andi_i32(tmp, tmp, 0xfffffffc);

+

+ tmp2 = tcg_temp_new_i32();

+ tcg_gen_movi_i32(tmp2, s->pc | 1);

+ store_reg(s, 14, tmp2);

+ gen_bx(s, tmp);

break;

}

/* unconditional branch */

@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)

break;

case 15:

- if (disas_thumb2_insn(env, s, insn))

- goto undef32;

+ /* thumb_insn_is_16bit() ensures we can't get here for

+ * a Thumb2 CPU, so this must be a thumb1 split BL/BLX.

+ */

+ assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2));

+

+ if (insn & (1 << 11)) {

+ /* 0b1111_1xxx_xxxx_xxxx : BL suffix */

+ offset = ((insn & 0x7ff) << 1) | 1;

+ tmp = load_reg(s, 14);

+ tcg_gen_addi_i32(tmp, tmp, offset);

+

+ tmp2 = tcg_temp_new_i32();

+ tcg_gen_movi_i32(tmp2, s->pc | 1);

+ store_reg(s, 14, tmp2);

+ gen_bx(s, tmp);

+ } else {

+ /* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix */

+ uint32_t uoffset = ((int32_t)insn << 21) >> 9;

+

+ tcg_gen_movi_i32(cpu_R[14], s->pc + 2 + uoffset);

+ }

break;

}

return;

-undef32:

- gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),

- default_exception_el(s));

- return;

illegal_op:

undef:

gen_exception_insn(s, 2, EXCP_UDEF, syn_uncategorized(),

@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)

{

DisasContext *dc = container_of(dcbase, DisasContext, base);

CPUARMState *env = cpu->env_ptr;

+ uint32_t insn;

+ bool is_16bit;

if (arm_pre_translate_insn(dc)) {

return;

}

- disas_thumb_insn(env, dc);

+ insn = arm_lduw_code(env, dc->pc, dc->sctlr_b);

+ is_16bit = thumb_insn_is_16bit(dc, insn);

+ dc->pc += 2;

+ if (!is_16bit) {

+ uint32_t insn2 = arm_lduw_code(env, dc->pc, dc->sctlr_b);

+

+ insn = insn << 16 | insn2;

+ dc->pc += 2;

+ }

+

+ if (dc->condexec_mask) {

+ uint32_t cond = dc->condexec_cond;

+

+ if (cond != 0x0e) { /* Skip conditional when condition is AL. */

+ dc->condlabel = gen_new_label();

+ arm_gen_test_cc(cond ^ 1, dc->condlabel);

+ dc->condjmp = 1;

+ }

+ }

+

+ if (is_16bit) {

+ disas_thumb_insn(dc, insn);

+ } else {

+ disas_thumb2_insn(dc, insn);

+ }

/* Advance the Thumb condexec condition. */

if (dc->condexec_mask) {

--

2.7.4

A few Thumb instructions are always unconditional even inside an

IT block (as opposed to being UNPREDICTABLE if used inside an

IT block): BKPT, the v8M SG instruction, and the A profile

HLT (debug halt) instruction.

This means we need to suppress the jump-over-instruction-on-condfail

code generation (though the IT state still advances as usual and

subsequent insns in the IT block may be conditional).

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 1507556919-24992-9-git-send-email-peter.maydell@linaro.org

target/arm/translate.c | 48 +++++++++++++++++++++++++++++++++++++++++++++++-

1 file changed, 47 insertions(+), 1 deletion(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c

--- a/target/arm/translate.c

+++ b/target/arm/translate.c

@@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)

in init_disas_context by adjusting max_insns. */

}

+static bool thumb_insn_is_unconditional(DisasContext *s, uint32_t insn)

+{

+ /* Return true if this Thumb insn is always unconditional,

+ * even inside an IT block. This is true of only a very few

+ * instructions: BKPT, HLT, and SG.

+ *

+ * A larger class of instructions are UNPREDICTABLE if used

+ * inside an IT block; we do not need to detect those here, because

+ * what we do by default (perform the cc check and update the IT

+ * bits state machine) is a permitted CONSTRAINED UNPREDICTABLE

+ * choice for those situations.

+ *

+ * insn is either a 16-bit or a 32-bit instruction; the two are

+ * distinguishable because for the 16-bit case the top 16 bits

+ * are zeroes, and that isn't a valid 32-bit encoding.

+ */

+ if ((insn & 0xffffff00) == 0xbe00) {

+ /* BKPT */

+ return true;

+ }

+

+ if ((insn & 0xffffffc0) == 0xba80 && arm_dc_feature(s, ARM_FEATURE_V8) &&

+ !arm_dc_feature(s, ARM_FEATURE_M)) {

+ /* HLT: v8A only. This is unconditional even when it is going to

+ * UNDEF; see the v8A ARM ARM DDI0487B.a H3.3.

+ * For v7 cores this was a plain old undefined encoding and so

+ * honours its cc check. (We might be using the encoding as

+ * a semihosting trap, but we don't change the cc check behaviour

+ * on that account, because a debugger connected to a real v7A

+ * core and emulating semihosting traps by catching the UNDEF

+ * exception would also only see cases where the cc check passed.

+ * No guest code should be trying to do a HLT semihosting trap

+ * in an IT block anyway.

+ */

+ return true;

+ }

+

+ if (insn == 0xe97fe97f && arm_dc_feature(s, ARM_FEATURE_V8) &&

+ arm_dc_feature(s, ARM_FEATURE_M)) {

+ /* SG: v8M only */

+ return true;

+ }

+

+ return false;

+}

+

static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)

{

DisasContext *dc = container_of(dcbase, DisasContext, base);

@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)

dc->pc += 2;

- if (dc->condexec_mask) {

+ if (dc->condexec_mask && !thumb_insn_is_unconditional(dc, insn)) {

uint32_t cond = dc->condexec_cond;

if (cond != 0x0e) { /* Skip conditional when condition is AL. */