1 | Target-arm queue... | 1 | Hi; here's the latest round of arm patches. I have included also |
---|---|---|---|
2 | my patchset for the RTC devices to avoid keeping time_t and | ||
3 | time_t diffs in 32-bit variables. | ||
2 | 4 | ||
3 | thanks | 5 | thanks |
4 | -- PMM | 6 | -- PMM |
5 | 7 | ||
6 | The following changes since commit 735286a4f88255e1463d42ce28d8d14181fd32d4: | 8 | The following changes since commit 156618d9ea67f2f2e31d9dedd97f2dcccbe6808c: |
7 | 9 | ||
8 | Merge remote-tracking branch 'remotes/juanquintela/tags/migration/20170613' into staging (2017-06-13 13:51:29 +0100) | 10 | Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2023-08-30 09:20:27 -0400) |
9 | 11 | ||
10 | are available in the git repository at: | 12 | are available in the Git repository at: |
11 | 13 | ||
12 | git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170613 | 14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230831 |
13 | 15 | ||
14 | for you to fetch changes up to 252a7a6a968c279a4636a86b0559ba3a930a90b5: | 16 | for you to fetch changes up to e73b8bb8a3e9a162f70e9ffbf922d4fafc96bbfb: |
15 | 17 | ||
16 | hw/intc/arm_gicv3_its: Allow save/restore (2017-06-13 14:57:01 +0100) | 18 | hw/arm: Set number of MPU regions correctly for an505, an521, an524 (2023-08-31 11:07:02 +0100) |
17 | 19 | ||
18 | ---------------------------------------------------------------- | 20 | ---------------------------------------------------------------- |
19 | target-arm queue: | 21 | target-arm queue: |
20 | * vITS: Support save/restore | 22 | * Some of the preliminary patches for Cortex-A710 support |
21 | * timer/aspeed: Fix timer enablement when reload is not set | 23 | * i.MX7 and i.MX6UL refactoring |
22 | * aspped: add temperature sensor device | 24 | * Implement SRC device for i.MX7 |
23 | * timer.h: Provide better monotonic time on ARM hosts | 25 | * Catch illegal-exception-return from EL3 with bad NSE/NS |
24 | * exynos4210: various cleanups | 26 | * Use 64-bit offsets for holding time_t differences in RTC devices |
25 | * exynos4210: support system poweroff | 27 | * Model correct number of MPU regions for an505, an521, an524 boards |
26 | 28 | ||
27 | ---------------------------------------------------------------- | 29 | ---------------------------------------------------------------- |
28 | Cédric Le Goater (3): | 30 | Alex Bennée (1): |
29 | hw/misc: add a TMP42{1, 2, 3} device model | 31 | target/arm: properly document FEAT_CRC32 |
30 | aspeed: add a temp sensor device on I2C bus 3 | ||
31 | timer/aspeed: fix timer enablement when a reload is not set | ||
32 | 32 | ||
33 | Eric Auger (4): | 33 | Jean-Christophe Dubois (6): |
34 | kvm-all: Pass an error object to kvm_device_access | 34 | Remove i.MX7 IOMUX GPR device from i.MX6UL |
35 | hw/intc/arm_gicv3_its: Implement state save/restore | 35 | Refactor i.MX6UL processor code |
36 | hw/intc/arm_gicv3_kvm: Implement pending table save | 36 | Add i.MX6UL missing devices. |
37 | hw/intc/arm_gicv3_its: Allow save/restore | 37 | Refactor i.MX7 processor code |
38 | Add i.MX7 missing TZ devices and memory regions | ||
39 | Add i.MX7 SRC device implementation | ||
38 | 40 | ||
39 | Krzysztof Kozlowski (9): | 41 | Peter Maydell (8): |
40 | hw/intc/exynos4210_gic: Use more meaningful name for local variable | 42 | target/arm: Catch illegal-exception-return from EL3 with bad NSE/NS |
41 | hw/timer/exynos4210_mct: Fix checkpatch style errors | 43 | hw/rtc/m48t59: Use 64-bit arithmetic in set_alarm() |
42 | hw/timer/exynos4210_mct: Cleanup indentation and empty new lines | 44 | hw/rtc/twl92230: Use int64_t for sec_offset and alm_sec |
43 | hw/timer/exynos4210_mct: Remove unused defines | 45 | hw/rtc/aspeed_rtc: Use 64-bit offset for holding time_t difference |
44 | hw/arm/exynos: Move DRAM initialization next boards | 46 | rtc: Use time_t for passing and returning time offsets |
45 | hw/arm/exynos: Declare local variables in some order | 47 | target/arm: Do all "ARM_FEATURE_X implies Y" checks in post_init |
46 | hw/arm/exynos: Use type define instead of hard-coded a9mpcore_priv string | 48 | hw/arm/armv7m: Add mpu-ns-regions and mpu-s-regions properties |
47 | hw/intc/exynos4210_gic: Constify array of combiner interrupts | 49 | hw/arm: Set number of MPU regions correctly for an505, an521, an524 |
48 | hw/misc/exynos4210_pmu: Add support for system poweroff | ||
49 | 50 | ||
50 | Pranith Kumar (1): | 51 | Richard Henderson (9): |
51 | timer.h: Provide better monotonic time | 52 | target/arm: Reduce dcz_blocksize to uint8_t |
53 | target/arm: Allow cpu to configure GM blocksize | ||
54 | target/arm: Support more GM blocksizes | ||
55 | target/arm: When tag memory is not present, set MTE=1 | ||
56 | target/arm: Introduce make_ccsidr64 | ||
57 | target/arm: Apply access checks to neoverse-n1 special registers | ||
58 | target/arm: Apply access checks to neoverse-v1 special registers | ||
59 | target/arm: Suppress FEAT_TRBE (Trace Buffer Extension) | ||
60 | target/arm: Implement FEAT_HPDS2 as a no-op | ||
52 | 61 | ||
53 | hw/misc/Makefile.objs | 1 + | 62 | docs/system/arm/emulation.rst | 2 + |
54 | include/hw/arm/exynos4210.h | 5 +- | 63 | include/hw/arm/armsse.h | 5 + |
55 | include/hw/intc/arm_gicv3_its_common.h | 8 + | 64 | include/hw/arm/armv7m.h | 8 + |
56 | include/migration/vmstate.h | 2 + | 65 | include/hw/arm/fsl-imx6ul.h | 158 ++++++++++++++++--- |
57 | include/qemu/timer.h | 5 +- | 66 | include/hw/arm/fsl-imx7.h | 338 ++++++++++++++++++++++++++++++----------- |
58 | include/sysemu/kvm.h | 11 +- | 67 | include/hw/misc/imx7_src.h | 66 ++++++++ |
59 | hw/arm/aspeed.c | 9 + | 68 | include/hw/rtc/aspeed_rtc.h | 2 +- |
60 | hw/arm/exynos4210.c | 27 +-- | 69 | include/sysemu/rtc.h | 4 +- |
61 | hw/arm/exynos4_boards.c | 50 +++- | 70 | target/arm/cpregs.h | 2 + |
62 | hw/intc/arm_gic_kvm.c | 9 +- | 71 | target/arm/cpu.h | 5 +- |
63 | hw/intc/arm_gicv3_common.c | 1 + | 72 | target/arm/internals.h | 6 - |
64 | hw/intc/arm_gicv3_its_common.c | 12 +- | 73 | target/arm/tcg/translate.h | 2 + |
65 | hw/intc/arm_gicv3_its_kvm.c | 131 +++++++++-- | 74 | hw/arm/armsse.c | 16 ++ |
66 | hw/intc/arm_gicv3_kvm.c | 48 +++- | 75 | hw/arm/armv7m.c | 21 +++ |
67 | hw/intc/exynos4210_gic.c | 14 +- | 76 | hw/arm/fsl-imx6ul.c | 174 +++++++++++++-------- |
68 | hw/misc/exynos4210_pmu.c | 20 +- | 77 | hw/arm/fsl-imx7.c | 201 +++++++++++++++++++----- |
69 | hw/misc/tmp421.c | 402 +++++++++++++++++++++++++++++++++ | 78 | hw/arm/mps2-tz.c | 29 ++++ |
70 | hw/timer/aspeed_timer.c | 37 ++- | 79 | hw/misc/imx7_src.c | 276 +++++++++++++++++++++++++++++++++ |
71 | hw/timer/exynos4210_mct.c | 50 ++-- | 80 | hw/rtc/aspeed_rtc.c | 5 +- |
72 | kvm-all.c | 14 +- | 81 | hw/rtc/m48t59.c | 2 +- |
73 | default-configs/arm-softmmu.mak | 1 + | 82 | hw/rtc/twl92230.c | 4 +- |
74 | 21 files changed, 741 insertions(+), 116 deletions(-) | 83 | softmmu/rtc.c | 4 +- |
75 | create mode 100644 hw/misc/tmp421.c | 84 | target/arm/cpu.c | 207 ++++++++++++++----------- |
85 | target/arm/helper.c | 15 +- | ||
86 | target/arm/tcg/cpu32.c | 2 +- | ||
87 | target/arm/tcg/cpu64.c | 102 +++++++++---- | ||
88 | target/arm/tcg/helper-a64.c | 9 ++ | ||
89 | target/arm/tcg/mte_helper.c | 90 ++++++++--- | ||
90 | target/arm/tcg/translate-a64.c | 5 +- | ||
91 | hw/misc/meson.build | 1 + | ||
92 | hw/misc/trace-events | 4 + | ||
93 | 31 files changed, 1393 insertions(+), 372 deletions(-) | ||
94 | create mode 100644 include/hw/misc/imx7_src.h | ||
95 | create mode 100644 hw/misc/imx7_src.c | ||
76 | 96 | diff view generated by jsdifflib |
1 | From: Krzysztof Kozlowski <krzk@kernel.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
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2 | 2 | ||
3 | Use a define for a9mpcore_priv device type name instead of hard-coded | 3 | This value is only 4 bits wide. |
4 | string. | ||
5 | 4 | ||
6 | Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> | 5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
8 | Message-id: 20230811214031.171020-2-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 10 | --- |
10 | hw/arm/exynos4210.c | 3 ++- | 11 | target/arm/cpu.h | 3 ++- |
11 | 1 file changed, 2 insertions(+), 1 deletion(-) | 12 | 1 file changed, 2 insertions(+), 1 deletion(-) |
12 | 13 | ||
13 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | 14 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
14 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/hw/arm/exynos4210.c | 16 | --- a/target/arm/cpu.h |
16 | +++ b/hw/arm/exynos4210.c | 17 | +++ b/target/arm/cpu.h |
17 | @@ -XXX,XX +XXX,XX @@ | 18 | @@ -XXX,XX +XXX,XX @@ struct ArchCPU { |
18 | #include "qemu-common.h" | 19 | bool prop_lpa2; |
19 | #include "qemu/log.h" | 20 | |
20 | #include "cpu.h" | 21 | /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ |
21 | +#include "hw/cpu/a9mpcore.h" | 22 | - uint32_t dcz_blocksize; |
22 | #include "hw/boards.h" | 23 | + uint8_t dcz_blocksize; |
23 | #include "sysemu/sysemu.h" | 24 | + |
24 | #include "hw/sysbus.h" | 25 | uint64_t rvbar_prop; /* Property/input signals. */ |
25 | @@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem) | 26 | |
26 | } | 27 | /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ |
27 | |||
28 | /* Private memory region and Internal GIC */ | ||
29 | - dev = qdev_create(NULL, "a9mpcore_priv"); | ||
30 | + dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV); | ||
31 | qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS); | ||
32 | qdev_init_nofail(dev); | ||
33 | busdev = SYS_BUS_DEVICE(dev); | ||
34 | -- | 28 | -- |
35 | 2.7.4 | 29 | 2.34.1 |
36 | 30 | ||
37 | 31 | diff view generated by jsdifflib |
1 | From: Eric Auger <eric.auger@redhat.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
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2 | 2 | ||
3 | In some circumstances, we don't want to abort if the | 3 | Previously we hard-coded the blocksize with GMID_EL1_BS. |
4 | kvm_device_access fails. This will be the case during ITS | 4 | But the value we choose for -cpu max does not match the |
5 | migration, in case the ITS table save/restore fails because | 5 | value that cortex-a710 uses. |
6 | the guest did not program the vITS correctly. So let's pass an | 6 | |
7 | error object to the function and return the ioctl value. New | 7 | Mirror the way we handle dcz_blocksize. |
8 | callers will be able to make a decision upon this returned | 8 | |
9 | value. | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
10 | 10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | |
11 | Existing callers pass &error_abort which will cause the | 11 | Message-id: 20230811214031.171020-3-richard.henderson@linaro.org |
12 | function to abort on failure. | ||
13 | |||
14 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | ||
15 | Reviewed-by: Juan Quintela <quintela@redhat.com> | ||
16 | Reviewed-by: Peter Xu <peterx@redhat.com> | ||
17 | Message-id: 1497023553-18411-2-git-send-email-eric.auger@redhat.com | ||
18 | [PMM: wrapped long line] | ||
19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
20 | --- | 13 | --- |
21 | include/sysemu/kvm.h | 11 +++++++---- | 14 | target/arm/cpu.h | 2 ++ |
22 | hw/intc/arm_gic_kvm.c | 9 +++++---- | 15 | target/arm/internals.h | 6 ----- |
23 | hw/intc/arm_gicv3_its_kvm.c | 2 +- | 16 | target/arm/tcg/translate.h | 2 ++ |
24 | hw/intc/arm_gicv3_kvm.c | 14 +++++++------- | 17 | target/arm/helper.c | 11 +++++--- |
25 | kvm-all.c | 14 ++++++++------ | 18 | target/arm/tcg/cpu64.c | 1 + |
26 | 5 files changed, 28 insertions(+), 22 deletions(-) | 19 | target/arm/tcg/mte_helper.c | 46 ++++++++++++++++++++++------------ |
27 | 20 | target/arm/tcg/translate-a64.c | 5 ++-- | |
28 | diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h | 21 | 7 files changed, 45 insertions(+), 28 deletions(-) |
29 | index XXXXXXX..XXXXXXX 100644 | 22 | |
30 | --- a/include/sysemu/kvm.h | 23 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
31 | +++ b/include/sysemu/kvm.h | 24 | index XXXXXXX..XXXXXXX 100644 |
32 | @@ -XXX,XX +XXX,XX @@ int kvm_device_check_attr(int fd, uint32_t group, uint64_t attr); | 25 | --- a/target/arm/cpu.h |
33 | * @attr: the attribute of that group to set or get | 26 | +++ b/target/arm/cpu.h |
34 | * @val: pointer to a storage area for the value | 27 | @@ -XXX,XX +XXX,XX @@ struct ArchCPU { |
35 | * @write: true for set and false for get operation | 28 | |
36 | + * @errp: error object handle | 29 | /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ |
37 | * | 30 | uint8_t dcz_blocksize; |
38 | - * This function is not allowed to fail. Use kvm_device_check_attr() | 31 | + /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */ |
39 | - * in order to check for the availability of optional attributes. | 32 | + uint8_t gm_blocksize; |
40 | + * Returns: 0 on success | 33 | |
41 | + * < 0 on error | 34 | uint64_t rvbar_prop; /* Property/input signals. */ |
42 | + * Use kvm_device_check_attr() in order to check for the availability | 35 | |
43 | + * of optional attributes. | 36 | diff --git a/target/arm/internals.h b/target/arm/internals.h |
44 | */ | 37 | index XXXXXXX..XXXXXXX 100644 |
45 | -void kvm_device_access(int fd, int group, uint64_t attr, | 38 | --- a/target/arm/internals.h |
46 | - void *val, bool write); | 39 | +++ b/target/arm/internals.h |
47 | +int kvm_device_access(int fd, int group, uint64_t attr, | 40 | @@ -XXX,XX +XXX,XX @@ void arm_log_exception(CPUState *cs); |
48 | + void *val, bool write, Error **errp); | 41 | |
49 | 42 | #endif /* !CONFIG_USER_ONLY */ | |
50 | /** | 43 | |
51 | * kvm_create_device - create a KVM device for the device control API | 44 | -/* |
52 | diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c | 45 | - * The log2 of the words in the tag block, for GMID_EL1.BS. |
53 | index XXXXXXX..XXXXXXX 100644 | 46 | - * The is the maximum, 256 bytes, which manipulates 64-bits of tags. |
54 | --- a/hw/intc/arm_gic_kvm.c | 47 | - */ |
55 | +++ b/hw/intc/arm_gic_kvm.c | 48 | -#define GMID_EL1_BS 6 |
56 | @@ -XXX,XX +XXX,XX @@ static void kvm_gicd_access(GICState *s, int offset, int cpu, | 49 | - |
57 | uint32_t *val, bool write) | 50 | /* |
51 | * SVE predicates are 1/8 the size of SVE vectors, and cannot use | ||
52 | * the same simd_desc() encoding due to restrictions on size. | ||
53 | diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h | ||
54 | index XXXXXXX..XXXXXXX 100644 | ||
55 | --- a/target/arm/tcg/translate.h | ||
56 | +++ b/target/arm/tcg/translate.h | ||
57 | @@ -XXX,XX +XXX,XX @@ typedef struct DisasContext { | ||
58 | int8_t btype; | ||
59 | /* A copy of cpu->dcz_blocksize. */ | ||
60 | uint8_t dcz_blocksize; | ||
61 | + /* A copy of cpu->gm_blocksize. */ | ||
62 | + uint8_t gm_blocksize; | ||
63 | /* True if this page is guarded. */ | ||
64 | bool guarded_page; | ||
65 | /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ | ||
66 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
67 | index XXXXXXX..XXXXXXX 100644 | ||
68 | --- a/target/arm/helper.c | ||
69 | +++ b/target/arm/helper.c | ||
70 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_reginfo[] = { | ||
71 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 6, | ||
72 | .access = PL1_RW, .accessfn = access_mte, | ||
73 | .fieldoffset = offsetof(CPUARMState, cp15.gcr_el1) }, | ||
74 | - { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64, | ||
75 | - .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4, | ||
76 | - .access = PL1_R, .accessfn = access_aa64_tid5, | ||
77 | - .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS }, | ||
78 | { .name = "TCO", .state = ARM_CP_STATE_AA64, | ||
79 | .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7, | ||
80 | .type = ARM_CP_NO_RAW, | ||
81 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
82 | * then define only a RAZ/WI version of PSTATE.TCO. | ||
83 | */ | ||
84 | if (cpu_isar_feature(aa64_mte, cpu)) { | ||
85 | + ARMCPRegInfo gmid_reginfo = { | ||
86 | + .name = "GMID_EL1", .state = ARM_CP_STATE_AA64, | ||
87 | + .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4, | ||
88 | + .access = PL1_R, .accessfn = access_aa64_tid5, | ||
89 | + .type = ARM_CP_CONST, .resetvalue = cpu->gm_blocksize, | ||
90 | + }; | ||
91 | + define_one_arm_cp_reg(cpu, &gmid_reginfo); | ||
92 | define_arm_cp_regs(cpu, mte_reginfo); | ||
93 | define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); | ||
94 | } else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) { | ||
95 | diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c | ||
96 | index XXXXXXX..XXXXXXX 100644 | ||
97 | --- a/target/arm/tcg/cpu64.c | ||
98 | +++ b/target/arm/tcg/cpu64.c | ||
99 | @@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj) | ||
100 | cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ | ||
101 | cpu->dcz_blocksize = 7; /* 512 bytes */ | ||
102 | #endif | ||
103 | + cpu->gm_blocksize = 6; /* 256 bytes */ | ||
104 | |||
105 | cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ); | ||
106 | cpu->sme_vq.supported = SVE_VQ_POW2_MAP; | ||
107 | diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c | ||
108 | index XXXXXXX..XXXXXXX 100644 | ||
109 | --- a/target/arm/tcg/mte_helper.c | ||
110 | +++ b/target/arm/tcg/mte_helper.c | ||
111 | @@ -XXX,XX +XXX,XX @@ void HELPER(st2g_stub)(CPUARMState *env, uint64_t ptr) | ||
112 | } | ||
113 | } | ||
114 | |||
115 | -#define LDGM_STGM_SIZE (4 << GMID_EL1_BS) | ||
116 | - | ||
117 | uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr) | ||
58 | { | 118 | { |
59 | kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS, | 119 | int mmu_idx = cpu_mmu_index(env, false); |
60 | - KVM_VGIC_ATTR(offset, cpu), val, write); | 120 | uintptr_t ra = GETPC(); |
61 | + KVM_VGIC_ATTR(offset, cpu), val, write, &error_abort); | 121 | + int gm_bs = env_archcpu(env)->gm_blocksize; |
122 | + int gm_bs_bytes = 4 << gm_bs; | ||
123 | void *tag_mem; | ||
124 | |||
125 | - ptr = QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE); | ||
126 | + ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes); | ||
127 | |||
128 | /* Trap if accessing an invalid page. */ | ||
129 | tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_LOAD, | ||
130 | - LDGM_STGM_SIZE, MMU_DATA_LOAD, | ||
131 | - LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra); | ||
132 | + gm_bs_bytes, MMU_DATA_LOAD, | ||
133 | + gm_bs_bytes / (2 * TAG_GRANULE), ra); | ||
134 | |||
135 | /* The tag is squashed to zero if the page does not support tags. */ | ||
136 | if (!tag_mem) { | ||
137 | return 0; | ||
138 | } | ||
139 | |||
140 | - QEMU_BUILD_BUG_ON(GMID_EL1_BS != 6); | ||
141 | /* | ||
142 | - * We are loading 64-bits worth of tags. The ordering of elements | ||
143 | - * within the word corresponds to a 64-bit little-endian operation. | ||
144 | + * The ordering of elements within the word corresponds to | ||
145 | + * a little-endian operation. | ||
146 | */ | ||
147 | - return ldq_le_p(tag_mem); | ||
148 | + switch (gm_bs) { | ||
149 | + case 6: | ||
150 | + /* 256 bytes -> 16 tags -> 64 result bits */ | ||
151 | + return ldq_le_p(tag_mem); | ||
152 | + default: | ||
153 | + /* cpu configured with unsupported gm blocksize. */ | ||
154 | + g_assert_not_reached(); | ||
155 | + } | ||
62 | } | 156 | } |
63 | 157 | ||
64 | static void kvm_gicc_access(GICState *s, int offset, int cpu, | 158 | void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val) |
65 | uint32_t *val, bool write) | ||
66 | { | 159 | { |
67 | kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_REGS, | 160 | int mmu_idx = cpu_mmu_index(env, false); |
68 | - KVM_VGIC_ATTR(offset, cpu), val, write); | 161 | uintptr_t ra = GETPC(); |
69 | + KVM_VGIC_ATTR(offset, cpu), val, write, &error_abort); | 162 | + int gm_bs = env_archcpu(env)->gm_blocksize; |
163 | + int gm_bs_bytes = 4 << gm_bs; | ||
164 | void *tag_mem; | ||
165 | |||
166 | - ptr = QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE); | ||
167 | + ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes); | ||
168 | |||
169 | /* Trap if accessing an invalid page. */ | ||
170 | tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE, | ||
171 | - LDGM_STGM_SIZE, MMU_DATA_LOAD, | ||
172 | - LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra); | ||
173 | + gm_bs_bytes, MMU_DATA_LOAD, | ||
174 | + gm_bs_bytes / (2 * TAG_GRANULE), ra); | ||
175 | |||
176 | /* | ||
177 | * Tag store only happens if the page support tags, | ||
178 | @@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val) | ||
179 | return; | ||
180 | } | ||
181 | |||
182 | - QEMU_BUILD_BUG_ON(GMID_EL1_BS != 6); | ||
183 | /* | ||
184 | - * We are storing 64-bits worth of tags. The ordering of elements | ||
185 | - * within the word corresponds to a 64-bit little-endian operation. | ||
186 | + * The ordering of elements within the word corresponds to | ||
187 | + * a little-endian operation. | ||
188 | */ | ||
189 | - stq_le_p(tag_mem, val); | ||
190 | + switch (gm_bs) { | ||
191 | + case 6: | ||
192 | + stq_le_p(tag_mem, val); | ||
193 | + break; | ||
194 | + default: | ||
195 | + /* cpu configured with unsupported gm blocksize. */ | ||
196 | + g_assert_not_reached(); | ||
197 | + } | ||
70 | } | 198 | } |
71 | 199 | ||
72 | #define for_each_irq_reg(_ctr, _max_irq, _field_width) \ | 200 | void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val) |
73 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp) | 201 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c |
74 | if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0)) { | 202 | index XXXXXXX..XXXXXXX 100644 |
75 | uint32_t numirqs = s->num_irq; | 203 | --- a/target/arm/tcg/translate-a64.c |
76 | kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0, | 204 | +++ b/target/arm/tcg/translate-a64.c |
77 | - &numirqs, true); | 205 | @@ -XXX,XX +XXX,XX @@ static bool trans_STGM(DisasContext *s, arg_ldst_tag *a) |
78 | + &numirqs, true, &error_abort); | 206 | gen_helper_stgm(cpu_env, addr, tcg_rt); |
79 | } | 207 | } else { |
80 | /* Tell the kernel to complete VGIC initialization now */ | 208 | MMUAccessType acc = MMU_DATA_STORE; |
81 | if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, | 209 | - int size = 4 << GMID_EL1_BS; |
82 | KVM_DEV_ARM_VGIC_CTRL_INIT)) { | 210 | + int size = 4 << s->gm_blocksize; |
83 | kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, | 211 | |
84 | - KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true); | 212 | clean_addr = clean_data_tbi(s, addr); |
85 | + KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, | 213 | tcg_gen_andi_i64(clean_addr, clean_addr, -size); |
86 | + &error_abort); | 214 | @@ -XXX,XX +XXX,XX @@ static bool trans_LDGM(DisasContext *s, arg_ldst_tag *a) |
87 | } | 215 | gen_helper_ldgm(tcg_rt, cpu_env, addr); |
88 | } else if (ret != -ENODEV && ret != -ENOTSUP) { | 216 | } else { |
89 | error_setg_errno(errp, -ret, "error creating in-kernel VGIC"); | 217 | MMUAccessType acc = MMU_DATA_LOAD; |
90 | diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c | 218 | - int size = 4 << GMID_EL1_BS; |
91 | index XXXXXXX..XXXXXXX 100644 | 219 | + int size = 4 << s->gm_blocksize; |
92 | --- a/hw/intc/arm_gicv3_its_kvm.c | 220 | |
93 | +++ b/hw/intc/arm_gicv3_its_kvm.c | 221 | clean_addr = clean_data_tbi(s, addr); |
94 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_realize(DeviceState *dev, Error **errp) | 222 | tcg_gen_andi_i64(clean_addr, clean_addr, -size); |
95 | 223 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, | |
96 | /* explicit init of the ITS */ | 224 | dc->cp_regs = arm_cpu->cp_regs; |
97 | kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, | 225 | dc->features = env->features; |
98 | - KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true); | 226 | dc->dcz_blocksize = arm_cpu->dcz_blocksize; |
99 | + KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, &error_abort); | 227 | + dc->gm_blocksize = arm_cpu->gm_blocksize; |
100 | 228 | ||
101 | /* register the base address */ | 229 | #ifdef CONFIG_USER_ONLY |
102 | kvm_arm_register_device(&s->iomem_its_cntrl, -1, KVM_DEV_ARM_VGIC_GRP_ADDR, | 230 | /* In sve_probe_page, we assume TBI is enabled. */ |
103 | diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c | ||
104 | index XXXXXXX..XXXXXXX 100644 | ||
105 | --- a/hw/intc/arm_gicv3_kvm.c | ||
106 | +++ b/hw/intc/arm_gicv3_kvm.c | ||
107 | @@ -XXX,XX +XXX,XX @@ static inline void kvm_gicd_access(GICv3State *s, int offset, | ||
108 | { | ||
109 | kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS, | ||
110 | KVM_VGIC_ATTR(offset, 0), | ||
111 | - val, write); | ||
112 | + val, write, &error_abort); | ||
113 | } | ||
114 | |||
115 | static inline void kvm_gicr_access(GICv3State *s, int offset, int cpu, | ||
116 | @@ -XXX,XX +XXX,XX @@ static inline void kvm_gicr_access(GICv3State *s, int offset, int cpu, | ||
117 | { | ||
118 | kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_REDIST_REGS, | ||
119 | KVM_VGIC_ATTR(offset, s->cpu[cpu].gicr_typer), | ||
120 | - val, write); | ||
121 | + val, write, &error_abort); | ||
122 | } | ||
123 | |||
124 | static inline void kvm_gicc_access(GICv3State *s, uint64_t reg, int cpu, | ||
125 | @@ -XXX,XX +XXX,XX @@ static inline void kvm_gicc_access(GICv3State *s, uint64_t reg, int cpu, | ||
126 | { | ||
127 | kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, | ||
128 | KVM_VGIC_ATTR(reg, s->cpu[cpu].gicr_typer), | ||
129 | - val, write); | ||
130 | + val, write, &error_abort); | ||
131 | } | ||
132 | |||
133 | static inline void kvm_gic_line_level_access(GICv3State *s, int irq, int cpu, | ||
134 | @@ -XXX,XX +XXX,XX @@ static inline void kvm_gic_line_level_access(GICv3State *s, int irq, int cpu, | ||
135 | KVM_VGIC_ATTR(irq, s->cpu[cpu].gicr_typer) | | ||
136 | (VGIC_LEVEL_INFO_LINE_LEVEL << | ||
137 | KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT), | ||
138 | - val, write); | ||
139 | + val, write, &error_abort); | ||
140 | } | ||
141 | |||
142 | /* Loop through each distributor IRQ related register; since bits | ||
143 | @@ -XXX,XX +XXX,XX @@ static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri) | ||
144 | /* Initialize to actual HW supported configuration */ | ||
145 | kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, | ||
146 | KVM_VGIC_ATTR(ICC_CTLR_EL1, cpu->mp_affinity), | ||
147 | - &c->icc_ctlr_el1[GICV3_NS], false); | ||
148 | + &c->icc_ctlr_el1[GICV3_NS], false, &error_abort); | ||
149 | |||
150 | c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS]; | ||
151 | } | ||
152 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp) | ||
153 | } | ||
154 | |||
155 | kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, | ||
156 | - 0, &s->num_irq, true); | ||
157 | + 0, &s->num_irq, true, &error_abort); | ||
158 | |||
159 | /* Tell the kernel to complete VGIC initialization now */ | ||
160 | kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, | ||
161 | - KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true); | ||
162 | + KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, &error_abort); | ||
163 | |||
164 | kvm_arm_register_device(&s->iomem_dist, -1, KVM_DEV_ARM_VGIC_GRP_ADDR, | ||
165 | KVM_VGIC_V3_ADDR_TYPE_DIST, s->dev_fd); | ||
166 | diff --git a/kvm-all.c b/kvm-all.c | ||
167 | index XXXXXXX..XXXXXXX 100644 | ||
168 | --- a/kvm-all.c | ||
169 | +++ b/kvm-all.c | ||
170 | @@ -XXX,XX +XXX,XX @@ | ||
171 | #include "qemu/option.h" | ||
172 | #include "qemu/config-file.h" | ||
173 | #include "qemu/error-report.h" | ||
174 | +#include "qapi/error.h" | ||
175 | #include "hw/hw.h" | ||
176 | #include "hw/pci/msi.h" | ||
177 | #include "hw/pci/msix.h" | ||
178 | @@ -XXX,XX +XXX,XX @@ int kvm_device_check_attr(int dev_fd, uint32_t group, uint64_t attr) | ||
179 | return kvm_device_ioctl(dev_fd, KVM_HAS_DEVICE_ATTR, &attribute) ? 0 : 1; | ||
180 | } | ||
181 | |||
182 | -void kvm_device_access(int fd, int group, uint64_t attr, | ||
183 | - void *val, bool write) | ||
184 | +int kvm_device_access(int fd, int group, uint64_t attr, | ||
185 | + void *val, bool write, Error **errp) | ||
186 | { | ||
187 | struct kvm_device_attr kvmattr; | ||
188 | int err; | ||
189 | @@ -XXX,XX +XXX,XX @@ void kvm_device_access(int fd, int group, uint64_t attr, | ||
190 | write ? KVM_SET_DEVICE_ATTR : KVM_GET_DEVICE_ATTR, | ||
191 | &kvmattr); | ||
192 | if (err < 0) { | ||
193 | - error_report("KVM_%s_DEVICE_ATTR failed: %s", | ||
194 | - write ? "SET" : "GET", strerror(-err)); | ||
195 | - error_printf("Group %d attr 0x%016" PRIx64 "\n", group, attr); | ||
196 | - abort(); | ||
197 | + error_setg_errno(errp, -err, | ||
198 | + "KVM_%s_DEVICE_ATTR failed: Group %d " | ||
199 | + "attr 0x%016" PRIx64, | ||
200 | + write ? "SET" : "GET", group, attr); | ||
201 | } | ||
202 | + return err; | ||
203 | } | ||
204 | |||
205 | /* Return 1 on success, 0 on failure */ | ||
206 | -- | 231 | -- |
207 | 2.7.4 | 232 | 2.34.1 |
208 | |||
209 | diff view generated by jsdifflib |
1 | From: Cédric Le Goater <clg@kaod.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | When a timer is enabled before a reload value is set, the controller | 3 | Support all of the easy GM block sizes. |
4 | waits for a reload value to be set before starting decrementing. This | 4 | Use direct memory operations, since the pointers are aligned. |
5 | fix tries to cover that case by changing the timer expiry only when | ||
6 | a reload value is valid. | ||
7 | 5 | ||
8 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 6 | While BS=2 (16 bytes, 1 tag) is a legal setting, that requires |
9 | Reviewed-by: Andrew Jeffery <andrew@aj.id.au> | 7 | an atomic store of one nibble. This is not difficult, but there |
10 | Message-id: 1496739312-32304-1-git-send-email-clg@kaod.org | 8 | is also no point in supporting it until required. |
9 | |||
10 | Note that cortex-a710 sets GM blocksize to match its cacheline | ||
11 | size of 64 bytes. I expect many implementations will also | ||
12 | match the cacheline, which makes 16 bytes very unlikely. | ||
13 | |||
14 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
16 | Message-id: 20230811214031.171020-4-richard.henderson@linaro.org | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 18 | --- |
13 | hw/timer/aspeed_timer.c | 37 +++++++++++++++++++++++++++++-------- | 19 | target/arm/cpu.c | 18 +++++++++--- |
14 | 1 file changed, 29 insertions(+), 8 deletions(-) | 20 | target/arm/tcg/mte_helper.c | 56 +++++++++++++++++++++++++++++++------ |
21 | 2 files changed, 62 insertions(+), 12 deletions(-) | ||
15 | 22 | ||
16 | diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c | 23 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
17 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/hw/timer/aspeed_timer.c | 25 | --- a/target/arm/cpu.c |
19 | +++ b/hw/timer/aspeed_timer.c | 26 | +++ b/target/arm/cpu.c |
20 | @@ -XXX,XX +XXX,XX @@ static uint64_t calculate_next(struct AspeedTimer *t) | 27 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
21 | next = seq[1]; | 28 | ID_PFR1, VIRTUALIZATION, 0); |
22 | } else if (now < seq[2]) { | ||
23 | next = seq[2]; | ||
24 | - } else { | ||
25 | + } else if (t->reload) { | ||
26 | reload_ns = muldiv64(t->reload, NANOSECONDS_PER_SECOND, rate); | ||
27 | t->start = now - ((now - t->start) % reload_ns); | ||
28 | + } else { | ||
29 | + /* no reload value, return 0 */ | ||
30 | + break; | ||
31 | } | ||
32 | } | 29 | } |
33 | 30 | ||
34 | return next; | 31 | + if (cpu_isar_feature(aa64_mte, cpu)) { |
35 | } | 32 | + /* |
36 | 33 | + * The architectural range of GM blocksize is 2-6, however qemu | |
37 | +static void aspeed_timer_mod(AspeedTimer *t) | 34 | + * doesn't support blocksize of 2 (see HELPER(ldgm)). |
38 | +{ | ||
39 | + uint64_t next = calculate_next(t); | ||
40 | + if (next) { | ||
41 | + timer_mod(&t->timer, next); | ||
42 | + } | ||
43 | +} | ||
44 | + | ||
45 | static void aspeed_timer_expire(void *opaque) | ||
46 | { | ||
47 | AspeedTimer *t = opaque; | ||
48 | @@ -XXX,XX +XXX,XX @@ static void aspeed_timer_expire(void *opaque) | ||
49 | qemu_set_irq(t->irq, t->level); | ||
50 | } | ||
51 | |||
52 | - timer_mod(&t->timer, calculate_next(t)); | ||
53 | + aspeed_timer_mod(t); | ||
54 | } | ||
55 | |||
56 | static uint64_t aspeed_timer_get_value(AspeedTimer *t, int reg) | ||
57 | @@ -XXX,XX +XXX,XX @@ static void aspeed_timer_set_value(AspeedTimerCtrlState *s, int timer, int reg, | ||
58 | uint32_t value) | ||
59 | { | ||
60 | AspeedTimer *t; | ||
61 | + uint32_t old_reload; | ||
62 | |||
63 | trace_aspeed_timer_set_value(timer, reg, value); | ||
64 | t = &s->timers[timer]; | ||
65 | switch (reg) { | ||
66 | + case TIMER_REG_RELOAD: | ||
67 | + old_reload = t->reload; | ||
68 | + t->reload = value; | ||
69 | + | ||
70 | + /* If the reload value was not previously set, or zero, and | ||
71 | + * the current value is valid, try to start the timer if it is | ||
72 | + * enabled. | ||
73 | + */ | 35 | + */ |
74 | + if (old_reload || !t->reload) { | 36 | + if (tcg_enabled()) { |
75 | + break; | 37 | + assert(cpu->gm_blocksize >= 3 && cpu->gm_blocksize <= 6); |
76 | + } | 38 | + } |
77 | + | 39 | + |
78 | case TIMER_REG_STATUS: | 40 | #ifndef CONFIG_USER_ONLY |
79 | if (timer_enabled(t)) { | 41 | - if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) { |
80 | uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | 42 | /* |
81 | @@ -XXX,XX +XXX,XX @@ static void aspeed_timer_set_value(AspeedTimerCtrlState *s, int timer, int reg, | 43 | * Disable the MTE feature bits if we do not have tag-memory |
82 | uint32_t rate = calculate_rate(t); | 44 | * provided by the machine. |
83 | 45 | */ | |
84 | t->start += muldiv64(delta, NANOSECONDS_PER_SECOND, rate); | 46 | - cpu->isar.id_aa64pfr1 = |
85 | - timer_mod(&t->timer, calculate_next(t)); | 47 | - FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); |
86 | + aspeed_timer_mod(t); | 48 | - } |
87 | } | 49 | + if (cpu->tag_memory == NULL) { |
88 | break; | 50 | + cpu->isar.id_aa64pfr1 = |
89 | - case TIMER_REG_RELOAD: | 51 | + FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); |
90 | - t->reload = value; | 52 | + } |
91 | - break; | 53 | #endif |
92 | case TIMER_REG_MATCH_FIRST: | 54 | + } |
93 | case TIMER_REG_MATCH_SECOND: | 55 | |
94 | t->match[reg - 2] = value; | 56 | if (tcg_enabled()) { |
95 | if (timer_enabled(t)) { | 57 | /* |
96 | - timer_mod(&t->timer, calculate_next(t)); | 58 | diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c |
97 | + aspeed_timer_mod(t); | 59 | index XXXXXXX..XXXXXXX 100644 |
98 | } | 60 | --- a/target/arm/tcg/mte_helper.c |
61 | +++ b/target/arm/tcg/mte_helper.c | ||
62 | @@ -XXX,XX +XXX,XX @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr) | ||
63 | int gm_bs = env_archcpu(env)->gm_blocksize; | ||
64 | int gm_bs_bytes = 4 << gm_bs; | ||
65 | void *tag_mem; | ||
66 | + uint64_t ret; | ||
67 | + int shift; | ||
68 | |||
69 | ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes); | ||
70 | |||
71 | @@ -XXX,XX +XXX,XX @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr) | ||
72 | |||
73 | /* | ||
74 | * The ordering of elements within the word corresponds to | ||
75 | - * a little-endian operation. | ||
76 | + * a little-endian operation. Computation of shift comes from | ||
77 | + * | ||
78 | + * index = address<LOG2_TAG_GRANULE+3:LOG2_TAG_GRANULE> | ||
79 | + * data<index*4+3:index*4> = tag | ||
80 | + * | ||
81 | + * Because of the alignment of ptr above, BS=6 has shift=0. | ||
82 | + * All memory operations are aligned. Defer support for BS=2, | ||
83 | + * requiring insertion or extraction of a nibble, until we | ||
84 | + * support a cpu that requires it. | ||
85 | */ | ||
86 | switch (gm_bs) { | ||
87 | + case 3: | ||
88 | + /* 32 bytes -> 2 tags -> 8 result bits */ | ||
89 | + ret = *(uint8_t *)tag_mem; | ||
90 | + break; | ||
91 | + case 4: | ||
92 | + /* 64 bytes -> 4 tags -> 16 result bits */ | ||
93 | + ret = cpu_to_le16(*(uint16_t *)tag_mem); | ||
94 | + break; | ||
95 | + case 5: | ||
96 | + /* 128 bytes -> 8 tags -> 32 result bits */ | ||
97 | + ret = cpu_to_le32(*(uint32_t *)tag_mem); | ||
98 | + break; | ||
99 | case 6: | ||
100 | /* 256 bytes -> 16 tags -> 64 result bits */ | ||
101 | - return ldq_le_p(tag_mem); | ||
102 | + return cpu_to_le64(*(uint64_t *)tag_mem); | ||
103 | default: | ||
104 | - /* cpu configured with unsupported gm blocksize. */ | ||
105 | + /* | ||
106 | + * CPU configured with unsupported/invalid gm blocksize. | ||
107 | + * This is detected early in arm_cpu_realizefn. | ||
108 | + */ | ||
109 | g_assert_not_reached(); | ||
110 | } | ||
111 | + shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4; | ||
112 | + return ret << shift; | ||
113 | } | ||
114 | |||
115 | void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val) | ||
116 | @@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val) | ||
117 | int gm_bs = env_archcpu(env)->gm_blocksize; | ||
118 | int gm_bs_bytes = 4 << gm_bs; | ||
119 | void *tag_mem; | ||
120 | + int shift; | ||
121 | |||
122 | ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes); | ||
123 | |||
124 | @@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val) | ||
125 | return; | ||
126 | } | ||
127 | |||
128 | - /* | ||
129 | - * The ordering of elements within the word corresponds to | ||
130 | - * a little-endian operation. | ||
131 | - */ | ||
132 | + /* See LDGM for comments on BS and on shift. */ | ||
133 | + shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4; | ||
134 | + val >>= shift; | ||
135 | switch (gm_bs) { | ||
136 | + case 3: | ||
137 | + /* 32 bytes -> 2 tags -> 8 result bits */ | ||
138 | + *(uint8_t *)tag_mem = val; | ||
139 | + break; | ||
140 | + case 4: | ||
141 | + /* 64 bytes -> 4 tags -> 16 result bits */ | ||
142 | + *(uint16_t *)tag_mem = cpu_to_le16(val); | ||
143 | + break; | ||
144 | + case 5: | ||
145 | + /* 128 bytes -> 8 tags -> 32 result bits */ | ||
146 | + *(uint32_t *)tag_mem = cpu_to_le32(val); | ||
147 | + break; | ||
148 | case 6: | ||
149 | - stq_le_p(tag_mem, val); | ||
150 | + /* 256 bytes -> 16 tags -> 64 result bits */ | ||
151 | + *(uint64_t *)tag_mem = cpu_to_le64(val); | ||
99 | break; | 152 | break; |
100 | default: | 153 | default: |
101 | @@ -XXX,XX +XXX,XX @@ static void aspeed_timer_ctrl_enable(AspeedTimer *t, bool enable) | 154 | /* cpu configured with unsupported gm blocksize. */ |
102 | trace_aspeed_timer_ctrl_enable(t->id, enable); | ||
103 | if (enable) { | ||
104 | t->start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
105 | - timer_mod(&t->timer, calculate_next(t)); | ||
106 | + aspeed_timer_mod(t); | ||
107 | } else { | ||
108 | timer_del(&t->timer); | ||
109 | } | ||
110 | -- | 155 | -- |
111 | 2.7.4 | 156 | 2.34.1 |
112 | |||
113 | diff view generated by jsdifflib |
1 | From: Pranith Kumar <bobby.prani@gmail.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Tested and confirmed that the stretch i386 debian qcow2 image on a | 3 | When the cpu support MTE, but the system does not, reduce cpu |
4 | raspberry pi 2 works. | 4 | support to user instructions at EL0 instead of completely |
5 | disabling MTE. If we encounter a cpu implementation which does | ||
6 | something else, we can revisit this setting. | ||
5 | 7 | ||
6 | Fixes: LP#: 893208 <https://bugs.launchpad.net/qemu/+bug/893208/> | 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Signed-off-by: Pranith Kumar <bobby.prani@gmail.com> | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> | 10 | Message-id: 20230811214031.171020-5-richard.henderson@linaro.org |
9 | Message-id: 20170418191817.10430-1-bobby.prani@gmail.com | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 12 | --- |
12 | include/qemu/timer.h | 5 ++--- | 13 | target/arm/cpu.c | 7 ++++--- |
13 | 1 file changed, 2 insertions(+), 3 deletions(-) | 14 | 1 file changed, 4 insertions(+), 3 deletions(-) |
14 | 15 | ||
15 | diff --git a/include/qemu/timer.h b/include/qemu/timer.h | 16 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
16 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/include/qemu/timer.h | 18 | --- a/target/arm/cpu.c |
18 | +++ b/include/qemu/timer.h | 19 | +++ b/target/arm/cpu.c |
19 | @@ -XXX,XX +XXX,XX @@ static inline int64_t cpu_get_host_ticks(void) | 20 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
20 | /* The host CPU doesn't have an easily accessible cycle counter. | 21 | |
21 | Just return a monotonically increasing value. This will be | 22 | #ifndef CONFIG_USER_ONLY |
22 | totally wrong, but hopefully better than nothing. */ | 23 | /* |
23 | -static inline int64_t cpu_get_host_ticks (void) | 24 | - * Disable the MTE feature bits if we do not have tag-memory |
24 | +static inline int64_t cpu_get_host_ticks(void) | 25 | - * provided by the machine. |
25 | { | 26 | + * If we do not have tag-memory provided by the machine, |
26 | - static int64_t ticks = 0; | 27 | + * reduce MTE support to instructions enabled at EL0. |
27 | - return ticks++; | 28 | + * This matches Cortex-A710 BROADCASTMTE input being LOW. |
28 | + return get_clock(); | 29 | */ |
29 | } | 30 | if (cpu->tag_memory == NULL) { |
31 | cpu->isar.id_aa64pfr1 = | ||
32 | - FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); | ||
33 | + FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1); | ||
34 | } | ||
30 | #endif | 35 | #endif |
31 | 36 | } | |
32 | -- | 37 | -- |
33 | 2.7.4 | 38 | 2.34.1 |
34 | |||
35 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Do not hard-code the constants for Neoverse V1. | ||
4 | |||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Message-id: 20230811214031.171020-6-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | ||
10 | target/arm/tcg/cpu64.c | 48 ++++++++++++++++++++++++++++-------------- | ||
11 | 1 file changed, 32 insertions(+), 16 deletions(-) | ||
12 | |||
13 | diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/arm/tcg/cpu64.c | ||
16 | +++ b/target/arm/tcg/cpu64.c | ||
17 | @@ -XXX,XX +XXX,XX @@ | ||
18 | #include "qemu/module.h" | ||
19 | #include "qapi/visitor.h" | ||
20 | #include "hw/qdev-properties.h" | ||
21 | +#include "qemu/units.h" | ||
22 | #include "internals.h" | ||
23 | #include "cpregs.h" | ||
24 | |||
25 | +static uint64_t make_ccsidr64(unsigned assoc, unsigned linesize, | ||
26 | + unsigned cachesize) | ||
27 | +{ | ||
28 | + unsigned lg_linesize = ctz32(linesize); | ||
29 | + unsigned sets; | ||
30 | + | ||
31 | + /* | ||
32 | + * The 64-bit CCSIDR_EL1 format is: | ||
33 | + * [55:32] number of sets - 1 | ||
34 | + * [23:3] associativity - 1 | ||
35 | + * [2:0] log2(linesize) - 4 | ||
36 | + * so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc | ||
37 | + */ | ||
38 | + assert(assoc != 0); | ||
39 | + assert(is_power_of_2(linesize)); | ||
40 | + assert(lg_linesize >= 4 && lg_linesize <= 7 + 4); | ||
41 | + | ||
42 | + /* sets * associativity * linesize == cachesize. */ | ||
43 | + sets = cachesize / (assoc * linesize); | ||
44 | + assert(cachesize % (assoc * linesize) == 0); | ||
45 | + | ||
46 | + return ((uint64_t)(sets - 1) << 32) | ||
47 | + | ((assoc - 1) << 3) | ||
48 | + | (lg_linesize - 4); | ||
49 | +} | ||
50 | + | ||
51 | static void aarch64_a35_initfn(Object *obj) | ||
52 | { | ||
53 | ARMCPU *cpu = ARM_CPU(obj); | ||
54 | @@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_v1_initfn(Object *obj) | ||
55 | * The Neoverse-V1 r1p2 TRM lists 32-bit format CCSIDR_EL1 values, | ||
56 | * but also says it implements CCIDX, which means they should be | ||
57 | * 64-bit format. So we here use values which are based on the textual | ||
58 | - * information in chapter 2 of the TRM (and on the fact that | ||
59 | - * sets * associativity * linesize == cachesize). | ||
60 | - * | ||
61 | - * The 64-bit CCSIDR_EL1 format is: | ||
62 | - * [55:32] number of sets - 1 | ||
63 | - * [23:3] associativity - 1 | ||
64 | - * [2:0] log2(linesize) - 4 | ||
65 | - * so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc | ||
66 | - * | ||
67 | - * L1: 4-way set associative 64-byte line size, total size 64K, | ||
68 | - * so sets is 256. | ||
69 | + * information in chapter 2 of the TRM: | ||
70 | * | ||
71 | + * L1: 4-way set associative 64-byte line size, total size 64K. | ||
72 | * L2: 8-way set associative, 64 byte line size, either 512K or 1MB. | ||
73 | - * We pick 1MB, so this has 2048 sets. | ||
74 | - * | ||
75 | * L3: No L3 (this matches the CLIDR_EL1 value). | ||
76 | */ | ||
77 | - cpu->ccsidr[0] = 0x000000ff0000001aull; /* 64KB L1 dcache */ | ||
78 | - cpu->ccsidr[1] = 0x000000ff0000001aull; /* 64KB L1 icache */ | ||
79 | - cpu->ccsidr[2] = 0x000007ff0000003aull; /* 1MB L2 cache */ | ||
80 | + cpu->ccsidr[0] = make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */ | ||
81 | + cpu->ccsidr[1] = cpu->ccsidr[0]; /* L1 icache */ | ||
82 | + cpu->ccsidr[2] = make_ccsidr64(8, 64, 1 * MiB); /* L2 cache */ | ||
83 | |||
84 | /* From 3.2.115 SCTLR_EL3 */ | ||
85 | cpu->reset_sctlr = 0x30c50838; | ||
86 | -- | ||
87 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Krzysztof Kozlowski <krzk@kernel.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | On all Exynos-based boards, the system powers down itself by driving | 3 | Access to many of the special registers is enabled or disabled |
4 | PS_HOLD signal low - eight bit in PS_HOLD_CONTROL register of PMU. | 4 | by ACTLR_EL[23], which we implement as constant 0, which means |
5 | Handle writing to respective PMU register to fix power off failure: | 5 | that all writes outside EL3 should trap. |
6 | 6 | ||
7 | reboot: Power down | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Unable to poweroff system | ||
9 | shutdown: 31 output lines suppressed due to ratelimiting | ||
10 | Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000000 | ||
11 | |||
12 | CPU: 0 PID: 1 Comm: shutdown Not tainted 4.11.0-rc8 #846 | ||
13 | Hardware name: SAMSUNG EXYNOS (Flattened Device Tree) | ||
14 | [<c031050c>] (unwind_backtrace) from [<c030ba6c>] (show_stack+0x10/0x14) | ||
15 | [<c030ba6c>] (show_stack) from [<c05b2800>] (dump_stack+0x88/0x9c) | ||
16 | [<c05b2800>] (dump_stack) from [<c03d3140>] (panic+0xdc/0x268) | ||
17 | [<c03d3140>] (panic) from [<c0343614>] (do_exit+0xa90/0xab4) | ||
18 | [<c0343614>] (do_exit) from [<c035f2dc>] (SyS_reboot+0x164/0x1d0) | ||
19 | [<c035f2dc>] (SyS_reboot) from [<c0307c80>] (ret_fast_syscall+0x0/0x3c) | ||
20 | |||
21 | Additionally the initial value of PS_HOLD has to be changed because | ||
22 | recent Linux kernel (v4.12-rc1) uses regmap cache for this access. | ||
23 | When the register is kept at reset value, the kernel will not issue a | ||
24 | write to it. Usually the bootloader sets the eight bit of PS_HOLD high | ||
25 | so mimic its existence here. | ||
26 | |||
27 | Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> | ||
28 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
29 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 9 | Message-id: 20230811214031.171020-7-richard.henderson@linaro.org |
30 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
31 | --- | 11 | --- |
32 | hw/misc/exynos4210_pmu.c | 20 +++++++++++++++++++- | 12 | target/arm/cpregs.h | 2 ++ |
33 | 1 file changed, 19 insertions(+), 1 deletion(-) | 13 | target/arm/helper.c | 4 ++-- |
14 | target/arm/tcg/cpu64.c | 46 +++++++++++++++++++++++++++++++++--------- | ||
15 | 3 files changed, 41 insertions(+), 11 deletions(-) | ||
34 | 16 | ||
35 | diff --git a/hw/misc/exynos4210_pmu.c b/hw/misc/exynos4210_pmu.c | 17 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h |
36 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
37 | --- a/hw/misc/exynos4210_pmu.c | 19 | --- a/target/arm/cpregs.h |
38 | +++ b/hw/misc/exynos4210_pmu.c | 20 | +++ b/target/arm/cpregs.h |
39 | @@ -XXX,XX +XXX,XX @@ | 21 | @@ -XXX,XX +XXX,XX @@ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } |
40 | 22 | void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); | |
41 | #include "qemu/osdep.h" | 23 | #endif |
42 | #include "hw/sysbus.h" | 24 | |
43 | +#include "sysemu/sysemu.h" | 25 | +CPAccessResult access_tvm_trvm(CPUARMState *, const ARMCPRegInfo *, bool); |
44 | 26 | + | |
45 | #ifndef DEBUG_PMU | 27 | #endif /* TARGET_ARM_CPREGS_H */ |
46 | #define DEBUG_PMU 0 | 28 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
47 | @@ -XXX,XX +XXX,XX @@ static const Exynos4210PmuReg exynos4210_pmu_regs[] = { | 29 | index XXXXXXX..XXXXXXX 100644 |
48 | {"PAD_RETENTION_MMCB_OPTION", PAD_RETENTION_MMCB_OPTION, 0x00000000}, | 30 | --- a/target/arm/helper.c |
49 | {"PAD_RETENTION_EBIA_OPTION", PAD_RETENTION_EBIA_OPTION, 0x00000000}, | 31 | +++ b/target/arm/helper.c |
50 | {"PAD_RETENTION_EBIB_OPTION", PAD_RETENTION_EBIB_OPTION, 0x00000000}, | 32 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri, |
51 | - {"PS_HOLD_CONTROL", PS_HOLD_CONTROL, 0x00005200}, | 33 | } |
52 | + /* | 34 | |
53 | + * PS_HOLD_CONTROL: reset value and manually toggle high the DATA bit. | 35 | /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */ |
54 | + * DATA bit high, set usually by bootloader, keeps system on. | 36 | -static CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri, |
55 | + */ | 37 | - bool isread) |
56 | + {"PS_HOLD_CONTROL", PS_HOLD_CONTROL, 0x00005200 | BIT(8)}, | 38 | +CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri, |
57 | {"XUSBXTI_CONFIGURATION", XUSBXTI_CONFIGURATION, 0x00000001}, | 39 | + bool isread) |
58 | {"XUSBXTI_STATUS", XUSBXTI_STATUS, 0x00000001}, | 40 | { |
59 | {"XUSBXTI_DURATION", XUSBXTI_DURATION, 0xFFF00000}, | 41 | if (arm_current_el(env) == 1) { |
60 | @@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210PmuState { | 42 | uint64_t trap = isread ? HCR_TRVM : HCR_TVM; |
61 | uint32_t reg[PMU_NUM_OF_REGISTERS]; | 43 | diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c |
62 | } Exynos4210PmuState; | 44 | index XXXXXXX..XXXXXXX 100644 |
63 | 45 | --- a/target/arm/tcg/cpu64.c | |
64 | +static void exynos4210_pmu_poweroff(void) | 46 | +++ b/target/arm/tcg/cpu64.c |
47 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a64fx_initfn(Object *obj) | ||
48 | /* TODO: Add A64FX specific HPC extension registers */ | ||
49 | } | ||
50 | |||
51 | +static CPAccessResult access_actlr_w(CPUARMState *env, const ARMCPRegInfo *r, | ||
52 | + bool read) | ||
65 | +{ | 53 | +{ |
66 | + PRINT_DEBUG("QEMU PMU: PS_HOLD bit down, powering off\n"); | 54 | + if (!read) { |
67 | + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); | 55 | + int el = arm_current_el(env); |
56 | + | ||
57 | + /* Because ACTLR_EL2 is constant 0, writes below EL2 trap to EL2. */ | ||
58 | + if (el < 2 && arm_is_el2_enabled(env)) { | ||
59 | + return CP_ACCESS_TRAP_EL2; | ||
60 | + } | ||
61 | + /* Because ACTLR_EL3 is constant 0, writes below EL3 trap to EL3. */ | ||
62 | + if (el < 3 && arm_feature(env, ARM_FEATURE_EL3)) { | ||
63 | + return CP_ACCESS_TRAP_EL3; | ||
64 | + } | ||
65 | + } | ||
66 | + return CP_ACCESS_OK; | ||
68 | +} | 67 | +} |
69 | + | 68 | + |
70 | static uint64_t exynos4210_pmu_read(void *opaque, hwaddr offset, | 69 | static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = { |
71 | unsigned size) | 70 | { .name = "ATCR_EL1", .state = ARM_CP_STATE_AA64, |
72 | { | 71 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0, |
73 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_pmu_write(void *opaque, hwaddr offset, | 72 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
74 | PRINT_DEBUG_EXTEND("%s <0x%04x> <- 0x%04x\n", reg_p->name, | 73 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
75 | (uint32_t)offset, (uint32_t)val); | 74 | + /* Traps and enables are the same as for TCR_EL1. */ |
76 | s->reg[i] = val; | 75 | + .accessfn = access_tvm_trvm, .fgt = FGT_TCR_EL1, }, |
77 | + if ((offset == PS_HOLD_CONTROL) && ((val & BIT(8)) == 0)) { | 76 | { .name = "ATCR_EL2", .state = ARM_CP_STATE_AA64, |
78 | + /* | 77 | .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0, |
79 | + * We are interested only in setting data bit | 78 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
80 | + * of PS_HOLD_CONTROL register to indicate power off request. | 79 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = { |
81 | + */ | 80 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
82 | + exynos4210_pmu_poweroff(); | 81 | { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64, |
83 | + } | 82 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0, |
84 | return; | 83 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
85 | } | 84 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
86 | reg_p++; | 85 | + .accessfn = access_actlr_w }, |
86 | { .name = "CPUACTLR2_EL1", .state = ARM_CP_STATE_AA64, | ||
87 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1, | ||
88 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
89 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, | ||
90 | + .accessfn = access_actlr_w }, | ||
91 | { .name = "CPUACTLR3_EL1", .state = ARM_CP_STATE_AA64, | ||
92 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2, | ||
93 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
94 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, | ||
95 | + .accessfn = access_actlr_w }, | ||
96 | /* | ||
97 | * Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU | ||
98 | * (and in particular its system registers). | ||
99 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = { | ||
100 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 }, | ||
101 | { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64, | ||
102 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4, | ||
103 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010 }, | ||
104 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010, | ||
105 | + .accessfn = access_actlr_w }, | ||
106 | { .name = "CPUPCR_EL3", .state = ARM_CP_STATE_AA64, | ||
107 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 1, | ||
108 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
109 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = { | ||
110 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
111 | { .name = "CPUPWRCTLR_EL1", .state = ARM_CP_STATE_AA64, | ||
112 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7, | ||
113 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
114 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, | ||
115 | + .accessfn = access_actlr_w }, | ||
116 | { .name = "ERXPFGCDN_EL1", .state = ARM_CP_STATE_AA64, | ||
117 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 2, | ||
118 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
119 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, | ||
120 | + .accessfn = access_actlr_w }, | ||
121 | { .name = "ERXPFGCTL_EL1", .state = ARM_CP_STATE_AA64, | ||
122 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 1, | ||
123 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
124 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, | ||
125 | + .accessfn = access_actlr_w }, | ||
126 | { .name = "ERXPFGF_EL1", .state = ARM_CP_STATE_AA64, | ||
127 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0, | ||
128 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
129 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, | ||
130 | + .accessfn = access_actlr_w }, | ||
131 | }; | ||
132 | |||
133 | static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu) | ||
87 | -- | 134 | -- |
88 | 2.7.4 | 135 | 2.34.1 |
89 | |||
90 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | There is only one additional EL1 register modeled, which | ||
4 | also needs to use access_actlr_w. | ||
5 | |||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Message-id: 20230811214031.171020-8-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/tcg/cpu64.c | 3 ++- | ||
12 | 1 file changed, 2 insertions(+), 1 deletion(-) | ||
13 | |||
14 | diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/tcg/cpu64.c | ||
17 | +++ b/target/arm/tcg/cpu64.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu) | ||
19 | static const ARMCPRegInfo neoverse_v1_cp_reginfo[] = { | ||
20 | { .name = "CPUECTLR2_EL1", .state = ARM_CP_STATE_AA64, | ||
21 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 5, | ||
22 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
23 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, | ||
24 | + .accessfn = access_actlr_w }, | ||
25 | { .name = "CPUPPMCR_EL3", .state = ARM_CP_STATE_AA64, | ||
26 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 0, | ||
27 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
28 | -- | ||
29 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Like FEAT_TRF (Self-hosted Trace Extension), suppress tracing | ||
4 | external to the cpu, which is out of scope for QEMU. | ||
5 | |||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Message-id: 20230811214031.171020-10-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/cpu.c | 3 +++ | ||
12 | 1 file changed, 3 insertions(+) | ||
13 | |||
14 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/cpu.c | ||
17 | +++ b/target/arm/cpu.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | ||
19 | /* FEAT_SPE (Statistical Profiling Extension) */ | ||
20 | cpu->isar.id_aa64dfr0 = | ||
21 | FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0); | ||
22 | + /* FEAT_TRBE (Trace Buffer Extension) */ | ||
23 | + cpu->isar.id_aa64dfr0 = | ||
24 | + FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0); | ||
25 | /* FEAT_TRF (Self-hosted Trace Extension) */ | ||
26 | cpu->isar.id_aa64dfr0 = | ||
27 | FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0); | ||
28 | -- | ||
29 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | This feature allows the operating system to set TCR_ELx.HWU* | ||
4 | to allow the implementation to use the PBHA bits from the | ||
5 | block and page descriptors for for IMPLEMENTATION DEFINED | ||
6 | purposes. Since QEMU has no need to use these bits, we may | ||
7 | simply ignore them. | ||
8 | |||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Message-id: 20230811214031.171020-11-richard.henderson@linaro.org | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | docs/system/arm/emulation.rst | 1 + | ||
15 | target/arm/tcg/cpu32.c | 2 +- | ||
16 | target/arm/tcg/cpu64.c | 2 +- | ||
17 | 3 files changed, 3 insertions(+), 2 deletions(-) | ||
18 | |||
19 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/docs/system/arm/emulation.rst | ||
22 | +++ b/docs/system/arm/emulation.rst | ||
23 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | ||
24 | - FEAT_HAFDBS (Hardware management of the access flag and dirty bit state) | ||
25 | - FEAT_HCX (Support for the HCRX_EL2 register) | ||
26 | - FEAT_HPDS (Hierarchical permission disables) | ||
27 | +- FEAT_HPDS2 (Translation table page-based hardware attributes) | ||
28 | - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions) | ||
29 | - FEAT_IDST (ID space trap handling) | ||
30 | - FEAT_IESB (Implicit error synchronization event) | ||
31 | diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/target/arm/tcg/cpu32.c | ||
34 | +++ b/target/arm/tcg/cpu32.c | ||
35 | @@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu) | ||
36 | cpu->isar.id_mmfr3 = t; | ||
37 | |||
38 | t = cpu->isar.id_mmfr4; | ||
39 | - t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* FEAT_AA32HPD */ | ||
40 | + t = FIELD_DP32(t, ID_MMFR4, HPDS, 2); /* FEAT_HPDS2 */ | ||
41 | t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | ||
42 | t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */ | ||
43 | t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */ | ||
44 | diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c | ||
45 | index XXXXXXX..XXXXXXX 100644 | ||
46 | --- a/target/arm/tcg/cpu64.c | ||
47 | +++ b/target/arm/tcg/cpu64.c | ||
48 | @@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj) | ||
49 | t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* FEAT_HAFDBS */ | ||
50 | t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */ | ||
51 | t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ | ||
52 | - t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */ | ||
53 | + t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 2); /* FEAT_HPDS2 */ | ||
54 | t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */ | ||
55 | t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 3); /* FEAT_PAN3 */ | ||
56 | t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */ | ||
57 | -- | ||
58 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Krzysztof Kozlowski <krzk@kernel.org> | 1 | From: Alex Bennée <alex.bennee@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Bring some more readability by declaring local function variables: first | 3 | This is a mandatory feature for Armv8.1 architectures but we don't |
4 | initialized ones and then the rest (with reversed-christmas-tree order). | 4 | state the feature clearly in our emulation list. Also include |
5 | FEAT_CRC32 comment in aarch64_max_tcg_initfn for ease of grepping. | ||
5 | 6 | ||
6 | Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> | 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 8 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> |
9 | Message-id: 20230824075406.1515566-1-alex.bennee@linaro.org | ||
10 | Cc: qemu-stable@nongnu.org | ||
11 | Message-Id: <20230222110104.3996971-1-alex.bennee@linaro.org> | ||
12 | [PMM: pluralize 'instructions' in docs] | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 14 | --- |
10 | hw/arm/exynos4210.c | 4 ++-- | 15 | docs/system/arm/emulation.rst | 1 + |
11 | 1 file changed, 2 insertions(+), 2 deletions(-) | 16 | target/arm/tcg/cpu64.c | 2 +- |
17 | 2 files changed, 2 insertions(+), 1 deletion(-) | ||
12 | 18 | ||
13 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | 19 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst |
14 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/hw/arm/exynos4210.c | 21 | --- a/docs/system/arm/emulation.rst |
16 | +++ b/hw/arm/exynos4210.c | 22 | +++ b/docs/system/arm/emulation.rst |
17 | @@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_calc_affinity(int cpu) | 23 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: |
18 | 24 | - FEAT_BBM at level 2 (Translation table break-before-make levels) | |
19 | Exynos4210State *exynos4210_init(MemoryRegion *system_mem) | 25 | - FEAT_BF16 (AArch64 BFloat16 instructions) |
20 | { | 26 | - FEAT_BTI (Branch Target Identification) |
21 | - int i, n; | 27 | +- FEAT_CRC32 (CRC32 instructions) |
22 | Exynos4210State *s = g_new(Exynos4210State, 1); | 28 | - FEAT_CSV2 (Cache speculation variant 2) |
23 | qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS]; | 29 | - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1) |
24 | - DeviceState *dev; | 30 | - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) |
25 | SysBusDevice *busdev; | 31 | diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c |
26 | ObjectClass *cpu_oc; | 32 | index XXXXXXX..XXXXXXX 100644 |
27 | + DeviceState *dev; | 33 | --- a/target/arm/tcg/cpu64.c |
28 | + int i, n; | 34 | +++ b/target/arm/tcg/cpu64.c |
29 | 35 | @@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj) | |
30 | cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, "cortex-a9"); | 36 | t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */ |
31 | assert(cpu_oc); | 37 | t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */ |
38 | t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */ | ||
39 | - t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); | ||
40 | + t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); /* FEAT_CRC32 */ | ||
41 | t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */ | ||
42 | t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */ | ||
43 | t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */ | ||
32 | -- | 44 | -- |
33 | 2.7.4 | 45 | 2.34.1 |
34 | 46 | ||
35 | 47 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Jean-Christophe Dubois <jcd@tribudubois.net> | ||
1 | 2 | ||
3 | i.MX7 IOMUX GPR device is not equivalent to i.MX6UL IOMUXC GPR device. | ||
4 | In particular, register 22 is not present on i.MX6UL and this is actualy | ||
5 | The only register that is really emulated in the i.MX7 IOMUX GPR device. | ||
6 | |||
7 | Note: The i.MX6UL code is actually also implementing the IOMUX GPR device | ||
8 | as an unimplemented device at the same bus adress and the 2 instantiations | ||
9 | were actualy colliding. So we go back to the unimplemented device for now. | ||
10 | |||
11 | Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> | ||
12 | Message-id: 48681bf51ee97646479bb261bee19abebbc8074e.1692964892.git.jcd@tribudubois.net | ||
13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
15 | --- | ||
16 | include/hw/arm/fsl-imx6ul.h | 2 -- | ||
17 | hw/arm/fsl-imx6ul.c | 11 ----------- | ||
18 | 2 files changed, 13 deletions(-) | ||
19 | |||
20 | diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h | ||
21 | index XXXXXXX..XXXXXXX 100644 | ||
22 | --- a/include/hw/arm/fsl-imx6ul.h | ||
23 | +++ b/include/hw/arm/fsl-imx6ul.h | ||
24 | @@ -XXX,XX +XXX,XX @@ | ||
25 | #include "hw/misc/imx6ul_ccm.h" | ||
26 | #include "hw/misc/imx6_src.h" | ||
27 | #include "hw/misc/imx7_snvs.h" | ||
28 | -#include "hw/misc/imx7_gpr.h" | ||
29 | #include "hw/intc/imx_gpcv2.h" | ||
30 | #include "hw/watchdog/wdt_imx2.h" | ||
31 | #include "hw/gpio/imx_gpio.h" | ||
32 | @@ -XXX,XX +XXX,XX @@ struct FslIMX6ULState { | ||
33 | IMX6SRCState src; | ||
34 | IMX7SNVSState snvs; | ||
35 | IMXGPCv2State gpcv2; | ||
36 | - IMX7GPRState gpr; | ||
37 | IMXSPIState spi[FSL_IMX6UL_NUM_ECSPIS]; | ||
38 | IMXI2CState i2c[FSL_IMX6UL_NUM_I2CS]; | ||
39 | IMXSerialState uart[FSL_IMX6UL_NUM_UARTS]; | ||
40 | diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/hw/arm/fsl-imx6ul.c | ||
43 | +++ b/hw/arm/fsl-imx6ul.c | ||
44 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj) | ||
45 | */ | ||
46 | object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS); | ||
47 | |||
48 | - /* | ||
49 | - * GPR | ||
50 | - */ | ||
51 | - object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR); | ||
52 | - | ||
53 | /* | ||
54 | * GPIOs 1 to 5 | ||
55 | */ | ||
56 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
57 | FSL_IMX6UL_WDOGn_IRQ[i])); | ||
58 | } | ||
59 | |||
60 | - /* | ||
61 | - * GPR | ||
62 | - */ | ||
63 | - sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort); | ||
64 | - sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX6UL_IOMUXC_GPR_ADDR); | ||
65 | - | ||
66 | /* | ||
67 | * SDMA | ||
68 | */ | ||
69 | -- | ||
70 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Krzysztof Kozlowski <krzk@kernel.org> | 1 | From: Jean-Christophe Dubois <jcd@tribudubois.net> |
---|---|---|---|
2 | 2 | ||
3 | Remove defines not used anywhere. | 3 | * Add Addr and size definition for most i.MX6UL devices in i.MX6UL header file. |
4 | * Use those newly defined named constants whenever possible. | ||
5 | * Standardize the way we init a familly of unimplemented devices | ||
6 | - SAI | ||
7 | - PWM | ||
8 | - CAN | ||
9 | * Add/rework few comments | ||
4 | 10 | ||
5 | Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> | 11 | Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> |
12 | Message-id: d579043fbd4e4b490370783fda43fc02c8e9be75.1692964892.git.jcd@tribudubois.net | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | --- | 15 | --- |
9 | hw/timer/exynos4210_mct.c | 3 --- | 16 | include/hw/arm/fsl-imx6ul.h | 156 +++++++++++++++++++++++++++++++----- |
10 | 1 file changed, 3 deletions(-) | 17 | hw/arm/fsl-imx6ul.c | 147 ++++++++++++++++++++++----------- |
18 | 2 files changed, 232 insertions(+), 71 deletions(-) | ||
11 | 19 | ||
12 | diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c | 20 | diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h |
13 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/hw/timer/exynos4210_mct.c | 22 | --- a/include/hw/arm/fsl-imx6ul.h |
15 | +++ b/hw/timer/exynos4210_mct.c | 23 | +++ b/include/hw/arm/fsl-imx6ul.h |
16 | @@ -XXX,XX +XXX,XX @@ enum LocalTimerRegCntIndexes { | 24 | @@ -XXX,XX +XXX,XX @@ |
17 | L_REG_CNT_AMOUNT | 25 | #include "exec/memory.h" |
26 | #include "cpu.h" | ||
27 | #include "qom/object.h" | ||
28 | +#include "qemu/units.h" | ||
29 | |||
30 | #define TYPE_FSL_IMX6UL "fsl-imx6ul" | ||
31 | OBJECT_DECLARE_SIMPLE_TYPE(FslIMX6ULState, FSL_IMX6UL) | ||
32 | @@ -XXX,XX +XXX,XX @@ enum FslIMX6ULConfiguration { | ||
33 | FSL_IMX6UL_NUM_ADCS = 2, | ||
34 | FSL_IMX6UL_NUM_USB_PHYS = 2, | ||
35 | FSL_IMX6UL_NUM_USBS = 2, | ||
36 | + FSL_IMX6UL_NUM_SAIS = 3, | ||
37 | + FSL_IMX6UL_NUM_CANS = 2, | ||
38 | + FSL_IMX6UL_NUM_PWMS = 4, | ||
18 | }; | 39 | }; |
19 | 40 | ||
20 | -#define MCT_NIRQ 6 | 41 | struct FslIMX6ULState { |
21 | #define MCT_SFR_SIZE 0x444 | 42 | @@ -XXX,XX +XXX,XX @@ struct FslIMX6ULState { |
22 | 43 | ||
23 | #define MCT_GT_CMP_NUM 4 | 44 | enum FslIMX6ULMemoryMap { |
24 | 45 | FSL_IMX6UL_MMDC_ADDR = 0x80000000, | |
25 | -#define MCT_GT_MAX_VAL UINT64_MAX | 46 | - FSL_IMX6UL_MMDC_SIZE = 2 * 1024 * 1024 * 1024UL, |
47 | + FSL_IMX6UL_MMDC_SIZE = (2 * GiB), | ||
48 | |||
49 | FSL_IMX6UL_QSPI1_MEM_ADDR = 0x60000000, | ||
50 | - FSL_IMX6UL_EIM_ALIAS_ADDR = 0x58000000, | ||
51 | - FSL_IMX6UL_EIM_CS_ADDR = 0x50000000, | ||
52 | - FSL_IMX6UL_AES_ENCRYPT_ADDR = 0x10000000, | ||
53 | - FSL_IMX6UL_QSPI1_RX_ADDR = 0x0C000000, | ||
54 | + FSL_IMX6UL_QSPI1_MEM_SIZE = (256 * MiB), | ||
55 | |||
56 | - /* AIPS-2 */ | ||
57 | + FSL_IMX6UL_EIM_ALIAS_ADDR = 0x58000000, | ||
58 | + FSL_IMX6UL_EIM_ALIAS_SIZE = (128 * MiB), | ||
59 | + | ||
60 | + FSL_IMX6UL_EIM_CS_ADDR = 0x50000000, | ||
61 | + FSL_IMX6UL_EIM_CS_SIZE = (128 * MiB), | ||
62 | + | ||
63 | + FSL_IMX6UL_AES_ENCRYPT_ADDR = 0x10000000, | ||
64 | + FSL_IMX6UL_AES_ENCRYPT_SIZE = (1 * MiB), | ||
65 | + | ||
66 | + FSL_IMX6UL_QSPI1_RX_ADDR = 0x0C000000, | ||
67 | + FSL_IMX6UL_QSPI1_RX_SIZE = (32 * MiB), | ||
68 | + | ||
69 | + /* AIPS-2 Begin */ | ||
70 | FSL_IMX6UL_UART6_ADDR = 0x021FC000, | ||
71 | + | ||
72 | FSL_IMX6UL_I2C4_ADDR = 0x021F8000, | ||
73 | + | ||
74 | FSL_IMX6UL_UART5_ADDR = 0x021F4000, | ||
75 | FSL_IMX6UL_UART4_ADDR = 0x021F0000, | ||
76 | FSL_IMX6UL_UART3_ADDR = 0x021EC000, | ||
77 | FSL_IMX6UL_UART2_ADDR = 0x021E8000, | ||
78 | + | ||
79 | FSL_IMX6UL_WDOG3_ADDR = 0x021E4000, | ||
80 | + | ||
81 | FSL_IMX6UL_QSPI_ADDR = 0x021E0000, | ||
82 | + FSL_IMX6UL_QSPI_SIZE = 0x500, | ||
83 | + | ||
84 | FSL_IMX6UL_SYS_CNT_CTRL_ADDR = 0x021DC000, | ||
85 | + FSL_IMX6UL_SYS_CNT_CTRL_SIZE = (16 * KiB), | ||
86 | + | ||
87 | FSL_IMX6UL_SYS_CNT_CMP_ADDR = 0x021D8000, | ||
88 | + FSL_IMX6UL_SYS_CNT_CMP_SIZE = (16 * KiB), | ||
89 | + | ||
90 | FSL_IMX6UL_SYS_CNT_RD_ADDR = 0x021D4000, | ||
91 | + FSL_IMX6UL_SYS_CNT_RD_SIZE = (16 * KiB), | ||
92 | + | ||
93 | FSL_IMX6UL_TZASC_ADDR = 0x021D0000, | ||
94 | + FSL_IMX6UL_TZASC_SIZE = (16 * KiB), | ||
95 | + | ||
96 | FSL_IMX6UL_PXP_ADDR = 0x021CC000, | ||
97 | + FSL_IMX6UL_PXP_SIZE = (16 * KiB), | ||
98 | + | ||
99 | FSL_IMX6UL_LCDIF_ADDR = 0x021C8000, | ||
100 | + FSL_IMX6UL_LCDIF_SIZE = 0x100, | ||
101 | + | ||
102 | FSL_IMX6UL_CSI_ADDR = 0x021C4000, | ||
103 | + FSL_IMX6UL_CSI_SIZE = 0x100, | ||
104 | + | ||
105 | FSL_IMX6UL_CSU_ADDR = 0x021C0000, | ||
106 | + FSL_IMX6UL_CSU_SIZE = (16 * KiB), | ||
107 | + | ||
108 | FSL_IMX6UL_OCOTP_CTRL_ADDR = 0x021BC000, | ||
109 | + FSL_IMX6UL_OCOTP_CTRL_SIZE = (4 * KiB), | ||
110 | + | ||
111 | FSL_IMX6UL_EIM_ADDR = 0x021B8000, | ||
112 | + FSL_IMX6UL_EIM_SIZE = 0x100, | ||
113 | + | ||
114 | FSL_IMX6UL_SIM2_ADDR = 0x021B4000, | ||
115 | + | ||
116 | FSL_IMX6UL_MMDC_CFG_ADDR = 0x021B0000, | ||
117 | + FSL_IMX6UL_MMDC_CFG_SIZE = (4 * KiB), | ||
118 | + | ||
119 | FSL_IMX6UL_ROMCP_ADDR = 0x021AC000, | ||
120 | + FSL_IMX6UL_ROMCP_SIZE = 0x300, | ||
121 | + | ||
122 | FSL_IMX6UL_I2C3_ADDR = 0x021A8000, | ||
123 | FSL_IMX6UL_I2C2_ADDR = 0x021A4000, | ||
124 | FSL_IMX6UL_I2C1_ADDR = 0x021A0000, | ||
125 | + | ||
126 | FSL_IMX6UL_ADC2_ADDR = 0x0219C000, | ||
127 | FSL_IMX6UL_ADC1_ADDR = 0x02198000, | ||
128 | + FSL_IMX6UL_ADCn_SIZE = 0x100, | ||
129 | + | ||
130 | FSL_IMX6UL_USDHC2_ADDR = 0x02194000, | ||
131 | FSL_IMX6UL_USDHC1_ADDR = 0x02190000, | ||
132 | - FSL_IMX6UL_SIM1_ADDR = 0x0218C000, | ||
133 | - FSL_IMX6UL_ENET1_ADDR = 0x02188000, | ||
134 | - FSL_IMX6UL_USBO2_USBMISC_ADDR = 0x02184800, | ||
135 | - FSL_IMX6UL_USBO2_USB_ADDR = 0x02184000, | ||
136 | - FSL_IMX6UL_USBO2_PL301_ADDR = 0x02180000, | ||
137 | - FSL_IMX6UL_AIPS2_CFG_ADDR = 0x0217C000, | ||
138 | - FSL_IMX6UL_CAAM_ADDR = 0x02140000, | ||
139 | - FSL_IMX6UL_A7MPCORE_DAP_ADDR = 0x02100000, | ||
140 | |||
141 | - /* AIPS-1 */ | ||
142 | + FSL_IMX6UL_SIM1_ADDR = 0x0218C000, | ||
143 | + FSL_IMX6UL_SIMn_SIZE = (16 * KiB), | ||
144 | + | ||
145 | + FSL_IMX6UL_ENET1_ADDR = 0x02188000, | ||
146 | + | ||
147 | + FSL_IMX6UL_USBO2_USBMISC_ADDR = 0x02184800, | ||
148 | + FSL_IMX6UL_USBO2_USB1_ADDR = 0x02184000, | ||
149 | + FSL_IMX6UL_USBO2_USB2_ADDR = 0x02184200, | ||
150 | + | ||
151 | + FSL_IMX6UL_USBO2_PL301_ADDR = 0x02180000, | ||
152 | + FSL_IMX6UL_USBO2_PL301_SIZE = (16 * KiB), | ||
153 | + | ||
154 | + FSL_IMX6UL_AIPS2_CFG_ADDR = 0x0217C000, | ||
155 | + FSL_IMX6UL_AIPS2_CFG_SIZE = 0x100, | ||
156 | + | ||
157 | + FSL_IMX6UL_CAAM_ADDR = 0x02140000, | ||
158 | + FSL_IMX6UL_CAAM_SIZE = (16 * KiB), | ||
159 | + | ||
160 | + FSL_IMX6UL_A7MPCORE_DAP_ADDR = 0x02100000, | ||
161 | + FSL_IMX6UL_A7MPCORE_DAP_SIZE = (4 * KiB), | ||
162 | + /* AIPS-2 End */ | ||
163 | + | ||
164 | + /* AIPS-1 Begin */ | ||
165 | FSL_IMX6UL_PWM8_ADDR = 0x020FC000, | ||
166 | FSL_IMX6UL_PWM7_ADDR = 0x020F8000, | ||
167 | FSL_IMX6UL_PWM6_ADDR = 0x020F4000, | ||
168 | FSL_IMX6UL_PWM5_ADDR = 0x020F0000, | ||
169 | + | ||
170 | FSL_IMX6UL_SDMA_ADDR = 0x020EC000, | ||
171 | + FSL_IMX6UL_SDMA_SIZE = 0x300, | ||
172 | + | ||
173 | FSL_IMX6UL_GPT2_ADDR = 0x020E8000, | ||
174 | + | ||
175 | FSL_IMX6UL_IOMUXC_GPR_ADDR = 0x020E4000, | ||
176 | + FSL_IMX6UL_IOMUXC_GPR_SIZE = 0x40, | ||
177 | + | ||
178 | FSL_IMX6UL_IOMUXC_ADDR = 0x020E0000, | ||
179 | + FSL_IMX6UL_IOMUXC_SIZE = 0x700, | ||
180 | + | ||
181 | FSL_IMX6UL_GPC_ADDR = 0x020DC000, | ||
182 | + | ||
183 | FSL_IMX6UL_SRC_ADDR = 0x020D8000, | ||
184 | + | ||
185 | FSL_IMX6UL_EPIT2_ADDR = 0x020D4000, | ||
186 | FSL_IMX6UL_EPIT1_ADDR = 0x020D0000, | ||
187 | + | ||
188 | FSL_IMX6UL_SNVS_HP_ADDR = 0x020CC000, | ||
189 | + | ||
190 | FSL_IMX6UL_USBPHY2_ADDR = 0x020CA000, | ||
191 | - FSL_IMX6UL_USBPHY2_SIZE = (4 * 1024), | ||
192 | FSL_IMX6UL_USBPHY1_ADDR = 0x020C9000, | ||
193 | - FSL_IMX6UL_USBPHY1_SIZE = (4 * 1024), | ||
194 | + | ||
195 | FSL_IMX6UL_ANALOG_ADDR = 0x020C8000, | ||
196 | + FSL_IMX6UL_ANALOG_SIZE = 0x300, | ||
197 | + | ||
198 | FSL_IMX6UL_CCM_ADDR = 0x020C4000, | ||
199 | + | ||
200 | FSL_IMX6UL_WDOG2_ADDR = 0x020C0000, | ||
201 | FSL_IMX6UL_WDOG1_ADDR = 0x020BC000, | ||
202 | + | ||
203 | FSL_IMX6UL_KPP_ADDR = 0x020B8000, | ||
204 | + FSL_IMX6UL_KPP_SIZE = 0x10, | ||
205 | + | ||
206 | FSL_IMX6UL_ENET2_ADDR = 0x020B4000, | ||
207 | + | ||
208 | FSL_IMX6UL_SNVS_LP_ADDR = 0x020B0000, | ||
209 | + FSL_IMX6UL_SNVS_LP_SIZE = (16 * KiB), | ||
210 | + | ||
211 | FSL_IMX6UL_GPIO5_ADDR = 0x020AC000, | ||
212 | FSL_IMX6UL_GPIO4_ADDR = 0x020A8000, | ||
213 | FSL_IMX6UL_GPIO3_ADDR = 0x020A4000, | ||
214 | FSL_IMX6UL_GPIO2_ADDR = 0x020A0000, | ||
215 | FSL_IMX6UL_GPIO1_ADDR = 0x0209C000, | ||
216 | + | ||
217 | FSL_IMX6UL_GPT1_ADDR = 0x02098000, | ||
218 | + | ||
219 | FSL_IMX6UL_CAN2_ADDR = 0x02094000, | ||
220 | FSL_IMX6UL_CAN1_ADDR = 0x02090000, | ||
221 | + FSL_IMX6UL_CANn_SIZE = (4 * KiB), | ||
222 | + | ||
223 | FSL_IMX6UL_PWM4_ADDR = 0x0208C000, | ||
224 | FSL_IMX6UL_PWM3_ADDR = 0x02088000, | ||
225 | FSL_IMX6UL_PWM2_ADDR = 0x02084000, | ||
226 | FSL_IMX6UL_PWM1_ADDR = 0x02080000, | ||
227 | + FSL_IMX6UL_PWMn_SIZE = 0x20, | ||
228 | + | ||
229 | FSL_IMX6UL_AIPS1_CFG_ADDR = 0x0207C000, | ||
230 | + FSL_IMX6UL_AIPS1_CFG_SIZE = (16 * KiB), | ||
231 | + | ||
232 | FSL_IMX6UL_BEE_ADDR = 0x02044000, | ||
233 | + FSL_IMX6UL_BEE_SIZE = (16 * KiB), | ||
234 | + | ||
235 | FSL_IMX6UL_TOUCH_CTRL_ADDR = 0x02040000, | ||
236 | + FSL_IMX6UL_TOUCH_CTRL_SIZE = 0x100, | ||
237 | + | ||
238 | FSL_IMX6UL_SPBA_ADDR = 0x0203C000, | ||
239 | + FSL_IMX6UL_SPBA_SIZE = 0x100, | ||
240 | + | ||
241 | FSL_IMX6UL_ASRC_ADDR = 0x02034000, | ||
242 | + FSL_IMX6UL_ASRC_SIZE = 0x100, | ||
243 | + | ||
244 | FSL_IMX6UL_SAI3_ADDR = 0x02030000, | ||
245 | FSL_IMX6UL_SAI2_ADDR = 0x0202C000, | ||
246 | FSL_IMX6UL_SAI1_ADDR = 0x02028000, | ||
247 | + FSL_IMX6UL_SAIn_SIZE = 0x200, | ||
248 | + | ||
249 | FSL_IMX6UL_UART8_ADDR = 0x02024000, | ||
250 | FSL_IMX6UL_UART1_ADDR = 0x02020000, | ||
251 | FSL_IMX6UL_UART7_ADDR = 0x02018000, | ||
252 | + | ||
253 | FSL_IMX6UL_ECSPI4_ADDR = 0x02014000, | ||
254 | FSL_IMX6UL_ECSPI3_ADDR = 0x02010000, | ||
255 | FSL_IMX6UL_ECSPI2_ADDR = 0x0200C000, | ||
256 | FSL_IMX6UL_ECSPI1_ADDR = 0x02008000, | ||
257 | + | ||
258 | FSL_IMX6UL_SPDIF_ADDR = 0x02004000, | ||
259 | + FSL_IMX6UL_SPDIF_SIZE = 0x100, | ||
260 | + /* AIPS-1 End */ | ||
261 | + | ||
262 | + FSL_IMX6UL_BCH_ADDR = 0x01808000, | ||
263 | + FSL_IMX6UL_BCH_SIZE = 0x200, | ||
264 | + | ||
265 | + FSL_IMX6UL_GPMI_ADDR = 0x01806000, | ||
266 | + FSL_IMX6UL_GPMI_SIZE = 0x200, | ||
267 | |||
268 | FSL_IMX6UL_APBH_DMA_ADDR = 0x01804000, | ||
269 | - FSL_IMX6UL_APBH_DMA_SIZE = (32 * 1024), | ||
270 | + FSL_IMX6UL_APBH_DMA_SIZE = (4 * KiB), | ||
271 | |||
272 | FSL_IMX6UL_A7MPCORE_ADDR = 0x00A00000, | ||
273 | |||
274 | FSL_IMX6UL_OCRAM_ALIAS_ADDR = 0x00920000, | ||
275 | - FSL_IMX6UL_OCRAM_ALIAS_SIZE = 0x00060000, | ||
276 | + FSL_IMX6UL_OCRAM_ALIAS_SIZE = (384 * KiB), | ||
277 | + | ||
278 | FSL_IMX6UL_OCRAM_MEM_ADDR = 0x00900000, | ||
279 | - FSL_IMX6UL_OCRAM_MEM_SIZE = 0x00020000, | ||
280 | + FSL_IMX6UL_OCRAM_MEM_SIZE = (128 * KiB), | ||
281 | + | ||
282 | FSL_IMX6UL_CAAM_MEM_ADDR = 0x00100000, | ||
283 | - FSL_IMX6UL_CAAM_MEM_SIZE = 0x00008000, | ||
284 | + FSL_IMX6UL_CAAM_MEM_SIZE = (32 * KiB), | ||
285 | + | ||
286 | FSL_IMX6UL_ROM_ADDR = 0x00000000, | ||
287 | - FSL_IMX6UL_ROM_SIZE = 0x00018000, | ||
288 | + FSL_IMX6UL_ROM_SIZE = (96 * KiB), | ||
289 | }; | ||
290 | |||
291 | enum FslIMX6ULIRQs { | ||
292 | diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c | ||
293 | index XXXXXXX..XXXXXXX 100644 | ||
294 | --- a/hw/arm/fsl-imx6ul.c | ||
295 | +++ b/hw/arm/fsl-imx6ul.c | ||
296 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj) | ||
297 | object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS); | ||
298 | |||
299 | /* | ||
300 | - * GPIOs 1 to 5 | ||
301 | + * GPIOs | ||
302 | */ | ||
303 | for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) { | ||
304 | snprintf(name, NAME_SIZE, "gpio%d", i); | ||
305 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj) | ||
306 | } | ||
307 | |||
308 | /* | ||
309 | - * GPT 1, 2 | ||
310 | + * GPTs | ||
311 | */ | ||
312 | for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) { | ||
313 | snprintf(name, NAME_SIZE, "gpt%d", i); | ||
314 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj) | ||
315 | } | ||
316 | |||
317 | /* | ||
318 | - * EPIT 1, 2 | ||
319 | + * EPITs | ||
320 | */ | ||
321 | for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) { | ||
322 | snprintf(name, NAME_SIZE, "epit%d", i + 1); | ||
323 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj) | ||
324 | } | ||
325 | |||
326 | /* | ||
327 | - * eCSPI | ||
328 | + * eCSPIs | ||
329 | */ | ||
330 | for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { | ||
331 | snprintf(name, NAME_SIZE, "spi%d", i + 1); | ||
332 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj) | ||
333 | } | ||
334 | |||
335 | /* | ||
336 | - * I2C | ||
337 | + * I2Cs | ||
338 | */ | ||
339 | for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { | ||
340 | snprintf(name, NAME_SIZE, "i2c%d", i + 1); | ||
341 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj) | ||
342 | } | ||
343 | |||
344 | /* | ||
345 | - * UART | ||
346 | + * UARTs | ||
347 | */ | ||
348 | for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) { | ||
349 | snprintf(name, NAME_SIZE, "uart%d", i); | ||
350 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj) | ||
351 | } | ||
352 | |||
353 | /* | ||
354 | - * Ethernet | ||
355 | + * Ethernets | ||
356 | */ | ||
357 | for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) { | ||
358 | snprintf(name, NAME_SIZE, "eth%d", i); | ||
359 | object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET); | ||
360 | } | ||
361 | |||
362 | - /* USB */ | ||
363 | + /* | ||
364 | + * USB PHYs | ||
365 | + */ | ||
366 | for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) { | ||
367 | snprintf(name, NAME_SIZE, "usbphy%d", i); | ||
368 | object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY); | ||
369 | } | ||
370 | + | ||
371 | + /* | ||
372 | + * USBs | ||
373 | + */ | ||
374 | for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) { | ||
375 | snprintf(name, NAME_SIZE, "usb%d", i); | ||
376 | object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA); | ||
377 | } | ||
378 | |||
379 | /* | ||
380 | - * SDHCI | ||
381 | + * SDHCIs | ||
382 | */ | ||
383 | for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) { | ||
384 | snprintf(name, NAME_SIZE, "usdhc%d", i); | ||
385 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj) | ||
386 | } | ||
387 | |||
388 | /* | ||
389 | - * Watchdog | ||
390 | + * Watchdogs | ||
391 | */ | ||
392 | for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) { | ||
393 | snprintf(name, NAME_SIZE, "wdt%d", i); | ||
394 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
395 | * A7MPCORE DAP | ||
396 | */ | ||
397 | create_unimplemented_device("a7mpcore-dap", FSL_IMX6UL_A7MPCORE_DAP_ADDR, | ||
398 | - 0x100000); | ||
399 | + FSL_IMX6UL_A7MPCORE_DAP_SIZE); | ||
400 | |||
401 | /* | ||
402 | - * GPT 1, 2 | ||
403 | + * GPTs | ||
404 | */ | ||
405 | for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) { | ||
406 | static const hwaddr FSL_IMX6UL_GPTn_ADDR[FSL_IMX6UL_NUM_GPTS] = { | ||
407 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
408 | } | ||
409 | |||
410 | /* | ||
411 | - * EPIT 1, 2 | ||
412 | + * EPITs | ||
413 | */ | ||
414 | for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) { | ||
415 | static const hwaddr FSL_IMX6UL_EPITn_ADDR[FSL_IMX6UL_NUM_EPITS] = { | ||
416 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
417 | } | ||
418 | |||
419 | /* | ||
420 | - * GPIO | ||
421 | + * GPIOs | ||
422 | */ | ||
423 | for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) { | ||
424 | static const hwaddr FSL_IMX6UL_GPIOn_ADDR[FSL_IMX6UL_NUM_GPIOS] = { | ||
425 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
426 | } | ||
427 | |||
428 | /* | ||
429 | - * IOMUXC and IOMUXC_GPR | ||
430 | + * IOMUXC | ||
431 | */ | ||
432 | - for (i = 0; i < 1; i++) { | ||
433 | - static const hwaddr FSL_IMX6UL_IOMUXCn_ADDR[FSL_IMX6UL_NUM_IOMUXCS] = { | ||
434 | - FSL_IMX6UL_IOMUXC_ADDR, | ||
435 | - FSL_IMX6UL_IOMUXC_GPR_ADDR, | ||
436 | - }; | ||
26 | - | 437 | - |
27 | #define MCT_GT_COUNTER_STEP 0x100000000ULL | 438 | - snprintf(name, NAME_SIZE, "iomuxc%d", i); |
28 | #define MCT_LT_COUNTER_STEP 0x100000000ULL | 439 | - create_unimplemented_device(name, FSL_IMX6UL_IOMUXCn_ADDR[i], 0x4000); |
29 | #define MCT_LT_CNT_LOW_LIMIT 0x100 | 440 | - } |
441 | + create_unimplemented_device("iomuxc", FSL_IMX6UL_IOMUXC_ADDR, | ||
442 | + FSL_IMX6UL_IOMUXC_SIZE); | ||
443 | + create_unimplemented_device("iomuxc_gpr", FSL_IMX6UL_IOMUXC_GPR_ADDR, | ||
444 | + FSL_IMX6UL_IOMUXC_GPR_SIZE); | ||
445 | |||
446 | /* | ||
447 | * CCM | ||
448 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
449 | sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort); | ||
450 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX6UL_GPC_ADDR); | ||
451 | |||
452 | - /* Initialize all ECSPI */ | ||
453 | + /* | ||
454 | + * ECSPIs | ||
455 | + */ | ||
456 | for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { | ||
457 | static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = { | ||
458 | FSL_IMX6UL_ECSPI1_ADDR, | ||
459 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
460 | } | ||
461 | |||
462 | /* | ||
463 | - * I2C | ||
464 | + * I2Cs | ||
465 | */ | ||
466 | for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { | ||
467 | static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = { | ||
468 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
469 | } | ||
470 | |||
471 | /* | ||
472 | - * UART | ||
473 | + * UARTs | ||
474 | */ | ||
475 | for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) { | ||
476 | static const hwaddr FSL_IMX6UL_UARTn_ADDR[FSL_IMX6UL_NUM_UARTS] = { | ||
477 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
478 | } | ||
479 | |||
480 | /* | ||
481 | - * Ethernet | ||
482 | + * Ethernets | ||
483 | * | ||
484 | * We must use two loops since phy_connected affects the other interface | ||
485 | * and we have to set all properties before calling sysbus_realize(). | ||
486 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
487 | FSL_IMX6UL_ENETn_TIMER_IRQ[i])); | ||
488 | } | ||
489 | |||
490 | - /* USB */ | ||
491 | + /* | ||
492 | + * USB PHYs | ||
493 | + */ | ||
494 | for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) { | ||
495 | + static const hwaddr | ||
496 | + FSL_IMX6UL_USB_PHYn_ADDR[FSL_IMX6UL_NUM_USB_PHYS] = { | ||
497 | + FSL_IMX6UL_USBPHY1_ADDR, | ||
498 | + FSL_IMX6UL_USBPHY2_ADDR, | ||
499 | + }; | ||
500 | + | ||
501 | sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort); | ||
502 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0, | ||
503 | - FSL_IMX6UL_USBPHY1_ADDR + i * 0x1000); | ||
504 | + FSL_IMX6UL_USB_PHYn_ADDR[i]); | ||
505 | } | ||
506 | |||
507 | + /* | ||
508 | + * USBs | ||
509 | + */ | ||
510 | for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) { | ||
511 | + static const hwaddr FSL_IMX6UL_USB02_USBn_ADDR[FSL_IMX6UL_NUM_USBS] = { | ||
512 | + FSL_IMX6UL_USBO2_USB1_ADDR, | ||
513 | + FSL_IMX6UL_USBO2_USB2_ADDR, | ||
514 | + }; | ||
515 | + | ||
516 | static const int FSL_IMX6UL_USBn_IRQ[] = { | ||
517 | FSL_IMX6UL_USB1_IRQ, | ||
518 | FSL_IMX6UL_USB2_IRQ, | ||
519 | }; | ||
520 | + | ||
521 | sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort); | ||
522 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, | ||
523 | - FSL_IMX6UL_USBO2_USB_ADDR + i * 0x200); | ||
524 | + FSL_IMX6UL_USB02_USBn_ADDR[i]); | ||
525 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, | ||
526 | qdev_get_gpio_in(DEVICE(&s->a7mpcore), | ||
527 | FSL_IMX6UL_USBn_IRQ[i])); | ||
528 | } | ||
529 | |||
530 | /* | ||
531 | - * USDHC | ||
532 | + * USDHCs | ||
533 | */ | ||
534 | for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) { | ||
535 | static const hwaddr FSL_IMX6UL_USDHCn_ADDR[FSL_IMX6UL_NUM_USDHCS] = { | ||
536 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
537 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6UL_SNVS_HP_ADDR); | ||
538 | |||
539 | /* | ||
540 | - * Watchdog | ||
541 | + * Watchdogs | ||
542 | */ | ||
543 | for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) { | ||
544 | static const hwaddr FSL_IMX6UL_WDOGn_ADDR[FSL_IMX6UL_NUM_WDTS] = { | ||
545 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
546 | FSL_IMX6UL_WDOG2_ADDR, | ||
547 | FSL_IMX6UL_WDOG3_ADDR, | ||
548 | }; | ||
549 | + | ||
550 | static const int FSL_IMX6UL_WDOGn_IRQ[FSL_IMX6UL_NUM_WDTS] = { | ||
551 | FSL_IMX6UL_WDOG1_IRQ, | ||
552 | FSL_IMX6UL_WDOG2_IRQ, | ||
553 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
554 | /* | ||
555 | * SDMA | ||
556 | */ | ||
557 | - create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, 0x4000); | ||
558 | + create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, | ||
559 | + FSL_IMX6UL_SDMA_SIZE); | ||
560 | |||
561 | /* | ||
562 | - * SAI (Audio SSI (Synchronous Serial Interface)) | ||
563 | + * SAIs (Audio SSI (Synchronous Serial Interface)) | ||
564 | */ | ||
565 | - create_unimplemented_device("sai1", FSL_IMX6UL_SAI1_ADDR, 0x4000); | ||
566 | - create_unimplemented_device("sai2", FSL_IMX6UL_SAI2_ADDR, 0x4000); | ||
567 | - create_unimplemented_device("sai3", FSL_IMX6UL_SAI3_ADDR, 0x4000); | ||
568 | + for (i = 0; i < FSL_IMX6UL_NUM_SAIS; i++) { | ||
569 | + static const hwaddr FSL_IMX6UL_SAIn_ADDR[FSL_IMX6UL_NUM_SAIS] = { | ||
570 | + FSL_IMX6UL_SAI1_ADDR, | ||
571 | + FSL_IMX6UL_SAI2_ADDR, | ||
572 | + FSL_IMX6UL_SAI3_ADDR, | ||
573 | + }; | ||
574 | + | ||
575 | + snprintf(name, NAME_SIZE, "sai%d", i); | ||
576 | + create_unimplemented_device(name, FSL_IMX6UL_SAIn_ADDR[i], | ||
577 | + FSL_IMX6UL_SAIn_SIZE); | ||
578 | + } | ||
579 | |||
580 | /* | ||
581 | - * PWM | ||
582 | + * PWMs | ||
583 | */ | ||
584 | - create_unimplemented_device("pwm1", FSL_IMX6UL_PWM1_ADDR, 0x4000); | ||
585 | - create_unimplemented_device("pwm2", FSL_IMX6UL_PWM2_ADDR, 0x4000); | ||
586 | - create_unimplemented_device("pwm3", FSL_IMX6UL_PWM3_ADDR, 0x4000); | ||
587 | - create_unimplemented_device("pwm4", FSL_IMX6UL_PWM4_ADDR, 0x4000); | ||
588 | + for (i = 0; i < FSL_IMX6UL_NUM_PWMS; i++) { | ||
589 | + static const hwaddr FSL_IMX6UL_PWMn_ADDR[FSL_IMX6UL_NUM_PWMS] = { | ||
590 | + FSL_IMX6UL_PWM1_ADDR, | ||
591 | + FSL_IMX6UL_PWM2_ADDR, | ||
592 | + FSL_IMX6UL_PWM3_ADDR, | ||
593 | + FSL_IMX6UL_PWM4_ADDR, | ||
594 | + }; | ||
595 | + | ||
596 | + snprintf(name, NAME_SIZE, "pwm%d", i); | ||
597 | + create_unimplemented_device(name, FSL_IMX6UL_PWMn_ADDR[i], | ||
598 | + FSL_IMX6UL_PWMn_SIZE); | ||
599 | + } | ||
600 | |||
601 | /* | ||
602 | * Audio ASRC (asynchronous sample rate converter) | ||
603 | */ | ||
604 | - create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR, 0x4000); | ||
605 | + create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR, | ||
606 | + FSL_IMX6UL_ASRC_SIZE); | ||
607 | |||
608 | /* | ||
609 | - * CAN | ||
610 | + * CANs | ||
611 | */ | ||
612 | - create_unimplemented_device("can1", FSL_IMX6UL_CAN1_ADDR, 0x4000); | ||
613 | - create_unimplemented_device("can2", FSL_IMX6UL_CAN2_ADDR, 0x4000); | ||
614 | + for (i = 0; i < FSL_IMX6UL_NUM_CANS; i++) { | ||
615 | + static const hwaddr FSL_IMX6UL_CANn_ADDR[FSL_IMX6UL_NUM_CANS] = { | ||
616 | + FSL_IMX6UL_CAN1_ADDR, | ||
617 | + FSL_IMX6UL_CAN2_ADDR, | ||
618 | + }; | ||
619 | + | ||
620 | + snprintf(name, NAME_SIZE, "can%d", i); | ||
621 | + create_unimplemented_device(name, FSL_IMX6UL_CANn_ADDR[i], | ||
622 | + FSL_IMX6UL_CANn_SIZE); | ||
623 | + } | ||
624 | |||
625 | /* | ||
626 | * APHB_DMA | ||
627 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
628 | }; | ||
629 | |||
630 | snprintf(name, NAME_SIZE, "adc%d", i); | ||
631 | - create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i], 0x4000); | ||
632 | + create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i], | ||
633 | + FSL_IMX6UL_ADCn_SIZE); | ||
634 | } | ||
635 | |||
636 | /* | ||
637 | * LCD | ||
638 | */ | ||
639 | - create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, 0x4000); | ||
640 | + create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, | ||
641 | + FSL_IMX6UL_LCDIF_SIZE); | ||
642 | |||
643 | /* | ||
644 | * ROM memory | ||
30 | -- | 645 | -- |
31 | 2.7.4 | 646 | 2.34.1 |
32 | |||
33 | diff view generated by jsdifflib |
1 | From: Krzysztof Kozlowski <krzk@kernel.org> | 1 | From: Jean-Christophe Dubois <jcd@tribudubois.net> |
---|---|---|---|
2 | 2 | ||
3 | Statements under 'case' were in some places wrongly indented bringing | 3 | * Add TZASC as unimplemented device. |
4 | confusion and making the code less readable. Remove also few unneeded | 4 | - Allow bare metal application to access this (unimplemented) device |
5 | blank lines. No functional changes. | 5 | * Add CSU as unimplemented device. |
6 | - Allow bare metal application to access this (unimplemented) device | ||
7 | * Add 4 missing PWM devices | ||
6 | 8 | ||
7 | Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> | 9 | Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> |
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
9 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 11 | Message-id: 59e4dc56e14eccfefd379275ec19048dff9c10b3.1692964892.git.jcd@tribudubois.net |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 13 | --- |
12 | hw/timer/exynos4210_mct.c | 45 ++++++++++++++++++++------------------------- | 14 | include/hw/arm/fsl-imx6ul.h | 2 +- |
13 | 1 file changed, 20 insertions(+), 25 deletions(-) | 15 | hw/arm/fsl-imx6ul.c | 16 ++++++++++++++++ |
16 | 2 files changed, 17 insertions(+), 1 deletion(-) | ||
14 | 17 | ||
15 | diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c | 18 | diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h |
16 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/timer/exynos4210_mct.c | 20 | --- a/include/hw/arm/fsl-imx6ul.h |
18 | +++ b/hw/timer/exynos4210_mct.c | 21 | +++ b/include/hw/arm/fsl-imx6ul.h |
19 | @@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_mct_read(void *opaque, hwaddr offset, | 22 | @@ -XXX,XX +XXX,XX @@ enum FslIMX6ULConfiguration { |
20 | 23 | FSL_IMX6UL_NUM_USBS = 2, | |
21 | case G_COMP_L(0): case G_COMP_L(1): case G_COMP_L(2): case G_COMP_L(3): | 24 | FSL_IMX6UL_NUM_SAIS = 3, |
22 | case G_COMP_U(0): case G_COMP_U(1): case G_COMP_U(2): case G_COMP_U(3): | 25 | FSL_IMX6UL_NUM_CANS = 2, |
23 | - index = GET_G_COMP_IDX(offset); | 26 | - FSL_IMX6UL_NUM_PWMS = 4, |
24 | - shift = 8 * (offset & 0x4); | 27 | + FSL_IMX6UL_NUM_PWMS = 8, |
25 | - value = UINT32_MAX & (s->g_timer.reg.comp[index] >> shift); | 28 | }; |
26 | + index = GET_G_COMP_IDX(offset); | 29 | |
27 | + shift = 8 * (offset & 0x4); | 30 | struct FslIMX6ULState { |
28 | + value = UINT32_MAX & (s->g_timer.reg.comp[index] >> shift); | 31 | diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c |
29 | break; | 32 | index XXXXXXX..XXXXXXX 100644 |
30 | 33 | --- a/hw/arm/fsl-imx6ul.c | |
31 | case G_TCON: | 34 | +++ b/hw/arm/fsl-imx6ul.c |
32 | @@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_mct_read(void *opaque, hwaddr offset, | 35 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) |
33 | lt_i = GET_L_TIMER_IDX(offset); | 36 | FSL_IMX6UL_PWM2_ADDR, |
34 | 37 | FSL_IMX6UL_PWM3_ADDR, | |
35 | value = exynos4210_lfrc_get_count(&s->l_timer[lt_i]); | 38 | FSL_IMX6UL_PWM4_ADDR, |
36 | - | 39 | + FSL_IMX6UL_PWM5_ADDR, |
37 | break; | 40 | + FSL_IMX6UL_PWM6_ADDR, |
38 | 41 | + FSL_IMX6UL_PWM7_ADDR, | |
39 | case L0_TCON: case L1_TCON: | 42 | + FSL_IMX6UL_PWM8_ADDR, |
40 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, | 43 | }; |
41 | 44 | ||
42 | case G_COMP_L(0): case G_COMP_L(1): case G_COMP_L(2): case G_COMP_L(3): | 45 | snprintf(name, NAME_SIZE, "pwm%d", i); |
43 | case G_COMP_U(0): case G_COMP_U(1): case G_COMP_U(2): case G_COMP_U(3): | 46 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) |
44 | - index = GET_G_COMP_IDX(offset); | 47 | create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, |
45 | - shift = 8 * (offset & 0x4); | 48 | FSL_IMX6UL_LCDIF_SIZE); |
46 | - s->g_timer.reg.comp[index] = | 49 | |
47 | - (s->g_timer.reg.comp[index] & | 50 | + /* |
48 | - (((uint64_t)UINT32_MAX << 32) >> shift)) + | 51 | + * CSU |
49 | - (value << shift); | 52 | + */ |
50 | + index = GET_G_COMP_IDX(offset); | 53 | + create_unimplemented_device("csu", FSL_IMX6UL_CSU_ADDR, |
51 | + shift = 8 * (offset & 0x4); | 54 | + FSL_IMX6UL_CSU_SIZE); |
52 | + s->g_timer.reg.comp[index] = | 55 | + |
53 | + (s->g_timer.reg.comp[index] & | 56 | + /* |
54 | + (((uint64_t)UINT32_MAX << 32) >> shift)) + | 57 | + * TZASC |
55 | + (value << shift); | 58 | + */ |
56 | 59 | + create_unimplemented_device("tzasc", FSL_IMX6UL_TZASC_ADDR, | |
57 | - DPRINTF("comparator %d write 0x%llx val << %d\n", index, value, shift); | 60 | + FSL_IMX6UL_TZASC_SIZE); |
58 | + DPRINTF("comparator %d write 0x%llx val << %d\n", index, value, shift); | 61 | + |
59 | 62 | /* | |
60 | - if (offset & 0x4) { | 63 | * ROM memory |
61 | - s->g_timer.reg.wstat |= G_WSTAT_COMP_U(index); | 64 | */ |
62 | - } else { | ||
63 | - s->g_timer.reg.wstat |= G_WSTAT_COMP_L(index); | ||
64 | - } | ||
65 | + if (offset & 0x4) { | ||
66 | + s->g_timer.reg.wstat |= G_WSTAT_COMP_U(index); | ||
67 | + } else { | ||
68 | + s->g_timer.reg.wstat |= G_WSTAT_COMP_L(index); | ||
69 | + } | ||
70 | |||
71 | - exynos4210_gfrc_restart(s); | ||
72 | - break; | ||
73 | + exynos4210_gfrc_restart(s); | ||
74 | + break; | ||
75 | |||
76 | case G_TCON: | ||
77 | old_val = s->g_timer.reg.tcon; | ||
78 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, | ||
79 | break; | ||
80 | |||
81 | case G_INT_ENB: | ||
82 | - | ||
83 | /* Raise IRQ if transition from disabled to enabled and CSTAT pending */ | ||
84 | for (i = 0; i < MCT_GT_CMP_NUM; i++) { | ||
85 | if ((value & G_INT_ENABLE(i)) > (s->g_timer.reg.tcon & | ||
86 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, | ||
87 | break; | ||
88 | |||
89 | case L0_TCNTB: case L1_TCNTB: | ||
90 | - | ||
91 | lt_i = GET_L_TIMER_IDX(offset); | ||
92 | index = GET_L_TIMER_CNT_REG_IDX(offset, lt_i); | ||
93 | |||
94 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, | ||
95 | break; | ||
96 | |||
97 | case L0_ICNTB: case L1_ICNTB: | ||
98 | - | ||
99 | lt_i = GET_L_TIMER_IDX(offset); | ||
100 | index = GET_L_TIMER_CNT_REG_IDX(offset, lt_i); | ||
101 | |||
102 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, | ||
103 | if (icntb_max[lt_i] < value) { | ||
104 | icntb_max[lt_i] = value; | ||
105 | } | ||
106 | -DPRINTF("local timer[%d] ICNTB write %llx; max=%x, min=%x\n\n", | ||
107 | - lt_i, value, icntb_max[lt_i], icntb_min[lt_i]); | ||
108 | + DPRINTF("local timer[%d] ICNTB write %llx; max=%x, min=%x\n\n", | ||
109 | + lt_i, value, icntb_max[lt_i], icntb_min[lt_i]); | ||
110 | #endif | ||
111 | -break; | ||
112 | + break; | ||
113 | |||
114 | case L0_FRCNTB: case L1_FRCNTB: | ||
115 | - | ||
116 | lt_i = GET_L_TIMER_IDX(offset); | ||
117 | index = GET_L_TIMER_CNT_REG_IDX(offset, lt_i); | ||
118 | |||
119 | -- | 65 | -- |
120 | 2.7.4 | 66 | 2.34.1 |
121 | 67 | ||
122 | 68 | diff view generated by jsdifflib |
1 | From: Eric Auger <eric.auger@redhat.com> | 1 | From: Jean-Christophe Dubois <jcd@tribudubois.net> |
---|---|---|---|
2 | 2 | ||
3 | This patch adds the flush of the LPI pending bits into the | 3 | * Add Addr and size definition for all i.MX7 devices in i.MX7 header file. |
4 | redistributor pending tables. This happens on VM stop. | 4 | * Use those newly defined named constants whenever possible. |
5 | * Standardize the way we init a familly of unimplemented devices | ||
6 | - SAI | ||
7 | - PWM | ||
8 | - CAN | ||
9 | * Add/rework few comments | ||
5 | 10 | ||
6 | There is no explicit restore as the tables are implicitly sync'ed | 11 | Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> |
7 | on ITS table restore and on LPI enable at redistributor level. | 12 | Message-id: 59e195d33e4d486a8d131392acd46633c8c10ed7.1692964892.git.jcd@tribudubois.net |
8 | |||
9 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | ||
10 | Message-id: 1497023553-18411-4-git-send-email-eric.auger@redhat.com | ||
11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 15 | --- |
14 | hw/intc/arm_gicv3_kvm.c | 34 ++++++++++++++++++++++++++++++++++ | 16 | include/hw/arm/fsl-imx7.h | 330 ++++++++++++++++++++++++++++---------- |
15 | 1 file changed, 34 insertions(+) | 17 | hw/arm/fsl-imx7.c | 130 ++++++++++----- |
18 | 2 files changed, 335 insertions(+), 125 deletions(-) | ||
16 | 19 | ||
17 | diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c | 20 | diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h |
18 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/hw/intc/arm_gicv3_kvm.c | 22 | --- a/include/hw/arm/fsl-imx7.h |
20 | +++ b/hw/intc/arm_gicv3_kvm.c | 23 | +++ b/include/hw/arm/fsl-imx7.h |
21 | @@ -XXX,XX +XXX,XX @@ | 24 | @@ -XXX,XX +XXX,XX @@ |
22 | #include "hw/sysbus.h" | 25 | #include "hw/misc/imx7_ccm.h" |
23 | #include "qemu/error-report.h" | 26 | #include "hw/misc/imx7_snvs.h" |
24 | #include "sysemu/kvm.h" | 27 | #include "hw/misc/imx7_gpr.h" |
25 | +#include "sysemu/sysemu.h" | 28 | -#include "hw/misc/imx6_src.h" |
26 | #include "kvm_arm.h" | 29 | #include "hw/watchdog/wdt_imx2.h" |
27 | #include "gicv3_internal.h" | 30 | #include "hw/gpio/imx_gpio.h" |
28 | #include "vgic_common.h" | 31 | #include "hw/char/imx_serial.h" |
29 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = { | 32 | @@ -XXX,XX +XXX,XX @@ |
30 | REGINFO_SENTINEL | 33 | #include "hw/usb/chipidea.h" |
34 | #include "cpu.h" | ||
35 | #include "qom/object.h" | ||
36 | +#include "qemu/units.h" | ||
37 | |||
38 | #define TYPE_FSL_IMX7 "fsl-imx7" | ||
39 | OBJECT_DECLARE_SIMPLE_TYPE(FslIMX7State, FSL_IMX7) | ||
40 | @@ -XXX,XX +XXX,XX @@ enum FslIMX7Configuration { | ||
41 | FSL_IMX7_NUM_ECSPIS = 4, | ||
42 | FSL_IMX7_NUM_USBS = 3, | ||
43 | FSL_IMX7_NUM_ADCS = 2, | ||
44 | + FSL_IMX7_NUM_SAIS = 3, | ||
45 | + FSL_IMX7_NUM_CANS = 2, | ||
46 | + FSL_IMX7_NUM_PWMS = 4, | ||
31 | }; | 47 | }; |
32 | 48 | ||
33 | +/** | 49 | struct FslIMX7State { |
34 | + * vm_change_state_handler - VM change state callback aiming at flushing | 50 | @@ -XXX,XX +XXX,XX @@ struct FslIMX7State { |
35 | + * RDIST pending tables into guest RAM | 51 | |
36 | + * | 52 | enum FslIMX7MemoryMap { |
37 | + * The tables get flushed to guest RAM whenever the VM gets stopped. | 53 | FSL_IMX7_MMDC_ADDR = 0x80000000, |
38 | + */ | 54 | - FSL_IMX7_MMDC_SIZE = 2 * 1024 * 1024 * 1024UL, |
39 | +static void vm_change_state_handler(void *opaque, int running, | 55 | + FSL_IMX7_MMDC_SIZE = (2 * GiB), |
40 | + RunState state) | 56 | |
41 | +{ | 57 | - FSL_IMX7_GPIO1_ADDR = 0x30200000, |
42 | + GICv3State *s = (GICv3State *)opaque; | 58 | - FSL_IMX7_GPIO2_ADDR = 0x30210000, |
43 | + Error *err = NULL; | 59 | - FSL_IMX7_GPIO3_ADDR = 0x30220000, |
44 | + int ret; | 60 | - FSL_IMX7_GPIO4_ADDR = 0x30230000, |
45 | + | 61 | - FSL_IMX7_GPIO5_ADDR = 0x30240000, |
46 | + if (running) { | 62 | - FSL_IMX7_GPIO6_ADDR = 0x30250000, |
47 | + return; | 63 | - FSL_IMX7_GPIO7_ADDR = 0x30260000, |
64 | + FSL_IMX7_QSPI1_MEM_ADDR = 0x60000000, | ||
65 | + FSL_IMX7_QSPI1_MEM_SIZE = (256 * MiB), | ||
66 | |||
67 | - FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000, | ||
68 | + FSL_IMX7_PCIE1_MEM_ADDR = 0x40000000, | ||
69 | + FSL_IMX7_PCIE1_MEM_SIZE = (256 * MiB), | ||
70 | |||
71 | - FSL_IMX7_WDOG1_ADDR = 0x30280000, | ||
72 | - FSL_IMX7_WDOG2_ADDR = 0x30290000, | ||
73 | - FSL_IMX7_WDOG3_ADDR = 0x302A0000, | ||
74 | - FSL_IMX7_WDOG4_ADDR = 0x302B0000, | ||
75 | + FSL_IMX7_QSPI1_RX_BUF_ADDR = 0x34000000, | ||
76 | + FSL_IMX7_QSPI1_RX_BUF_SIZE = (32 * MiB), | ||
77 | |||
78 | - FSL_IMX7_IOMUXC_LPSR_ADDR = 0x302C0000, | ||
79 | + /* PCIe Peripherals */ | ||
80 | + FSL_IMX7_PCIE_REG_ADDR = 0x33800000, | ||
81 | |||
82 | - FSL_IMX7_GPT1_ADDR = 0x302D0000, | ||
83 | - FSL_IMX7_GPT2_ADDR = 0x302E0000, | ||
84 | - FSL_IMX7_GPT3_ADDR = 0x302F0000, | ||
85 | - FSL_IMX7_GPT4_ADDR = 0x30300000, | ||
86 | + /* MMAP Peripherals */ | ||
87 | + FSL_IMX7_DMA_APBH_ADDR = 0x33000000, | ||
88 | + FSL_IMX7_DMA_APBH_SIZE = 0x8000, | ||
89 | |||
90 | - FSL_IMX7_IOMUXC_ADDR = 0x30330000, | ||
91 | - FSL_IMX7_IOMUXC_GPR_ADDR = 0x30340000, | ||
92 | - FSL_IMX7_IOMUXCn_SIZE = 0x1000, | ||
93 | + /* GPV configuration */ | ||
94 | + FSL_IMX7_GPV6_ADDR = 0x32600000, | ||
95 | + FSL_IMX7_GPV5_ADDR = 0x32500000, | ||
96 | + FSL_IMX7_GPV4_ADDR = 0x32400000, | ||
97 | + FSL_IMX7_GPV3_ADDR = 0x32300000, | ||
98 | + FSL_IMX7_GPV2_ADDR = 0x32200000, | ||
99 | + FSL_IMX7_GPV1_ADDR = 0x32100000, | ||
100 | + FSL_IMX7_GPV0_ADDR = 0x32000000, | ||
101 | + FSL_IMX7_GPVn_SIZE = (1 * MiB), | ||
102 | |||
103 | - FSL_IMX7_OCOTP_ADDR = 0x30350000, | ||
104 | - FSL_IMX7_OCOTP_SIZE = 0x10000, | ||
105 | + /* Arm Peripherals */ | ||
106 | + FSL_IMX7_A7MPCORE_ADDR = 0x31000000, | ||
107 | |||
108 | - FSL_IMX7_ANALOG_ADDR = 0x30360000, | ||
109 | - FSL_IMX7_SNVS_ADDR = 0x30370000, | ||
110 | - FSL_IMX7_CCM_ADDR = 0x30380000, | ||
111 | + /* AIPS-3 Begin */ | ||
112 | |||
113 | - FSL_IMX7_SRC_ADDR = 0x30390000, | ||
114 | - FSL_IMX7_SRC_SIZE = 0x1000, | ||
115 | + FSL_IMX7_ENET2_ADDR = 0x30BF0000, | ||
116 | + FSL_IMX7_ENET1_ADDR = 0x30BE0000, | ||
117 | |||
118 | - FSL_IMX7_ADC1_ADDR = 0x30610000, | ||
119 | - FSL_IMX7_ADC2_ADDR = 0x30620000, | ||
120 | - FSL_IMX7_ADCn_SIZE = 0x1000, | ||
121 | + FSL_IMX7_SDMA_ADDR = 0x30BD0000, | ||
122 | + FSL_IMX7_SDMA_SIZE = (4 * KiB), | ||
123 | |||
124 | - FSL_IMX7_PWM1_ADDR = 0x30660000, | ||
125 | - FSL_IMX7_PWM2_ADDR = 0x30670000, | ||
126 | - FSL_IMX7_PWM3_ADDR = 0x30680000, | ||
127 | - FSL_IMX7_PWM4_ADDR = 0x30690000, | ||
128 | - FSL_IMX7_PWMn_SIZE = 0x10000, | ||
129 | + FSL_IMX7_EIM_ADDR = 0x30BC0000, | ||
130 | + FSL_IMX7_EIM_SIZE = (4 * KiB), | ||
131 | |||
132 | - FSL_IMX7_PCIE_PHY_ADDR = 0x306D0000, | ||
133 | - FSL_IMX7_PCIE_PHY_SIZE = 0x10000, | ||
134 | + FSL_IMX7_QSPI_ADDR = 0x30BB0000, | ||
135 | + FSL_IMX7_QSPI_SIZE = 0x8000, | ||
136 | |||
137 | - FSL_IMX7_GPC_ADDR = 0x303A0000, | ||
138 | + FSL_IMX7_SIM2_ADDR = 0x30BA0000, | ||
139 | + FSL_IMX7_SIM1_ADDR = 0x30B90000, | ||
140 | + FSL_IMX7_SIMn_SIZE = (4 * KiB), | ||
141 | + | ||
142 | + FSL_IMX7_USDHC3_ADDR = 0x30B60000, | ||
143 | + FSL_IMX7_USDHC2_ADDR = 0x30B50000, | ||
144 | + FSL_IMX7_USDHC1_ADDR = 0x30B40000, | ||
145 | + | ||
146 | + FSL_IMX7_USB3_ADDR = 0x30B30000, | ||
147 | + FSL_IMX7_USBMISC3_ADDR = 0x30B30200, | ||
148 | + FSL_IMX7_USB2_ADDR = 0x30B20000, | ||
149 | + FSL_IMX7_USBMISC2_ADDR = 0x30B20200, | ||
150 | + FSL_IMX7_USB1_ADDR = 0x30B10000, | ||
151 | + FSL_IMX7_USBMISC1_ADDR = 0x30B10200, | ||
152 | + FSL_IMX7_USBMISCn_SIZE = 0x200, | ||
153 | + | ||
154 | + FSL_IMX7_USB_PL301_ADDR = 0x30AD0000, | ||
155 | + FSL_IMX7_USB_PL301_SIZE = (64 * KiB), | ||
156 | + | ||
157 | + FSL_IMX7_SEMAPHORE_HS_ADDR = 0x30AC0000, | ||
158 | + FSL_IMX7_SEMAPHORE_HS_SIZE = (64 * KiB), | ||
159 | + | ||
160 | + FSL_IMX7_MUB_ADDR = 0x30AB0000, | ||
161 | + FSL_IMX7_MUA_ADDR = 0x30AA0000, | ||
162 | + FSL_IMX7_MUn_SIZE = (KiB), | ||
163 | + | ||
164 | + FSL_IMX7_UART7_ADDR = 0x30A90000, | ||
165 | + FSL_IMX7_UART6_ADDR = 0x30A80000, | ||
166 | + FSL_IMX7_UART5_ADDR = 0x30A70000, | ||
167 | + FSL_IMX7_UART4_ADDR = 0x30A60000, | ||
168 | + | ||
169 | + FSL_IMX7_I2C4_ADDR = 0x30A50000, | ||
170 | + FSL_IMX7_I2C3_ADDR = 0x30A40000, | ||
171 | + FSL_IMX7_I2C2_ADDR = 0x30A30000, | ||
172 | + FSL_IMX7_I2C1_ADDR = 0x30A20000, | ||
173 | + | ||
174 | + FSL_IMX7_CAN2_ADDR = 0x30A10000, | ||
175 | + FSL_IMX7_CAN1_ADDR = 0x30A00000, | ||
176 | + FSL_IMX7_CANn_SIZE = (4 * KiB), | ||
177 | + | ||
178 | + FSL_IMX7_AIPS3_CONF_ADDR = 0x309F0000, | ||
179 | + FSL_IMX7_AIPS3_CONF_SIZE = (64 * KiB), | ||
180 | |||
181 | FSL_IMX7_CAAM_ADDR = 0x30900000, | ||
182 | - FSL_IMX7_CAAM_SIZE = 0x40000, | ||
183 | + FSL_IMX7_CAAM_SIZE = (256 * KiB), | ||
184 | |||
185 | - FSL_IMX7_CAN1_ADDR = 0x30A00000, | ||
186 | - FSL_IMX7_CAN2_ADDR = 0x30A10000, | ||
187 | - FSL_IMX7_CANn_SIZE = 0x10000, | ||
188 | + FSL_IMX7_SPBA_ADDR = 0x308F0000, | ||
189 | + FSL_IMX7_SPBA_SIZE = (4 * KiB), | ||
190 | |||
191 | - FSL_IMX7_I2C1_ADDR = 0x30A20000, | ||
192 | - FSL_IMX7_I2C2_ADDR = 0x30A30000, | ||
193 | - FSL_IMX7_I2C3_ADDR = 0x30A40000, | ||
194 | - FSL_IMX7_I2C4_ADDR = 0x30A50000, | ||
195 | + FSL_IMX7_SAI3_ADDR = 0x308C0000, | ||
196 | + FSL_IMX7_SAI2_ADDR = 0x308B0000, | ||
197 | + FSL_IMX7_SAI1_ADDR = 0x308A0000, | ||
198 | + FSL_IMX7_SAIn_SIZE = (4 * KiB), | ||
199 | |||
200 | - FSL_IMX7_ECSPI1_ADDR = 0x30820000, | ||
201 | - FSL_IMX7_ECSPI2_ADDR = 0x30830000, | ||
202 | - FSL_IMX7_ECSPI3_ADDR = 0x30840000, | ||
203 | - FSL_IMX7_ECSPI4_ADDR = 0x30630000, | ||
204 | - | ||
205 | - FSL_IMX7_LCDIF_ADDR = 0x30730000, | ||
206 | - FSL_IMX7_LCDIF_SIZE = 0x1000, | ||
207 | - | ||
208 | - FSL_IMX7_UART1_ADDR = 0x30860000, | ||
209 | + FSL_IMX7_UART3_ADDR = 0x30880000, | ||
210 | /* | ||
211 | * Some versions of the reference manual claim that UART2 is @ | ||
212 | * 0x30870000, but experiments with HW + DT files in upstream | ||
213 | @@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap { | ||
214 | * actually located @ 0x30890000 | ||
215 | */ | ||
216 | FSL_IMX7_UART2_ADDR = 0x30890000, | ||
217 | - FSL_IMX7_UART3_ADDR = 0x30880000, | ||
218 | - FSL_IMX7_UART4_ADDR = 0x30A60000, | ||
219 | - FSL_IMX7_UART5_ADDR = 0x30A70000, | ||
220 | - FSL_IMX7_UART6_ADDR = 0x30A80000, | ||
221 | - FSL_IMX7_UART7_ADDR = 0x30A90000, | ||
222 | + FSL_IMX7_UART1_ADDR = 0x30860000, | ||
223 | |||
224 | - FSL_IMX7_SAI1_ADDR = 0x308A0000, | ||
225 | - FSL_IMX7_SAI2_ADDR = 0x308B0000, | ||
226 | - FSL_IMX7_SAI3_ADDR = 0x308C0000, | ||
227 | - FSL_IMX7_SAIn_SIZE = 0x10000, | ||
228 | + FSL_IMX7_ECSPI3_ADDR = 0x30840000, | ||
229 | + FSL_IMX7_ECSPI2_ADDR = 0x30830000, | ||
230 | + FSL_IMX7_ECSPI1_ADDR = 0x30820000, | ||
231 | + FSL_IMX7_ECSPIn_SIZE = (4 * KiB), | ||
232 | |||
233 | - FSL_IMX7_ENET1_ADDR = 0x30BE0000, | ||
234 | - FSL_IMX7_ENET2_ADDR = 0x30BF0000, | ||
235 | + /* AIPS-3 End */ | ||
236 | |||
237 | - FSL_IMX7_USB1_ADDR = 0x30B10000, | ||
238 | - FSL_IMX7_USBMISC1_ADDR = 0x30B10200, | ||
239 | - FSL_IMX7_USB2_ADDR = 0x30B20000, | ||
240 | - FSL_IMX7_USBMISC2_ADDR = 0x30B20200, | ||
241 | - FSL_IMX7_USB3_ADDR = 0x30B30000, | ||
242 | - FSL_IMX7_USBMISC3_ADDR = 0x30B30200, | ||
243 | - FSL_IMX7_USBMISCn_SIZE = 0x200, | ||
244 | + /* AIPS-2 Begin */ | ||
245 | |||
246 | - FSL_IMX7_USDHC1_ADDR = 0x30B40000, | ||
247 | - FSL_IMX7_USDHC2_ADDR = 0x30B50000, | ||
248 | - FSL_IMX7_USDHC3_ADDR = 0x30B60000, | ||
249 | + FSL_IMX7_AXI_DEBUG_MON_ADDR = 0x307E0000, | ||
250 | + FSL_IMX7_AXI_DEBUG_MON_SIZE = (64 * KiB), | ||
251 | |||
252 | - FSL_IMX7_SDMA_ADDR = 0x30BD0000, | ||
253 | - FSL_IMX7_SDMA_SIZE = 0x1000, | ||
254 | + FSL_IMX7_PERFMON2_ADDR = 0x307D0000, | ||
255 | + FSL_IMX7_PERFMON1_ADDR = 0x307C0000, | ||
256 | + FSL_IMX7_PERFMONn_SIZE = (64 * KiB), | ||
257 | + | ||
258 | + FSL_IMX7_DDRC_ADDR = 0x307A0000, | ||
259 | + FSL_IMX7_DDRC_SIZE = (4 * KiB), | ||
260 | + | ||
261 | + FSL_IMX7_DDRC_PHY_ADDR = 0x30790000, | ||
262 | + FSL_IMX7_DDRC_PHY_SIZE = (4 * KiB), | ||
263 | + | ||
264 | + FSL_IMX7_TZASC_ADDR = 0x30780000, | ||
265 | + FSL_IMX7_TZASC_SIZE = (64 * KiB), | ||
266 | + | ||
267 | + FSL_IMX7_MIPI_DSI_ADDR = 0x30760000, | ||
268 | + FSL_IMX7_MIPI_DSI_SIZE = (4 * KiB), | ||
269 | + | ||
270 | + FSL_IMX7_MIPI_CSI_ADDR = 0x30750000, | ||
271 | + FSL_IMX7_MIPI_CSI_SIZE = 0x4000, | ||
272 | + | ||
273 | + FSL_IMX7_LCDIF_ADDR = 0x30730000, | ||
274 | + FSL_IMX7_LCDIF_SIZE = 0x8000, | ||
275 | + | ||
276 | + FSL_IMX7_CSI_ADDR = 0x30710000, | ||
277 | + FSL_IMX7_CSI_SIZE = (4 * KiB), | ||
278 | + | ||
279 | + FSL_IMX7_PXP_ADDR = 0x30700000, | ||
280 | + FSL_IMX7_PXP_SIZE = 0x4000, | ||
281 | + | ||
282 | + FSL_IMX7_EPDC_ADDR = 0x306F0000, | ||
283 | + FSL_IMX7_EPDC_SIZE = (4 * KiB), | ||
284 | + | ||
285 | + FSL_IMX7_PCIE_PHY_ADDR = 0x306D0000, | ||
286 | + FSL_IMX7_PCIE_PHY_SIZE = (4 * KiB), | ||
287 | + | ||
288 | + FSL_IMX7_SYSCNT_CTRL_ADDR = 0x306C0000, | ||
289 | + FSL_IMX7_SYSCNT_CMP_ADDR = 0x306B0000, | ||
290 | + FSL_IMX7_SYSCNT_RD_ADDR = 0x306A0000, | ||
291 | + | ||
292 | + FSL_IMX7_PWM4_ADDR = 0x30690000, | ||
293 | + FSL_IMX7_PWM3_ADDR = 0x30680000, | ||
294 | + FSL_IMX7_PWM2_ADDR = 0x30670000, | ||
295 | + FSL_IMX7_PWM1_ADDR = 0x30660000, | ||
296 | + FSL_IMX7_PWMn_SIZE = (4 * KiB), | ||
297 | + | ||
298 | + FSL_IMX7_FlEXTIMER2_ADDR = 0x30650000, | ||
299 | + FSL_IMX7_FlEXTIMER1_ADDR = 0x30640000, | ||
300 | + FSL_IMX7_FLEXTIMERn_SIZE = (4 * KiB), | ||
301 | + | ||
302 | + FSL_IMX7_ECSPI4_ADDR = 0x30630000, | ||
303 | + | ||
304 | + FSL_IMX7_ADC2_ADDR = 0x30620000, | ||
305 | + FSL_IMX7_ADC1_ADDR = 0x30610000, | ||
306 | + FSL_IMX7_ADCn_SIZE = (4 * KiB), | ||
307 | + | ||
308 | + FSL_IMX7_AIPS2_CONF_ADDR = 0x305F0000, | ||
309 | + FSL_IMX7_AIPS2_CONF_SIZE = (64 * KiB), | ||
310 | + | ||
311 | + /* AIPS-2 End */ | ||
312 | + | ||
313 | + /* AIPS-1 Begin */ | ||
314 | + | ||
315 | + FSL_IMX7_CSU_ADDR = 0x303E0000, | ||
316 | + FSL_IMX7_CSU_SIZE = (64 * KiB), | ||
317 | + | ||
318 | + FSL_IMX7_RDC_ADDR = 0x303D0000, | ||
319 | + FSL_IMX7_RDC_SIZE = (4 * KiB), | ||
320 | + | ||
321 | + FSL_IMX7_SEMAPHORE2_ADDR = 0x303C0000, | ||
322 | + FSL_IMX7_SEMAPHORE1_ADDR = 0x303B0000, | ||
323 | + FSL_IMX7_SEMAPHOREn_SIZE = (4 * KiB), | ||
324 | + | ||
325 | + FSL_IMX7_GPC_ADDR = 0x303A0000, | ||
326 | + | ||
327 | + FSL_IMX7_SRC_ADDR = 0x30390000, | ||
328 | + FSL_IMX7_SRC_SIZE = (4 * KiB), | ||
329 | + | ||
330 | + FSL_IMX7_CCM_ADDR = 0x30380000, | ||
331 | + | ||
332 | + FSL_IMX7_SNVS_HP_ADDR = 0x30370000, | ||
333 | + | ||
334 | + FSL_IMX7_ANALOG_ADDR = 0x30360000, | ||
335 | + | ||
336 | + FSL_IMX7_OCOTP_ADDR = 0x30350000, | ||
337 | + FSL_IMX7_OCOTP_SIZE = 0x10000, | ||
338 | + | ||
339 | + FSL_IMX7_IOMUXC_GPR_ADDR = 0x30340000, | ||
340 | + FSL_IMX7_IOMUXC_GPR_SIZE = (4 * KiB), | ||
341 | + | ||
342 | + FSL_IMX7_IOMUXC_ADDR = 0x30330000, | ||
343 | + FSL_IMX7_IOMUXC_SIZE = (4 * KiB), | ||
344 | + | ||
345 | + FSL_IMX7_KPP_ADDR = 0x30320000, | ||
346 | + FSL_IMX7_KPP_SIZE = (4 * KiB), | ||
347 | + | ||
348 | + FSL_IMX7_ROMCP_ADDR = 0x30310000, | ||
349 | + FSL_IMX7_ROMCP_SIZE = (4 * KiB), | ||
350 | + | ||
351 | + FSL_IMX7_GPT4_ADDR = 0x30300000, | ||
352 | + FSL_IMX7_GPT3_ADDR = 0x302F0000, | ||
353 | + FSL_IMX7_GPT2_ADDR = 0x302E0000, | ||
354 | + FSL_IMX7_GPT1_ADDR = 0x302D0000, | ||
355 | + | ||
356 | + FSL_IMX7_IOMUXC_LPSR_ADDR = 0x302C0000, | ||
357 | + FSL_IMX7_IOMUXC_LPSR_SIZE = (4 * KiB), | ||
358 | + | ||
359 | + FSL_IMX7_WDOG4_ADDR = 0x302B0000, | ||
360 | + FSL_IMX7_WDOG3_ADDR = 0x302A0000, | ||
361 | + FSL_IMX7_WDOG2_ADDR = 0x30290000, | ||
362 | + FSL_IMX7_WDOG1_ADDR = 0x30280000, | ||
363 | + | ||
364 | + FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000, | ||
365 | + | ||
366 | + FSL_IMX7_GPIO7_ADDR = 0x30260000, | ||
367 | + FSL_IMX7_GPIO6_ADDR = 0x30250000, | ||
368 | + FSL_IMX7_GPIO5_ADDR = 0x30240000, | ||
369 | + FSL_IMX7_GPIO4_ADDR = 0x30230000, | ||
370 | + FSL_IMX7_GPIO3_ADDR = 0x30220000, | ||
371 | + FSL_IMX7_GPIO2_ADDR = 0x30210000, | ||
372 | + FSL_IMX7_GPIO1_ADDR = 0x30200000, | ||
373 | + | ||
374 | + FSL_IMX7_AIPS1_CONF_ADDR = 0x301F0000, | ||
375 | + FSL_IMX7_AIPS1_CONF_SIZE = (64 * KiB), | ||
376 | |||
377 | - FSL_IMX7_A7MPCORE_ADDR = 0x31000000, | ||
378 | FSL_IMX7_A7MPCORE_DAP_ADDR = 0x30000000, | ||
379 | + FSL_IMX7_A7MPCORE_DAP_SIZE = (1 * MiB), | ||
380 | |||
381 | - FSL_IMX7_PCIE_REG_ADDR = 0x33800000, | ||
382 | - FSL_IMX7_PCIE_REG_SIZE = 16 * 1024, | ||
383 | + /* AIPS-1 End */ | ||
384 | |||
385 | - FSL_IMX7_GPR_ADDR = 0x30340000, | ||
386 | + FSL_IMX7_EIM_CS0_ADDR = 0x28000000, | ||
387 | + FSL_IMX7_EIM_CS0_SIZE = (128 * MiB), | ||
388 | |||
389 | - FSL_IMX7_DMA_APBH_ADDR = 0x33000000, | ||
390 | - FSL_IMX7_DMA_APBH_SIZE = 0x2000, | ||
391 | + FSL_IMX7_OCRAM_PXP_ADDR = 0x00940000, | ||
392 | + FSL_IMX7_OCRAM_PXP_SIZE = (32 * KiB), | ||
393 | + | ||
394 | + FSL_IMX7_OCRAM_EPDC_ADDR = 0x00920000, | ||
395 | + FSL_IMX7_OCRAM_EPDC_SIZE = (128 * KiB), | ||
396 | + | ||
397 | + FSL_IMX7_OCRAM_MEM_ADDR = 0x00900000, | ||
398 | + FSL_IMX7_OCRAM_MEM_SIZE = (128 * KiB), | ||
399 | + | ||
400 | + FSL_IMX7_TCMU_ADDR = 0x00800000, | ||
401 | + FSL_IMX7_TCMU_SIZE = (32 * KiB), | ||
402 | + | ||
403 | + FSL_IMX7_TCML_ADDR = 0x007F8000, | ||
404 | + FSL_IMX7_TCML_SIZE = (32 * KiB), | ||
405 | + | ||
406 | + FSL_IMX7_OCRAM_S_ADDR = 0x00180000, | ||
407 | + FSL_IMX7_OCRAM_S_SIZE = (32 * KiB), | ||
408 | + | ||
409 | + FSL_IMX7_CAAM_MEM_ADDR = 0x00100000, | ||
410 | + FSL_IMX7_CAAM_MEM_SIZE = (32 * KiB), | ||
411 | + | ||
412 | + FSL_IMX7_ROM_ADDR = 0x00000000, | ||
413 | + FSL_IMX7_ROM_SIZE = (96 * KiB), | ||
414 | }; | ||
415 | |||
416 | enum FslIMX7IRQs { | ||
417 | diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c | ||
418 | index XXXXXXX..XXXXXXX 100644 | ||
419 | --- a/hw/arm/fsl-imx7.c | ||
420 | +++ b/hw/arm/fsl-imx7.c | ||
421 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj) | ||
422 | char name[NAME_SIZE]; | ||
423 | int i; | ||
424 | |||
425 | + /* | ||
426 | + * CPUs | ||
427 | + */ | ||
428 | for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX7_NUM_CPUS); i++) { | ||
429 | snprintf(name, NAME_SIZE, "cpu%d", i); | ||
430 | object_initialize_child(obj, name, &s->cpu[i], | ||
431 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj) | ||
432 | TYPE_A15MPCORE_PRIV); | ||
433 | |||
434 | /* | ||
435 | - * GPIOs 1 to 7 | ||
436 | + * GPIOs | ||
437 | */ | ||
438 | for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) { | ||
439 | snprintf(name, NAME_SIZE, "gpio%d", i); | ||
440 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj) | ||
441 | } | ||
442 | |||
443 | /* | ||
444 | - * GPT1, 2, 3, 4 | ||
445 | + * GPTs | ||
446 | */ | ||
447 | for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) { | ||
448 | snprintf(name, NAME_SIZE, "gpt%d", i); | ||
449 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj) | ||
450 | */ | ||
451 | object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2); | ||
452 | |||
453 | + /* | ||
454 | + * ECSPIs | ||
455 | + */ | ||
456 | for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) { | ||
457 | snprintf(name, NAME_SIZE, "spi%d", i + 1); | ||
458 | object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI); | ||
459 | } | ||
460 | |||
461 | - | ||
462 | + /* | ||
463 | + * I2Cs | ||
464 | + */ | ||
465 | for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) { | ||
466 | snprintf(name, NAME_SIZE, "i2c%d", i + 1); | ||
467 | object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C); | ||
468 | } | ||
469 | |||
470 | /* | ||
471 | - * UART | ||
472 | + * UARTs | ||
473 | */ | ||
474 | for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) { | ||
475 | snprintf(name, NAME_SIZE, "uart%d", i); | ||
476 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj) | ||
477 | } | ||
478 | |||
479 | /* | ||
480 | - * Ethernet | ||
481 | + * Ethernets | ||
482 | */ | ||
483 | for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) { | ||
484 | snprintf(name, NAME_SIZE, "eth%d", i); | ||
485 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj) | ||
486 | } | ||
487 | |||
488 | /* | ||
489 | - * SDHCI | ||
490 | + * SDHCIs | ||
491 | */ | ||
492 | for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) { | ||
493 | snprintf(name, NAME_SIZE, "usdhc%d", i); | ||
494 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj) | ||
495 | object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS); | ||
496 | |||
497 | /* | ||
498 | - * Watchdog | ||
499 | + * Watchdogs | ||
500 | */ | ||
501 | for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) { | ||
502 | snprintf(name, NAME_SIZE, "wdt%d", i); | ||
503 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj) | ||
504 | */ | ||
505 | object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR); | ||
506 | |||
507 | + /* | ||
508 | + * PCIE | ||
509 | + */ | ||
510 | object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST); | ||
511 | |||
512 | + /* | ||
513 | + * USBs | ||
514 | + */ | ||
515 | for (i = 0; i < FSL_IMX7_NUM_USBS; i++) { | ||
516 | snprintf(name, NAME_SIZE, "usb%d", i); | ||
517 | object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA); | ||
518 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
519 | return; | ||
520 | } | ||
521 | |||
522 | + /* | ||
523 | + * CPUs | ||
524 | + */ | ||
525 | for (i = 0; i < smp_cpus; i++) { | ||
526 | o = OBJECT(&s->cpu[i]); | ||
527 | |||
528 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
529 | * A7MPCORE DAP | ||
530 | */ | ||
531 | create_unimplemented_device("a7mpcore-dap", FSL_IMX7_A7MPCORE_DAP_ADDR, | ||
532 | - 0x100000); | ||
533 | + FSL_IMX7_A7MPCORE_DAP_SIZE); | ||
534 | |||
535 | /* | ||
536 | - * GPT1, 2, 3, 4 | ||
537 | + * GPTs | ||
538 | */ | ||
539 | for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) { | ||
540 | static const hwaddr FSL_IMX7_GPTn_ADDR[FSL_IMX7_NUM_GPTS] = { | ||
541 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
542 | FSL_IMX7_GPTn_IRQ[i])); | ||
543 | } | ||
544 | |||
545 | + /* | ||
546 | + * GPIOs | ||
547 | + */ | ||
548 | for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) { | ||
549 | static const hwaddr FSL_IMX7_GPIOn_ADDR[FSL_IMX7_NUM_GPIOS] = { | ||
550 | FSL_IMX7_GPIO1_ADDR, | ||
551 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
552 | /* | ||
553 | * IOMUXC and IOMUXC_LPSR | ||
554 | */ | ||
555 | - for (i = 0; i < FSL_IMX7_NUM_IOMUXCS; i++) { | ||
556 | - static const hwaddr FSL_IMX7_IOMUXCn_ADDR[FSL_IMX7_NUM_IOMUXCS] = { | ||
557 | - FSL_IMX7_IOMUXC_ADDR, | ||
558 | - FSL_IMX7_IOMUXC_LPSR_ADDR, | ||
559 | - }; | ||
560 | - | ||
561 | - snprintf(name, NAME_SIZE, "iomuxc%d", i); | ||
562 | - create_unimplemented_device(name, FSL_IMX7_IOMUXCn_ADDR[i], | ||
563 | - FSL_IMX7_IOMUXCn_SIZE); | ||
564 | - } | ||
565 | + create_unimplemented_device("iomuxc", FSL_IMX7_IOMUXC_ADDR, | ||
566 | + FSL_IMX7_IOMUXC_SIZE); | ||
567 | + create_unimplemented_device("iomuxc_lspr", FSL_IMX7_IOMUXC_LPSR_ADDR, | ||
568 | + FSL_IMX7_IOMUXC_LPSR_SIZE); | ||
569 | |||
570 | /* | ||
571 | * CCM | ||
572 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
573 | sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort); | ||
574 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX7_GPC_ADDR); | ||
575 | |||
576 | - /* Initialize all ECSPI */ | ||
577 | + /* | ||
578 | + * ECSPIs | ||
579 | + */ | ||
580 | for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) { | ||
581 | static const hwaddr FSL_IMX7_SPIn_ADDR[FSL_IMX7_NUM_ECSPIS] = { | ||
582 | FSL_IMX7_ECSPI1_ADDR, | ||
583 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
584 | FSL_IMX7_SPIn_IRQ[i])); | ||
585 | } | ||
586 | |||
587 | + /* | ||
588 | + * I2Cs | ||
589 | + */ | ||
590 | for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) { | ||
591 | static const hwaddr FSL_IMX7_I2Cn_ADDR[FSL_IMX7_NUM_I2CS] = { | ||
592 | FSL_IMX7_I2C1_ADDR, | ||
593 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
594 | } | ||
595 | |||
596 | /* | ||
597 | - * UART | ||
598 | + * UARTs | ||
599 | */ | ||
600 | for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) { | ||
601 | static const hwaddr FSL_IMX7_UARTn_ADDR[FSL_IMX7_NUM_UARTS] = { | ||
602 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
603 | } | ||
604 | |||
605 | /* | ||
606 | - * Ethernet | ||
607 | + * Ethernets | ||
608 | * | ||
609 | * We must use two loops since phy_connected affects the other interface | ||
610 | * and we have to set all properties before calling sysbus_realize(). | ||
611 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
612 | } | ||
613 | |||
614 | /* | ||
615 | - * USDHC | ||
616 | + * USDHCs | ||
617 | */ | ||
618 | for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) { | ||
619 | static const hwaddr FSL_IMX7_USDHCn_ADDR[FSL_IMX7_NUM_USDHCS] = { | ||
620 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
621 | * SNVS | ||
622 | */ | ||
623 | sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort); | ||
624 | - sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_ADDR); | ||
625 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_HP_ADDR); | ||
626 | |||
627 | /* | ||
628 | * SRC | ||
629 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
630 | create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZE); | ||
631 | |||
632 | /* | ||
633 | - * Watchdog | ||
634 | + * Watchdogs | ||
635 | */ | ||
636 | for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) { | ||
637 | static const hwaddr FSL_IMX7_WDOGn_ADDR[FSL_IMX7_NUM_WDTS] = { | ||
638 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
639 | create_unimplemented_device("caam", FSL_IMX7_CAAM_ADDR, FSL_IMX7_CAAM_SIZE); | ||
640 | |||
641 | /* | ||
642 | - * PWM | ||
643 | + * PWMs | ||
644 | */ | ||
645 | - create_unimplemented_device("pwm1", FSL_IMX7_PWM1_ADDR, FSL_IMX7_PWMn_SIZE); | ||
646 | - create_unimplemented_device("pwm2", FSL_IMX7_PWM2_ADDR, FSL_IMX7_PWMn_SIZE); | ||
647 | - create_unimplemented_device("pwm3", FSL_IMX7_PWM3_ADDR, FSL_IMX7_PWMn_SIZE); | ||
648 | - create_unimplemented_device("pwm4", FSL_IMX7_PWM4_ADDR, FSL_IMX7_PWMn_SIZE); | ||
649 | + for (i = 0; i < FSL_IMX7_NUM_PWMS; i++) { | ||
650 | + static const hwaddr FSL_IMX7_PWMn_ADDR[FSL_IMX7_NUM_PWMS] = { | ||
651 | + FSL_IMX7_PWM1_ADDR, | ||
652 | + FSL_IMX7_PWM2_ADDR, | ||
653 | + FSL_IMX7_PWM3_ADDR, | ||
654 | + FSL_IMX7_PWM4_ADDR, | ||
655 | + }; | ||
656 | + | ||
657 | + snprintf(name, NAME_SIZE, "pwm%d", i); | ||
658 | + create_unimplemented_device(name, FSL_IMX7_PWMn_ADDR[i], | ||
659 | + FSL_IMX7_PWMn_SIZE); | ||
48 | + } | 660 | + } |
49 | + | 661 | |
50 | + ret = kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, | 662 | /* |
51 | + KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES, | 663 | - * CAN |
52 | + NULL, true, &err); | 664 | + * CANs |
53 | + if (err) { | 665 | */ |
54 | + error_report_err(err); | 666 | - create_unimplemented_device("can1", FSL_IMX7_CAN1_ADDR, FSL_IMX7_CANn_SIZE); |
667 | - create_unimplemented_device("can2", FSL_IMX7_CAN2_ADDR, FSL_IMX7_CANn_SIZE); | ||
668 | + for (i = 0; i < FSL_IMX7_NUM_CANS; i++) { | ||
669 | + static const hwaddr FSL_IMX7_CANn_ADDR[FSL_IMX7_NUM_CANS] = { | ||
670 | + FSL_IMX7_CAN1_ADDR, | ||
671 | + FSL_IMX7_CAN2_ADDR, | ||
672 | + }; | ||
673 | + | ||
674 | + snprintf(name, NAME_SIZE, "can%d", i); | ||
675 | + create_unimplemented_device(name, FSL_IMX7_CANn_ADDR[i], | ||
676 | + FSL_IMX7_CANn_SIZE); | ||
55 | + } | 677 | + } |
56 | + if (ret < 0 && ret != -EFAULT) { | 678 | |
57 | + abort(); | 679 | /* |
680 | - * SAI (Audio SSI (Synchronous Serial Interface)) | ||
681 | + * SAIs (Audio SSI (Synchronous Serial Interface)) | ||
682 | */ | ||
683 | - create_unimplemented_device("sai1", FSL_IMX7_SAI1_ADDR, FSL_IMX7_SAIn_SIZE); | ||
684 | - create_unimplemented_device("sai2", FSL_IMX7_SAI2_ADDR, FSL_IMX7_SAIn_SIZE); | ||
685 | - create_unimplemented_device("sai2", FSL_IMX7_SAI3_ADDR, FSL_IMX7_SAIn_SIZE); | ||
686 | + for (i = 0; i < FSL_IMX7_NUM_SAIS; i++) { | ||
687 | + static const hwaddr FSL_IMX7_SAIn_ADDR[FSL_IMX7_NUM_SAIS] = { | ||
688 | + FSL_IMX7_SAI1_ADDR, | ||
689 | + FSL_IMX7_SAI2_ADDR, | ||
690 | + FSL_IMX7_SAI3_ADDR, | ||
691 | + }; | ||
692 | + | ||
693 | + snprintf(name, NAME_SIZE, "sai%d", i); | ||
694 | + create_unimplemented_device(name, FSL_IMX7_SAIn_ADDR[i], | ||
695 | + FSL_IMX7_SAIn_SIZE); | ||
58 | + } | 696 | + } |
59 | +} | 697 | |
60 | + | 698 | /* |
61 | + | 699 | * OCOTP |
62 | static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp) | 700 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) |
63 | { | 701 | create_unimplemented_device("ocotp", FSL_IMX7_OCOTP_ADDR, |
64 | GICv3State *s = KVM_ARM_GICV3(dev); | 702 | FSL_IMX7_OCOTP_SIZE); |
65 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp) | 703 | |
66 | return; | 704 | + /* |
67 | } | 705 | + * GPR |
68 | } | 706 | + */ |
69 | + if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, | 707 | sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort); |
70 | + KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES)) { | 708 | - sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_GPR_ADDR); |
71 | + qemu_add_vm_change_state_handler(vm_change_state_handler, s); | 709 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_IOMUXC_GPR_ADDR); |
72 | + } | 710 | |
711 | + /* | ||
712 | + * PCIE | ||
713 | + */ | ||
714 | sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort); | ||
715 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX7_PCIE_REG_ADDR); | ||
716 | |||
717 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
718 | irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_IRQ); | ||
719 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq); | ||
720 | |||
721 | - | ||
722 | + /* | ||
723 | + * USBs | ||
724 | + */ | ||
725 | for (i = 0; i < FSL_IMX7_NUM_USBS; i++) { | ||
726 | static const hwaddr FSL_IMX7_USBMISCn_ADDR[FSL_IMX7_NUM_USBS] = { | ||
727 | FSL_IMX7_USBMISC1_ADDR, | ||
728 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
729 | */ | ||
730 | create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR, | ||
731 | FSL_IMX7_PCIE_PHY_SIZE); | ||
732 | + | ||
73 | } | 733 | } |
74 | 734 | ||
75 | static void kvm_arm_gicv3_class_init(ObjectClass *klass, void *data) | 735 | static Property fsl_imx7_properties[] = { |
76 | -- | 736 | -- |
77 | 2.7.4 | 737 | 2.34.1 |
78 | |||
79 | diff view generated by jsdifflib |
1 | From: Cédric Le Goater <clg@kaod.org> | 1 | From: Jean-Christophe Dubois <jcd@tribudubois.net> |
---|---|---|---|
2 | 2 | ||
3 | Temperatures can be changed from the monitor with : | 3 | * Add TZASC as unimplemented device. |
4 | - Allow bare metal application to access this (unimplemented) device | ||
5 | * Add CSU as unimplemented device. | ||
6 | - Allow bare metal application to access this (unimplemented) device | ||
7 | * Add various memory segments | ||
8 | - OCRAM | ||
9 | - OCRAM EPDC | ||
10 | - OCRAM PXP | ||
11 | - OCRAM S | ||
12 | - ROM | ||
13 | - CAAM | ||
4 | 14 | ||
5 | (qemu) qom-set /machine/unattached/device[2] temperature0 12000 | 15 | Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> |
16 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
17 | Message-id: f887a3483996ba06d40bd62ffdfb0ecf68621987.1692964892.git.jcd@tribudubois.net | ||
18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
19 | --- | ||
20 | include/hw/arm/fsl-imx7.h | 7 +++++ | ||
21 | hw/arm/fsl-imx7.c | 63 +++++++++++++++++++++++++++++++++++++++ | ||
22 | 2 files changed, 70 insertions(+) | ||
6 | 23 | ||
7 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 24 | diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h |
8 | Message-id: 1496739230-32109-3-git-send-email-clg@kaod.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | hw/arm/aspeed.c | 9 +++++++++ | ||
13 | 1 file changed, 9 insertions(+) | ||
14 | |||
15 | diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/arm/aspeed.c | 26 | --- a/include/hw/arm/fsl-imx7.h |
18 | +++ b/hw/arm/aspeed.c | 27 | +++ b/include/hw/arm/fsl-imx7.h |
19 | @@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine, | 28 | @@ -XXX,XX +XXX,XX @@ struct FslIMX7State { |
20 | static void palmetto_bmc_i2c_init(AspeedBoardState *bmc) | 29 | IMX7GPRState gpr; |
21 | { | 30 | ChipideaState usb[FSL_IMX7_NUM_USBS]; |
22 | AspeedSoCState *soc = &bmc->soc; | 31 | DesignwarePCIEHost pcie; |
23 | + DeviceState *dev; | 32 | + MemoryRegion rom; |
24 | 33 | + MemoryRegion caam; | |
25 | /* The palmetto platform expects a ds3231 RTC but a ds1338 is | 34 | + MemoryRegion ocram; |
26 | * enough to provide basic RTC features. Alarms will be missing */ | 35 | + MemoryRegion ocram_epdc; |
27 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), "ds1338", 0x68); | 36 | + MemoryRegion ocram_pxp; |
37 | + MemoryRegion ocram_s; | ||
28 | + | 38 | + |
29 | + /* add a TMP423 temperature sensor */ | 39 | uint32_t phy_num[FSL_IMX7_NUM_ETHS]; |
30 | + dev = i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 2), | 40 | bool phy_connected[FSL_IMX7_NUM_ETHS]; |
31 | + "tmp423", 0x4c); | 41 | }; |
32 | + object_property_set_int(OBJECT(dev), 31000, "temperature0", &error_abort); | 42 | diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c |
33 | + object_property_set_int(OBJECT(dev), 28000, "temperature1", &error_abort); | 43 | index XXXXXXX..XXXXXXX 100644 |
34 | + object_property_set_int(OBJECT(dev), 20000, "temperature2", &error_abort); | 44 | --- a/hw/arm/fsl-imx7.c |
35 | + object_property_set_int(OBJECT(dev), 110000, "temperature3", &error_abort); | 45 | +++ b/hw/arm/fsl-imx7.c |
46 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
47 | create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR, | ||
48 | FSL_IMX7_PCIE_PHY_SIZE); | ||
49 | |||
50 | + /* | ||
51 | + * CSU | ||
52 | + */ | ||
53 | + create_unimplemented_device("csu", FSL_IMX7_CSU_ADDR, | ||
54 | + FSL_IMX7_CSU_SIZE); | ||
55 | + | ||
56 | + /* | ||
57 | + * TZASC | ||
58 | + */ | ||
59 | + create_unimplemented_device("tzasc", FSL_IMX7_TZASC_ADDR, | ||
60 | + FSL_IMX7_TZASC_SIZE); | ||
61 | + | ||
62 | + /* | ||
63 | + * OCRAM memory | ||
64 | + */ | ||
65 | + memory_region_init_ram(&s->ocram, NULL, "imx7.ocram", | ||
66 | + FSL_IMX7_OCRAM_MEM_SIZE, | ||
67 | + &error_abort); | ||
68 | + memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_MEM_ADDR, | ||
69 | + &s->ocram); | ||
70 | + | ||
71 | + /* | ||
72 | + * OCRAM EPDC memory | ||
73 | + */ | ||
74 | + memory_region_init_ram(&s->ocram_epdc, NULL, "imx7.ocram_epdc", | ||
75 | + FSL_IMX7_OCRAM_EPDC_SIZE, | ||
76 | + &error_abort); | ||
77 | + memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_EPDC_ADDR, | ||
78 | + &s->ocram_epdc); | ||
79 | + | ||
80 | + /* | ||
81 | + * OCRAM PXP memory | ||
82 | + */ | ||
83 | + memory_region_init_ram(&s->ocram_pxp, NULL, "imx7.ocram_pxp", | ||
84 | + FSL_IMX7_OCRAM_PXP_SIZE, | ||
85 | + &error_abort); | ||
86 | + memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_PXP_ADDR, | ||
87 | + &s->ocram_pxp); | ||
88 | + | ||
89 | + /* | ||
90 | + * OCRAM_S memory | ||
91 | + */ | ||
92 | + memory_region_init_ram(&s->ocram_s, NULL, "imx7.ocram_s", | ||
93 | + FSL_IMX7_OCRAM_S_SIZE, | ||
94 | + &error_abort); | ||
95 | + memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_S_ADDR, | ||
96 | + &s->ocram_s); | ||
97 | + | ||
98 | + /* | ||
99 | + * ROM memory | ||
100 | + */ | ||
101 | + memory_region_init_rom(&s->rom, OBJECT(dev), "imx7.rom", | ||
102 | + FSL_IMX7_ROM_SIZE, &error_abort); | ||
103 | + memory_region_add_subregion(get_system_memory(), FSL_IMX7_ROM_ADDR, | ||
104 | + &s->rom); | ||
105 | + | ||
106 | + /* | ||
107 | + * CAAM memory | ||
108 | + */ | ||
109 | + memory_region_init_rom(&s->caam, OBJECT(dev), "imx7.caam", | ||
110 | + FSL_IMX7_CAAM_MEM_SIZE, &error_abort); | ||
111 | + memory_region_add_subregion(get_system_memory(), FSL_IMX7_CAAM_MEM_ADDR, | ||
112 | + &s->caam); | ||
36 | } | 113 | } |
37 | 114 | ||
38 | static void palmetto_bmc_init(MachineState *machine) | 115 | static Property fsl_imx7_properties[] = { |
39 | -- | 116 | -- |
40 | 2.7.4 | 117 | 2.34.1 |
41 | 118 | ||
42 | 119 | diff view generated by jsdifflib |
1 | From: Cédric Le Goater <clg@kaod.org> | 1 | From: Jean-Christophe Dubois <jcd@tribudubois.net> |
---|---|---|---|
2 | 2 | ||
3 | Largely inspired by the TMP105 temperature sensor, here is a model for | 3 | The SRC device is normally used to start the secondary CPU. |
4 | the TMP42{1,2,3} temperature sensors. | 4 | |
5 | 5 | When running Linux directly, QEMU is emulating a PSCI interface that UBOOT | |
6 | Specs can be found here : | 6 | is installing at boot time and therefore the fact that the SRC device is |
7 | 7 | unimplemented is hidden as Qemu respond directly to PSCI requets without | |
8 | http://www.ti.com/lit/gpn/tmp421 | 8 | using the SRC device. |
9 | 9 | ||
10 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 10 | But if you try to run a more bare metal application (maybe uboot itself), |
11 | Message-id: 1496739230-32109-2-git-send-email-clg@kaod.org | 11 | then it is not possible to start the secondary CPU as the SRC is an |
12 | unimplemented device. | ||
13 | |||
14 | This patch adds the ability to start the secondary CPU through the SRC | ||
15 | device so that you can use this feature in bare metal applications. | ||
16 | |||
17 | Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> | ||
18 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
19 | Message-id: ce9a0162defd2acee5dc7f8a674743de0cded569.1692964892.git.jcd@tribudubois.net | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 20 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | --- | 21 | --- |
15 | hw/misc/Makefile.objs | 1 + | 22 | include/hw/arm/fsl-imx7.h | 3 +- |
16 | hw/misc/tmp421.c | 402 ++++++++++++++++++++++++++++++++++++++++ | 23 | include/hw/misc/imx7_src.h | 66 +++++++++ |
17 | default-configs/arm-softmmu.mak | 1 + | 24 | hw/arm/fsl-imx7.c | 8 +- |
18 | 3 files changed, 404 insertions(+) | 25 | hw/misc/imx7_src.c | 276 +++++++++++++++++++++++++++++++++++++ |
19 | create mode 100644 hw/misc/tmp421.c | 26 | hw/misc/meson.build | 1 + |
20 | 27 | hw/misc/trace-events | 4 + | |
21 | diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs | 28 | 6 files changed, 356 insertions(+), 2 deletions(-) |
29 | create mode 100644 include/hw/misc/imx7_src.h | ||
30 | create mode 100644 hw/misc/imx7_src.c | ||
31 | |||
32 | diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h | ||
22 | index XXXXXXX..XXXXXXX 100644 | 33 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/hw/misc/Makefile.objs | 34 | --- a/include/hw/arm/fsl-imx7.h |
24 | +++ b/hw/misc/Makefile.objs | 35 | +++ b/include/hw/arm/fsl-imx7.h |
25 | @@ -XXX,XX +XXX,XX @@ | 36 | @@ -XXX,XX +XXX,XX @@ |
26 | common-obj-$(CONFIG_APPLESMC) += applesmc.o | 37 | #include "hw/misc/imx7_ccm.h" |
27 | common-obj-$(CONFIG_MAX111X) += max111x.o | 38 | #include "hw/misc/imx7_snvs.h" |
28 | common-obj-$(CONFIG_TMP105) += tmp105.o | 39 | #include "hw/misc/imx7_gpr.h" |
29 | +common-obj-$(CONFIG_TMP421) += tmp421.o | 40 | +#include "hw/misc/imx7_src.h" |
30 | common-obj-$(CONFIG_ISA_DEBUG) += debugexit.o | 41 | #include "hw/watchdog/wdt_imx2.h" |
31 | common-obj-$(CONFIG_SGA) += sga.o | 42 | #include "hw/gpio/imx_gpio.h" |
32 | common-obj-$(CONFIG_ISA_TESTDEV) += pc-testdev.o | 43 | #include "hw/char/imx_serial.h" |
33 | diff --git a/hw/misc/tmp421.c b/hw/misc/tmp421.c | 44 | @@ -XXX,XX +XXX,XX @@ struct FslIMX7State { |
45 | IMX7CCMState ccm; | ||
46 | IMX7AnalogState analog; | ||
47 | IMX7SNVSState snvs; | ||
48 | + IMX7SRCState src; | ||
49 | IMXGPCv2State gpcv2; | ||
50 | IMXSPIState spi[FSL_IMX7_NUM_ECSPIS]; | ||
51 | IMXI2CState i2c[FSL_IMX7_NUM_I2CS]; | ||
52 | @@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap { | ||
53 | FSL_IMX7_GPC_ADDR = 0x303A0000, | ||
54 | |||
55 | FSL_IMX7_SRC_ADDR = 0x30390000, | ||
56 | - FSL_IMX7_SRC_SIZE = (4 * KiB), | ||
57 | |||
58 | FSL_IMX7_CCM_ADDR = 0x30380000, | ||
59 | |||
60 | diff --git a/include/hw/misc/imx7_src.h b/include/hw/misc/imx7_src.h | ||
34 | new file mode 100644 | 61 | new file mode 100644 |
35 | index XXXXXXX..XXXXXXX | 62 | index XXXXXXX..XXXXXXX |
36 | --- /dev/null | 63 | --- /dev/null |
37 | +++ b/hw/misc/tmp421.c | 64 | +++ b/include/hw/misc/imx7_src.h |
38 | @@ -XXX,XX +XXX,XX @@ | 65 | @@ -XXX,XX +XXX,XX @@ |
39 | +/* | 66 | +/* |
40 | + * Texas Instruments TMP421 temperature sensor. | 67 | + * IMX7 System Reset Controller |
41 | + * | 68 | + * |
42 | + * Copyright (c) 2016 IBM Corporation. | 69 | + * Copyright (C) 2023 Jean-Christophe Dubois <jcd@tribudubois.net> |
43 | + * | 70 | + * |
44 | + * Largely inspired by : | 71 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. |
72 | + * See the COPYING file in the top-level directory. | ||
73 | + */ | ||
74 | + | ||
75 | +#ifndef IMX7_SRC_H | ||
76 | +#define IMX7_SRC_H | ||
77 | + | ||
78 | +#include "hw/sysbus.h" | ||
79 | +#include "qemu/bitops.h" | ||
80 | +#include "qom/object.h" | ||
81 | + | ||
82 | +#define SRC_SCR 0 | ||
83 | +#define SRC_A7RCR0 1 | ||
84 | +#define SRC_A7RCR1 2 | ||
85 | +#define SRC_M4RCR 3 | ||
86 | +#define SRC_ERCR 5 | ||
87 | +#define SRC_HSICPHY_RCR 7 | ||
88 | +#define SRC_USBOPHY1_RCR 8 | ||
89 | +#define SRC_USBOPHY2_RCR 9 | ||
90 | +#define SRC_MPIPHY_RCR 10 | ||
91 | +#define SRC_PCIEPHY_RCR 11 | ||
92 | +#define SRC_SBMR1 22 | ||
93 | +#define SRC_SRSR 23 | ||
94 | +#define SRC_SISR 26 | ||
95 | +#define SRC_SIMR 27 | ||
96 | +#define SRC_SBMR2 28 | ||
97 | +#define SRC_GPR1 29 | ||
98 | +#define SRC_GPR2 30 | ||
99 | +#define SRC_GPR3 31 | ||
100 | +#define SRC_GPR4 32 | ||
101 | +#define SRC_GPR5 33 | ||
102 | +#define SRC_GPR6 34 | ||
103 | +#define SRC_GPR7 35 | ||
104 | +#define SRC_GPR8 36 | ||
105 | +#define SRC_GPR9 37 | ||
106 | +#define SRC_GPR10 38 | ||
107 | +#define SRC_MAX 39 | ||
108 | + | ||
109 | +/* SRC_A7SCR1 */ | ||
110 | +#define R_CORE1_ENABLE_SHIFT 1 | ||
111 | +#define R_CORE1_ENABLE_LENGTH 1 | ||
112 | +/* SRC_A7SCR0 */ | ||
113 | +#define R_CORE1_RST_SHIFT 5 | ||
114 | +#define R_CORE1_RST_LENGTH 1 | ||
115 | +#define R_CORE0_RST_SHIFT 4 | ||
116 | +#define R_CORE0_RST_LENGTH 1 | ||
117 | + | ||
118 | +#define TYPE_IMX7_SRC "imx7.src" | ||
119 | +OBJECT_DECLARE_SIMPLE_TYPE(IMX7SRCState, IMX7_SRC) | ||
120 | + | ||
121 | +struct IMX7SRCState { | ||
122 | + /* <private> */ | ||
123 | + SysBusDevice parent_obj; | ||
124 | + | ||
125 | + /* <public> */ | ||
126 | + MemoryRegion iomem; | ||
127 | + | ||
128 | + uint32_t regs[SRC_MAX]; | ||
129 | +}; | ||
130 | + | ||
131 | +#endif /* IMX7_SRC_H */ | ||
132 | diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c | ||
133 | index XXXXXXX..XXXXXXX 100644 | ||
134 | --- a/hw/arm/fsl-imx7.c | ||
135 | +++ b/hw/arm/fsl-imx7.c | ||
136 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj) | ||
137 | */ | ||
138 | object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2); | ||
139 | |||
140 | + /* | ||
141 | + * SRC | ||
142 | + */ | ||
143 | + object_initialize_child(obj, "src", &s->src, TYPE_IMX7_SRC); | ||
144 | + | ||
145 | /* | ||
146 | * ECSPIs | ||
147 | */ | ||
148 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
149 | /* | ||
150 | * SRC | ||
151 | */ | ||
152 | - create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZE); | ||
153 | + sysbus_realize(SYS_BUS_DEVICE(&s->src), &error_abort); | ||
154 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX7_SRC_ADDR); | ||
155 | |||
156 | /* | ||
157 | * Watchdogs | ||
158 | diff --git a/hw/misc/imx7_src.c b/hw/misc/imx7_src.c | ||
159 | new file mode 100644 | ||
160 | index XXXXXXX..XXXXXXX | ||
161 | --- /dev/null | ||
162 | +++ b/hw/misc/imx7_src.c | ||
163 | @@ -XXX,XX +XXX,XX @@ | ||
164 | +/* | ||
165 | + * IMX7 System Reset Controller | ||
45 | + * | 166 | + * |
46 | + * Texas Instruments TMP105 temperature sensor. | 167 | + * Copyright (c) 2023 Jean-Christophe Dubois <jcd@tribudubois.net> |
47 | + * | 168 | + * |
48 | + * Copyright (C) 2008 Nokia Corporation | 169 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. |
49 | + * Written by Andrzej Zaborowski <andrew@openedhand.com> | 170 | + * See the COPYING file in the top-level directory. |
50 | + * | 171 | + * |
51 | + * This program is free software; you can redistribute it and/or | ||
52 | + * modify it under the terms of the GNU General Public License as | ||
53 | + * published by the Free Software Foundation; either version 2 or | ||
54 | + * (at your option) version 3 of the License. | ||
55 | + * | ||
56 | + * This program is distributed in the hope that it will be useful, | ||
57 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
58 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
59 | + * GNU General Public License for more details. | ||
60 | + * | ||
61 | + * You should have received a copy of the GNU General Public License along | ||
62 | + * with this program; if not, see <http://www.gnu.org/licenses/>. | ||
63 | + */ | 172 | + */ |
64 | + | 173 | + |
65 | +#include "qemu/osdep.h" | 174 | +#include "qemu/osdep.h" |
66 | +#include "hw/hw.h" | 175 | +#include "hw/misc/imx7_src.h" |
67 | +#include "hw/i2c/i2c.h" | 176 | +#include "migration/vmstate.h" |
68 | +#include "qapi/error.h" | 177 | +#include "qemu/bitops.h" |
69 | +#include "qapi/visitor.h" | 178 | +#include "qemu/log.h" |
70 | + | 179 | +#include "qemu/main-loop.h" |
71 | +/* Manufacturer / Device ID's */ | 180 | +#include "qemu/module.h" |
72 | +#define TMP421_MANUFACTURER_ID 0x55 | 181 | +#include "target/arm/arm-powerctl.h" |
73 | +#define TMP421_DEVICE_ID 0x21 | 182 | +#include "hw/core/cpu.h" |
74 | +#define TMP422_DEVICE_ID 0x22 | 183 | +#include "hw/registerfields.h" |
75 | +#define TMP423_DEVICE_ID 0x23 | 184 | + |
76 | + | 185 | +#include "trace.h" |
77 | +typedef struct DeviceInfo { | 186 | + |
78 | + int model; | 187 | +static const char *imx7_src_reg_name(uint32_t reg) |
79 | + const char *name; | 188 | +{ |
80 | +} DeviceInfo; | 189 | + static char unknown[20]; |
81 | + | 190 | + |
82 | +static const DeviceInfo devices[] = { | 191 | + switch (reg) { |
83 | + { TMP421_DEVICE_ID, "tmp421" }, | 192 | + case SRC_SCR: |
84 | + { TMP422_DEVICE_ID, "tmp422" }, | 193 | + return "SRC_SCR"; |
85 | + { TMP423_DEVICE_ID, "tmp423" }, | 194 | + case SRC_A7RCR0: |
195 | + return "SRC_A7RCR0"; | ||
196 | + case SRC_A7RCR1: | ||
197 | + return "SRC_A7RCR1"; | ||
198 | + case SRC_M4RCR: | ||
199 | + return "SRC_M4RCR"; | ||
200 | + case SRC_ERCR: | ||
201 | + return "SRC_ERCR"; | ||
202 | + case SRC_HSICPHY_RCR: | ||
203 | + return "SRC_HSICPHY_RCR"; | ||
204 | + case SRC_USBOPHY1_RCR: | ||
205 | + return "SRC_USBOPHY1_RCR"; | ||
206 | + case SRC_USBOPHY2_RCR: | ||
207 | + return "SRC_USBOPHY2_RCR"; | ||
208 | + case SRC_PCIEPHY_RCR: | ||
209 | + return "SRC_PCIEPHY_RCR"; | ||
210 | + case SRC_SBMR1: | ||
211 | + return "SRC_SBMR1"; | ||
212 | + case SRC_SRSR: | ||
213 | + return "SRC_SRSR"; | ||
214 | + case SRC_SISR: | ||
215 | + return "SRC_SISR"; | ||
216 | + case SRC_SIMR: | ||
217 | + return "SRC_SIMR"; | ||
218 | + case SRC_SBMR2: | ||
219 | + return "SRC_SBMR2"; | ||
220 | + case SRC_GPR1: | ||
221 | + return "SRC_GPR1"; | ||
222 | + case SRC_GPR2: | ||
223 | + return "SRC_GPR2"; | ||
224 | + case SRC_GPR3: | ||
225 | + return "SRC_GPR3"; | ||
226 | + case SRC_GPR4: | ||
227 | + return "SRC_GPR4"; | ||
228 | + case SRC_GPR5: | ||
229 | + return "SRC_GPR5"; | ||
230 | + case SRC_GPR6: | ||
231 | + return "SRC_GPR6"; | ||
232 | + case SRC_GPR7: | ||
233 | + return "SRC_GPR7"; | ||
234 | + case SRC_GPR8: | ||
235 | + return "SRC_GPR8"; | ||
236 | + case SRC_GPR9: | ||
237 | + return "SRC_GPR9"; | ||
238 | + case SRC_GPR10: | ||
239 | + return "SRC_GPR10"; | ||
240 | + default: | ||
241 | + sprintf(unknown, "%u ?", reg); | ||
242 | + return unknown; | ||
243 | + } | ||
244 | +} | ||
245 | + | ||
246 | +static const VMStateDescription vmstate_imx7_src = { | ||
247 | + .name = TYPE_IMX7_SRC, | ||
248 | + .version_id = 1, | ||
249 | + .minimum_version_id = 1, | ||
250 | + .fields = (VMStateField[]) { | ||
251 | + VMSTATE_UINT32_ARRAY(regs, IMX7SRCState, SRC_MAX), | ||
252 | + VMSTATE_END_OF_LIST() | ||
253 | + }, | ||
86 | +}; | 254 | +}; |
87 | + | 255 | + |
88 | +typedef struct TMP421State { | 256 | +static void imx7_src_reset(DeviceState *dev) |
89 | + /*< private >*/ | 257 | +{ |
90 | + I2CSlave i2c; | 258 | + IMX7SRCState *s = IMX7_SRC(dev); |
91 | + /*< public >*/ | 259 | + |
92 | + | 260 | + memset(s->regs, 0, sizeof(s->regs)); |
93 | + int16_t temperature[4]; | 261 | + |
94 | + | 262 | + /* Set reset values */ |
95 | + uint8_t status; | 263 | + s->regs[SRC_SCR] = 0xA0; |
96 | + uint8_t config[2]; | 264 | + s->regs[SRC_SRSR] = 0x1; |
97 | + uint8_t rate; | 265 | + s->regs[SRC_SIMR] = 0x1F; |
98 | + | 266 | +} |
99 | + uint8_t len; | 267 | + |
100 | + uint8_t buf[2]; | 268 | +static uint64_t imx7_src_read(void *opaque, hwaddr offset, unsigned size) |
101 | + uint8_t pointer; | 269 | +{ |
102 | + | 270 | + uint32_t value = 0; |
103 | +} TMP421State; | 271 | + IMX7SRCState *s = (IMX7SRCState *)opaque; |
104 | + | 272 | + uint32_t index = offset >> 2; |
105 | +typedef struct TMP421Class { | 273 | + |
106 | + I2CSlaveClass parent_class; | 274 | + if (index < SRC_MAX) { |
107 | + DeviceInfo *dev; | 275 | + value = s->regs[index]; |
108 | +} TMP421Class; | 276 | + } else { |
109 | + | 277 | + qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" |
110 | +#define TYPE_TMP421 "tmp421-generic" | 278 | + HWADDR_PRIx "\n", TYPE_IMX7_SRC, __func__, offset); |
111 | +#define TMP421(obj) OBJECT_CHECK(TMP421State, (obj), TYPE_TMP421) | 279 | + } |
112 | + | 280 | + |
113 | +#define TMP421_CLASS(klass) \ | 281 | + trace_imx7_src_read(imx7_src_reg_name(index), value); |
114 | + OBJECT_CLASS_CHECK(TMP421Class, (klass), TYPE_TMP421) | 282 | + |
115 | +#define TMP421_GET_CLASS(obj) \ | 283 | + return value; |
116 | + OBJECT_GET_CLASS(TMP421Class, (obj), TYPE_TMP421) | 284 | +} |
117 | + | 285 | + |
118 | +/* the TMP421 registers */ | 286 | + |
119 | +#define TMP421_STATUS_REG 0x08 | 287 | +/* |
120 | +#define TMP421_STATUS_BUSY (1 << 7) | 288 | + * The reset is asynchronous so we need to defer clearing the reset |
121 | +#define TMP421_CONFIG_REG_1 0x09 | 289 | + * bit until the work is completed. |
122 | +#define TMP421_CONFIG_RANGE (1 << 2) | 290 | + */ |
123 | +#define TMP421_CONFIG_SHUTDOWN (1 << 6) | 291 | + |
124 | +#define TMP421_CONFIG_REG_2 0x0A | 292 | +struct SRCSCRResetInfo { |
125 | +#define TMP421_CONFIG_RC (1 << 2) | 293 | + IMX7SRCState *s; |
126 | +#define TMP421_CONFIG_LEN (1 << 3) | 294 | + uint32_t reset_bit; |
127 | +#define TMP421_CONFIG_REN (1 << 4) | 295 | +}; |
128 | +#define TMP421_CONFIG_REN2 (1 << 5) | 296 | + |
129 | +#define TMP421_CONFIG_REN3 (1 << 6) | 297 | +static void imx7_clear_reset_bit(CPUState *cpu, run_on_cpu_data data) |
130 | + | 298 | +{ |
131 | +#define TMP421_CONVERSION_RATE_REG 0x0B | 299 | + struct SRCSCRResetInfo *ri = data.host_ptr; |
132 | +#define TMP421_ONE_SHOT 0x0F | 300 | + IMX7SRCState *s = ri->s; |
133 | + | 301 | + |
134 | +#define TMP421_RESET 0xFC | 302 | + assert(qemu_mutex_iothread_locked()); |
135 | +#define TMP421_MANUFACTURER_ID_REG 0xFE | 303 | + |
136 | +#define TMP421_DEVICE_ID_REG 0xFF | 304 | + s->regs[SRC_A7RCR0] = deposit32(s->regs[SRC_A7RCR0], ri->reset_bit, 1, 0); |
137 | + | 305 | + |
138 | +#define TMP421_TEMP_MSB0 0x00 | 306 | + trace_imx7_src_write(imx7_src_reg_name(SRC_A7RCR0), s->regs[SRC_A7RCR0]); |
139 | +#define TMP421_TEMP_MSB1 0x01 | 307 | + |
140 | +#define TMP421_TEMP_MSB2 0x02 | 308 | + g_free(ri); |
141 | +#define TMP421_TEMP_MSB3 0x03 | 309 | +} |
142 | +#define TMP421_TEMP_LSB0 0x10 | 310 | + |
143 | +#define TMP421_TEMP_LSB1 0x11 | 311 | +static void imx7_defer_clear_reset_bit(uint32_t cpuid, |
144 | +#define TMP421_TEMP_LSB2 0x12 | 312 | + IMX7SRCState *s, |
145 | +#define TMP421_TEMP_LSB3 0x13 | 313 | + uint32_t reset_shift) |
146 | + | 314 | +{ |
147 | +static const int32_t mins[2] = { -40000, -55000 }; | 315 | + struct SRCSCRResetInfo *ri; |
148 | +static const int32_t maxs[2] = { 127000, 150000 }; | 316 | + CPUState *cpu = arm_get_cpu_by_id(cpuid); |
149 | + | 317 | + |
150 | +static void tmp421_get_temperature(Object *obj, Visitor *v, const char *name, | 318 | + if (!cpu) { |
151 | + void *opaque, Error **errp) | ||
152 | +{ | ||
153 | + TMP421State *s = TMP421(obj); | ||
154 | + bool ext_range = (s->config[0] & TMP421_CONFIG_RANGE); | ||
155 | + int offset = ext_range * 64 * 256; | ||
156 | + int64_t value; | ||
157 | + int tempid; | ||
158 | + | ||
159 | + if (sscanf(name, "temperature%d", &tempid) != 1) { | ||
160 | + error_setg(errp, "error reading %s: %m", name); | ||
161 | + return; | 319 | + return; |
162 | + } | 320 | + } |
163 | + | 321 | + |
164 | + if (tempid >= 4 || tempid < 0) { | 322 | + ri = g_new(struct SRCSCRResetInfo, 1); |
165 | + error_setg(errp, "error reading %s", name); | 323 | + ri->s = s; |
324 | + ri->reset_bit = reset_shift; | ||
325 | + | ||
326 | + async_run_on_cpu(cpu, imx7_clear_reset_bit, RUN_ON_CPU_HOST_PTR(ri)); | ||
327 | +} | ||
328 | + | ||
329 | + | ||
330 | +static void imx7_src_write(void *opaque, hwaddr offset, uint64_t value, | ||
331 | + unsigned size) | ||
332 | +{ | ||
333 | + IMX7SRCState *s = (IMX7SRCState *)opaque; | ||
334 | + uint32_t index = offset >> 2; | ||
335 | + long unsigned int change_mask; | ||
336 | + uint32_t current_value = value; | ||
337 | + | ||
338 | + if (index >= SRC_MAX) { | ||
339 | + qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" | ||
340 | + HWADDR_PRIx "\n", TYPE_IMX7_SRC, __func__, offset); | ||
166 | + return; | 341 | + return; |
167 | + } | 342 | + } |
168 | + | 343 | + |
169 | + value = ((s->temperature[tempid] - offset) * 1000 + 128) / 256; | 344 | + trace_imx7_src_write(imx7_src_reg_name(SRC_A7RCR0), s->regs[SRC_A7RCR0]); |
170 | + | 345 | + |
171 | + visit_type_int(v, name, &value, errp); | 346 | + change_mask = s->regs[index] ^ (uint32_t)current_value; |
172 | +} | 347 | + |
173 | + | 348 | + switch (index) { |
174 | +/* Units are 0.001 centigrades relative to 0 C. s->temperature is 8.8 | 349 | + case SRC_A7RCR0: |
175 | + * fixed point, so units are 1/256 centigrades. A simple ratio will do. | 350 | + if (FIELD_EX32(change_mask, CORE0, RST)) { |
176 | + */ | 351 | + arm_reset_cpu(0); |
177 | +static void tmp421_set_temperature(Object *obj, Visitor *v, const char *name, | 352 | + imx7_defer_clear_reset_bit(0, s, R_CORE0_RST_SHIFT); |
178 | + void *opaque, Error **errp) | 353 | + } |
179 | +{ | 354 | + if (FIELD_EX32(change_mask, CORE1, RST)) { |
180 | + TMP421State *s = TMP421(obj); | 355 | + arm_reset_cpu(1); |
181 | + Error *local_err = NULL; | 356 | + imx7_defer_clear_reset_bit(1, s, R_CORE1_RST_SHIFT); |
182 | + int64_t temp; | 357 | + } |
183 | + bool ext_range = (s->config[0] & TMP421_CONFIG_RANGE); | 358 | + s->regs[index] = current_value; |
184 | + int offset = ext_range * 64 * 256; | ||
185 | + int tempid; | ||
186 | + | ||
187 | + visit_type_int(v, name, &temp, &local_err); | ||
188 | + if (local_err) { | ||
189 | + error_propagate(errp, local_err); | ||
190 | + return; | ||
191 | + } | ||
192 | + | ||
193 | + if (temp >= maxs[ext_range] || temp < mins[ext_range]) { | ||
194 | + error_setg(errp, "value %" PRId64 ".%03" PRIu64 " °C is out of range", | ||
195 | + temp / 1000, temp % 1000); | ||
196 | + return; | ||
197 | + } | ||
198 | + | ||
199 | + if (sscanf(name, "temperature%d", &tempid) != 1) { | ||
200 | + error_setg(errp, "error reading %s: %m", name); | ||
201 | + return; | ||
202 | + } | ||
203 | + | ||
204 | + if (tempid >= 4 || tempid < 0) { | ||
205 | + error_setg(errp, "error reading %s", name); | ||
206 | + return; | ||
207 | + } | ||
208 | + | ||
209 | + s->temperature[tempid] = (int16_t) ((temp * 256 - 128) / 1000) + offset; | ||
210 | +} | ||
211 | + | ||
212 | +static void tmp421_read(TMP421State *s) | ||
213 | +{ | ||
214 | + TMP421Class *sc = TMP421_GET_CLASS(s); | ||
215 | + | ||
216 | + s->len = 0; | ||
217 | + | ||
218 | + switch (s->pointer) { | ||
219 | + case TMP421_MANUFACTURER_ID_REG: | ||
220 | + s->buf[s->len++] = TMP421_MANUFACTURER_ID; | ||
221 | + break; | 359 | + break; |
222 | + case TMP421_DEVICE_ID_REG: | 360 | + case SRC_A7RCR1: |
223 | + s->buf[s->len++] = sc->dev->model; | 361 | + /* |
362 | + * On real hardware when the system reset controller starts a | ||
363 | + * secondary CPU it runs through some boot ROM code which reads | ||
364 | + * the SRC_GPRX registers controlling the start address and branches | ||
365 | + * to it. | ||
366 | + * Here we are taking a short cut and branching directly to the | ||
367 | + * requested address (we don't want to run the boot ROM code inside | ||
368 | + * QEMU) | ||
369 | + */ | ||
370 | + if (FIELD_EX32(change_mask, CORE1, ENABLE)) { | ||
371 | + if (FIELD_EX32(current_value, CORE1, ENABLE)) { | ||
372 | + /* CORE 1 is brought up */ | ||
373 | + arm_set_cpu_on(1, s->regs[SRC_GPR3], s->regs[SRC_GPR4], | ||
374 | + 3, false); | ||
375 | + } else { | ||
376 | + /* CORE 1 is shut down */ | ||
377 | + arm_set_cpu_off(1); | ||
378 | + } | ||
379 | + /* We clear the reset bits as the processor changed state */ | ||
380 | + imx7_defer_clear_reset_bit(1, s, R_CORE1_RST_SHIFT); | ||
381 | + clear_bit(R_CORE1_RST_SHIFT, &change_mask); | ||
382 | + } | ||
383 | + s->regs[index] = current_value; | ||
224 | + break; | 384 | + break; |
225 | + case TMP421_CONFIG_REG_1: | 385 | + default: |
226 | + s->buf[s->len++] = s->config[0]; | 386 | + s->regs[index] = current_value; |
227 | + break; | ||
228 | + case TMP421_CONFIG_REG_2: | ||
229 | + s->buf[s->len++] = s->config[1]; | ||
230 | + break; | ||
231 | + case TMP421_CONVERSION_RATE_REG: | ||
232 | + s->buf[s->len++] = s->rate; | ||
233 | + break; | ||
234 | + case TMP421_STATUS_REG: | ||
235 | + s->buf[s->len++] = s->status; | ||
236 | + break; | ||
237 | + | ||
238 | + /* FIXME: check for channel enablement in config registers */ | ||
239 | + case TMP421_TEMP_MSB0: | ||
240 | + s->buf[s->len++] = (((uint16_t) s->temperature[0]) >> 8); | ||
241 | + s->buf[s->len++] = (((uint16_t) s->temperature[0]) >> 0) & 0xf0; | ||
242 | + break; | ||
243 | + case TMP421_TEMP_MSB1: | ||
244 | + s->buf[s->len++] = (((uint16_t) s->temperature[1]) >> 8); | ||
245 | + s->buf[s->len++] = (((uint16_t) s->temperature[1]) >> 0) & 0xf0; | ||
246 | + break; | ||
247 | + case TMP421_TEMP_MSB2: | ||
248 | + s->buf[s->len++] = (((uint16_t) s->temperature[2]) >> 8); | ||
249 | + s->buf[s->len++] = (((uint16_t) s->temperature[2]) >> 0) & 0xf0; | ||
250 | + break; | ||
251 | + case TMP421_TEMP_MSB3: | ||
252 | + s->buf[s->len++] = (((uint16_t) s->temperature[3]) >> 8); | ||
253 | + s->buf[s->len++] = (((uint16_t) s->temperature[3]) >> 0) & 0xf0; | ||
254 | + break; | ||
255 | + case TMP421_TEMP_LSB0: | ||
256 | + s->buf[s->len++] = (((uint16_t) s->temperature[0]) >> 0) & 0xf0; | ||
257 | + break; | ||
258 | + case TMP421_TEMP_LSB1: | ||
259 | + s->buf[s->len++] = (((uint16_t) s->temperature[1]) >> 0) & 0xf0; | ||
260 | + break; | ||
261 | + case TMP421_TEMP_LSB2: | ||
262 | + s->buf[s->len++] = (((uint16_t) s->temperature[2]) >> 0) & 0xf0; | ||
263 | + break; | ||
264 | + case TMP421_TEMP_LSB3: | ||
265 | + s->buf[s->len++] = (((uint16_t) s->temperature[3]) >> 0) & 0xf0; | ||
266 | + break; | 387 | + break; |
267 | + } | 388 | + } |
268 | +} | 389 | +} |
269 | + | 390 | + |
270 | +static void tmp421_reset(I2CSlave *i2c); | 391 | +static const struct MemoryRegionOps imx7_src_ops = { |
271 | + | 392 | + .read = imx7_src_read, |
272 | +static void tmp421_write(TMP421State *s) | 393 | + .write = imx7_src_write, |
273 | +{ | 394 | + .endianness = DEVICE_NATIVE_ENDIAN, |
274 | + switch (s->pointer) { | 395 | + .valid = { |
275 | + case TMP421_CONVERSION_RATE_REG: | 396 | + /* |
276 | + s->rate = s->buf[0]; | 397 | + * Our device would not work correctly if the guest was doing |
277 | + break; | 398 | + * unaligned access. This might not be a limitation on the real |
278 | + case TMP421_CONFIG_REG_1: | 399 | + * device but in practice there is no reason for a guest to access |
279 | + s->config[0] = s->buf[0]; | 400 | + * this device unaligned. |
280 | + break; | 401 | + */ |
281 | + case TMP421_CONFIG_REG_2: | 402 | + .min_access_size = 4, |
282 | + s->config[1] = s->buf[0]; | 403 | + .max_access_size = 4, |
283 | + break; | 404 | + .unaligned = false, |
284 | + case TMP421_RESET: | 405 | + }, |
285 | + tmp421_reset(I2C_SLAVE(s)); | ||
286 | + break; | ||
287 | + } | ||
288 | +} | ||
289 | + | ||
290 | +static int tmp421_rx(I2CSlave *i2c) | ||
291 | +{ | ||
292 | + TMP421State *s = TMP421(i2c); | ||
293 | + | ||
294 | + if (s->len < 2) { | ||
295 | + return s->buf[s->len++]; | ||
296 | + } else { | ||
297 | + return 0xff; | ||
298 | + } | ||
299 | +} | ||
300 | + | ||
301 | +static int tmp421_tx(I2CSlave *i2c, uint8_t data) | ||
302 | +{ | ||
303 | + TMP421State *s = TMP421(i2c); | ||
304 | + | ||
305 | + if (s->len == 0) { | ||
306 | + /* first byte is the register pointer for a read or write | ||
307 | + * operation */ | ||
308 | + s->pointer = data; | ||
309 | + s->len++; | ||
310 | + } else if (s->len == 1) { | ||
311 | + /* second byte is the data to write. The device only supports | ||
312 | + * one byte writes */ | ||
313 | + s->buf[0] = data; | ||
314 | + tmp421_write(s); | ||
315 | + } | ||
316 | + | ||
317 | + return 0; | ||
318 | +} | ||
319 | + | ||
320 | +static int tmp421_event(I2CSlave *i2c, enum i2c_event event) | ||
321 | +{ | ||
322 | + TMP421State *s = TMP421(i2c); | ||
323 | + | ||
324 | + if (event == I2C_START_RECV) { | ||
325 | + tmp421_read(s); | ||
326 | + } | ||
327 | + | ||
328 | + s->len = 0; | ||
329 | + return 0; | ||
330 | +} | ||
331 | + | ||
332 | +static const VMStateDescription vmstate_tmp421 = { | ||
333 | + .name = "TMP421", | ||
334 | + .version_id = 0, | ||
335 | + .minimum_version_id = 0, | ||
336 | + .fields = (VMStateField[]) { | ||
337 | + VMSTATE_UINT8(len, TMP421State), | ||
338 | + VMSTATE_UINT8_ARRAY(buf, TMP421State, 2), | ||
339 | + VMSTATE_UINT8(pointer, TMP421State), | ||
340 | + VMSTATE_UINT8_ARRAY(config, TMP421State, 2), | ||
341 | + VMSTATE_UINT8(status, TMP421State), | ||
342 | + VMSTATE_UINT8(rate, TMP421State), | ||
343 | + VMSTATE_INT16_ARRAY(temperature, TMP421State, 4), | ||
344 | + VMSTATE_I2C_SLAVE(i2c, TMP421State), | ||
345 | + VMSTATE_END_OF_LIST() | ||
346 | + } | ||
347 | +}; | 406 | +}; |
348 | + | 407 | + |
349 | +static void tmp421_reset(I2CSlave *i2c) | 408 | +static void imx7_src_realize(DeviceState *dev, Error **errp) |
350 | +{ | 409 | +{ |
351 | + TMP421State *s = TMP421(i2c); | 410 | + IMX7SRCState *s = IMX7_SRC(dev); |
352 | + TMP421Class *sc = TMP421_GET_CLASS(s); | 411 | + |
353 | + | 412 | + memory_region_init_io(&s->iomem, OBJECT(dev), &imx7_src_ops, s, |
354 | + memset(s->temperature, 0, sizeof(s->temperature)); | 413 | + TYPE_IMX7_SRC, 0x1000); |
355 | + s->pointer = 0; | 414 | + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); |
356 | + | 415 | +} |
357 | + s->config[0] = 0; /* TMP421_CONFIG_RANGE */ | 416 | + |
358 | + | 417 | +static void imx7_src_class_init(ObjectClass *klass, void *data) |
359 | + /* resistance correction and channel enablement */ | ||
360 | + switch (sc->dev->model) { | ||
361 | + case TMP421_DEVICE_ID: | ||
362 | + s->config[1] = 0x1c; | ||
363 | + break; | ||
364 | + case TMP422_DEVICE_ID: | ||
365 | + s->config[1] = 0x3c; | ||
366 | + break; | ||
367 | + case TMP423_DEVICE_ID: | ||
368 | + s->config[1] = 0x7c; | ||
369 | + break; | ||
370 | + } | ||
371 | + | ||
372 | + s->rate = 0x7; /* 8Hz */ | ||
373 | + s->status = 0; | ||
374 | +} | ||
375 | + | ||
376 | +static int tmp421_init(I2CSlave *i2c) | ||
377 | +{ | ||
378 | + TMP421State *s = TMP421(i2c); | ||
379 | + | ||
380 | + tmp421_reset(&s->i2c); | ||
381 | + | ||
382 | + return 0; | ||
383 | +} | ||
384 | + | ||
385 | +static void tmp421_initfn(Object *obj) | ||
386 | +{ | ||
387 | + object_property_add(obj, "temperature0", "int", | ||
388 | + tmp421_get_temperature, | ||
389 | + tmp421_set_temperature, NULL, NULL, NULL); | ||
390 | + object_property_add(obj, "temperature1", "int", | ||
391 | + tmp421_get_temperature, | ||
392 | + tmp421_set_temperature, NULL, NULL, NULL); | ||
393 | + object_property_add(obj, "temperature2", "int", | ||
394 | + tmp421_get_temperature, | ||
395 | + tmp421_set_temperature, NULL, NULL, NULL); | ||
396 | + object_property_add(obj, "temperature3", "int", | ||
397 | + tmp421_get_temperature, | ||
398 | + tmp421_set_temperature, NULL, NULL, NULL); | ||
399 | +} | ||
400 | + | ||
401 | +static void tmp421_class_init(ObjectClass *klass, void *data) | ||
402 | +{ | 418 | +{ |
403 | + DeviceClass *dc = DEVICE_CLASS(klass); | 419 | + DeviceClass *dc = DEVICE_CLASS(klass); |
404 | + I2CSlaveClass *k = I2C_SLAVE_CLASS(klass); | 420 | + |
405 | + TMP421Class *sc = TMP421_CLASS(klass); | 421 | + dc->realize = imx7_src_realize; |
406 | + | 422 | + dc->reset = imx7_src_reset; |
407 | + k->init = tmp421_init; | 423 | + dc->vmsd = &vmstate_imx7_src; |
408 | + k->event = tmp421_event; | 424 | + dc->desc = "i.MX6 System Reset Controller"; |
409 | + k->recv = tmp421_rx; | 425 | +} |
410 | + k->send = tmp421_tx; | 426 | + |
411 | + dc->vmsd = &vmstate_tmp421; | 427 | +static const TypeInfo imx7_src_info = { |
412 | + sc->dev = (DeviceInfo *) data; | 428 | + .name = TYPE_IMX7_SRC, |
413 | +} | 429 | + .parent = TYPE_SYS_BUS_DEVICE, |
414 | + | 430 | + .instance_size = sizeof(IMX7SRCState), |
415 | +static const TypeInfo tmp421_info = { | 431 | + .class_init = imx7_src_class_init, |
416 | + .name = TYPE_TMP421, | ||
417 | + .parent = TYPE_I2C_SLAVE, | ||
418 | + .instance_size = sizeof(TMP421State), | ||
419 | + .class_size = sizeof(TMP421Class), | ||
420 | + .instance_init = tmp421_initfn, | ||
421 | + .abstract = true, | ||
422 | +}; | 432 | +}; |
423 | + | 433 | + |
424 | +static void tmp421_register_types(void) | 434 | +static void imx7_src_register_types(void) |
425 | +{ | 435 | +{ |
426 | + int i; | 436 | + type_register_static(&imx7_src_info); |
427 | + | 437 | +} |
428 | + type_register_static(&tmp421_info); | 438 | + |
429 | + for (i = 0; i < ARRAY_SIZE(devices); ++i) { | 439 | +type_init(imx7_src_register_types) |
430 | + TypeInfo ti = { | 440 | diff --git a/hw/misc/meson.build b/hw/misc/meson.build |
431 | + .name = devices[i].name, | ||
432 | + .parent = TYPE_TMP421, | ||
433 | + .class_init = tmp421_class_init, | ||
434 | + .class_data = (void *) &devices[i], | ||
435 | + }; | ||
436 | + type_register(&ti); | ||
437 | + } | ||
438 | +} | ||
439 | + | ||
440 | +type_init(tmp421_register_types) | ||
441 | diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak | ||
442 | index XXXXXXX..XXXXXXX 100644 | 441 | index XXXXXXX..XXXXXXX 100644 |
443 | --- a/default-configs/arm-softmmu.mak | 442 | --- a/hw/misc/meson.build |
444 | +++ b/default-configs/arm-softmmu.mak | 443 | +++ b/hw/misc/meson.build |
445 | @@ -XXX,XX +XXX,XX @@ CONFIG_TWL92230=y | 444 | @@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_IMX', if_true: files( |
446 | CONFIG_TSC2005=y | 445 | 'imx6_src.c', |
447 | CONFIG_LM832X=y | 446 | 'imx6ul_ccm.c', |
448 | CONFIG_TMP105=y | 447 | 'imx7_ccm.c', |
449 | +CONFIG_TMP421=y | 448 | + 'imx7_src.c', |
450 | CONFIG_STELLARIS=y | 449 | 'imx7_gpr.c', |
451 | CONFIG_STELLARIS_INPUT=y | 450 | 'imx7_snvs.c', |
452 | CONFIG_STELLARIS_ENET=y | 451 | 'imx_ccm.c', |
452 | diff --git a/hw/misc/trace-events b/hw/misc/trace-events | ||
453 | index XXXXXXX..XXXXXXX 100644 | ||
454 | --- a/hw/misc/trace-events | ||
455 | +++ b/hw/misc/trace-events | ||
456 | @@ -XXX,XX +XXX,XX @@ ccm_clock_freq(uint32_t clock, uint32_t freq) "(Clock = %d) = %d" | ||
457 | ccm_read_reg(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32 | ||
458 | ccm_write_reg(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32 | ||
459 | |||
460 | +# imx7_src.c | ||
461 | +imx7_src_read(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32 | ||
462 | +imx7_src_write(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32 | ||
463 | + | ||
464 | # iotkit-sysinfo.c | ||
465 | iotkit_sysinfo_read(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysInfo read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | ||
466 | iotkit_sysinfo_write(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysInfo write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | ||
453 | -- | 467 | -- |
454 | 2.7.4 | 468 | 2.34.1 |
455 | |||
456 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | The architecture requires (R_TYTWB) that an attempt to return from EL3 | ||
2 | when SCR_EL3.{NSE,NS} are {1,0} is an illegal exception return. (This | ||
3 | enforces that the CPU can't ever be executing below EL3 with the | ||
4 | NSE,NS bits indicating an invalid security state.) | ||
1 | 5 | ||
6 | We were missing this check; add it. | ||
7 | |||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20230807150618.101357-1-peter.maydell@linaro.org | ||
11 | --- | ||
12 | target/arm/tcg/helper-a64.c | 9 +++++++++ | ||
13 | 1 file changed, 9 insertions(+) | ||
14 | |||
15 | diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/tcg/helper-a64.c | ||
18 | +++ b/target/arm/tcg/helper-a64.c | ||
19 | @@ -XXX,XX +XXX,XX @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) | ||
20 | spsr &= ~PSTATE_SS; | ||
21 | } | ||
22 | |||
23 | + /* | ||
24 | + * FEAT_RME forbids return from EL3 with an invalid security state. | ||
25 | + * We don't need an explicit check for FEAT_RME here because we enforce | ||
26 | + * in scr_write() that you can't set the NSE bit without it. | ||
27 | + */ | ||
28 | + if (cur_el == 3 && (env->cp15.scr_el3 & (SCR_NS | SCR_NSE)) == SCR_NSE) { | ||
29 | + goto illegal_return; | ||
30 | + } | ||
31 | + | ||
32 | new_el = el_from_spsr(spsr); | ||
33 | if (new_el == -1) { | ||
34 | goto illegal_return; | ||
35 | -- | ||
36 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Krzysztof Kozlowski <krzk@kernel.org> | 1 | In the m48t59 device we almost always use 64-bit arithmetic when |
---|---|---|---|
2 | dealing with time_t deltas. The one exception is in set_alarm(), | ||
3 | which currently uses a plain 'int' to hold the difference between two | ||
4 | time_t values. Switch to int64_t instead to avoid any possible | ||
5 | overflow issues. | ||
2 | 6 | ||
3 | The static array of interrupt combiner mappings is not modified so it | ||
4 | can be made const for code safeness. | ||
5 | |||
6 | Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> | ||
7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
9 | --- | 9 | --- |
10 | hw/intc/exynos4210_gic.c | 2 +- | 10 | hw/rtc/m48t59.c | 2 +- |
11 | 1 file changed, 1 insertion(+), 1 deletion(-) | 11 | 1 file changed, 1 insertion(+), 1 deletion(-) |
12 | 12 | ||
13 | diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c | 13 | diff --git a/hw/rtc/m48t59.c b/hw/rtc/m48t59.c |
14 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/hw/intc/exynos4210_gic.c | 15 | --- a/hw/rtc/m48t59.c |
16 | +++ b/hw/intc/exynos4210_gic.c | 16 | +++ b/hw/rtc/m48t59.c |
17 | @@ -XXX,XX +XXX,XX @@ enum ExtInt { | 17 | @@ -XXX,XX +XXX,XX @@ static void alarm_cb (void *opaque) |
18 | * which is INTG16 in Internal Interrupt Combiner. | 18 | |
19 | */ | 19 | static void set_alarm(M48t59State *NVRAM) |
20 | 20 | { | |
21 | -static uint32_t | 21 | - int diff; |
22 | +static const uint32_t | 22 | + int64_t diff; |
23 | combiner_grp_to_gic_id[64-EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { | 23 | if (NVRAM->alrm_timer != NULL) { |
24 | /* int combiner groups 16-19 */ | 24 | timer_del(NVRAM->alrm_timer); |
25 | { }, { }, { }, { }, | 25 | diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset; |
26 | -- | 26 | -- |
27 | 2.7.4 | 27 | 2.34.1 |
28 | 28 | ||
29 | 29 | diff view generated by jsdifflib |
1 | From: Krzysztof Kozlowski <krzk@kernel.org> | 1 | In the twl92230 device, use int64_t for the two state fields |
---|---|---|---|
2 | sec_offset and alm_sec, because we set these to values that | ||
3 | are either time_t or differences between two time_t values. | ||
2 | 4 | ||
3 | Fix checkpatch errors: | 5 | These fields aren't saved in vmstate anywhere, so we can |
4 | 1. ERROR: spaces required around that '+' (ctx:VxV) | 6 | safely widen them. |
5 | 2. ERROR: spaces required around that '&' (ctx:VxV) | ||
6 | 7 | ||
7 | No functional changes. | ||
8 | |||
9 | Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
13 | --- | 10 | --- |
14 | hw/timer/exynos4210_mct.c | 4 ++-- | 11 | hw/rtc/twl92230.c | 4 ++-- |
15 | 1 file changed, 2 insertions(+), 2 deletions(-) | 12 | 1 file changed, 2 insertions(+), 2 deletions(-) |
16 | 13 | ||
17 | diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c | 14 | diff --git a/hw/rtc/twl92230.c b/hw/rtc/twl92230.c |
18 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/hw/timer/exynos4210_mct.c | 16 | --- a/hw/rtc/twl92230.c |
20 | +++ b/hw/timer/exynos4210_mct.c | 17 | +++ b/hw/rtc/twl92230.c |
21 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_update_freq(Exynos4210MCTState *s) | 18 | @@ -XXX,XX +XXX,XX @@ struct MenelausState { |
22 | { | 19 | struct tm tm; |
23 | uint32_t freq = s->freq; | 20 | struct tm new; |
24 | s->freq = 24000000 / | 21 | struct tm alm; |
25 | - ((MCT_CFG_GET_PRESCALER(s->reg_mct_cfg)+1) * | 22 | - int sec_offset; |
26 | + ((MCT_CFG_GET_PRESCALER(s->reg_mct_cfg) + 1) * | 23 | - int alm_sec; |
27 | MCT_CFG_GET_DIVIDER(s->reg_mct_cfg)); | 24 | + int64_t sec_offset; |
28 | 25 | + int64_t alm_sec; | |
29 | if (freq != s->freq) { | 26 | int next_comp; |
30 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, | 27 | } rtc; |
31 | 28 | uint16_t rtc_next_vmstate; | |
32 | DPRINTF("comparator %d write 0x%llx val << %d\n", index, value, shift); | ||
33 | |||
34 | - if (offset&0x4) { | ||
35 | + if (offset & 0x4) { | ||
36 | s->g_timer.reg.wstat |= G_WSTAT_COMP_U(index); | ||
37 | } else { | ||
38 | s->g_timer.reg.wstat |= G_WSTAT_COMP_L(index); | ||
39 | -- | 29 | -- |
40 | 2.7.4 | 30 | 2.34.1 |
41 | 31 | ||
42 | 32 | diff view generated by jsdifflib |
1 | From: Krzysztof Kozlowski <krzk@kernel.org> | 1 | In the aspeed_rtc device we store a difference between two time_t |
---|---|---|---|
2 | values in an 'int'. This is not really correct when time_t could | ||
3 | be 64 bits. Enlarge the field to 'int64_t'. | ||
2 | 4 | ||
3 | There are to SysBusDevice variables in exynos4210_gic_realize() | 5 | This is a migration compatibility break for the aspeed boards. |
4 | function: one for the device itself and second for arm_gic device. Add | 6 | While we are changing the vmstate, remove the accidental |
5 | a prefix "gic" to the second one so it will be easier to understand the | 7 | duplicate of the offset field. |
6 | code. | ||
7 | 8 | ||
8 | While at it, put local uninitialized 'i' variable at the end, next to | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | other uninitialized ones. | 10 | Reviewed-by: Cédric Le Goater <clg@kaod.org> |
11 | --- | ||
12 | include/hw/rtc/aspeed_rtc.h | 2 +- | ||
13 | hw/rtc/aspeed_rtc.c | 5 ++--- | ||
14 | 2 files changed, 3 insertions(+), 4 deletions(-) | ||
10 | 15 | ||
11 | Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> | 16 | diff --git a/include/hw/rtc/aspeed_rtc.h b/include/hw/rtc/aspeed_rtc.h |
12 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
15 | --- | ||
16 | hw/intc/exynos4210_gic.c | 12 ++++++------ | ||
17 | 1 file changed, 6 insertions(+), 6 deletions(-) | ||
18 | |||
19 | diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c | ||
20 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/hw/intc/exynos4210_gic.c | 18 | --- a/include/hw/rtc/aspeed_rtc.h |
22 | +++ b/hw/intc/exynos4210_gic.c | 19 | +++ b/include/hw/rtc/aspeed_rtc.h |
23 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_gic_init(Object *obj) | 20 | @@ -XXX,XX +XXX,XX @@ struct AspeedRtcState { |
24 | DeviceState *dev = DEVICE(obj); | 21 | qemu_irq irq; |
25 | Exynos4210GicState *s = EXYNOS4210_GIC(obj); | 22 | |
26 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | 23 | uint32_t reg[0x18]; |
27 | - uint32_t i; | 24 | - int offset; |
28 | const char cpu_prefix[] = "exynos4210-gic-alias_cpu"; | 25 | + int64_t offset; |
29 | const char dist_prefix[] = "exynos4210-gic-alias_dist"; | 26 | |
30 | char cpu_alias_name[sizeof(cpu_prefix) + 3]; | 27 | }; |
31 | char dist_alias_name[sizeof(cpu_prefix) + 3]; | 28 | |
32 | - SysBusDevice *busdev; | 29 | diff --git a/hw/rtc/aspeed_rtc.c b/hw/rtc/aspeed_rtc.c |
33 | + SysBusDevice *gicbusdev; | 30 | index XXXXXXX..XXXXXXX 100644 |
34 | + uint32_t i; | 31 | --- a/hw/rtc/aspeed_rtc.c |
35 | 32 | +++ b/hw/rtc/aspeed_rtc.c | |
36 | s->gic = qdev_create(NULL, "arm_gic"); | 33 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps aspeed_rtc_ops = { |
37 | qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); | 34 | |
38 | qdev_prop_set_uint32(s->gic, "num-irq", EXYNOS4210_GIC_NIRQ); | 35 | static const VMStateDescription vmstate_aspeed_rtc = { |
39 | qdev_init_nofail(s->gic); | 36 | .name = TYPE_ASPEED_RTC, |
40 | - busdev = SYS_BUS_DEVICE(s->gic); | 37 | - .version_id = 1, |
41 | + gicbusdev = SYS_BUS_DEVICE(s->gic); | 38 | + .version_id = 2, |
42 | 39 | .fields = (VMStateField[]) { | |
43 | /* Pass through outbound IRQ lines from the GIC */ | 40 | VMSTATE_UINT32_ARRAY(reg, AspeedRtcState, 0x18), |
44 | - sysbus_pass_irq(sbd, busdev); | 41 | - VMSTATE_INT32(offset, AspeedRtcState), |
45 | + sysbus_pass_irq(sbd, gicbusdev); | 42 | - VMSTATE_INT32(offset, AspeedRtcState), |
46 | 43 | + VMSTATE_INT64(offset, AspeedRtcState), | |
47 | /* Pass through inbound GPIO lines to the GIC */ | 44 | VMSTATE_END_OF_LIST() |
48 | qdev_init_gpio_in(dev, exynos4210_gic_set_irq, | 45 | } |
49 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_gic_init(Object *obj) | 46 | }; |
50 | sprintf(cpu_alias_name, "%s%x", cpu_prefix, i); | ||
51 | memory_region_init_alias(&s->cpu_alias[i], obj, | ||
52 | cpu_alias_name, | ||
53 | - sysbus_mmio_get_region(busdev, 1), | ||
54 | + sysbus_mmio_get_region(gicbusdev, 1), | ||
55 | 0, | ||
56 | EXYNOS4210_GIC_CPU_REGION_SIZE); | ||
57 | memory_region_add_subregion(&s->cpu_container, | ||
58 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_gic_init(Object *obj) | ||
59 | sprintf(dist_alias_name, "%s%x", dist_prefix, i); | ||
60 | memory_region_init_alias(&s->dist_alias[i], obj, | ||
61 | dist_alias_name, | ||
62 | - sysbus_mmio_get_region(busdev, 0), | ||
63 | + sysbus_mmio_get_region(gicbusdev, 0), | ||
64 | 0, | ||
65 | EXYNOS4210_GIC_DIST_REGION_SIZE); | ||
66 | memory_region_add_subregion(&s->dist_container, | ||
67 | -- | 47 | -- |
68 | 2.7.4 | 48 | 2.34.1 |
69 | 49 | ||
70 | 50 | diff view generated by jsdifflib |
1 | From: Krzysztof Kozlowski <krzk@kernel.org> | 1 | The functions qemu_get_timedate() and qemu_timedate_diff() take |
---|---|---|---|
2 | and return a time offset as an integer. Coverity points out that | ||
3 | means that when an RTC device implementation holds an offset | ||
4 | as a time_t, as the m48t59 does, the time_t will get truncated. | ||
5 | (CID 1507157, 1517772). | ||
2 | 6 | ||
3 | Before QOM-ifying the Exynos4 SoC model, move the DRAM initialization | 7 | The functions work with time_t internally, so make them use that type |
4 | from exynos4210.c to exynos4_boards.c because DRAM is board specific, | 8 | in their APIs. |
5 | not SoC. | ||
6 | 9 | ||
7 | Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> | 10 | Note that this won't help any Y2038 issues where either the device |
8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 11 | model itself is keeping the offset in a 32-bit integer, or where the |
12 | hardware under emulation has Y2038 or other rollover problems. If we | ||
13 | missed any cases of the former then hopefully Coverity will warn us | ||
14 | about them since after this patch we'd be truncating a time_t in | ||
15 | assignments from qemu_timedate_diff().) | ||
16 | |||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
18 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
10 | --- | 19 | --- |
11 | include/hw/arm/exynos4210.h | 5 +---- | 20 | include/sysemu/rtc.h | 4 ++-- |
12 | hw/arm/exynos4210.c | 20 +----------------- | 21 | softmmu/rtc.c | 4 ++-- |
13 | hw/arm/exynos4_boards.c | 50 ++++++++++++++++++++++++++++++++++++++------- | 22 | 2 files changed, 4 insertions(+), 4 deletions(-) |
14 | 3 files changed, 45 insertions(+), 30 deletions(-) | ||
15 | 23 | ||
16 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | 24 | diff --git a/include/sysemu/rtc.h b/include/sysemu/rtc.h |
17 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/include/hw/arm/exynos4210.h | 26 | --- a/include/sysemu/rtc.h |
19 | +++ b/include/hw/arm/exynos4210.h | 27 | +++ b/include/sysemu/rtc.h |
20 | @@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210State { | 28 | @@ -XXX,XX +XXX,XX @@ |
21 | MemoryRegion iram_mem; | 29 | * The behaviour of the clock whose value this function returns will |
22 | MemoryRegion irom_mem; | 30 | * depend on the -rtc command line option passed by the user. |
23 | MemoryRegion irom_alias_mem; | 31 | */ |
24 | - MemoryRegion dram0_mem; | 32 | -void qemu_get_timedate(struct tm *tm, int offset); |
25 | - MemoryRegion dram1_mem; | 33 | +void qemu_get_timedate(struct tm *tm, time_t offset); |
26 | MemoryRegion boot_secondary; | 34 | |
27 | MemoryRegion bootreg_mem; | 35 | /** |
28 | I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER]; | 36 | * qemu_timedate_diff: Return difference between a struct tm and the RTC |
29 | @@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210State { | 37 | @@ -XXX,XX +XXX,XX @@ void qemu_get_timedate(struct tm *tm, int offset); |
30 | void exynos4210_write_secondary(ARMCPU *cpu, | 38 | * a timestamp one hour further ahead than the current RTC time |
31 | const struct arm_boot_info *info); | 39 | * then this function will return 3600. |
32 | 40 | */ | |
33 | -Exynos4210State *exynos4210_init(MemoryRegion *system_mem, | 41 | -int qemu_timedate_diff(struct tm *tm); |
34 | - unsigned long ram_size); | 42 | +time_t qemu_timedate_diff(struct tm *tm); |
35 | +Exynos4210State *exynos4210_init(MemoryRegion *system_mem); | 43 | |
36 | 44 | #endif | |
37 | /* Initialize exynos4210 IRQ subsystem stub */ | 45 | diff --git a/softmmu/rtc.c b/softmmu/rtc.c |
38 | qemu_irq *exynos4210_init_irq(Exynos4210Irq *env); | ||
39 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
40 | index XXXXXXX..XXXXXXX 100644 | 46 | index XXXXXXX..XXXXXXX 100644 |
41 | --- a/hw/arm/exynos4210.c | 47 | --- a/softmmu/rtc.c |
42 | +++ b/hw/arm/exynos4210.c | 48 | +++ b/softmmu/rtc.c |
43 | @@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_calc_affinity(int cpu) | 49 | @@ -XXX,XX +XXX,XX @@ static time_t qemu_ref_timedate(QEMUClockType clock) |
44 | return mp_affinity; | 50 | return value; |
45 | } | 51 | } |
46 | 52 | ||
47 | -Exynos4210State *exynos4210_init(MemoryRegion *system_mem, | 53 | -void qemu_get_timedate(struct tm *tm, int offset) |
48 | - unsigned long ram_size) | 54 | +void qemu_get_timedate(struct tm *tm, time_t offset) |
49 | +Exynos4210State *exynos4210_init(MemoryRegion *system_mem) | ||
50 | { | 55 | { |
51 | int i, n; | 56 | time_t ti = qemu_ref_timedate(rtc_clock); |
52 | Exynos4210State *s = g_new(Exynos4210State, 1); | 57 | |
53 | qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS]; | 58 | @@ -XXX,XX +XXX,XX @@ void qemu_get_timedate(struct tm *tm, int offset) |
54 | - unsigned long mem_size; | ||
55 | DeviceState *dev; | ||
56 | SysBusDevice *busdev; | ||
57 | ObjectClass *cpu_oc; | ||
58 | @@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem, | ||
59 | memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR, | ||
60 | &s->iram_mem); | ||
61 | |||
62 | - /* DRAM */ | ||
63 | - mem_size = ram_size; | ||
64 | - if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) { | ||
65 | - memory_region_init_ram(&s->dram1_mem, NULL, "exynos4210.dram1", | ||
66 | - mem_size - EXYNOS4210_DRAM_MAX_SIZE, &error_fatal); | ||
67 | - vmstate_register_ram_global(&s->dram1_mem); | ||
68 | - memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR, | ||
69 | - &s->dram1_mem); | ||
70 | - mem_size = EXYNOS4210_DRAM_MAX_SIZE; | ||
71 | - } | ||
72 | - memory_region_init_ram(&s->dram0_mem, NULL, "exynos4210.dram0", mem_size, | ||
73 | - &error_fatal); | ||
74 | - vmstate_register_ram_global(&s->dram0_mem); | ||
75 | - memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR, | ||
76 | - &s->dram0_mem); | ||
77 | - | ||
78 | /* PMU. | ||
79 | * The only reason of existence at the moment is that secondary CPU boot | ||
80 | * loader uses PMU INFORM5 register as a holding pen. | ||
81 | diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c | ||
82 | index XXXXXXX..XXXXXXX 100644 | ||
83 | --- a/hw/arm/exynos4_boards.c | ||
84 | +++ b/hw/arm/exynos4_boards.c | ||
85 | @@ -XXX,XX +XXX,XX @@ | ||
86 | */ | ||
87 | |||
88 | #include "qemu/osdep.h" | ||
89 | +#include "qapi/error.h" | ||
90 | #include "qemu/error-report.h" | ||
91 | #include "qemu-common.h" | ||
92 | #include "cpu.h" | ||
93 | @@ -XXX,XX +XXX,XX @@ typedef enum Exynos4BoardType { | ||
94 | EXYNOS4_NUM_OF_BOARDS | ||
95 | } Exynos4BoardType; | ||
96 | |||
97 | +typedef struct Exynos4BoardState { | ||
98 | + Exynos4210State *soc; | ||
99 | + MemoryRegion dram0_mem; | ||
100 | + MemoryRegion dram1_mem; | ||
101 | +} Exynos4BoardState; | ||
102 | + | ||
103 | static int exynos4_board_id[EXYNOS4_NUM_OF_BOARDS] = { | ||
104 | [EXYNOS4_BOARD_NURI] = 0xD33, | ||
105 | [EXYNOS4_BOARD_SMDKC210] = 0xB16, | ||
106 | @@ -XXX,XX +XXX,XX @@ static void lan9215_init(uint32_t base, qemu_irq irq) | ||
107 | } | 59 | } |
108 | } | 60 | } |
109 | 61 | ||
110 | -static Exynos4210State *exynos4_boards_init_common(MachineState *machine, | 62 | -int qemu_timedate_diff(struct tm *tm) |
111 | - Exynos4BoardType board_type) | 63 | +time_t qemu_timedate_diff(struct tm *tm) |
112 | +static void exynos4_boards_init_ram(Exynos4BoardState *s, | ||
113 | + MemoryRegion *system_mem, | ||
114 | + unsigned long ram_size) | ||
115 | +{ | ||
116 | + unsigned long mem_size = ram_size; | ||
117 | + | ||
118 | + if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) { | ||
119 | + memory_region_init_ram(&s->dram1_mem, NULL, "exynos4210.dram1", | ||
120 | + mem_size - EXYNOS4210_DRAM_MAX_SIZE, | ||
121 | + &error_fatal); | ||
122 | + vmstate_register_ram_global(&s->dram1_mem); | ||
123 | + memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR, | ||
124 | + &s->dram1_mem); | ||
125 | + mem_size = EXYNOS4210_DRAM_MAX_SIZE; | ||
126 | + } | ||
127 | + | ||
128 | + memory_region_init_ram(&s->dram0_mem, NULL, "exynos4210.dram0", mem_size, | ||
129 | + &error_fatal); | ||
130 | + vmstate_register_ram_global(&s->dram0_mem); | ||
131 | + memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR, | ||
132 | + &s->dram0_mem); | ||
133 | +} | ||
134 | + | ||
135 | +static Exynos4BoardState * | ||
136 | +exynos4_boards_init_common(MachineState *machine, | ||
137 | + Exynos4BoardType board_type) | ||
138 | { | 64 | { |
139 | + Exynos4BoardState *s = g_new(Exynos4BoardState, 1); | 65 | time_t seconds; |
140 | MachineClass *mc = MACHINE_GET_CLASS(machine); | ||
141 | |||
142 | if (smp_cpus != EXYNOS4210_NCPUS && !qtest_enabled()) { | ||
143 | @@ -XXX,XX +XXX,XX @@ static Exynos4210State *exynos4_boards_init_common(MachineState *machine, | ||
144 | machine->kernel_cmdline, | ||
145 | machine->initrd_filename); | ||
146 | |||
147 | - return exynos4210_init(get_system_memory(), | ||
148 | - exynos4_board_ram_size[board_type]); | ||
149 | + exynos4_boards_init_ram(s, get_system_memory(), | ||
150 | + exynos4_board_ram_size[board_type]); | ||
151 | + | ||
152 | + s->soc = exynos4210_init(get_system_memory()); | ||
153 | + | ||
154 | + return s; | ||
155 | } | ||
156 | |||
157 | static void nuri_init(MachineState *machine) | ||
158 | @@ -XXX,XX +XXX,XX @@ static void nuri_init(MachineState *machine) | ||
159 | |||
160 | static void smdkc210_init(MachineState *machine) | ||
161 | { | ||
162 | - Exynos4210State *s = exynos4_boards_init_common(machine, | ||
163 | - EXYNOS4_BOARD_SMDKC210); | ||
164 | + Exynos4BoardState *s = exynos4_boards_init_common(machine, | ||
165 | + EXYNOS4_BOARD_SMDKC210); | ||
166 | |||
167 | lan9215_init(SMDK_LAN9118_BASE_ADDR, | ||
168 | - qemu_irq_invert(s->irq_table[exynos4210_get_irq(37, 1)])); | ||
169 | + qemu_irq_invert(s->soc->irq_table[exynos4210_get_irq(37, 1)])); | ||
170 | arm_load_kernel(ARM_CPU(first_cpu), &exynos4_board_binfo); | ||
171 | } | ||
172 | 66 | ||
173 | -- | 67 | -- |
174 | 2.7.4 | 68 | 2.34.1 |
175 | 69 | ||
176 | 70 | diff view generated by jsdifflib |
1 | From: Eric Auger <eric.auger@redhat.com> | 1 | Where architecturally one ARM_FEATURE_X flag implies another |
---|---|---|---|
2 | 2 | ARM_FEATURE_Y, we allow the CPU init function to only set X, and then | |
3 | We need to handle both registers and ITS tables. While | 3 | set Y for it. Currently we do this in two places -- we set a few |
4 | register handling is standard, ITS table handling is more | 4 | flags in arm_cpu_post_init() because we need them to decide which |
5 | challenging since the kernel API is devised so that the | 5 | properties to create on the CPU object, and then we do the rest in |
6 | tables are flushed into guest RAM and not in vmstate buffers. | 6 | arm_cpu_realizefn(). However, this is fragile, because it's easy to |
7 | 7 | add a new property and not notice that this means that an X-implies-Y | |
8 | Flushing the ITS tables on device pre_save() is too late | 8 | check now has to move from realize to post-init. |
9 | since the guest RAM is already saved at this point. | 9 | |
10 | 10 | As a specific example, the pmsav7-dregion property is conditional | |
11 | Table flushing needs to happen when we are sure the vcpus | 11 | on ARM_FEATURE_PMSA && ARM_FEATURE_V7, which means it won't appear |
12 | are stopped and before the last dirty page saving. The | 12 | on the Cortex-M33 and -M55, because they set ARM_FEATURE_V8 and |
13 | right point is RUN_STATE_FINISH_MIGRATE but sometimes the | 13 | rely on V8-implies-V7, which doesn't happen until the realizefn. |
14 | VM gets stopped before migration launch so let's simply | 14 | |
15 | flush the tables each time the VM gets stopped. | 15 | Move all of these X-implies-Y checks into a new function, which |
16 | 16 | we call at the top of arm_cpu_post_init(), so the feature bits | |
17 | For regular ITS registers we just can use vmstate pre_save() | 17 | are available at that point. |
18 | and post_load() callbacks. | 18 | |
19 | 19 | This does now give us the reverse issue, that if there's a feature | |
20 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | 20 | bit which is enabled or disabled by the setting of a property then |
21 | Message-id: 1497023553-18411-3-git-send-email-eric.auger@redhat.com | 21 | then X-implies-Y features that are dependent on that property need to |
22 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 22 | be in realize, not in this new function. But the only one of those |
23 | is the "EL3 implies VBAR" which is already in the right place, so | ||
24 | putting things this way round seems better to me. | ||
25 | |||
23 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 26 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
27 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
28 | Message-id: 20230724174335.2150499-2-peter.maydell@linaro.org | ||
24 | --- | 29 | --- |
25 | include/hw/intc/arm_gicv3_its_common.h | 8 +++ | 30 | target/arm/cpu.c | 179 +++++++++++++++++++++++++---------------------- |
26 | hw/intc/arm_gicv3_its_common.c | 10 ++++ | 31 | 1 file changed, 97 insertions(+), 82 deletions(-) |
27 | hw/intc/arm_gicv3_its_kvm.c | 105 +++++++++++++++++++++++++++++++++ | 32 | |
28 | 3 files changed, 123 insertions(+) | 33 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
29 | |||
30 | diff --git a/include/hw/intc/arm_gicv3_its_common.h b/include/hw/intc/arm_gicv3_its_common.h | ||
31 | index XXXXXXX..XXXXXXX 100644 | 34 | index XXXXXXX..XXXXXXX 100644 |
32 | --- a/include/hw/intc/arm_gicv3_its_common.h | 35 | --- a/target/arm/cpu.c |
33 | +++ b/include/hw/intc/arm_gicv3_its_common.h | 36 | +++ b/target/arm/cpu.c |
34 | @@ -XXX,XX +XXX,XX @@ | 37 | @@ -XXX,XX +XXX,XX @@ unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) |
35 | #define ITS_TRANS_SIZE 0x10000 | 38 | NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; |
36 | #define ITS_SIZE (ITS_CONTROL_SIZE + ITS_TRANS_SIZE) | ||
37 | |||
38 | +#define GITS_CTLR 0x0 | ||
39 | +#define GITS_IIDR 0x4 | ||
40 | +#define GITS_CBASER 0x80 | ||
41 | +#define GITS_CWRITER 0x88 | ||
42 | +#define GITS_CREADR 0x90 | ||
43 | +#define GITS_BASER 0x100 | ||
44 | + | ||
45 | struct GICv3ITSState { | ||
46 | SysBusDevice parent_obj; | ||
47 | |||
48 | @@ -XXX,XX +XXX,XX @@ struct GICv3ITSState { | ||
49 | |||
50 | /* Registers */ | ||
51 | uint32_t ctlr; | ||
52 | + uint32_t iidr; | ||
53 | uint64_t cbaser; | ||
54 | uint64_t cwriter; | ||
55 | uint64_t creadr; | ||
56 | diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c | ||
57 | index XXXXXXX..XXXXXXX 100644 | ||
58 | --- a/hw/intc/arm_gicv3_its_common.c | ||
59 | +++ b/hw/intc/arm_gicv3_its_common.c | ||
60 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_its = { | ||
61 | .pre_save = gicv3_its_pre_save, | ||
62 | .post_load = gicv3_its_post_load, | ||
63 | .unmigratable = true, | ||
64 | + .fields = (VMStateField[]) { | ||
65 | + VMSTATE_UINT32(ctlr, GICv3ITSState), | ||
66 | + VMSTATE_UINT32(iidr, GICv3ITSState), | ||
67 | + VMSTATE_UINT64(cbaser, GICv3ITSState), | ||
68 | + VMSTATE_UINT64(cwriter, GICv3ITSState), | ||
69 | + VMSTATE_UINT64(creadr, GICv3ITSState), | ||
70 | + VMSTATE_UINT64_ARRAY(baser, GICv3ITSState, 8), | ||
71 | + VMSTATE_END_OF_LIST() | ||
72 | + }, | ||
73 | }; | ||
74 | |||
75 | static MemTxResult gicv3_its_trans_read(void *opaque, hwaddr offset, | ||
76 | @@ -XXX,XX +XXX,XX @@ static void gicv3_its_common_reset(DeviceState *dev) | ||
77 | s->cbaser = 0; | ||
78 | s->cwriter = 0; | ||
79 | s->creadr = 0; | ||
80 | + s->iidr = 0; | ||
81 | memset(&s->baser, 0, sizeof(s->baser)); | ||
82 | |||
83 | gicv3_its_post_load(s, 0); | ||
84 | diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c | ||
85 | index XXXXXXX..XXXXXXX 100644 | ||
86 | --- a/hw/intc/arm_gicv3_its_kvm.c | ||
87 | +++ b/hw/intc/arm_gicv3_its_kvm.c | ||
88 | @@ -XXX,XX +XXX,XX @@ static int kvm_its_send_msi(GICv3ITSState *s, uint32_t value, uint16_t devid) | ||
89 | return kvm_vm_ioctl(kvm_state, KVM_SIGNAL_MSI, &msi); | ||
90 | } | 39 | } |
91 | 40 | ||
92 | +/** | 41 | +static void arm_cpu_propagate_feature_implications(ARMCPU *cpu) |
93 | + * vm_change_state_handler - VM change state callback aiming at flushing | ||
94 | + * ITS tables into guest RAM | ||
95 | + * | ||
96 | + * The tables get flushed to guest RAM whenever the VM gets stopped. | ||
97 | + */ | ||
98 | +static void vm_change_state_handler(void *opaque, int running, | ||
99 | + RunState state) | ||
100 | +{ | 42 | +{ |
101 | + GICv3ITSState *s = (GICv3ITSState *)opaque; | 43 | + CPUARMState *env = &cpu->env; |
102 | + Error *err = NULL; | 44 | + bool no_aa32 = false; |
103 | + int ret; | 45 | + |
104 | + | 46 | + /* |
105 | + if (running) { | 47 | + * Some features automatically imply others: set the feature |
106 | + return; | 48 | + * bits explicitly for these cases. |
107 | + } | 49 | + */ |
108 | + | 50 | + |
109 | + ret = kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, | 51 | + if (arm_feature(env, ARM_FEATURE_M)) { |
110 | + KVM_DEV_ARM_ITS_SAVE_TABLES, NULL, true, &err); | 52 | + set_feature(env, ARM_FEATURE_PMSA); |
111 | + if (err) { | 53 | + } |
112 | + error_report_err(err); | 54 | + |
113 | + } | 55 | + if (arm_feature(env, ARM_FEATURE_V8)) { |
114 | + if (ret < 0 && ret != -EFAULT) { | 56 | + if (arm_feature(env, ARM_FEATURE_M)) { |
115 | + abort(); | 57 | + set_feature(env, ARM_FEATURE_V7); |
58 | + } else { | ||
59 | + set_feature(env, ARM_FEATURE_V7VE); | ||
60 | + } | ||
61 | + } | ||
62 | + | ||
63 | + /* | ||
64 | + * There exist AArch64 cpus without AArch32 support. When KVM | ||
65 | + * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. | ||
66 | + * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. | ||
67 | + * As a general principle, we also do not make ID register | ||
68 | + * consistency checks anywhere unless using TCG, because only | ||
69 | + * for TCG would a consistency-check failure be a QEMU bug. | ||
70 | + */ | ||
71 | + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | ||
72 | + no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); | ||
73 | + } | ||
74 | + | ||
75 | + if (arm_feature(env, ARM_FEATURE_V7VE)) { | ||
76 | + /* | ||
77 | + * v7 Virtualization Extensions. In real hardware this implies | ||
78 | + * EL2 and also the presence of the Security Extensions. | ||
79 | + * For QEMU, for backwards-compatibility we implement some | ||
80 | + * CPUs or CPU configs which have no actual EL2 or EL3 but do | ||
81 | + * include the various other features that V7VE implies. | ||
82 | + * Presence of EL2 itself is ARM_FEATURE_EL2, and of the | ||
83 | + * Security Extensions is ARM_FEATURE_EL3. | ||
84 | + */ | ||
85 | + assert(!tcg_enabled() || no_aa32 || | ||
86 | + cpu_isar_feature(aa32_arm_div, cpu)); | ||
87 | + set_feature(env, ARM_FEATURE_LPAE); | ||
88 | + set_feature(env, ARM_FEATURE_V7); | ||
89 | + } | ||
90 | + if (arm_feature(env, ARM_FEATURE_V7)) { | ||
91 | + set_feature(env, ARM_FEATURE_VAPA); | ||
92 | + set_feature(env, ARM_FEATURE_THUMB2); | ||
93 | + set_feature(env, ARM_FEATURE_MPIDR); | ||
94 | + if (!arm_feature(env, ARM_FEATURE_M)) { | ||
95 | + set_feature(env, ARM_FEATURE_V6K); | ||
96 | + } else { | ||
97 | + set_feature(env, ARM_FEATURE_V6); | ||
98 | + } | ||
99 | + | ||
100 | + /* | ||
101 | + * Always define VBAR for V7 CPUs even if it doesn't exist in | ||
102 | + * non-EL3 configs. This is needed by some legacy boards. | ||
103 | + */ | ||
104 | + set_feature(env, ARM_FEATURE_VBAR); | ||
105 | + } | ||
106 | + if (arm_feature(env, ARM_FEATURE_V6K)) { | ||
107 | + set_feature(env, ARM_FEATURE_V6); | ||
108 | + set_feature(env, ARM_FEATURE_MVFR); | ||
109 | + } | ||
110 | + if (arm_feature(env, ARM_FEATURE_V6)) { | ||
111 | + set_feature(env, ARM_FEATURE_V5); | ||
112 | + if (!arm_feature(env, ARM_FEATURE_M)) { | ||
113 | + assert(!tcg_enabled() || no_aa32 || | ||
114 | + cpu_isar_feature(aa32_jazelle, cpu)); | ||
115 | + set_feature(env, ARM_FEATURE_AUXCR); | ||
116 | + } | ||
117 | + } | ||
118 | + if (arm_feature(env, ARM_FEATURE_V5)) { | ||
119 | + set_feature(env, ARM_FEATURE_V4T); | ||
120 | + } | ||
121 | + if (arm_feature(env, ARM_FEATURE_LPAE)) { | ||
122 | + set_feature(env, ARM_FEATURE_V7MP); | ||
123 | + } | ||
124 | + if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { | ||
125 | + set_feature(env, ARM_FEATURE_CBAR); | ||
126 | + } | ||
127 | + if (arm_feature(env, ARM_FEATURE_THUMB2) && | ||
128 | + !arm_feature(env, ARM_FEATURE_M)) { | ||
129 | + set_feature(env, ARM_FEATURE_THUMB_DSP); | ||
116 | + } | 130 | + } |
117 | +} | 131 | +} |
118 | + | 132 | + |
119 | static void kvm_arm_its_realize(DeviceState *dev, Error **errp) | 133 | void arm_cpu_post_init(Object *obj) |
120 | { | 134 | { |
121 | GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev); | 135 | ARMCPU *cpu = ARM_CPU(obj); |
122 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_realize(DeviceState *dev, Error **errp) | 136 | |
123 | kvm_msi_use_devid = true; | 137 | - /* M profile implies PMSA. We have to do this here rather than |
124 | kvm_gsi_direct_mapping = false; | 138 | - * in realize with the other feature-implication checks because |
125 | kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled(); | 139 | - * we look at the PMSA bit to see if we should add some properties. |
126 | + | ||
127 | + qemu_add_vm_change_state_handler(vm_change_state_handler, s); | ||
128 | } | ||
129 | |||
130 | static void kvm_arm_its_init(Object *obj) | ||
131 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_init(Object *obj) | ||
132 | &error_abort); | ||
133 | } | ||
134 | |||
135 | +/** | ||
136 | + * kvm_arm_its_pre_save - handles the saving of ITS registers. | ||
137 | + * ITS tables are flushed into guest RAM separately and earlier, | ||
138 | + * through the VM change state handler, since at the moment pre_save() | ||
139 | + * is called, the guest RAM has already been saved. | ||
140 | + */ | ||
141 | +static void kvm_arm_its_pre_save(GICv3ITSState *s) | ||
142 | +{ | ||
143 | + int i; | ||
144 | + | ||
145 | + for (i = 0; i < 8; i++) { | ||
146 | + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, | ||
147 | + GITS_BASER + i * 8, &s->baser[i], false, | ||
148 | + &error_abort); | ||
149 | + } | ||
150 | + | ||
151 | + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, | ||
152 | + GITS_CTLR, &s->ctlr, false, &error_abort); | ||
153 | + | ||
154 | + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, | ||
155 | + GITS_CBASER, &s->cbaser, false, &error_abort); | ||
156 | + | ||
157 | + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, | ||
158 | + GITS_CREADR, &s->creadr, false, &error_abort); | ||
159 | + | ||
160 | + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, | ||
161 | + GITS_CWRITER, &s->cwriter, false, &error_abort); | ||
162 | + | ||
163 | + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, | ||
164 | + GITS_IIDR, &s->iidr, false, &error_abort); | ||
165 | +} | ||
166 | + | ||
167 | +/** | ||
168 | + * kvm_arm_its_post_load - Restore both the ITS registers and tables | ||
169 | + */ | ||
170 | +static void kvm_arm_its_post_load(GICv3ITSState *s) | ||
171 | +{ | ||
172 | + int i; | ||
173 | + | ||
174 | + if (!s->iidr) { | ||
175 | + return; | ||
176 | + } | ||
177 | + | ||
178 | + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, | ||
179 | + GITS_IIDR, &s->iidr, true, &error_abort); | ||
180 | + | ||
181 | + /* | 140 | + /* |
182 | + * must be written before GITS_CREADR since GITS_CBASER write | 141 | + * Some features imply others. Figure this out now, because we |
183 | + * access resets GITS_CREADR. | 142 | + * are going to look at the feature bits in deciding which |
184 | + */ | 143 | + * properties to add. |
185 | + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, | 144 | */ |
186 | + GITS_CBASER, &s->cbaser, true, &error_abort); | 145 | - if (arm_feature(&cpu->env, ARM_FEATURE_M)) { |
187 | + | 146 | - set_feature(&cpu->env, ARM_FEATURE_PMSA); |
188 | + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, | 147 | - } |
189 | + GITS_CREADR, &s->creadr, true, &error_abort); | 148 | + arm_cpu_propagate_feature_implications(cpu); |
190 | + | 149 | |
191 | + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, | 150 | if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || |
192 | + GITS_CWRITER, &s->cwriter, true, &error_abort); | 151 | arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { |
193 | + | 152 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
194 | + | 153 | CPUARMState *env = &cpu->env; |
195 | + for (i = 0; i < 8; i++) { | 154 | int pagebits; |
196 | + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, | 155 | Error *local_err = NULL; |
197 | + GITS_BASER + i * 8, &s->baser[i], true, | 156 | - bool no_aa32 = false; |
198 | + &error_abort); | 157 | |
199 | + } | 158 | /* Use pc-relative instructions in system-mode */ |
200 | + | 159 | #ifndef CONFIG_USER_ONLY |
201 | + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, | 160 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
202 | + KVM_DEV_ARM_ITS_RESTORE_TABLES, NULL, true, | 161 | cpu->isar.id_isar3 = u; |
203 | + &error_abort); | 162 | } |
204 | + | 163 | |
205 | + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, | 164 | - /* Some features automatically imply others: */ |
206 | + GITS_CTLR, &s->ctlr, true, &error_abort); | 165 | - if (arm_feature(env, ARM_FEATURE_V8)) { |
207 | +} | 166 | - if (arm_feature(env, ARM_FEATURE_M)) { |
208 | + | 167 | - set_feature(env, ARM_FEATURE_V7); |
209 | static void kvm_arm_its_class_init(ObjectClass *klass, void *data) | 168 | - } else { |
210 | { | 169 | - set_feature(env, ARM_FEATURE_V7VE); |
211 | DeviceClass *dc = DEVICE_CLASS(klass); | 170 | - } |
212 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_class_init(ObjectClass *klass, void *data) | 171 | - } |
213 | 172 | - | |
214 | dc->realize = kvm_arm_its_realize; | 173 | - /* |
215 | icc->send_msi = kvm_its_send_msi; | 174 | - * There exist AArch64 cpus without AArch32 support. When KVM |
216 | + icc->pre_save = kvm_arm_its_pre_save; | 175 | - * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. |
217 | + icc->post_load = kvm_arm_its_post_load; | 176 | - * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. |
218 | } | 177 | - * As a general principle, we also do not make ID register |
219 | 178 | - * consistency checks anywhere unless using TCG, because only | |
220 | static const TypeInfo kvm_arm_its_info = { | 179 | - * for TCG would a consistency-check failure be a QEMU bug. |
180 | - */ | ||
181 | - if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | ||
182 | - no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); | ||
183 | - } | ||
184 | - | ||
185 | - if (arm_feature(env, ARM_FEATURE_V7VE)) { | ||
186 | - /* v7 Virtualization Extensions. In real hardware this implies | ||
187 | - * EL2 and also the presence of the Security Extensions. | ||
188 | - * For QEMU, for backwards-compatibility we implement some | ||
189 | - * CPUs or CPU configs which have no actual EL2 or EL3 but do | ||
190 | - * include the various other features that V7VE implies. | ||
191 | - * Presence of EL2 itself is ARM_FEATURE_EL2, and of the | ||
192 | - * Security Extensions is ARM_FEATURE_EL3. | ||
193 | - */ | ||
194 | - assert(!tcg_enabled() || no_aa32 || | ||
195 | - cpu_isar_feature(aa32_arm_div, cpu)); | ||
196 | - set_feature(env, ARM_FEATURE_LPAE); | ||
197 | - set_feature(env, ARM_FEATURE_V7); | ||
198 | - } | ||
199 | - if (arm_feature(env, ARM_FEATURE_V7)) { | ||
200 | - set_feature(env, ARM_FEATURE_VAPA); | ||
201 | - set_feature(env, ARM_FEATURE_THUMB2); | ||
202 | - set_feature(env, ARM_FEATURE_MPIDR); | ||
203 | - if (!arm_feature(env, ARM_FEATURE_M)) { | ||
204 | - set_feature(env, ARM_FEATURE_V6K); | ||
205 | - } else { | ||
206 | - set_feature(env, ARM_FEATURE_V6); | ||
207 | - } | ||
208 | - | ||
209 | - /* Always define VBAR for V7 CPUs even if it doesn't exist in | ||
210 | - * non-EL3 configs. This is needed by some legacy boards. | ||
211 | - */ | ||
212 | - set_feature(env, ARM_FEATURE_VBAR); | ||
213 | - } | ||
214 | - if (arm_feature(env, ARM_FEATURE_V6K)) { | ||
215 | - set_feature(env, ARM_FEATURE_V6); | ||
216 | - set_feature(env, ARM_FEATURE_MVFR); | ||
217 | - } | ||
218 | - if (arm_feature(env, ARM_FEATURE_V6)) { | ||
219 | - set_feature(env, ARM_FEATURE_V5); | ||
220 | - if (!arm_feature(env, ARM_FEATURE_M)) { | ||
221 | - assert(!tcg_enabled() || no_aa32 || | ||
222 | - cpu_isar_feature(aa32_jazelle, cpu)); | ||
223 | - set_feature(env, ARM_FEATURE_AUXCR); | ||
224 | - } | ||
225 | - } | ||
226 | - if (arm_feature(env, ARM_FEATURE_V5)) { | ||
227 | - set_feature(env, ARM_FEATURE_V4T); | ||
228 | - } | ||
229 | - if (arm_feature(env, ARM_FEATURE_LPAE)) { | ||
230 | - set_feature(env, ARM_FEATURE_V7MP); | ||
231 | - } | ||
232 | - if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { | ||
233 | - set_feature(env, ARM_FEATURE_CBAR); | ||
234 | - } | ||
235 | - if (arm_feature(env, ARM_FEATURE_THUMB2) && | ||
236 | - !arm_feature(env, ARM_FEATURE_M)) { | ||
237 | - set_feature(env, ARM_FEATURE_THUMB_DSP); | ||
238 | - } | ||
239 | |||
240 | /* | ||
241 | * We rely on no XScale CPU having VFP so we can use the same bits in the | ||
221 | -- | 242 | -- |
222 | 2.7.4 | 243 | 2.34.1 |
223 | |||
224 | diff view generated by jsdifflib |
1 | From: Eric Auger <eric.auger@redhat.com> | 1 | M-profile CPUs generally allow configuration of the number of MPU |
---|---|---|---|
2 | regions that they have. We don't currently model this, so our | ||
3 | implementations of some of the board models provide CPUs with the | ||
4 | wrong number of regions. RTOSes like Zephyr that hardcode the | ||
5 | expected number of regions may therefore not run on the model if they | ||
6 | are set up to run on real hardware. | ||
2 | 7 | ||
3 | We change the restoration priority of both the GICv3 and ITS. The | 8 | Add properties mpu-ns-regions and mpu-s-regions to the ARMV7M object, |
4 | GICv3 must be restored before the ITS and the ITS needs to be restored | 9 | matching the ability of hardware to configure the number of Secure |
5 | before PCIe devices since it translates their MSI transactions. | 10 | and NonSecure regions separately. Our actual CPU implementation |
11 | doesn't currently support that, and it happens that none of the MPS | ||
12 | boards we model set the number of regions differently for Secure vs | ||
13 | NonSecure, so we provide an interface to the boards and SoCs that | ||
14 | won't need to change if we ever do add that functionality in future, | ||
15 | but make it an error to configure the two properties to different | ||
16 | values. | ||
6 | 17 | ||
7 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | 18 | (The property name on the CPU is the somewhat misnamed-for-M-profile |
8 | Reviewed-by: Juan Quintela <quintela@redhat.com> | 19 | "pmsav7-dregion", so we don't follow that naming convention for |
9 | Message-id: 1497023553-18411-5-git-send-email-eric.auger@redhat.com | 20 | the properties here. The TRM doesn't say what the CPU configuration |
21 | variable names are, so we pick something, and follow the lowercase | ||
22 | convention we already have for properties here.) | ||
23 | |||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 24 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
25 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
26 | Message-id: 20230724174335.2150499-3-peter.maydell@linaro.org | ||
11 | --- | 27 | --- |
12 | include/migration/vmstate.h | 2 ++ | 28 | include/hw/arm/armv7m.h | 8 ++++++++ |
13 | hw/intc/arm_gicv3_common.c | 1 + | 29 | hw/arm/armv7m.c | 21 +++++++++++++++++++++ |
14 | hw/intc/arm_gicv3_its_common.c | 2 +- | 30 | 2 files changed, 29 insertions(+) |
15 | hw/intc/arm_gicv3_its_kvm.c | 24 ++++++++++++------------ | ||
16 | 4 files changed, 16 insertions(+), 13 deletions(-) | ||
17 | 31 | ||
18 | diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h | 32 | diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h |
19 | index XXXXXXX..XXXXXXX 100644 | 33 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/include/migration/vmstate.h | 34 | --- a/include/hw/arm/armv7m.h |
21 | +++ b/include/migration/vmstate.h | 35 | +++ b/include/hw/arm/armv7m.h |
22 | @@ -XXX,XX +XXX,XX @@ enum VMStateFlags { | 36 | @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MState, ARMV7M) |
23 | typedef enum { | 37 | * + Property "vfp": enable VFP (forwarded to CPU object) |
24 | MIG_PRI_DEFAULT = 0, | 38 | * + Property "dsp": enable DSP (forwarded to CPU object) |
25 | MIG_PRI_IOMMU, /* Must happen before PCI devices */ | 39 | * + Property "enable-bitband": expose bitbanded IO |
26 | + MIG_PRI_GICV3_ITS, /* Must happen before PCI devices */ | 40 | + * + Property "mpu-ns-regions": number of Non-Secure MPU regions (forwarded |
27 | + MIG_PRI_GICV3, /* Must happen before the ITS */ | 41 | + * to CPU object pmsav7-dregion property; default is whatever the default |
28 | MIG_PRI_MAX, | 42 | + * for the CPU is) |
29 | } MigrationPriority; | 43 | + * + Property "mpu-s-regions": number of Secure MPU regions (default is |
30 | 44 | + * whatever the default for the CPU is; must currently be set to the same | |
31 | diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c | 45 | + * value as mpu-ns-regions if the CPU implements the Security Extension) |
46 | * + Clock input "refclk" is the external reference clock for the systick timers | ||
47 | * + Clock input "cpuclk" is the main CPU clock | ||
48 | */ | ||
49 | @@ -XXX,XX +XXX,XX @@ struct ARMv7MState { | ||
50 | Object *idau; | ||
51 | uint32_t init_svtor; | ||
52 | uint32_t init_nsvtor; | ||
53 | + uint32_t mpu_ns_regions; | ||
54 | + uint32_t mpu_s_regions; | ||
55 | bool enable_bitband; | ||
56 | bool start_powered_off; | ||
57 | bool vfp; | ||
58 | diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c | ||
32 | index XXXXXXX..XXXXXXX 100644 | 59 | index XXXXXXX..XXXXXXX 100644 |
33 | --- a/hw/intc/arm_gicv3_common.c | 60 | --- a/hw/arm/armv7m.c |
34 | +++ b/hw/intc/arm_gicv3_common.c | 61 | +++ b/hw/arm/armv7m.c |
35 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_gicv3 = { | 62 | @@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp) |
36 | .minimum_version_id = 1, | 63 | } |
37 | .pre_save = gicv3_pre_save, | 64 | } |
38 | .post_load = gicv3_post_load, | 65 | |
39 | + .priority = MIG_PRI_GICV3, | 66 | + /* |
40 | .fields = (VMStateField[]) { | 67 | + * Real M-profile hardware can be configured with a different number of |
41 | VMSTATE_UINT32(gicd_ctlr, GICv3State), | 68 | + * MPU regions for Secure vs NonSecure. QEMU's CPU implementation doesn't |
42 | VMSTATE_UINT32_ARRAY(gicd_statusr, GICv3State, 2), | 69 | + * support that yet, so catch attempts to select that. |
43 | diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c | 70 | + */ |
44 | index XXXXXXX..XXXXXXX 100644 | 71 | + if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) && |
45 | --- a/hw/intc/arm_gicv3_its_common.c | 72 | + s->mpu_ns_regions != s->mpu_s_regions) { |
46 | +++ b/hw/intc/arm_gicv3_its_common.c | 73 | + error_setg(errp, |
47 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_its = { | 74 | + "mpu-ns-regions and mpu-s-regions properties must have the same value"); |
48 | .name = "arm_gicv3_its", | 75 | + return; |
49 | .pre_save = gicv3_its_pre_save, | 76 | + } |
50 | .post_load = gicv3_its_post_load, | 77 | + if (s->mpu_ns_regions != UINT_MAX && |
51 | - .unmigratable = true, | 78 | + object_property_find(OBJECT(s->cpu), "pmsav7-dregion")) { |
52 | + .priority = MIG_PRI_GICV3_ITS, | 79 | + if (!object_property_set_uint(OBJECT(s->cpu), "pmsav7-dregion", |
53 | .fields = (VMStateField[]) { | 80 | + s->mpu_ns_regions, errp)) { |
54 | VMSTATE_UINT32(ctlr, GICv3ITSState), | ||
55 | VMSTATE_UINT32(iidr, GICv3ITSState), | ||
56 | diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c | ||
57 | index XXXXXXX..XXXXXXX 100644 | ||
58 | --- a/hw/intc/arm_gicv3_its_kvm.c | ||
59 | +++ b/hw/intc/arm_gicv3_its_kvm.c | ||
60 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_realize(DeviceState *dev, Error **errp) | ||
61 | GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev); | ||
62 | Error *local_err = NULL; | ||
63 | |||
64 | - /* | ||
65 | - * Block migration of a KVM GICv3 ITS device: the API for saving and | ||
66 | - * restoring the state in the kernel is not yet available | ||
67 | - */ | ||
68 | - error_setg(&s->migration_blocker, "vITS migration is not implemented"); | ||
69 | - migrate_add_blocker(s->migration_blocker, &local_err); | ||
70 | - if (local_err) { | ||
71 | - error_propagate(errp, local_err); | ||
72 | - error_free(s->migration_blocker); | ||
73 | - return; | ||
74 | - } | ||
75 | - | ||
76 | s->dev_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_ITS, false); | ||
77 | if (s->dev_fd < 0) { | ||
78 | error_setg_errno(errp, -s->dev_fd, "error creating in-kernel ITS"); | ||
79 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_realize(DeviceState *dev, Error **errp) | ||
80 | |||
81 | gicv3_its_init_mmio(s, NULL); | ||
82 | |||
83 | + if (!kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, | ||
84 | + GITS_CTLR)) { | ||
85 | + error_setg(&s->migration_blocker, "This operating system kernel " | ||
86 | + "does not support vITS migration"); | ||
87 | + migrate_add_blocker(s->migration_blocker, &local_err); | ||
88 | + if (local_err) { | ||
89 | + error_propagate(errp, local_err); | ||
90 | + error_free(s->migration_blocker); | ||
91 | + return; | 81 | + return; |
92 | + } | 82 | + } |
93 | + } | 83 | + } |
94 | + | 84 | + |
95 | kvm_msi_use_devid = true; | 85 | /* |
96 | kvm_gsi_direct_mapping = false; | 86 | * Tell the CPU where the NVIC is; it will fail realize if it doesn't |
97 | kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled(); | 87 | * have one. Similarly, tell the NVIC where its CPU is. |
88 | @@ -XXX,XX +XXX,XX @@ static Property armv7m_properties[] = { | ||
89 | false), | ||
90 | DEFINE_PROP_BOOL("vfp", ARMv7MState, vfp, true), | ||
91 | DEFINE_PROP_BOOL("dsp", ARMv7MState, dsp, true), | ||
92 | + DEFINE_PROP_UINT32("mpu-ns-regions", ARMv7MState, mpu_ns_regions, UINT_MAX), | ||
93 | + DEFINE_PROP_UINT32("mpu-s-regions", ARMv7MState, mpu_s_regions, UINT_MAX), | ||
94 | DEFINE_PROP_END_OF_LIST(), | ||
95 | }; | ||
96 | |||
98 | -- | 97 | -- |
99 | 2.7.4 | 98 | 2.34.1 |
100 | 99 | ||
101 | 100 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | The IoTKit, SSE200 and SSE300 all default to 8 MPU regions. The | |
2 | MPS2/MPS3 FPGA images don't override these except in the case of | ||
3 | AN547, which uses 16 MPU regions. | ||
4 | |||
5 | Define properties on the ARMSSE object for the MPU regions (using the | ||
6 | same names as the documented RTL configuration settings, and | ||
7 | following the pattern we already have for this device of using | ||
8 | all-caps names as the RTL does), and set them in the board code. | ||
9 | |||
10 | We don't actually need to override the default except on AN547, | ||
11 | but it's simpler code to have the board code set them always | ||
12 | rather than tracking which board subtypes want to set them to | ||
13 | a non-default value separately from what that value is. | ||
14 | |||
15 | Tho overall effect is that for mps2-an505, mps2-an521 and mps3-an524 | ||
16 | we now correctly use 8 MPU regions, while mps3-an547 stays at its | ||
17 | current 16 regions. | ||
18 | |||
19 | It's possible some guest code wrongly depended on the previous | ||
20 | incorrectly modeled number of memory regions. (Such guest code | ||
21 | should ideally check the number of regions via the MPU_TYPE | ||
22 | register.) The old behaviour can be obtained with additional | ||
23 | -global arguments to QEMU: | ||
24 | |||
25 | For mps2-an521 and mps2-an524: | ||
26 | -global sse-200.CPU0_MPU_NS=16 -global sse-200.CPU0_MPU_S=16 -global sse-200.CPU1_MPU_NS=16 -global sse-200.CPU1_MPU_S=16 | ||
27 | |||
28 | For mps2-an505: | ||
29 | -global sse-200.CPU0_MPU_NS=16 -global sse-200.CPU0_MPU_S=16 | ||
30 | |||
31 | NB that the way the implementation allows this use of -global | ||
32 | is slightly fragile: if the board code explicitly sets the | ||
33 | properties on the sse-200 object, this overrides the -global | ||
34 | command line option. So we rely on: | ||
35 | - the boards that need fixing all happen to use the SSE defaults | ||
36 | - we can write the board code to only set the property if it | ||
37 | is different from the default, rather than having all boards | ||
38 | explicitly set the property | ||
39 | - the board that does need to use a non-default value happens | ||
40 | to need to set it to the same value (16) we previously used | ||
41 | This works, but there are some kinds of refactoring of the | ||
42 | mps2-tz.c code that would break the support for -global here. | ||
43 | |||
44 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1772 | ||
45 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
46 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
47 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
48 | Message-id: 20230724174335.2150499-4-peter.maydell@linaro.org | ||
49 | --- | ||
50 | include/hw/arm/armsse.h | 5 +++++ | ||
51 | hw/arm/armsse.c | 16 ++++++++++++++++ | ||
52 | hw/arm/mps2-tz.c | 29 +++++++++++++++++++++++++++++ | ||
53 | 3 files changed, 50 insertions(+) | ||
54 | |||
55 | diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h | ||
56 | index XXXXXXX..XXXXXXX 100644 | ||
57 | --- a/include/hw/arm/armsse.h | ||
58 | +++ b/include/hw/arm/armsse.h | ||
59 | @@ -XXX,XX +XXX,XX @@ | ||
60 | * (matching the hardware) is that for CPU0 in an IoTKit and CPU1 in an | ||
61 | * SSE-200 both are present; CPU0 in an SSE-200 has neither. | ||
62 | * Since the IoTKit has only one CPU, it does not have the CPU1_* properties. | ||
63 | + * + QOM properties "CPU0_MPU_NS", "CPU0_MPU_S", "CPU1_MPU_NS" and "CPU1_MPU_S" | ||
64 | + * which set the number of MPU regions on the CPUs. If there is only one | ||
65 | + * CPU the CPU1 properties are not present. | ||
66 | * + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CPU 0, | ||
67 | * which are wired to its NVIC lines 32 .. n+32 | ||
68 | * + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts for | ||
69 | @@ -XXX,XX +XXX,XX @@ struct ARMSSE { | ||
70 | uint32_t exp_numirq; | ||
71 | uint32_t sram_addr_width; | ||
72 | uint32_t init_svtor; | ||
73 | + uint32_t cpu_mpu_ns[SSE_MAX_CPUS]; | ||
74 | + uint32_t cpu_mpu_s[SSE_MAX_CPUS]; | ||
75 | bool cpu_fpu[SSE_MAX_CPUS]; | ||
76 | bool cpu_dsp[SSE_MAX_CPUS]; | ||
77 | }; | ||
78 | diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c | ||
79 | index XXXXXXX..XXXXXXX 100644 | ||
80 | --- a/hw/arm/armsse.c | ||
81 | +++ b/hw/arm/armsse.c | ||
82 | @@ -XXX,XX +XXX,XX @@ static Property iotkit_properties[] = { | ||
83 | DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), | ||
84 | DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true), | ||
85 | DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true), | ||
86 | + DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8), | ||
87 | + DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8), | ||
88 | DEFINE_PROP_END_OF_LIST() | ||
89 | }; | ||
90 | |||
91 | @@ -XXX,XX +XXX,XX @@ static Property sse200_properties[] = { | ||
92 | DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false), | ||
93 | DEFINE_PROP_BOOL("CPU1_FPU", ARMSSE, cpu_fpu[1], true), | ||
94 | DEFINE_PROP_BOOL("CPU1_DSP", ARMSSE, cpu_dsp[1], true), | ||
95 | + DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8), | ||
96 | + DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8), | ||
97 | + DEFINE_PROP_UINT32("CPU1_MPU_NS", ARMSSE, cpu_mpu_ns[1], 8), | ||
98 | + DEFINE_PROP_UINT32("CPU1_MPU_S", ARMSSE, cpu_mpu_s[1], 8), | ||
99 | DEFINE_PROP_END_OF_LIST() | ||
100 | }; | ||
101 | |||
102 | @@ -XXX,XX +XXX,XX @@ static Property sse300_properties[] = { | ||
103 | DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), | ||
104 | DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true), | ||
105 | DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true), | ||
106 | + DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8), | ||
107 | + DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8), | ||
108 | DEFINE_PROP_END_OF_LIST() | ||
109 | }; | ||
110 | |||
111 | @@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp) | ||
112 | return; | ||
113 | } | ||
114 | } | ||
115 | + if (!object_property_set_uint(cpuobj, "mpu-ns-regions", | ||
116 | + s->cpu_mpu_ns[i], errp)) { | ||
117 | + return; | ||
118 | + } | ||
119 | + if (!object_property_set_uint(cpuobj, "mpu-s-regions", | ||
120 | + s->cpu_mpu_s[i], errp)) { | ||
121 | + return; | ||
122 | + } | ||
123 | |||
124 | if (i > 0) { | ||
125 | memory_region_add_subregion_overlap(&s->cpu_container[i], 0, | ||
126 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c | ||
127 | index XXXXXXX..XXXXXXX 100644 | ||
128 | --- a/hw/arm/mps2-tz.c | ||
129 | +++ b/hw/arm/mps2-tz.c | ||
130 | @@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineClass { | ||
131 | int uart_overflow_irq; /* number of the combined UART overflow IRQ */ | ||
132 | uint32_t init_svtor; /* init-svtor setting for SSE */ | ||
133 | uint32_t sram_addr_width; /* SRAM_ADDR_WIDTH setting for SSE */ | ||
134 | + uint32_t cpu0_mpu_ns; /* CPU0_MPU_NS setting for SSE */ | ||
135 | + uint32_t cpu0_mpu_s; /* CPU0_MPU_S setting for SSE */ | ||
136 | + uint32_t cpu1_mpu_ns; /* CPU1_MPU_NS setting for SSE */ | ||
137 | + uint32_t cpu1_mpu_s; /* CPU1_MPU_S setting for SSE */ | ||
138 | const RAMInfo *raminfo; | ||
139 | const char *armsse_type; | ||
140 | uint32_t boot_ram_size; /* size of ram at address 0; 0 == find in raminfo */ | ||
141 | @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE) | ||
142 | #define MPS3_DDR_SIZE (2 * GiB) | ||
143 | #endif | ||
144 | |||
145 | +/* For cpu{0,1}_mpu_{ns,s}, means "leave at SSE's default value" */ | ||
146 | +#define MPU_REGION_DEFAULT UINT32_MAX | ||
147 | + | ||
148 | static const uint32_t an505_oscclk[] = { | ||
149 | 40000000, | ||
150 | 24580000, | ||
151 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) | ||
152 | OBJECT(system_memory), &error_abort); | ||
153 | qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq); | ||
154 | qdev_prop_set_uint32(iotkitdev, "init-svtor", mmc->init_svtor); | ||
155 | + if (mmc->cpu0_mpu_ns != MPU_REGION_DEFAULT) { | ||
156 | + qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_NS", mmc->cpu0_mpu_ns); | ||
157 | + } | ||
158 | + if (mmc->cpu0_mpu_s != MPU_REGION_DEFAULT) { | ||
159 | + qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_S", mmc->cpu0_mpu_s); | ||
160 | + } | ||
161 | + if (object_property_find(OBJECT(iotkitdev), "CPU1_MPU_NS")) { | ||
162 | + if (mmc->cpu1_mpu_ns != MPU_REGION_DEFAULT) { | ||
163 | + qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_NS", mmc->cpu1_mpu_ns); | ||
164 | + } | ||
165 | + if (mmc->cpu1_mpu_s != MPU_REGION_DEFAULT) { | ||
166 | + qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_S", mmc->cpu1_mpu_s); | ||
167 | + } | ||
168 | + } | ||
169 | qdev_prop_set_uint32(iotkitdev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width); | ||
170 | qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk); | ||
171 | qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk); | ||
172 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_class_init(ObjectClass *oc, void *data) | ||
173 | { | ||
174 | MachineClass *mc = MACHINE_CLASS(oc); | ||
175 | IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc); | ||
176 | + MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); | ||
177 | |||
178 | mc->init = mps2tz_common_init; | ||
179 | mc->reset = mps2_machine_reset; | ||
180 | iic->check = mps2_tz_idau_check; | ||
181 | + | ||
182 | + /* Most machines leave these at the SSE defaults */ | ||
183 | + mmc->cpu0_mpu_ns = MPU_REGION_DEFAULT; | ||
184 | + mmc->cpu0_mpu_s = MPU_REGION_DEFAULT; | ||
185 | + mmc->cpu1_mpu_ns = MPU_REGION_DEFAULT; | ||
186 | + mmc->cpu1_mpu_s = MPU_REGION_DEFAULT; | ||
187 | } | ||
188 | |||
189 | static void mps2tz_set_default_ram_info(MPS2TZMachineClass *mmc) | ||
190 | @@ -XXX,XX +XXX,XX @@ static void mps3tz_an547_class_init(ObjectClass *oc, void *data) | ||
191 | mmc->numirq = 96; | ||
192 | mmc->uart_overflow_irq = 48; | ||
193 | mmc->init_svtor = 0x00000000; | ||
194 | + mmc->cpu0_mpu_s = mmc->cpu0_mpu_ns = 16; | ||
195 | mmc->sram_addr_width = 21; | ||
196 | mmc->raminfo = an547_raminfo; | ||
197 | mmc->armsse_type = TYPE_SSE300; | ||
198 | -- | ||
199 | 2.34.1 | ||
200 | |||
201 | diff view generated by jsdifflib |