If EL3 is not implemented (ie only one security state) then the
one and only ICC_BPR1 register behaves like the Non-secure
ICC_BPR1 in an EL3-present configuration. In particular, its
reset value is GIC_MIN_BPR_NS, not GIC_MIN_BPR.

Correct the erroneous reset value; this fixes a problem where
we might hit the assert added in commit a89ff39ee901.

Reported-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/arm_gicv3_cpuif.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index 09d8ba0..5cbafaf 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -2039,11 +2039,7 @@ static void icc_reset(CPUARMState *env, const ARMCPRegInfo *ri)
     cs->icc_pmr_el1 = 0;
     cs->icc_bpr[GICV3_G0] = GIC_MIN_BPR;
     cs->icc_bpr[GICV3_G1] = GIC_MIN_BPR;
-    if (arm_feature(env, ARM_FEATURE_EL3)) {
-        cs->icc_bpr[GICV3_G1NS] = GIC_MIN_BPR_NS;
-    } else {
-        cs->icc_bpr[GICV3_G1NS] = GIC_MIN_BPR;
-    }
+    cs->icc_bpr[GICV3_G1NS] = GIC_MIN_BPR_NS;
     memset(cs->icc_apr, 0, sizeof(cs->icc_apr));
     memset(cs->icc_igrpen, 0, sizeof(cs->icc_igrpen));
     cs->icc_ctlr_el3 = ICC_CTLR_EL3_NDS | ICC_CTLR_EL3_A3V |
-- 
2.7.4

Peter Maydell <peter.maydell@linaro.org> writes:

> If EL3 is not implemented (ie only one security state) then the
> one and only ICC_BPR1 register behaves like the Non-secure
> ICC_BPR1 in an EL3-present configuration. In particular, its
> reset value is GIC_MIN_BPR_NS, not GIC_MIN_BPR.
>
> Correct the erroneous reset value; this fixes a problem where
> we might hit the assert added in commit a89ff39ee901.
>
> Reported-by: Alex Bennée <alex.bennee@linaro.org>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>

> ---
>  hw/intc/arm_gicv3_cpuif.c | 6 +-----
>  1 file changed, 1 insertion(+), 5 deletions(-)
>
> diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
> index 09d8ba0..5cbafaf 100644
> --- a/hw/intc/arm_gicv3_cpuif.c
> +++ b/hw/intc/arm_gicv3_cpuif.c
> @@ -2039,11 +2039,7 @@ static void icc_reset(CPUARMState *env, const ARMCPRegInfo *ri)
>      cs->icc_pmr_el1 = 0;
>      cs->icc_bpr[GICV3_G0] = GIC_MIN_BPR;
>      cs->icc_bpr[GICV3_G1] = GIC_MIN_BPR;
> -    if (arm_feature(env, ARM_FEATURE_EL3)) {
> -        cs->icc_bpr[GICV3_G1NS] = GIC_MIN_BPR_NS;
> -    } else {
> -        cs->icc_bpr[GICV3_G1NS] = GIC_MIN_BPR;
> -    }
> +    cs->icc_bpr[GICV3_G1NS] = GIC_MIN_BPR_NS;
>      memset(cs->icc_apr, 0, sizeof(cs->icc_apr));
>      memset(cs->icc_igrpen, 0, sizeof(cs->icc_igrpen));
>      cs->icc_ctlr_el3 = ICC_CTLR_EL3_NDS | ICC_CTLR_EL3_A3V |


--
Alex Bennée

On 7 June 2017 at 17:13, Alex Bennée <alex.bennee@linaro.org> wrote:
>
> Peter Maydell <peter.maydell@linaro.org> writes:
>
>> If EL3 is not implemented (ie only one security state) then the
>> one and only ICC_BPR1 register behaves like the Non-secure
>> ICC_BPR1 in an EL3-present configuration. In particular, its
>> reset value is GIC_MIN_BPR_NS, not GIC_MIN_BPR.
>>
>> Correct the erroneous reset value; this fixes a problem where
>> we might hit the assert added in commit a89ff39ee901.
>>
>> Reported-by: Alex Bennée <alex.bennee@linaro.org>
>> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> Tested-by: Alex Bennée <alex.bennee@linaro.org>

Thanks; applied to master as a fix for an assertion failure
(still not sure why I don't see it).

-- PMM