The access_type argument to get_phys_addr_lpae() is an MMUAccessType;

use the enum constant MMU_DATA_LOAD rather than a literal 0 when we

call it in S1_ptw_translate().

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20200330210400.11724-3-peter.maydell@linaro.org

---

target/arm/helper.c | 5 +++--

1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/helper.c

+++ b/target/arm/helper.c

@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,

pcacheattrs = &cacheattrs;

}

- ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_Stage2, &s2pa,

- &txattrs, &s2prot, &s2size, fi, pcacheattrs);

+ ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, ARMMMUIdx_Stage2,

+ &s2pa, &txattrs, &s2prot, &s2size, fi,

+ pcacheattrs);

if (ret) {

assert(fi->type != ARMFault_None);

fi->s2addr = addr;

--

2.20.1

In aarch64_max_initfn() we update both 32-bit and 64-bit ID

registers. The intended pattern is that for 64-bit ID registers we

use FIELD_DP64 and the uint64_t 't' register, while 32-bit ID

registers use FIELD_DP32 and the uint32_t 'u' register. For

ID_AA64DFR0 we accidentally used 'u', meaning that the top 32 bits of

this 64-bit ID register would end up always zero. Luckily at the

moment that's what they should be anyway, so this bug has no visible

effects.

Use the right-sized variable.

Fixes: 3bec78447a958d481991

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Message-id: 20200423110915.10527-1-peter.maydell@linaro.org

---

target/arm/cpu64.c | 6 +++---

1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu64.c

+++ b/target/arm/cpu64.c

@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)

u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */

cpu->isar.id_mmfr4 = u;

- u = cpu->isar.id_aa64dfr0;

- u = FIELD_DP64(u, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */

- cpu->isar.id_aa64dfr0 = u;

+ t = cpu->isar.id_aa64dfr0;

+ t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */

+ cpu->isar.id_aa64dfr0 = t;

u = cpu->isar.id_dfr0;

u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */

--

2.20.1

MIDR_EL1 is a 64-bit system register with the top 32-bit being RES0.

Represent it in QEMU's ARMCPU struct with a uint64_t, not a

uint32_t.

This fixes an error when compiling with -Werror=conversion

because we were manipulating the register value using a

local uint64_t variable:

target/arm/cpu64.c: In function ‘aarch64_max_initfn’:

target/arm/cpu64.c:628:21: error: conversion from ‘uint64_t’ {aka ‘long unsigned int’} to ‘uint32_t’ {aka ‘unsigned int’} may change value [-Werror=conversion]

628 | cpu->midr = t;

| ^

and future-proofs us against a possible future architecture

change using some of the top 32 bits.

Suggested-by: Laurent Desnogues <laurent.desnogues@gmail.com>

Suggested-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>

Message-id: 20200428172634.29707-1-f4bug@amsat.org

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Remove inclusion of arm_gicv3_common.h, this already gets

included via xlnx-versal.h.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Reviewed-by: Luc Michel <luc.michel@greensocs.com>

Message-id: 20200427181649.26851-2-edgar.iglesias@gmail.com

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

hw/arm/xlnx-versal.c | 1 -

1 file changed, 1 deletion(-)

diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/xlnx-versal.c

+++ b/hw/arm/xlnx-versal.c

@@ -XXX,XX +XXX,XX @@

#include "hw/arm/boot.h"

#include "kvm_arm.h"

#include "hw/misc/unimp.h"

-#include "hw/intc/arm_gicv3_common.h"

#include "hw/arm/xlnx-versal.h"

#include "hw/char/pl011.h"

--

2.20.1

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Move misplaced comment.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Luc Michel <luc.michel@greensocs.com>

Message-id: 20200427181649.26851-3-edgar.iglesias@gmail.com

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

hw/arm/xlnx-versal.c | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/xlnx-versal.c

+++ b/hw/arm/xlnx-versal.c

@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s)

obj = object_new(XLNX_VERSAL_ACPU_TYPE);

if (!obj) {

- /* Secondary CPUs start in PSCI powered-down state */

error_report("Unable to create apu.cpu[%d] of type %s",

i, XLNX_VERSAL_ACPU_TYPE);

exit(EXIT_FAILURE);

@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s)

object_property_set_int(obj, s->cfg.psci_conduit,

"psci-conduit", &error_abort);

if (i) {

+ /* Secondary CPUs start in PSCI powered-down state */

object_property_set_bool(obj, true,

"start-powered-off", &error_abort);

}

--

2.20.1