[libvirt PATCH 0/8] Improve heuristics for computing baseline CPU models

Jiri Denemark posted 8 patches 1 week, 4 days ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/libvirt tags/patchew/cover.1651683161.git.jdenemar@redhat.com
src/cpu/cpu_x86.c                             | 156 ++++++++++++------
src/cpu_map/x86_cpu64-rhel5.xml               |   2 +-
src/cpu_map/x86_cpu64-rhel6.xml               |   2 +-
tests/cputest.c                               | 136 ++++++++++++---
.../cputestdata/x86_64-baseline-1-result.xml  |   5 -
tests/cputestdata/x86_64-baseline-1.xml       |  20 ---
.../cputestdata/x86_64-baseline-2-result.xml  |   4 -
tests/cputestdata/x86_64-baseline-2.xml       |  22 ---
.../x86_64-baseline-5-expanded.xml            |  47 ------
tests/cputestdata/x86_64-baseline-5.xml       |  35 ----
.../x86_64-baseline-6-migratable.xml          |  10 --
.../cputestdata/x86_64-baseline-7-result.xml  |   4 -
tests/cputestdata/x86_64-baseline-7.xml       |  24 ---
.../cputestdata/x86_64-baseline-8-result.xml  |   4 -
tests/cputestdata/x86_64-baseline-8.xml       |  28 ----
...-baseline-Westmere+Nehalem-migratable.xml} |   8 +-
...6_64-baseline-Westmere+Nehalem-result.xml} |   8 +-
...l => x86_64-baseline-Westmere+Nehalem.xml} |   0
... => x86_64-baseline-features-expanded.xml} |   0
...ml => x86_64-baseline-features-result.xml} |   0
...ine-4.xml => x86_64-baseline-features.xml} |   0
.../x86_64-baseline-no-vendor-result.xml      |   3 +-
...ml => x86_64-baseline-simple-expanded.xml} |   0
....xml => x86_64-baseline-simple-result.xml} |   0
...eline-3.xml => x86_64-baseline-simple.xml} |   0
.../x86_64-cpuid-Atom-D510-guest.xml          |   5 +-
.../x86_64-cpuid-Atom-N450-guest.xml          |   5 +-
.../x86_64-cpuid-Phenom-B95-json.xml          |  21 ++-
...id-baseline-Broadwell-IBRS+Cascadelake.xml |  14 ++
..._64-cpuid-baseline-Cascadelake+Icelake.xml |  15 ++
...puid-baseline-Cascadelake+Skylake-IBRS.xml |  13 ++
..._64-cpuid-baseline-Cascadelake+Skylake.xml |   8 +
...-cpuid-baseline-Cooperlake+Cascadelake.xml |  22 +++
...6_64-cpuid-baseline-Cooperlake+Icelake.xml |  15 ++
.../x86_64-cpuid-baseline-EPYC+Rome.xml       |  13 ++
.../x86_64-cpuid-baseline-Haswell+Skylake.xml |  14 ++
...-baseline-Haswell-noTSX-IBRS+Broadwell.xml |  14 ++
...seline-Haswell-noTSX-IBRS+Skylake-IBRS.xml |  14 ++
...id-baseline-Haswell-noTSX-IBRS+Skylake.xml |  14 ++
.../x86_64-cpuid-baseline-Ryzen+Rome.xml      |  13 ++
...4-cpuid-baseline-Skylake-Client+Server.xml |   9 +
.../x86_64-host+guest,models-result.xml       |  10 +-
.../domaincapsdata/qemu_3.1.0-tcg.x86_64.xml  |  35 ++--
.../domaincapsdata/qemu_4.0.0-tcg.x86_64.xml  |  36 ++--
.../domaincapsdata/qemu_4.1.0-tcg.x86_64.xml  |  37 +++--
.../domaincapsdata/qemu_4.2.0-tcg.x86_64.xml  |  37 +++--
.../domaincapsdata/qemu_5.0.0-tcg.x86_64.xml  |  36 ++--
.../domaincapsdata/qemu_5.1.0-tcg.x86_64.xml  |  36 ++--
.../domaincapsdata/qemu_5.2.0-tcg.x86_64.xml  |  36 ++--
.../domaincapsdata/qemu_6.0.0-tcg.x86_64.xml  |  36 ++--
.../domaincapsdata/qemu_6.1.0-tcg.x86_64.xml  |  36 ++--
.../domaincapsdata/qemu_6.2.0-tcg.x86_64.xml  |  36 ++--
.../domaincapsdata/qemu_7.0.0-tcg.x86_64.xml  |  36 ++--
tests/qemuxml2argvdata/cpu-fallback.args      |   2 +-
.../cpu-host-model-cmt.x86_64-4.0.0.args      |   2 +-
.../cpu-host-model-fallback.args              |   2 +-
56 files changed, 681 insertions(+), 459 deletions(-)
delete mode 100644 tests/cputestdata/x86_64-baseline-1-result.xml
delete mode 100644 tests/cputestdata/x86_64-baseline-1.xml
delete mode 100644 tests/cputestdata/x86_64-baseline-2-result.xml
delete mode 100644 tests/cputestdata/x86_64-baseline-2.xml
delete mode 100644 tests/cputestdata/x86_64-baseline-5-expanded.xml
delete mode 100644 tests/cputestdata/x86_64-baseline-5.xml
delete mode 100644 tests/cputestdata/x86_64-baseline-6-migratable.xml
delete mode 100644 tests/cputestdata/x86_64-baseline-7-result.xml
delete mode 100644 tests/cputestdata/x86_64-baseline-7.xml
delete mode 100644 tests/cputestdata/x86_64-baseline-8-result.xml
delete mode 100644 tests/cputestdata/x86_64-baseline-8.xml
rename tests/cputestdata/{x86_64-baseline-5-result.xml => x86_64-baseline-Westmere+Nehalem-migratable.xml} (51%)
rename tests/cputestdata/{x86_64-baseline-6-result.xml => x86_64-baseline-Westmere+Nehalem-result.xml} (54%)
rename tests/cputestdata/{x86_64-baseline-6.xml => x86_64-baseline-Westmere+Nehalem.xml} (100%)
rename tests/cputestdata/{x86_64-baseline-4-expanded.xml => x86_64-baseline-features-expanded.xml} (100%)
rename tests/cputestdata/{x86_64-baseline-4-result.xml => x86_64-baseline-features-result.xml} (100%)
rename tests/cputestdata/{x86_64-baseline-4.xml => x86_64-baseline-features.xml} (100%)
rename tests/cputestdata/{x86_64-baseline-3-expanded.xml => x86_64-baseline-simple-expanded.xml} (100%)
rename tests/cputestdata/{x86_64-baseline-3-result.xml => x86_64-baseline-simple-result.xml} (100%)
rename tests/cputestdata/{x86_64-baseline-3.xml => x86_64-baseline-simple.xml} (100%)
create mode 100644 tests/cputestdata/x86_64-cpuid-baseline-Broadwell-IBRS+Cascadelake.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-baseline-Cascadelake+Icelake.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-baseline-Cascadelake+Skylake-IBRS.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-baseline-Cascadelake+Skylake.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-baseline-Cooperlake+Cascadelake.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-baseline-Cooperlake+Icelake.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-baseline-EPYC+Rome.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-baseline-Haswell+Skylake.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-baseline-Haswell-noTSX-IBRS+Broadwell.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-baseline-Haswell-noTSX-IBRS+Skylake-IBRS.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-baseline-Haswell-noTSX-IBRS+Skylake.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-baseline-Ryzen+Rome.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-baseline-Skylake-Client+Server.xml
[libvirt PATCH 0/8] Improve heuristics for computing baseline CPU models
Posted by Jiri Denemark 1 week, 4 days ago
See 7/8 and 8/8 for details.

https://bugzilla.redhat.com/show_bug.cgi?id=1851227

Jiri Denemark (8):
  cpu_map: Disable cpu64-rhel* for host-model and baseline
  cputest: Drop some old artificial baseline tests
  cputest: Give better names to baseline tests
  cputest: Add some real world baseline tests
  cpu_x86: Consolidate signature match in x86DecodeUseCandidate
  cpu_x86: Refactor feature list comparison in x86DecodeUseCandidate
  cpu_x86: Penalize disabled features when computing CPU model
  cpu_x86: Ignore enabled features for input models in
    x86DecodeUseCandidate

 src/cpu/cpu_x86.c                             | 156 ++++++++++++------
 src/cpu_map/x86_cpu64-rhel5.xml               |   2 +-
 src/cpu_map/x86_cpu64-rhel6.xml               |   2 +-
 tests/cputest.c                               | 136 ++++++++++++---
 .../cputestdata/x86_64-baseline-1-result.xml  |   5 -
 tests/cputestdata/x86_64-baseline-1.xml       |  20 ---
 .../cputestdata/x86_64-baseline-2-result.xml  |   4 -
 tests/cputestdata/x86_64-baseline-2.xml       |  22 ---
 .../x86_64-baseline-5-expanded.xml            |  47 ------
 tests/cputestdata/x86_64-baseline-5.xml       |  35 ----
 .../x86_64-baseline-6-migratable.xml          |  10 --
 .../cputestdata/x86_64-baseline-7-result.xml  |   4 -
 tests/cputestdata/x86_64-baseline-7.xml       |  24 ---
 .../cputestdata/x86_64-baseline-8-result.xml  |   4 -
 tests/cputestdata/x86_64-baseline-8.xml       |  28 ----
 ...-baseline-Westmere+Nehalem-migratable.xml} |   8 +-
 ...6_64-baseline-Westmere+Nehalem-result.xml} |   8 +-
 ...l => x86_64-baseline-Westmere+Nehalem.xml} |   0
 ... => x86_64-baseline-features-expanded.xml} |   0
 ...ml => x86_64-baseline-features-result.xml} |   0
 ...ine-4.xml => x86_64-baseline-features.xml} |   0
 .../x86_64-baseline-no-vendor-result.xml      |   3 +-
 ...ml => x86_64-baseline-simple-expanded.xml} |   0
 ....xml => x86_64-baseline-simple-result.xml} |   0
 ...eline-3.xml => x86_64-baseline-simple.xml} |   0
 .../x86_64-cpuid-Atom-D510-guest.xml          |   5 +-
 .../x86_64-cpuid-Atom-N450-guest.xml          |   5 +-
 .../x86_64-cpuid-Phenom-B95-json.xml          |  21 ++-
 ...id-baseline-Broadwell-IBRS+Cascadelake.xml |  14 ++
 ..._64-cpuid-baseline-Cascadelake+Icelake.xml |  15 ++
 ...puid-baseline-Cascadelake+Skylake-IBRS.xml |  13 ++
 ..._64-cpuid-baseline-Cascadelake+Skylake.xml |   8 +
 ...-cpuid-baseline-Cooperlake+Cascadelake.xml |  22 +++
 ...6_64-cpuid-baseline-Cooperlake+Icelake.xml |  15 ++
 .../x86_64-cpuid-baseline-EPYC+Rome.xml       |  13 ++
 .../x86_64-cpuid-baseline-Haswell+Skylake.xml |  14 ++
 ...-baseline-Haswell-noTSX-IBRS+Broadwell.xml |  14 ++
 ...seline-Haswell-noTSX-IBRS+Skylake-IBRS.xml |  14 ++
 ...id-baseline-Haswell-noTSX-IBRS+Skylake.xml |  14 ++
 .../x86_64-cpuid-baseline-Ryzen+Rome.xml      |  13 ++
 ...4-cpuid-baseline-Skylake-Client+Server.xml |   9 +
 .../x86_64-host+guest,models-result.xml       |  10 +-
 .../domaincapsdata/qemu_3.1.0-tcg.x86_64.xml  |  35 ++--
 .../domaincapsdata/qemu_4.0.0-tcg.x86_64.xml  |  36 ++--
 .../domaincapsdata/qemu_4.1.0-tcg.x86_64.xml  |  37 +++--
 .../domaincapsdata/qemu_4.2.0-tcg.x86_64.xml  |  37 +++--
 .../domaincapsdata/qemu_5.0.0-tcg.x86_64.xml  |  36 ++--
 .../domaincapsdata/qemu_5.1.0-tcg.x86_64.xml  |  36 ++--
 .../domaincapsdata/qemu_5.2.0-tcg.x86_64.xml  |  36 ++--
 .../domaincapsdata/qemu_6.0.0-tcg.x86_64.xml  |  36 ++--
 .../domaincapsdata/qemu_6.1.0-tcg.x86_64.xml  |  36 ++--
 .../domaincapsdata/qemu_6.2.0-tcg.x86_64.xml  |  36 ++--
 .../domaincapsdata/qemu_7.0.0-tcg.x86_64.xml  |  36 ++--
 tests/qemuxml2argvdata/cpu-fallback.args      |   2 +-
 .../cpu-host-model-cmt.x86_64-4.0.0.args      |   2 +-
 .../cpu-host-model-fallback.args              |   2 +-
 56 files changed, 681 insertions(+), 459 deletions(-)
 delete mode 100644 tests/cputestdata/x86_64-baseline-1-result.xml
 delete mode 100644 tests/cputestdata/x86_64-baseline-1.xml
 delete mode 100644 tests/cputestdata/x86_64-baseline-2-result.xml
 delete mode 100644 tests/cputestdata/x86_64-baseline-2.xml
 delete mode 100644 tests/cputestdata/x86_64-baseline-5-expanded.xml
 delete mode 100644 tests/cputestdata/x86_64-baseline-5.xml
 delete mode 100644 tests/cputestdata/x86_64-baseline-6-migratable.xml
 delete mode 100644 tests/cputestdata/x86_64-baseline-7-result.xml
 delete mode 100644 tests/cputestdata/x86_64-baseline-7.xml
 delete mode 100644 tests/cputestdata/x86_64-baseline-8-result.xml
 delete mode 100644 tests/cputestdata/x86_64-baseline-8.xml
 rename tests/cputestdata/{x86_64-baseline-5-result.xml => x86_64-baseline-Westmere+Nehalem-migratable.xml} (51%)
 rename tests/cputestdata/{x86_64-baseline-6-result.xml => x86_64-baseline-Westmere+Nehalem-result.xml} (54%)
 rename tests/cputestdata/{x86_64-baseline-6.xml => x86_64-baseline-Westmere+Nehalem.xml} (100%)
 rename tests/cputestdata/{x86_64-baseline-4-expanded.xml => x86_64-baseline-features-expanded.xml} (100%)
 rename tests/cputestdata/{x86_64-baseline-4-result.xml => x86_64-baseline-features-result.xml} (100%)
 rename tests/cputestdata/{x86_64-baseline-4.xml => x86_64-baseline-features.xml} (100%)
 rename tests/cputestdata/{x86_64-baseline-3-expanded.xml => x86_64-baseline-simple-expanded.xml} (100%)
 rename tests/cputestdata/{x86_64-baseline-3-result.xml => x86_64-baseline-simple-result.xml} (100%)
 rename tests/cputestdata/{x86_64-baseline-3.xml => x86_64-baseline-simple.xml} (100%)
 create mode 100644 tests/cputestdata/x86_64-cpuid-baseline-Broadwell-IBRS+Cascadelake.xml
 create mode 100644 tests/cputestdata/x86_64-cpuid-baseline-Cascadelake+Icelake.xml
 create mode 100644 tests/cputestdata/x86_64-cpuid-baseline-Cascadelake+Skylake-IBRS.xml
 create mode 100644 tests/cputestdata/x86_64-cpuid-baseline-Cascadelake+Skylake.xml
 create mode 100644 tests/cputestdata/x86_64-cpuid-baseline-Cooperlake+Cascadelake.xml
 create mode 100644 tests/cputestdata/x86_64-cpuid-baseline-Cooperlake+Icelake.xml
 create mode 100644 tests/cputestdata/x86_64-cpuid-baseline-EPYC+Rome.xml
 create mode 100644 tests/cputestdata/x86_64-cpuid-baseline-Haswell+Skylake.xml
 create mode 100644 tests/cputestdata/x86_64-cpuid-baseline-Haswell-noTSX-IBRS+Broadwell.xml
 create mode 100644 tests/cputestdata/x86_64-cpuid-baseline-Haswell-noTSX-IBRS+Skylake-IBRS.xml
 create mode 100644 tests/cputestdata/x86_64-cpuid-baseline-Haswell-noTSX-IBRS+Skylake.xml
 create mode 100644 tests/cputestdata/x86_64-cpuid-baseline-Ryzen+Rome.xml
 create mode 100644 tests/cputestdata/x86_64-cpuid-baseline-Skylake-Client+Server.xml

-- 
2.35.1
Re: [libvirt PATCH 0/8] Improve heuristics for computing baseline CPU models
Posted by Michal Prívozník 1 week, 4 days ago
On 5/4/22 18:54, Jiri Denemark wrote:
> See 7/8 and 8/8 for details.
> 
> https://bugzilla.redhat.com/show_bug.cgi?id=1851227
> 
> Jiri Denemark (8):
>   cpu_map: Disable cpu64-rhel* for host-model and baseline
>   cputest: Drop some old artificial baseline tests
>   cputest: Give better names to baseline tests
>   cputest: Add some real world baseline tests
>   cpu_x86: Consolidate signature match in x86DecodeUseCandidate
>   cpu_x86: Refactor feature list comparison in x86DecodeUseCandidate
>   cpu_x86: Penalize disabled features when computing CPU model
>   cpu_x86: Ignore enabled features for input models in
>     x86DecodeUseCandidate
> 

>  56 files changed, 681 insertions(+), 459 deletions(-)
> 

Reviewed-by: Michal Privoznik <mprivozn@redhat.com>

Michal