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  3. [PATCH v3 00/12] Improve versioned CPU support in libvirt
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[PATCH v3 02/12] cpu_map: add canonical names to existing CPU models

Jonathon Jongsma posted 12 patches 1 year, 8 months ago
[PATCH v3 02/12] cpu_map: add canonical names to existing CPU models
Posted by Jonathon Jongsma 1 year, 8 months ago 
Signed-off-by: Jonathon Jongsma <jjongsma@redhat.com>
---
 src/cpu_map/x86_Broadwell-IBRS.xml            | 1 +
 src/cpu_map/x86_Broadwell-noTSX-IBRS.xml      | 1 +
 src/cpu_map/x86_Broadwell-noTSX.xml           | 1 +
 src/cpu_map/x86_Broadwell.xml                 | 1 +
 src/cpu_map/x86_Cascadelake-Server-noTSX.xml  | 1 +
 src/cpu_map/x86_Cascadelake-Server.xml        | 1 +
 src/cpu_map/x86_Cooperlake.xml                | 1 +
 src/cpu_map/x86_Dhyana.xml                    | 1 +
 src/cpu_map/x86_EPYC-IBPB.xml                 | 1 +
 src/cpu_map/x86_EPYC-Milan.xml                | 1 +
 src/cpu_map/x86_EPYC-Rome.xml                 | 1 +
 src/cpu_map/x86_EPYC.xml                      | 1 +
 src/cpu_map/x86_Haswell-IBRS.xml              | 1 +
 src/cpu_map/x86_Haswell-noTSX-IBRS.xml        | 1 +
 src/cpu_map/x86_Haswell-noTSX.xml             | 1 +
 src/cpu_map/x86_Haswell.xml                   | 1 +
 src/cpu_map/x86_Icelake-Server-noTSX.xml      | 1 +
 src/cpu_map/x86_Icelake-Server.xml            | 1 +
 src/cpu_map/x86_IvyBridge-IBRS.xml            | 1 +
 src/cpu_map/x86_IvyBridge.xml                 | 1 +
 src/cpu_map/x86_Nehalem-IBRS.xml              | 1 +
 src/cpu_map/x86_Nehalem.xml                   | 1 +
 src/cpu_map/x86_SandyBridge-IBRS.xml          | 1 +
 src/cpu_map/x86_SandyBridge.xml               | 1 +
 src/cpu_map/x86_SapphireRapids.xml            | 1 +
 src/cpu_map/x86_Skylake-Client-IBRS.xml       | 1 +
 src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml | 1 +
 src/cpu_map/x86_Skylake-Client.xml            | 1 +
 src/cpu_map/x86_Skylake-Server-IBRS.xml       | 1 +
 src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml | 1 +
 src/cpu_map/x86_Skylake-Server.xml            | 1 +
 src/cpu_map/x86_Snowridge.xml                 | 1 +
 src/cpu_map/x86_Westmere-IBRS.xml             | 1 +
 src/cpu_map/x86_Westmere.xml                  | 1 +
 34 files changed, 34 insertions(+)

diff --git a/src/cpu_map/x86_Broadwell-IBRS.xml b/src/cpu_map/x86_Broadwell-IBRS.xml
index 9033d5fcd5..13568eac81 100644
--- a/src/cpu_map/x86_Broadwell-IBRS.xml
+++ b/src/cpu_map/x86_Broadwell-IBRS.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Broadwell-IBRS'>
+    <canonical_name>Broadwell-v3</canonical_name>
     <decode host='on' guest='on'/>
     <signature family='6' model='61'/> <!-- 0306d0 -->
     <signature family='6' model='71'/> <!-- 040670 -->
diff --git a/src/cpu_map/x86_Broadwell-noTSX-IBRS.xml b/src/cpu_map/x86_Broadwell-noTSX-IBRS.xml
index c044b60e36..4ec35ce3a2 100644
--- a/src/cpu_map/x86_Broadwell-noTSX-IBRS.xml
+++ b/src/cpu_map/x86_Broadwell-noTSX-IBRS.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Broadwell-noTSX-IBRS'>
+    <canonical_name>Broadwell-v4</canonical_name>
     <decode host='on' guest='on'/>
     <signature family='6' model='61'/> <!-- 0306d0 -->
     <signature family='6' model='71'/> <!-- 040670 -->
diff --git a/src/cpu_map/x86_Broadwell-noTSX.xml b/src/cpu_map/x86_Broadwell-noTSX.xml
index 637f29ba1c..3fed34e3a4 100644
--- a/src/cpu_map/x86_Broadwell-noTSX.xml
+++ b/src/cpu_map/x86_Broadwell-noTSX.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Broadwell-noTSX'>
+    <canonical_name>Broadwell-v2</canonical_name>
     <decode host='on' guest='on'/>
     <signature family='6' model='61'/> <!-- 0306d0 -->
     <signature family='6' model='71'/> <!-- 040670 -->
diff --git a/src/cpu_map/x86_Broadwell.xml b/src/cpu_map/x86_Broadwell.xml
index 82939a4509..79c96c3857 100644
--- a/src/cpu_map/x86_Broadwell.xml
+++ b/src/cpu_map/x86_Broadwell.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Broadwell'>
+    <canonical_name>Broadwell-v1</canonical_name>
     <decode host='on' guest='on'/>
     <signature family='6' model='61'/> <!-- 0306d0 -->
     <signature family='6' model='71'/> <!-- 040670 -->
diff --git a/src/cpu_map/x86_Cascadelake-Server-noTSX.xml b/src/cpu_map/x86_Cascadelake-Server-noTSX.xml
index bfd4629836..e1b2a820dc 100644
--- a/src/cpu_map/x86_Cascadelake-Server-noTSX.xml
+++ b/src/cpu_map/x86_Cascadelake-Server-noTSX.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Cascadelake-Server-noTSX'>
+    <canonical_name>Cascadelake-Server-v3</canonical_name>
     <decode host='on' guest='off'/>
     <signature family='6' model='85' stepping='5-7'/> <!-- 050654 -->
     <vendor name='Intel'/>
diff --git a/src/cpu_map/x86_Cascadelake-Server.xml b/src/cpu_map/x86_Cascadelake-Server.xml
index 335e9cb584..4e72518e0d 100644
--- a/src/cpu_map/x86_Cascadelake-Server.xml
+++ b/src/cpu_map/x86_Cascadelake-Server.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Cascadelake-Server'>
+    <canonical_name>Cascadelake-Server-v1</canonical_name>
     <decode host='on' guest='on'/>
     <signature family='6' model='85' stepping='5-7'/> <!-- 050654 -->
     <vendor name='Intel'/>
diff --git a/src/cpu_map/x86_Cooperlake.xml b/src/cpu_map/x86_Cooperlake.xml
index ceca687334..d2967daf3b 100644
--- a/src/cpu_map/x86_Cooperlake.xml
+++ b/src/cpu_map/x86_Cooperlake.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Cooperlake'>
+    <canonical_name>Cooperlake-v1</canonical_name>
     <decode host='on' guest='on'/>
     <signature family='6' model='85' stepping='10-11'/> <!-- 05065b -->
     <vendor name='Intel'/>
diff --git a/src/cpu_map/x86_Dhyana.xml b/src/cpu_map/x86_Dhyana.xml
index cfde07f99f..a7fb540973 100644
--- a/src/cpu_map/x86_Dhyana.xml
+++ b/src/cpu_map/x86_Dhyana.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Dhyana'>
+    <canonical_name>Dhyana-v1</canonical_name>
     <decode host='on' guest='on'/>
     <signature family='24' model='0'/> <!-- 900f00 -->
     <vendor name='Hygon'/>
diff --git a/src/cpu_map/x86_EPYC-IBPB.xml b/src/cpu_map/x86_EPYC-IBPB.xml
index fc5aadf52e..28f0113392 100644
--- a/src/cpu_map/x86_EPYC-IBPB.xml
+++ b/src/cpu_map/x86_EPYC-IBPB.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='EPYC-IBPB'>
+    <canonical_name>EPYC-v2</canonical_name>
     <decode host='on' guest='on'/>
     <signature family='23' model='1'/> <!-- 800f10 -->
     <vendor name='AMD'/>
diff --git a/src/cpu_map/x86_EPYC-Milan.xml b/src/cpu_map/x86_EPYC-Milan.xml
index 3055e175fa..0dfdbb5b4b 100644
--- a/src/cpu_map/x86_EPYC-Milan.xml
+++ b/src/cpu_map/x86_EPYC-Milan.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='EPYC-Milan'>
+    <canonical_name>EPYC-Milan-v1</canonical_name>
     <decode host='on' guest='on'/>
     <signature family='25' model='1'/>
     <vendor name='AMD'/>
diff --git a/src/cpu_map/x86_EPYC-Rome.xml b/src/cpu_map/x86_EPYC-Rome.xml
index e54d0a48d8..794f3a8ff6 100644
--- a/src/cpu_map/x86_EPYC-Rome.xml
+++ b/src/cpu_map/x86_EPYC-Rome.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='EPYC-Rome'>
+    <canonical_name>EPYC-Rome-v1</canonical_name>
     <decode host='on' guest='on'/>
     <signature family='23' model='49'/>
     <vendor name='AMD'/>
diff --git a/src/cpu_map/x86_EPYC.xml b/src/cpu_map/x86_EPYC.xml
index 3b406de37a..852ca047e4 100644
--- a/src/cpu_map/x86_EPYC.xml
+++ b/src/cpu_map/x86_EPYC.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='EPYC'>
+    <canonical_name>EPYC-v1</canonical_name>
     <decode host='on' guest='on'/>
     <signature family='23' model='1'/> <!-- 800f10 -->
     <vendor name='AMD'/>
diff --git a/src/cpu_map/x86_Haswell-IBRS.xml b/src/cpu_map/x86_Haswell-IBRS.xml
index 0ffe2bae0d..49da1fff06 100644
--- a/src/cpu_map/x86_Haswell-IBRS.xml
+++ b/src/cpu_map/x86_Haswell-IBRS.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Haswell-IBRS'>
+    <canonical_name>Haswell-v3</canonical_name>
     <decode host='on' guest='on'/>
     <signature family='6' model='60'/> <!-- 0306c0 -->
     <signature family='6' model='63'/> <!-- 0306f0 -->
diff --git a/src/cpu_map/x86_Haswell-noTSX-IBRS.xml b/src/cpu_map/x86_Haswell-noTSX-IBRS.xml
index 75d709c009..49cac64ff6 100644
--- a/src/cpu_map/x86_Haswell-noTSX-IBRS.xml
+++ b/src/cpu_map/x86_Haswell-noTSX-IBRS.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Haswell-noTSX-IBRS'>
+    <canonical_name>Haswell-v4</canonical_name>
     <decode host='on' guest='on'/>
     <signature family='6' model='60'/> <!-- 0306c0 -->
     <signature family='6' model='63'/> <!-- 0306f0 -->
diff --git a/src/cpu_map/x86_Haswell-noTSX.xml b/src/cpu_map/x86_Haswell-noTSX.xml
index b0a0faa856..7d2834be9b 100644
--- a/src/cpu_map/x86_Haswell-noTSX.xml
+++ b/src/cpu_map/x86_Haswell-noTSX.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Haswell-noTSX'>
+    <canonical_name>Haswell-v2</canonical_name>
     <decode host='on' guest='on'/>
     <signature family='6' model='60'/> <!-- 0306c0 -->
     <signature family='6' model='63'/> <!-- 0306f0 -->
diff --git a/src/cpu_map/x86_Haswell.xml b/src/cpu_map/x86_Haswell.xml
index ee16b30f19..8bbd929db2 100644
--- a/src/cpu_map/x86_Haswell.xml
+++ b/src/cpu_map/x86_Haswell.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Haswell'>
+    <canonical_name>Haswell-v1</canonical_name>
     <decode host='on' guest='on'/>
     <signature family='6' model='60'/> <!-- 0306c0 -->
     <signature family='6' model='63'/> <!-- 0306f0 -->
diff --git a/src/cpu_map/x86_Icelake-Server-noTSX.xml b/src/cpu_map/x86_Icelake-Server-noTSX.xml
index 7c9c32c977..e13135cb81 100644
--- a/src/cpu_map/x86_Icelake-Server-noTSX.xml
+++ b/src/cpu_map/x86_Icelake-Server-noTSX.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Icelake-Server-noTSX'>
+    <canonical_name>Icelake-Server-v2</canonical_name>
     <decode host='on' guest='off'/>
     <signature family='6' model='106'/> <!-- 0606A5 -->
     <vendor name='Intel'/>
diff --git a/src/cpu_map/x86_Icelake-Server.xml b/src/cpu_map/x86_Icelake-Server.xml
index b4685bead0..575f2c1014 100644
--- a/src/cpu_map/x86_Icelake-Server.xml
+++ b/src/cpu_map/x86_Icelake-Server.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Icelake-Server'>
+    <canonical_name>Icelake-Server-v1</canonical_name>
     <decode host='on' guest='on'/>
     <signature family='6' model='106'/> <!-- 0606A5 -->
     <vendor name='Intel'/>
diff --git a/src/cpu_map/x86_IvyBridge-IBRS.xml b/src/cpu_map/x86_IvyBridge-IBRS.xml
index 430bc3232d..48720671fa 100644
--- a/src/cpu_map/x86_IvyBridge-IBRS.xml
+++ b/src/cpu_map/x86_IvyBridge-IBRS.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='IvyBridge-IBRS'>
+    <canonical_name>IvyBridge-v2</canonical_name>
     <decode host='on' guest='on'/>
     <signature family='6' model='58'/> <!-- 0306a0 -->
     <signature family='6' model='62'/> <!-- 0306e0 -->
diff --git a/src/cpu_map/x86_IvyBridge.xml b/src/cpu_map/x86_IvyBridge.xml
index eaf5d02e82..34057a6bd6 100644
--- a/src/cpu_map/x86_IvyBridge.xml
+++ b/src/cpu_map/x86_IvyBridge.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='IvyBridge'>
+    <canonical_name>IvyBridge-v1</canonical_name>
     <decode host='on' guest='on'/>
     <signature family='6' model='58'/> <!-- 0306a0 -->
     <signature family='6' model='62'/> <!-- 0306e0 -->
diff --git a/src/cpu_map/x86_Nehalem-IBRS.xml b/src/cpu_map/x86_Nehalem-IBRS.xml
index 00d0d2fe51..8745efe977 100644
--- a/src/cpu_map/x86_Nehalem-IBRS.xml
+++ b/src/cpu_map/x86_Nehalem-IBRS.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Nehalem-IBRS'>
+    <canonical_name>Nehalem-v2</canonical_name>
     <decode host='on' guest='on'/>
     <signature family='6' model='26'/> <!-- 0106a0 -->
     <signature family='6' model='30'/> <!-- 0106e0 -->
diff --git a/src/cpu_map/x86_Nehalem.xml b/src/cpu_map/x86_Nehalem.xml
index 9968001fe7..d5717b4264 100644
--- a/src/cpu_map/x86_Nehalem.xml
+++ b/src/cpu_map/x86_Nehalem.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Nehalem'>
+    <canonical_name>Nehalem-v1</canonical_name>
     <decode host='on' guest='on'/>
     <signature family='6' model='26'/> <!-- 0106a0 -->
     <signature family='6' model='30'/> <!-- 0106e0 -->
diff --git a/src/cpu_map/x86_SandyBridge-IBRS.xml b/src/cpu_map/x86_SandyBridge-IBRS.xml
index fbdb4f2bf6..2a596bf5f0 100644
--- a/src/cpu_map/x86_SandyBridge-IBRS.xml
+++ b/src/cpu_map/x86_SandyBridge-IBRS.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='SandyBridge-IBRS'>
+    <canonical_name>SandyBridge-v2</canonical_name>
     <decode host='on' guest='on'/>
     <signature family='6' model='42'/> <!-- 0206a0 -->
     <signature family='6' model='45'/> <!-- 0206d0 -->
diff --git a/src/cpu_map/x86_SandyBridge.xml b/src/cpu_map/x86_SandyBridge.xml
index 7c85ed42df..3ee0273264 100644
--- a/src/cpu_map/x86_SandyBridge.xml
+++ b/src/cpu_map/x86_SandyBridge.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='SandyBridge'>
+    <canonical_name>SandyBridge-v1</canonical_name>
     <decode host='on' guest='on'/>
     <signature family='6' model='42'/> <!-- 0206a0 -->
     <signature family='6' model='45'/> <!-- 0206d0 -->
diff --git a/src/cpu_map/x86_SapphireRapids.xml b/src/cpu_map/x86_SapphireRapids.xml
index 2297feeeca..a658561fa1 100644
--- a/src/cpu_map/x86_SapphireRapids.xml
+++ b/src/cpu_map/x86_SapphireRapids.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='SapphireRapids'>
+    <canonical_name>SapphireRapids-v1</canonical_name>
     <decode host='on' guest='on'/>
     <signature family='6' model='143'/>
     <vendor name='Intel'/>
diff --git a/src/cpu_map/x86_Skylake-Client-IBRS.xml b/src/cpu_map/x86_Skylake-Client-IBRS.xml
index 5709e7c2f9..3d81bc0f2b 100644
--- a/src/cpu_map/x86_Skylake-Client-IBRS.xml
+++ b/src/cpu_map/x86_Skylake-Client-IBRS.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Skylake-Client-IBRS'>
+    <canonical_name>Skylake-Client-v2</canonical_name>
     <decode host='on' guest='on'/>
     <signature family='6' model='94'/> <!-- 0506e0 -->
     <signature family='6' model='78'/> <!-- 0406e0 -->
diff --git a/src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml b/src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml
index ffba34502a..0cb420f5e6 100644
--- a/src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml
+++ b/src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Skylake-Client-noTSX-IBRS'>
+    <canonical_name>Skylake-Client-v3</canonical_name>
     <decode host='on' guest='off'/>
     <signature family='6' model='94'/> <!-- 0506e0 -->
     <signature family='6' model='78'/> <!-- 0406e0 -->
diff --git a/src/cpu_map/x86_Skylake-Client.xml b/src/cpu_map/x86_Skylake-Client.xml
index 14cd57e176..608fa23de7 100644
--- a/src/cpu_map/x86_Skylake-Client.xml
+++ b/src/cpu_map/x86_Skylake-Client.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Skylake-Client'>
+    <canonical_name>Skylake-Client-v1</canonical_name>
     <decode host='on' guest='on'/>
     <signature family='6' model='94'/> <!-- 0506e0 -->
     <signature family='6' model='78'/> <!-- 0406e0 -->
diff --git a/src/cpu_map/x86_Skylake-Server-IBRS.xml b/src/cpu_map/x86_Skylake-Server-IBRS.xml
index 9fb3488809..ad54ca85c9 100644
--- a/src/cpu_map/x86_Skylake-Server-IBRS.xml
+++ b/src/cpu_map/x86_Skylake-Server-IBRS.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Skylake-Server-IBRS'>
+    <canonical_name>Skylake-Server-v2</canonical_name>
     <decode host='on' guest='on'/>
     <signature family='6' model='85' stepping='0-4'/> <!-- 050654 -->
     <vendor name='Intel'/>
diff --git a/src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml b/src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml
index c162c0acc3..896aa5a7bf 100644
--- a/src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml
+++ b/src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Skylake-Server-noTSX-IBRS'>
+    <canonical_name>Skylake-Server-v3</canonical_name>
     <decode host='on' guest='off'/>
     <signature family='6' model='85' stepping='0-4'/> <!-- 050654 -->
     <vendor name='Intel'/>
diff --git a/src/cpu_map/x86_Skylake-Server.xml b/src/cpu_map/x86_Skylake-Server.xml
index e022d94c84..5d76828c0c 100644
--- a/src/cpu_map/x86_Skylake-Server.xml
+++ b/src/cpu_map/x86_Skylake-Server.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Skylake-Server'>
+    <canonical_name>Skylake-Server-v1</canonical_name>
     <decode host='on' guest='on'/>
     <signature family='6' model='85' stepping='0-4'/> <!-- 050654 -->
     <vendor name='Intel'/>
diff --git a/src/cpu_map/x86_Snowridge.xml b/src/cpu_map/x86_Snowridge.xml
index 383a24d367..87686502c1 100644
--- a/src/cpu_map/x86_Snowridge.xml
+++ b/src/cpu_map/x86_Snowridge.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Snowridge'>
+    <canonical_name>Snowridge-v1</canonical_name>
     <decode host='on' guest='on'/>
     <signature family='6' model='134'/> <!-- 080665 -->
     <vendor name='Intel'/>
diff --git a/src/cpu_map/x86_Westmere-IBRS.xml b/src/cpu_map/x86_Westmere-IBRS.xml
index c7898f0c22..f8ad746a22 100644
--- a/src/cpu_map/x86_Westmere-IBRS.xml
+++ b/src/cpu_map/x86_Westmere-IBRS.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Westmere-IBRS'>
+    <canonical_name>Westmere-v2</canonical_name>
     <decode host='on' guest='on'/>
     <signature family='6' model='44'/> <!-- 0206c0 -->
     <vendor name='Intel'/>
diff --git a/src/cpu_map/x86_Westmere.xml b/src/cpu_map/x86_Westmere.xml
index 16e4ad6c30..120140a3ce 100644
--- a/src/cpu_map/x86_Westmere.xml
+++ b/src/cpu_map/x86_Westmere.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Westmere'>
+    <canonical_name>Westmere-v1</canonical_name>
     <decode host='on' guest='on'/>
     <signature family='6' model='44'/> <!-- 0206c0 -->
     <signature family='6' model='47'/> <!-- 0206f0 -->
-- 
2.41.0
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Re: [PATCH v3 02/12] cpu_map: add canonical names to existing CPU models
Posted by Daniel P. Berrangé 1 year, 6 months ago 
On Fri, Dec 15, 2023 at 04:11:58PM -0600, Jonathon Jongsma wrote:
> Signed-off-by: Jonathon Jongsma <jjongsma@redhat.com>
> ---
>  src/cpu_map/x86_Broadwell-IBRS.xml            | 1 +
>  src/cpu_map/x86_Broadwell-noTSX-IBRS.xml      | 1 +
>  src/cpu_map/x86_Broadwell-noTSX.xml           | 1 +
>  src/cpu_map/x86_Broadwell.xml                 | 1 +
>  src/cpu_map/x86_Cascadelake-Server-noTSX.xml  | 1 +
>  src/cpu_map/x86_Cascadelake-Server.xml        | 1 +
>  src/cpu_map/x86_Cooperlake.xml                | 1 +
>  src/cpu_map/x86_Dhyana.xml                    | 1 +
>  src/cpu_map/x86_EPYC-IBPB.xml                 | 1 +
>  src/cpu_map/x86_EPYC-Milan.xml                | 1 +
>  src/cpu_map/x86_EPYC-Rome.xml                 | 1 +
>  src/cpu_map/x86_EPYC.xml                      | 1 +
>  src/cpu_map/x86_Haswell-IBRS.xml              | 1 +
>  src/cpu_map/x86_Haswell-noTSX-IBRS.xml        | 1 +
>  src/cpu_map/x86_Haswell-noTSX.xml             | 1 +
>  src/cpu_map/x86_Haswell.xml                   | 1 +
>  src/cpu_map/x86_Icelake-Server-noTSX.xml      | 1 +
>  src/cpu_map/x86_Icelake-Server.xml            | 1 +
>  src/cpu_map/x86_IvyBridge-IBRS.xml            | 1 +
>  src/cpu_map/x86_IvyBridge.xml                 | 1 +
>  src/cpu_map/x86_Nehalem-IBRS.xml              | 1 +
>  src/cpu_map/x86_Nehalem.xml                   | 1 +
>  src/cpu_map/x86_SandyBridge-IBRS.xml          | 1 +
>  src/cpu_map/x86_SandyBridge.xml               | 1 +
>  src/cpu_map/x86_SapphireRapids.xml            | 1 +
>  src/cpu_map/x86_Skylake-Client-IBRS.xml       | 1 +
>  src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml | 1 +
>  src/cpu_map/x86_Skylake-Client.xml            | 1 +
>  src/cpu_map/x86_Skylake-Server-IBRS.xml       | 1 +
>  src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml | 1 +
>  src/cpu_map/x86_Skylake-Server.xml            | 1 +
>  src/cpu_map/x86_Snowridge.xml                 | 1 +
>  src/cpu_map/x86_Westmere-IBRS.xml             | 1 +
>  src/cpu_map/x86_Westmere.xml                  | 1 +
>  34 files changed, 34 insertions(+)


> 
> diff --git a/src/cpu_map/x86_Broadwell-IBRS.xml b/src/cpu_map/x86_Broadwell-IBRS.xml
> index 9033d5fcd5..13568eac81 100644
> --- a/src/cpu_map/x86_Broadwell-IBRS.xml
> +++ b/src/cpu_map/x86_Broadwell-IBRS.xml
> @@ -1,5 +1,6 @@
>  <cpus>
>    <model name='Broadwell-IBRS'>
> +    <canonical_name>Broadwell-v3</canonical_name>
>      <decode host='on' guest='on'/>
>      <signature family='6' model='61'/> <!-- 0306d0 -->
>      <signature family='6' model='71'/> <!-- 040670 -->
> diff --git a/src/cpu_map/x86_Broadwell-noTSX-IBRS.xml b/src/cpu_map/x86_Broadwell-noTSX-IBRS.xml
> index c044b60e36..4ec35ce3a2 100644
> --- a/src/cpu_map/x86_Broadwell-noTSX-IBRS.xml
> +++ b/src/cpu_map/x86_Broadwell-noTSX-IBRS.xml
> @@ -1,5 +1,6 @@
>  <cpus>
>    <model name='Broadwell-noTSX-IBRS'>
> +    <canonical_name>Broadwell-v4</canonical_name>
>      <decode host='on' guest='on'/>
>      <signature family='6' model='61'/> <!-- 0306d0 -->
>      <signature family='6' model='71'/> <!-- 040670 -->
> diff --git a/src/cpu_map/x86_Broadwell-noTSX.xml b/src/cpu_map/x86_Broadwell-noTSX.xml
> index 637f29ba1c..3fed34e3a4 100644
> --- a/src/cpu_map/x86_Broadwell-noTSX.xml
> +++ b/src/cpu_map/x86_Broadwell-noTSX.xml
> @@ -1,5 +1,6 @@
>  <cpus>
>    <model name='Broadwell-noTSX'>
> +    <canonical_name>Broadwell-v2</canonical_name>
>      <decode host='on' guest='on'/>
>      <signature family='6' model='61'/> <!-- 0306d0 -->
>      <signature family='6' model='71'/> <!-- 040670 -->
> diff --git a/src/cpu_map/x86_Broadwell.xml b/src/cpu_map/x86_Broadwell.xml
> index 82939a4509..79c96c3857 100644
> --- a/src/cpu_map/x86_Broadwell.xml
> +++ b/src/cpu_map/x86_Broadwell.xml
> @@ -1,5 +1,6 @@
>  <cpus>
>    <model name='Broadwell'>
> +    <canonical_name>Broadwell-v1</canonical_name>
>      <decode host='on' guest='on'/>
>      <signature family='6' model='61'/> <!-- 0306d0 -->
>      <signature family='6' model='71'/> <!-- 040670 -->

In theory the expansion from the plain CPU model names (ie without
the noXXXX suffix) can vary per machine type. In practice QEMU has
never changed it thus far, so its always 'v1'.

Lets be clear that although this expansion can vary per machine
type, libvirt's CPU model database is independant of machine
type, and thus we've decided to arbitrary fix the base CPU model
names to the '-v1' CPU models.

Can you put something in the commit message to this effect.

With regards,
Daniel
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