[libvirt PATCH 0/3] Add script to sync from QEMU i386 cpu models

Tim Wiederhake posted 3 patches 1 week ago
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git fetch https://github.com/patchew-project/libvirt tags/patchew/20201015141805.143762-1-twiederh@redhat.com
src/cpu_map/arm_Falkor.xml                    |   6 +-
src/cpu_map/arm_Kunpeng-920.xml               |   6 +-
src/cpu_map/arm_ThunderX299xx.xml             |   6 +-
src/cpu_map/arm_cortex-a53.xml                |   6 +-
src/cpu_map/arm_cortex-a57.xml                |   6 +-
src/cpu_map/arm_cortex-a72.xml                |   6 +-
src/cpu_map/arm_features.xml                  |  34 +-
src/cpu_map/index.xml                         |  12 +-
src/cpu_map/ppc64_POWER6.xml                  |   6 +-
src/cpu_map/ppc64_POWER7.xml                  |   8 +-
src/cpu_map/ppc64_POWER8.xml                  |  10 +-
src/cpu_map/ppc64_POWER9.xml                  |   6 +-
src/cpu_map/ppc64_POWERPC_e5500.xml           |   6 +-
src/cpu_map/ppc64_POWERPC_e6500.xml           |   6 +-
src/cpu_map/ppc64_vendors.xml                 |   4 +-
src/cpu_map/sync_qemu_i386.py                 | 361 +++++++++
src/cpu_map/x86_486.xml                       |  18 +-
src/cpu_map/x86_Broadwell-IBRS.xml            | 135 ++--
src/cpu_map/x86_Broadwell-noTSX-IBRS.xml      | 131 ++--
src/cpu_map/x86_Broadwell-noTSX.xml           | 129 ++--
src/cpu_map/x86_Broadwell.xml                 | 132 ++--
src/cpu_map/x86_Cascadelake-Server-noTSX.xml  | 166 ++--
src/cpu_map/x86_Cascadelake-Server.xml        | 169 ++--
src/cpu_map/x86_Conroe.xml                    |  70 +-
src/cpu_map/x86_Cooperlake.xml                |  14 +-
src/cpu_map/x86_Denverton.xml                 |  74 ++
src/cpu_map/x86_Dhyana.xml                    | 144 ++--
src/cpu_map/x86_EPYC-IBPB.xml                 | 157 ++--
src/cpu_map/x86_EPYC-Rome.xml                 | 169 ++--
src/cpu_map/x86_EPYC.xml                      | 150 ++--
src/cpu_map/x86_Haswell-IBRS.xml              | 128 ++--
src/cpu_map/x86_Haswell-noTSX-IBRS.xml        | 124 +--
src/cpu_map/x86_Haswell-noTSX.xml             | 122 +--
src/cpu_map/x86_Haswell.xml                   | 124 +--
src/cpu_map/x86_Icelake-Client-noTSX.xml      | 164 ++--
src/cpu_map/x86_Icelake-Client.xml            | 167 ++--
src/cpu_map/x86_Icelake-Server-noTSX.xml      | 197 ++---
src/cpu_map/x86_Icelake-Server.xml            | 185 ++---
src/cpu_map/x86_IvyBridge-IBRS.xml            | 109 +--
src/cpu_map/x86_IvyBridge.xml                 | 106 +--
src/cpu_map/x86_KnightsMill.xml               |  77 ++
src/cpu_map/x86_Nehalem-IBRS.xml              |  84 +-
src/cpu_map/x86_Nehalem.xml                   |  81 +-
src/cpu_map/x86_Opteron_G1.xml                |  65 +-
src/cpu_map/x86_Opteron_G2.xml                |  72 +-
src/cpu_map/x86_Opteron_G3.xml                |  82 +-
src/cpu_map/x86_Opteron_G4.xml                | 105 +--
src/cpu_map/x86_Opteron_G5.xml                | 111 +--
src/cpu_map/x86_Penryn.xml                    |  74 +-
src/cpu_map/x86_SandyBridge-IBRS.xml          |  98 +--
src/cpu_map/x86_SandyBridge.xml               |  95 +--
src/cpu_map/x86_Skylake-Client-IBRS.xml       | 148 ++--
src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml | 144 ++--
src/cpu_map/x86_Skylake-Client.xml            | 145 ++--
src/cpu_map/x86_Skylake-Server-IBRS.xml       | 158 ++--
src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml | 155 ++--
src/cpu_map/x86_Skylake-Server.xml            | 156 ++--
src/cpu_map/x86_Snowridge.xml                 |  79 ++
src/cpu_map/x86_Westmere-IBRS.xml             |  85 +-
src/cpu_map/x86_Westmere.xml                  |  84 +-
src/cpu_map/x86_athlon.xml                    |  60 +-
src/cpu_map/x86_core2duo.xml                  |  72 +-
src/cpu_map/x86_coreduo.xml                   |  62 +-
src/cpu_map/x86_cpu64-rhel5.xml               |  54 +-
src/cpu_map/x86_cpu64-rhel6.xml               |  58 +-
src/cpu_map/x86_features.xml                  | 724 +++++++++---------
src/cpu_map/x86_kvm32.xml                     |  57 +-
src/cpu_map/x86_kvm64.xml                     |  65 +-
src/cpu_map/x86_n270.xml                      |  66 +-
src/cpu_map/x86_pentium.xml                   |  31 +-
src/cpu_map/x86_pentium2.xml                  |  49 +-
src/cpu_map/x86_pentium3.xml                  |  51 +-
src/cpu_map/x86_pentiumpro.xml                |  38 +-
src/cpu_map/x86_phenom.xml                    |  83 +-
src/cpu_map/x86_qemu32.xml                    |  48 +-
src/cpu_map/x86_qemu64.xml                    |  75 +-
src/cpu_map/x86_vendors.xml                   |   6 +-
77 files changed, 4160 insertions(+), 3110 deletions(-)
create mode 100755 src/cpu_map/sync_qemu_i386.py
create mode 100644 src/cpu_map/x86_Denverton.xml
create mode 100644 src/cpu_map/x86_KnightsMill.xml
create mode 100644 src/cpu_map/x86_Snowridge.xml

[libvirt PATCH 0/3] Add script to sync from QEMU i386 cpu models

Posted by Tim Wiederhake 1 week ago
This hopefully makes synchronization with QEMU faster and less
error prone.

Patch #3 showcases the changes to the cpu models the script
suggests for qemu 8d90bfc5c31ad60f6049dd39be636b06bc00b652.

Tim Wiederhake (3):
  cpu_map: Unify apostrophe and quotation mark usage
  cpu_map: Add script to sync from QEMU i386 cpu models
  [DONTMERGE] Sample output of new sync script

 src/cpu_map/arm_Falkor.xml                    |   6 +-
 src/cpu_map/arm_Kunpeng-920.xml               |   6 +-
 src/cpu_map/arm_ThunderX299xx.xml             |   6 +-
 src/cpu_map/arm_cortex-a53.xml                |   6 +-
 src/cpu_map/arm_cortex-a57.xml                |   6 +-
 src/cpu_map/arm_cortex-a72.xml                |   6 +-
 src/cpu_map/arm_features.xml                  |  34 +-
 src/cpu_map/index.xml                         |  12 +-
 src/cpu_map/ppc64_POWER6.xml                  |   6 +-
 src/cpu_map/ppc64_POWER7.xml                  |   8 +-
 src/cpu_map/ppc64_POWER8.xml                  |  10 +-
 src/cpu_map/ppc64_POWER9.xml                  |   6 +-
 src/cpu_map/ppc64_POWERPC_e5500.xml           |   6 +-
 src/cpu_map/ppc64_POWERPC_e6500.xml           |   6 +-
 src/cpu_map/ppc64_vendors.xml                 |   4 +-
 src/cpu_map/sync_qemu_i386.py                 | 361 +++++++++
 src/cpu_map/x86_486.xml                       |  18 +-
 src/cpu_map/x86_Broadwell-IBRS.xml            | 135 ++--
 src/cpu_map/x86_Broadwell-noTSX-IBRS.xml      | 131 ++--
 src/cpu_map/x86_Broadwell-noTSX.xml           | 129 ++--
 src/cpu_map/x86_Broadwell.xml                 | 132 ++--
 src/cpu_map/x86_Cascadelake-Server-noTSX.xml  | 166 ++--
 src/cpu_map/x86_Cascadelake-Server.xml        | 169 ++--
 src/cpu_map/x86_Conroe.xml                    |  70 +-
 src/cpu_map/x86_Cooperlake.xml                |  14 +-
 src/cpu_map/x86_Denverton.xml                 |  74 ++
 src/cpu_map/x86_Dhyana.xml                    | 144 ++--
 src/cpu_map/x86_EPYC-IBPB.xml                 | 157 ++--
 src/cpu_map/x86_EPYC-Rome.xml                 | 169 ++--
 src/cpu_map/x86_EPYC.xml                      | 150 ++--
 src/cpu_map/x86_Haswell-IBRS.xml              | 128 ++--
 src/cpu_map/x86_Haswell-noTSX-IBRS.xml        | 124 +--
 src/cpu_map/x86_Haswell-noTSX.xml             | 122 +--
 src/cpu_map/x86_Haswell.xml                   | 124 +--
 src/cpu_map/x86_Icelake-Client-noTSX.xml      | 164 ++--
 src/cpu_map/x86_Icelake-Client.xml            | 167 ++--
 src/cpu_map/x86_Icelake-Server-noTSX.xml      | 197 ++---
 src/cpu_map/x86_Icelake-Server.xml            | 185 ++---
 src/cpu_map/x86_IvyBridge-IBRS.xml            | 109 +--
 src/cpu_map/x86_IvyBridge.xml                 | 106 +--
 src/cpu_map/x86_KnightsMill.xml               |  77 ++
 src/cpu_map/x86_Nehalem-IBRS.xml              |  84 +-
 src/cpu_map/x86_Nehalem.xml                   |  81 +-
 src/cpu_map/x86_Opteron_G1.xml                |  65 +-
 src/cpu_map/x86_Opteron_G2.xml                |  72 +-
 src/cpu_map/x86_Opteron_G3.xml                |  82 +-
 src/cpu_map/x86_Opteron_G4.xml                | 105 +--
 src/cpu_map/x86_Opteron_G5.xml                | 111 +--
 src/cpu_map/x86_Penryn.xml                    |  74 +-
 src/cpu_map/x86_SandyBridge-IBRS.xml          |  98 +--
 src/cpu_map/x86_SandyBridge.xml               |  95 +--
 src/cpu_map/x86_Skylake-Client-IBRS.xml       | 148 ++--
 src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml | 144 ++--
 src/cpu_map/x86_Skylake-Client.xml            | 145 ++--
 src/cpu_map/x86_Skylake-Server-IBRS.xml       | 158 ++--
 src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml | 155 ++--
 src/cpu_map/x86_Skylake-Server.xml            | 156 ++--
 src/cpu_map/x86_Snowridge.xml                 |  79 ++
 src/cpu_map/x86_Westmere-IBRS.xml             |  85 +-
 src/cpu_map/x86_Westmere.xml                  |  84 +-
 src/cpu_map/x86_athlon.xml                    |  60 +-
 src/cpu_map/x86_core2duo.xml                  |  72 +-
 src/cpu_map/x86_coreduo.xml                   |  62 +-
 src/cpu_map/x86_cpu64-rhel5.xml               |  54 +-
 src/cpu_map/x86_cpu64-rhel6.xml               |  58 +-
 src/cpu_map/x86_features.xml                  | 724 +++++++++---------
 src/cpu_map/x86_kvm32.xml                     |  57 +-
 src/cpu_map/x86_kvm64.xml                     |  65 +-
 src/cpu_map/x86_n270.xml                      |  66 +-
 src/cpu_map/x86_pentium.xml                   |  31 +-
 src/cpu_map/x86_pentium2.xml                  |  49 +-
 src/cpu_map/x86_pentium3.xml                  |  51 +-
 src/cpu_map/x86_pentiumpro.xml                |  38 +-
 src/cpu_map/x86_phenom.xml                    |  83 +-
 src/cpu_map/x86_qemu32.xml                    |  48 +-
 src/cpu_map/x86_qemu64.xml                    |  75 +-
 src/cpu_map/x86_vendors.xml                   |   6 +-
 77 files changed, 4160 insertions(+), 3110 deletions(-)
 create mode 100755 src/cpu_map/sync_qemu_i386.py
 create mode 100644 src/cpu_map/x86_Denverton.xml
 create mode 100644 src/cpu_map/x86_KnightsMill.xml
 create mode 100644 src/cpu_map/x86_Snowridge.xml

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2.26.2