Adds SetCacheMtrrLib library for AMD processor based boards.
This library sets MTRR value or various memory ranges.

Signed-off-by: Abdul Lateef Attar <abdattar@amd.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Abner Chang <abner.chang@amd.com
Cc: Michael D Kinney <michael.d.kinney@intel.com>
---
 Platform/AMD/BoardPkg/BoardPkg.dsc            |  10 ++
 .../SetCacheMtrrLib/SetCacheMtrrLib.inf       |  37 +++++
 .../Library/SetCacheMtrrLib/SetCacheMtrrLib.c | 132 ++++++++++++++++++
 3 files changed, 179 insertions(+)
 create mode 100644 Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf
 create mode 100644 Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c

diff --git a/Platform/AMD/BoardPkg/BoardPkg.dsc b/Platform/AMD/BoardPkg/BoardPkg.dsc
index cb4065b86c60..aa0ee8287cd8 100644
--- a/Platform/AMD/BoardPkg/BoardPkg.dsc
+++ b/Platform/AMD/BoardPkg/BoardPkg.dsc
@@ -18,3 +18,13 @@ [Defines]
 
 [Packages]
   BoardPkg/BoardPkg.dec
+  MinPlatformPkg/MinPlatformPkg.dec
+  MdePkg/MdePkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses.common.PEIM]
+  SetCacheMtrrLib|BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf
+
+[Components.IA32]
+  BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf
+
diff --git a/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf b/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf
new file mode 100644
index 000000000000..c66661d3f8dc
--- /dev/null
+++ b/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf
@@ -0,0 +1,37 @@
+## @file
+# Component information file for Platform SetCacheMtrr Library.
+# This library implementation is for AMD processor based platforms.
+#
+# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION                    = 1.29
+  BASE_NAME                      = PeiSetCacheMtrrLib
+  FILE_GUID                      = 1E8468E0-5EB4-4088-9B52-BFDC6E4DAE87
+  MODULE_TYPE                    = PEIM
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = SetCacheMtrrLib
+
+[LibraryClasses]
+  BaseLib
+  DebugLib
+  MtrrLib
+
+[Packages]
+  MinPlatformPkg/MinPlatformPkg.dec
+  MdePkg/MdePkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+
+[Sources]
+  SetCacheMtrrLib.c
+
+[Guids]
+
+[Pcd]
+  gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress
+  gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize
+
diff --git a/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c b/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c
new file mode 100644
index 000000000000..18404405d9fa
--- /dev/null
+++ b/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c
@@ -0,0 +1,132 @@
+/** @file
+
+SetCacheMtrr library functions.
+This library implementation is for AMD processor based platforms.
+
+Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR>
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/MtrrLib.h>
+
+/**
+  This function sets the cache MTRR values for PEI phase.
+**/
+VOID
+EFIAPI
+SetCacheMtrr (
+  VOID
+  )
+{
+  EFI_STATUS  Status;
+
+  Status = MtrrSetMemoryAttribute (
+             0,
+             0xA0000,
+             CacheWriteBack
+             );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((
+      DEBUG_ERROR,
+      "Error(%r) in setting CacheWriteBack for 0-0x9FFFF\n",
+      Status
+      ));
+  }
+
+  Status = MtrrSetMemoryAttribute (
+             0xA0000,
+             0x20000,
+             CacheUncacheable
+             );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((
+      DEBUG_ERROR,
+      "Error(%r) in setting CacheUncacheable for 0xA0000-0xBFFFF\n",
+      Status
+      ));
+  }
+
+  Status = MtrrSetMemoryAttribute (
+             0xC0000,
+             0x40000,
+             CacheWriteProtected
+             );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((
+      DEBUG_ERROR,
+      "Error(%r) in setting CacheWriteProtected for 0xC0000-0xFFFFF\n",
+      Status
+      ));
+  }
+
+  Status = MtrrSetMemoryAttribute (
+             0x100000,
+             0xAFF00000,
+             CacheWriteBack
+             );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((
+      DEBUG_ERROR,
+      "Error(%r) in setting CacheWriteBack for 0x100000-0xAFFFFFFF\n",
+      Status
+      ));
+  }
+
+  Status = MtrrSetMemoryAttribute (
+             PcdGet32 (PcdFlashAreaBaseAddress),
+             PcdGet32 (PcdFlashAreaSize),
+             CacheWriteProtected
+             );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((
+      DEBUG_ERROR,
+      "Error(%r) in setting CacheWriteProtected for 0x%X-0x%X\n",
+      Status,
+      PcdGet32 (PcdFlashAreaBaseAddress),
+      PcdGet32 (PcdFlashAreaBaseAddress) + PcdGet32 (PcdFlashAreaSize)
+      ));
+  }
+
+  MtrrDebugPrintAllMtrrs ();
+  return;
+}
+
+/**
+  Update MTRR setting in EndOfPei phase.
+  This function will set the MTRR value as CacheUncacheable
+  for Flash address.
+
+  @retval  EFI_SUCCESS  The function completes successfully.
+  @retval  Others       Some error occurs.
+**/
+EFI_STATUS
+EFIAPI
+SetCacheMtrrAfterEndOfPei (
+  VOID
+  )
+{
+  EFI_STATUS  Status;
+
+  Status = MtrrSetMemoryAttribute (
+             PcdGet32 (PcdFlashAreaBaseAddress),
+             PcdGet32 (PcdFlashAreaSize),
+             CacheUncacheable
+             );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((
+      DEBUG_ERROR,
+      "Error(%r) in setting CacheUncacheable for 0x%X-0x%X\n",
+      Status,
+      PcdGet32 (PcdFlashAreaBaseAddress),
+      PcdGet32 (PcdFlashAreaBaseAddress) + PcdGet32 (PcdFlashAreaSize)
+      ));
+  }
+
+  MtrrDebugPrintAllMtrrs ();
+  return EFI_SUCCESS;
+}
-- 
2.25.1



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