Adds AMD/BoardPkg to support MinPlatformPkg framework. Adds AMD/PlatformPkg, which provide supporting modules and libraries for AMD based platform. PR: https://github.com/tianocore/edk2-platforms/pull/69 Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Abdul Lateef Attar (4): Platform/AMD: Adds BoardPkg and PlatformPkg Platform/AMD/PlatformPkg: Adds PciHotPlug init protocol implementation Platform/AMD/BoarkPkg: Adds SetCacheMtrrLib library Maintainers.txt: Adds AMD/BoardPkg and AMD/PlatformPkg maintainers Platform/AMD/BoardPkg/BoardPkg.dec | 18 + Platform/AMD/PlatformPkg/PlatformPkg.dec | 31 ++ Platform/AMD/BoardPkg/BoardPkg.dsc | 30 ++ Platform/AMD/PlatformPkg/PlatformPkg.dsc | 43 +++ .../SetCacheMtrrLib/SetCacheMtrrLib.inf | 37 ++ .../PlatformPkg/PciHotPlug/PciHotPlugInit.inf | 41 +++ .../Library/SetCacheMtrrLib/SetCacheMtrrLib.c | 132 +++++++ .../PlatformPkg/PciHotPlug/PciHotPlugInit.c | 340 ++++++++++++++++++ Maintainers.txt | 6 + 9 files changed, 678 insertions(+) create mode 100644 Platform/AMD/BoardPkg/BoardPkg.dec create mode 100644 Platform/AMD/PlatformPkg/PlatformPkg.dec create mode 100644 Platform/AMD/BoardPkg/BoardPkg.dsc create mode 100644 Platform/AMD/PlatformPkg/PlatformPkg.dsc create mode 100644 Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf create mode 100644 Platform/AMD/PlatformPkg/PciHotPlug/PciHotPlugInit.inf create mode 100644 Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c create mode 100644 Platform/AMD/PlatformPkg/PciHotPlug/PciHotPlugInit.c -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101302): https://edk2.groups.io/g/devel/message/101302 Mute This Topic: https://groups.io/mt/97667839/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=- Adds initial DEC and DSC file for BoardPkg and PlatformPkg packages, which supports AMD processor family based boards and platforms. Signed-off-by: Abdul Lateef Attar <abdattar@amd.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Abner Chang <abner.chang@amd.com> --- Platform/AMD/BoardPkg/BoardPkg.dec | 18 ++++++++++++++++++ Platform/AMD/PlatformPkg/PlatformPkg.dec | 15 +++++++++++++++ Platform/AMD/BoardPkg/BoardPkg.dsc | 20 ++++++++++++++++++++ Platform/AMD/PlatformPkg/PlatformPkg.dsc | 20 ++++++++++++++++++++ 4 files changed, 73 insertions(+) create mode 100644 Platform/AMD/BoardPkg/BoardPkg.dec create mode 100644 Platform/AMD/PlatformPkg/PlatformPkg.dec create mode 100644 Platform/AMD/BoardPkg/BoardPkg.dsc create mode 100644 Platform/AMD/PlatformPkg/PlatformPkg.dsc diff --git a/Platform/AMD/BoardPkg/BoardPkg.dec b/Platform/AMD/BoardPkg/BoardPkg.dec new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/AMD/BoardPkg/BoardPkg.dec @@ -XXX,XX +XXX,XX @@ +## @file BoardPkg.dec +# Declaration file for AMD's BoardPkg. +# +# This package supports AMD processor family based board as per the MinPlatform +# Arch specification. +# +# Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# @par Specification Reference: +# -https://tianocore-docs.github.io/edk2-MinimumPlatformSpecification/draft/ 0.7 +## + +[Defines] + DEC_SPECIFICATION = 1.27 + PACKAGE_NAME = BoardPkg + PACKAGE_GUID = 44F9D761-9ECB-43DD-A5AC-177E5048701B + PACKAGE_VERSION = 0.1 diff --git a/Platform/AMD/PlatformPkg/PlatformPkg.dec b/Platform/AMD/PlatformPkg/PlatformPkg.dec new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/AMD/PlatformPkg/PlatformPkg.dec @@ -XXX,XX +XXX,XX @@ +## @file PlatformPkg.dec +# Declaration file for AMD's PlatformPkg. +# +# This package supports AMD processory family based platform. +# +# Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + DEC_SPECIFICATION = 1.27 + PACKAGE_NAME = PlatformPkg + PACKAGE_GUID = 38FBA311-E2AA-4620-9A90-9A23753D1878 + PACKAGE_VERSION = 0.1 diff --git a/Platform/AMD/BoardPkg/BoardPkg.dsc b/Platform/AMD/BoardPkg/BoardPkg.dsc new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/AMD/BoardPkg/BoardPkg.dsc @@ -XXX,XX +XXX,XX @@ +## @file +# BoardPkg.dsc +# +# Description file for AMD BoardPkg +# +# Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + DSC_SPECIFICATION = 1.30 + PLATFORM_GUID = 88F8A9AE-2FA0-4D58-A6F9-05F635C05F4E + PLATFORM_NAME = BoardPkg + PLATFORM_VERSION = 0.1 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + BUILD_TARGETS = DEBUG | RELEASE | NOOPT + SUPPORTED_ARCHITECTURES = IA32 | X64 + +[Packages] + BoardPkg/BoardPkg.dec diff --git a/Platform/AMD/PlatformPkg/PlatformPkg.dsc b/Platform/AMD/PlatformPkg/PlatformPkg.dsc new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/AMD/PlatformPkg/PlatformPkg.dsc @@ -XXX,XX +XXX,XX @@ +## @file +# PlatformPkg.dsc +# +# Description file for AMD PlatformPkg +# +# Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + DSC_SPECIFICATION = 1.30 + PLATFORM_GUID = 2F7C29F2-7F35-4B49-B97D-F0E61BD42FC0 + PLATFORM_NAME = PlatformPkg + PLATFORM_VERSION = 0.1 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + BUILD_TARGETS = DEBUG | RELEASE | NOOPT + SUPPORTED_ARCHITECTURES = IA32 | X64 + +[Packages] + PlatformPkg/PlatformPkg.dec -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101303): https://edk2.groups.io/g/devel/message/101303 Mute This Topic: https://groups.io/mt/97667840/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=- Adds PCI hotplug init protocol implementation. Signed-off-by: Abdul Lateef Attar <abdattar@amd.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Abner Chang <abner.chang@amd.com Cc: Michael D Kinney <michael.d.kinney@intel.com> --- Platform/AMD/PlatformPkg/PlatformPkg.dec | 16 + Platform/AMD/PlatformPkg/PlatformPkg.dsc | 23 ++ .../PlatformPkg/PciHotPlug/PciHotPlugInit.inf | 41 +++ .../PlatformPkg/PciHotPlug/PciHotPlugInit.c | 340 ++++++++++++++++++ 4 files changed, 420 insertions(+) create mode 100644 Platform/AMD/PlatformPkg/PciHotPlug/PciHotPlugInit.inf create mode 100644 Platform/AMD/PlatformPkg/PciHotPlug/PciHotPlugInit.c diff --git a/Platform/AMD/PlatformPkg/PlatformPkg.dec b/Platform/AMD/PlatformPkg/PlatformPkg.dec index XXXXXXX..XXXXXXX 100644 --- a/Platform/AMD/PlatformPkg/PlatformPkg.dec +++ b/Platform/AMD/PlatformPkg/PlatformPkg.dec @@ -XXX,XX +XXX,XX @@ [Defines] PACKAGE_NAME = PlatformPkg PACKAGE_GUID = 38FBA311-E2AA-4620-9A90-9A23753D1878 PACKAGE_VERSION = 0.1 + +[Guids] + gPlatformPkgTokenSpaceGuid = { 0x95ECA58D, 0x09B6, 0x4420, { 0xB4, 0xE7, 0x01, 0x7F, 0x6A, 0x5B, 0x26, 0x0F }} + +[PcdsDynamic, PcdsDynamicEx] + # + # PCI HotPlug Resource Padding + # + # IO Resource padding in bytes, default 4KB + gPlatformPkgTokenSpaceGuid.PcdPciHotPlugResourcePadIO|0x00001000|UINT64|0x10000000 + # PreFetch Memory padding in bytes, default 2MB + gPlatformPkgTokenSpaceGuid.PcdPciHotPlugResourcePadPMem|0x00200000|UINT64|0x10000001 + # Non-PreFetch Memory padding in bytes, default 1MB + gPlatformPkgTokenSpaceGuid.PcdPciHotPlugResourcePadMem|0x00100000|UINT64|0x10000002 + # PCI bus padding, number of bus to reserve, default 2 bus + gPlatformPkgTokenSpaceGuid.PcdPciHotPlugResourcePadBus|2|UINT8|0x10000003 diff --git a/Platform/AMD/PlatformPkg/PlatformPkg.dsc b/Platform/AMD/PlatformPkg/PlatformPkg.dsc index XXXXXXX..XXXXXXX 100644 --- a/Platform/AMD/PlatformPkg/PlatformPkg.dsc +++ b/Platform/AMD/PlatformPkg/PlatformPkg.dsc @@ -XXX,XX +XXX,XX @@ [Defines] BUILD_TARGETS = DEBUG | RELEASE | NOOPT SUPPORTED_ARCHITECTURES = IA32 | X64 + [Packages] PlatformPkg/PlatformPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses.Common] + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + RegisterFilterLib|MdePkg/Library/RegisterFilterLibNull/RegisterFilterLibNull.inf + SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf + PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf + PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf + +[Components.X64] + PlatformPkg/PciHotPlug/PciHotPlugInit.inf diff --git a/Platform/AMD/PlatformPkg/PciHotPlug/PciHotPlugInit.inf b/Platform/AMD/PlatformPkg/PciHotPlug/PciHotPlugInit.inf new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/AMD/PlatformPkg/PciHotPlug/PciHotPlugInit.inf @@ -XXX,XX +XXX,XX @@ +## @file +# This driver implements EFI_PCI_HOT_PLUG_INIT_PROTOCOL. +# Adds resource padding information, for PCIe hotplug purposes. +# +# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION = 1.29 + BASE_NAME = PciHotPlugInit + FILE_GUID = 8B67D95F-78B7-484F-8F16-5F22AB388B0C + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 0.1 + ENTRY_POINT = PciHotPlugInitialize + +[Sources] + PciHotPlugInit.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + PlatformPkg/PlatformPkg.dec + +[LibraryClasses] + UefiDriverEntryPoint + UefiBootServicesTableLib + DebugLib + MemoryAllocationLib + +[Protocols] + gEfiPciHotPlugInitProtocolGuid + +[Pcd] + gPlatformPkgTokenSpaceGuid.PcdPciHotPlugResourcePadIO + gPlatformPkgTokenSpaceGuid.PcdPciHotPlugResourcePadPMem + gPlatformPkgTokenSpaceGuid.PcdPciHotPlugResourcePadMem + gPlatformPkgTokenSpaceGuid.PcdPciHotPlugResourcePadBus + +[Depex] + TRUE diff --git a/Platform/AMD/PlatformPkg/PciHotPlug/PciHotPlugInit.c b/Platform/AMD/PlatformPkg/PciHotPlug/PciHotPlugInit.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/AMD/PlatformPkg/PciHotPlug/PciHotPlugInit.c @@ -XXX,XX +XXX,XX @@ +/** @file + This file declares EFI PCI Hot Plug Init Protocol. + + This protocol provides the necessary functionality to initialize the Hot Plug + Controllers (HPCs) and the buses that they control. This protocol also provides + information regarding resource padding. + + @par Note: + This source has the reference of OVMF PciHotPluginit.c and Intel platform PciHotPlug.c. + + This protocol is required only on platforms that support one or more PCI Hot + Plug* slots or CardBus sockets. + + The EFI_PCI_HOT_PLUG_INIT_PROTOCOL provides a mechanism for the PCI bus enumerator + to properly initialize the HPCs and CardBus sockets that require initialization. + The HPC initialization takes place before the PCI enumeration process is complete. + There cannot be more than one instance of this protocol in a system. This protocol + is installed on its own separate handle. + + Because the system may include multiple HPCs, one instance of this protocol + should represent all of them. The protocol functions use the device path of + the HPC to identify the HPC. When the PCI bus enumerator finds a root HPC, it + will call EFI_PCI_HOT_PLUG_INIT_PROTOCOL.InitializeRootHpc(). If InitializeRootHpc() + is unable to initialize a root HPC, the PCI enumerator will ignore that root HPC + and continue the enumeration process. If the HPC is not initialized, the devices + that it controls may not be initialized, and no resource padding will be provided. + + From the standpoint of the PCI bus enumerator, HPCs are divided into the following + two classes: + + - Root HPC: + These HPCs must be initialized by calling InitializeRootHpc() during the + enumeration process. These HPCs will also require resource padding. The + platform code must have a priori knowledge of these devices and must know + how to initialize them. There may not be any way to access their PCI + configuration space before the PCI enumerator programs all the upstream + bridges and thus enables the path to these devices. The PCI bus enumerator + is responsible for determining the PCI bus address of the HPC before it + calls InitializeRootHpc(). + - Nonroot HPC: + These HPCs will not need explicit initialization during enumeration process. + These HPCs will require resource padding. The platform code does not have + to have a priori knowledge of these devices. + + Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR> + Copyright (C) 2016, Red Hat, Inc.<BR> + Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is defined in UEFI Platform Initialization Specification 1.2 + Volume 5: Standards + +**/ + +#include <Uefi/UefiBaseType.h> +#include <Uefi/UefiSpec.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/DebugLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Protocol/PciHotPlugInit.h> + +// +// The protocol interface this driver produces. +// +STATIC EFI_PCI_HOT_PLUG_INIT_PROTOCOL mPciHotPlugInit; + +/** + Returns a list of root Hot Plug Controllers (HPCs) that require initialization + during the boot process. + + This procedure returns a list of root HPCs. The PCI bus driver must initialize + these controllers during the boot process. The PCI bus driver may or may not be + able to detect these HPCs. If the platform includes a PCI-to-CardBus bridge, it + can be included in this list if it requires initialization. The HpcList must be + self consistent. An HPC cannot control any of its parent buses. Only one HPC can + control a PCI bus. Because this list includes only root HPCs, no HPC in the list + can be a child of another HPC. This policy must be enforced by the + EFI_PCI_HOT_PLUG_INIT_PROTOCOL. The PCI bus driver may not check for such + invalid conditions. The callee allocates the buffer HpcList + + @param[in] This Pointer to the EFI_PCI_HOT_PLUG_INIT_PROTOCOL instance. + @param[out] HpcCount The number of root HPCs that were returned. + @param[out] HpcList The list of root HPCs. HpcCount defines the number of + elements in this list. + + @retval EFI_SUCCESS HpcList was returned. + @retval EFI_OUT_OF_RESOURCES HpcList was not returned due to insufficient + resources. + @retval EFI_INVALID_PARAMETER HpcCount is NULL or HpcList is NULL. + +**/ +EFI_STATUS +EFIAPI +GetRootHpcList ( + IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This, + OUT UINTN *HpcCount, + OUT EFI_HPC_LOCATION **HpcList + ) +{ + if ((HpcCount == NULL) || (HpcList == NULL)) { + return EFI_INVALID_PARAMETER; + } + + // + // Platform BIOS not doing any extra/special HPC initialization + // Hence returning the HpcCount as zero and HpcList as NULL + // + *HpcCount = 0; + *HpcList = NULL; + + return EFI_SUCCESS; +} + +/** + Initializes one root Hot Plug Controller (HPC). This process may causes + initialization of its subordinate buses. + + This function initializes the specified HPC. At the end of initialization, + the hot-plug slots or sockets (controlled by this HPC) are powered and are + connected to the bus. All the necessary registers in the HPC are set up. For + a Standard (PCI) Hot Plug Controller (SHPC), the registers that must be set + up are defined in the PCI Standard Hot Plug Controller and Subsystem + Specification. + + @param[in] This Pointer to the EFI_PCI_HOT_PLUG_INIT_PROTOCOL instance. + @param[in] HpcDevicePath The device path to the HPC that is being initialized. + @param[in] HpcPciAddress The address of the HPC function on the PCI bus. + @param[in] Event The event that should be signaled when the HPC + initialization is complete. Set to NULL if the + caller wants to wait until the entire initialization + process is complete. + @param[out] HpcState The state of the HPC hardware. The state is + EFI_HPC_STATE_INITIALIZED or EFI_HPC_STATE_ENABLED. + + @retval EFI_SUCCESS If Event is NULL, the specific HPC was successfully + initialized. If Event is not NULL, Event will be + signaled at a later time when initialization is complete. + @retval EFI_UNSUPPORTED This instance of EFI_PCI_HOT_PLUG_INIT_PROTOCOL + does not support the specified HPC. + @retval EFI_OUT_OF_RESOURCES Initialization failed due to insufficient + resources. + @retval EFI_INVALID_PARAMETER HpcState is NULL. + +**/ +EFI_STATUS +EFIAPI +InitializeRootHpc ( + IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This, + IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath, + IN UINT64 HpcPciAddress, + IN EFI_EVENT Event, OPTIONAL + OUT EFI_HPC_STATE *HpcState + ) +{ + if (HpcState == NULL) { + return EFI_INVALID_PARAMETER; + } + + // + // This Platform doesnt have any non-enumerated HPC. + // Hence no extra initialization required from Platform BIOS. + // + return EFI_UNSUPPORTED; +} + +/** + Returns the resource padding that is required by the PCI bus that is controlled + by the specified Hot Plug Controller (HPC). + + This function returns the resource padding that is required by the PCI bus that + is controlled by the specified HPC. This member function is called for all the + root HPCs and nonroot HPCs that are detected by the PCI bus enumerator. This + function will be called before PCI resource allocation is completed. This function + must be called after all the root HPCs, with the possible exception of a + PCI-to-CardBus bridge, have completed initialization. + + @param[in] This Pointer to the EFI_PCI_HOT_PLUG_INIT_PROTOCOL instance. + @param[in] HpcDevicePath The device path to the HPC. + @param[in] HpcPciAddress The address of the HPC function on the PCI bus. + @param[out] HpcState The state of the HPC hardware. + @param[out] Padding The amount of resource padding that is required by the + PCI bus under the control of the specified HPC. + @param[out] Attributes Describes how padding is accounted for. The padding + is returned in the form of ACPI 2.0 resource descriptors. + + @retval EFI_SUCCESS The resource padding was successfully returned. + @retval EFI_UNSUPPORTED This instance of the EFI_PCI_HOT_PLUG_INIT_PROTOCOL + does not support the specified HPC. + @retval EFI_NOT_READY This function was called before HPC initialization + is complete. + @retval EFI_INVALID_PARAMETER HpcState or Padding or Attributes is NULL. + @retval EFI_OUT_OF_RESOURCES ACPI 2.0 resource descriptors for Padding + cannot be allocated due to insufficient resources. + +**/ +EFI_STATUS +EFIAPI +GetResourcePadding ( + IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This, + IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath, + IN UINT64 HpcPciAddress, + OUT EFI_HPC_STATE *HpcState, + OUT VOID **Padding, + OUT EFI_HPC_PADDING_ATTRIBUTES *Attributes + ) +{ + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *PaddingResource; + + // + // Need total 5 resources + // 1 - IO resource + // 2 - Mem resource + // 3 - PMem resource + // 4 - Bus resource + // 5 - end tag resource + PaddingResource = AllocateZeroPool (4 * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)); + if (PaddingResource == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + *Padding = (VOID *)PaddingResource; + + // + // Padding for bus + // + *Attributes = EfiPaddingPciBus; + + PaddingResource->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR; + PaddingResource->Len = (UINT16)( + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - + OFFSET_OF ( + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR, + ResType + ) + ); + PaddingResource->ResType = ACPI_ADDRESS_SPACE_TYPE_BUS; + PaddingResource->GenFlag = 0x0; + PaddingResource->SpecificFlag = 0; + PaddingResource->AddrRangeMin = 0; + PaddingResource->AddrRangeMax = 0; + PaddingResource->AddrLen = PcdGet8 (PcdPciHotPlugResourcePadBus); + + // + // Padding for non-prefetchable memory + // + PaddingResource++; + PaddingResource->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR; + PaddingResource->Len = (UINT16)( + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - + OFFSET_OF ( + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR, + ResType + ) + ); + PaddingResource->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM; + PaddingResource->GenFlag = 0x0; + PaddingResource->AddrSpaceGranularity = 32; + PaddingResource->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_NON_CACHEABLE; + PaddingResource->AddrRangeMin = 0; + PaddingResource->AddrLen = PcdGet64 (PcdPciHotPlugResourcePadMem); + PaddingResource->AddrRangeMax = PaddingResource->AddrLen - 1; + + // + // Padding for prefetchable memory + // + PaddingResource++; + PaddingResource->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR; + PaddingResource->Len = (UINT16)( + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - + OFFSET_OF ( + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR, + ResType + ) + ); + PaddingResource->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM; + PaddingResource->GenFlag = 0x0; + PaddingResource->AddrSpaceGranularity = 32; + PaddingResource->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE; + PaddingResource->AddrLen = PcdGet64 (PcdPciHotPlugResourcePadPMem); + PaddingResource->AddrRangeMax = PaddingResource->AddrLen - 1; + + // + // Padding for I/O + // + PaddingResource++; + PaddingResource->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR; + PaddingResource->Len = (UINT16)( + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - + OFFSET_OF ( + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR, + ResType + ) + ); + PaddingResource->ResType = ACPI_ADDRESS_SPACE_TYPE_IO; + PaddingResource->GenFlag = 0x0; + PaddingResource->SpecificFlag = 0; + PaddingResource->AddrRangeMin = 0; + PaddingResource->AddrLen = PcdGet64 (PcdPciHotPlugResourcePadIO); + PaddingResource->AddrRangeMax = PaddingResource->AddrLen - 1; + + // + // Terminate the entries. + // + PaddingResource++; + ((EFI_ACPI_END_TAG_DESCRIPTOR *)PaddingResource)->Desc = ACPI_END_TAG_DESCRIPTOR; + ((EFI_ACPI_END_TAG_DESCRIPTOR *)PaddingResource)->Checksum = 0x0; + + *HpcState = EFI_HPC_STATE_INITIALIZED | EFI_HPC_STATE_ENABLED; + + return EFI_SUCCESS; +} + +/** + Entry point for this driver. + + @param[in] ImageHandle Image handle of this driver. + @param[in] SystemTable Pointer to SystemTable. + + @retval EFI_SUCESS Driver has loaded successfully. + @return Error codes from lower level functions. + +**/ +EFI_STATUS +EFIAPI +PciHotPlugInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + mPciHotPlugInit.GetRootHpcList = GetRootHpcList; + mPciHotPlugInit.InitializeRootHpc = InitializeRootHpc; + mPciHotPlugInit.GetResourcePadding = GetResourcePadding; + return gBS->InstallMultipleProtocolInterfaces ( + &ImageHandle, + &gEfiPciHotPlugInitProtocolGuid, + &mPciHotPlugInit, + NULL + ); +} -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101304): https://edk2.groups.io/g/devel/message/101304 Mute This Topic: https://groups.io/mt/97667843/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=- Adds SetCacheMtrrLib library for AMD processor based boards. This library sets MTRR value or various memory ranges. Signed-off-by: Abdul Lateef Attar <abdattar@amd.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Abner Chang <abner.chang@amd.com Cc: Michael D Kinney <michael.d.kinney@intel.com> --- Platform/AMD/BoardPkg/BoardPkg.dsc | 10 ++ .../SetCacheMtrrLib/SetCacheMtrrLib.inf | 37 +++++ .../Library/SetCacheMtrrLib/SetCacheMtrrLib.c | 132 ++++++++++++++++++ 3 files changed, 179 insertions(+) create mode 100644 Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf create mode 100644 Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c diff --git a/Platform/AMD/BoardPkg/BoardPkg.dsc b/Platform/AMD/BoardPkg/BoardPkg.dsc index XXXXXXX..XXXXXXX 100644 --- a/Platform/AMD/BoardPkg/BoardPkg.dsc +++ b/Platform/AMD/BoardPkg/BoardPkg.dsc @@ -XXX,XX +XXX,XX @@ [Defines] [Packages] BoardPkg/BoardPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses.common.PEIM] + SetCacheMtrrLib|BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf + +[Components.IA32] + BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf + diff --git a/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf b/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf @@ -XXX,XX +XXX,XX @@ +## @file +# Component information file for Platform SetCacheMtrr Library. +# This library implementation is for AMD processor based platforms. +# +# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 1.29 + BASE_NAME = PeiSetCacheMtrrLib + FILE_GUID = 1E8468E0-5EB4-4088-9B52-BFDC6E4DAE87 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + LIBRARY_CLASS = SetCacheMtrrLib + +[LibraryClasses] + BaseLib + DebugLib + MtrrLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[Sources] + SetCacheMtrrLib.c + +[Guids] + +[Pcd] + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize + diff --git a/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c b/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c @@ -XXX,XX +XXX,XX @@ +/** @file + +SetCacheMtrr library functions. +This library implementation is for AMD processor based platforms. + +Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR> + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <Uefi.h> +#include <PiPei.h> +#include <Library/DebugLib.h> +#include <Library/MtrrLib.h> + +/** + This function sets the cache MTRR values for PEI phase. +**/ +VOID +EFIAPI +SetCacheMtrr ( + VOID + ) +{ + EFI_STATUS Status; + + Status = MtrrSetMemoryAttribute ( + 0, + 0xA0000, + CacheWriteBack + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "Error(%r) in setting CacheWriteBack for 0-0x9FFFF\n", + Status + )); + } + + Status = MtrrSetMemoryAttribute ( + 0xA0000, + 0x20000, + CacheUncacheable + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "Error(%r) in setting CacheUncacheable for 0xA0000-0xBFFFF\n", + Status + )); + } + + Status = MtrrSetMemoryAttribute ( + 0xC0000, + 0x40000, + CacheWriteProtected + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "Error(%r) in setting CacheWriteProtected for 0xC0000-0xFFFFF\n", + Status + )); + } + + Status = MtrrSetMemoryAttribute ( + 0x100000, + 0xAFF00000, + CacheWriteBack + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "Error(%r) in setting CacheWriteBack for 0x100000-0xAFFFFFFF\n", + Status + )); + } + + Status = MtrrSetMemoryAttribute ( + PcdGet32 (PcdFlashAreaBaseAddress), + PcdGet32 (PcdFlashAreaSize), + CacheWriteProtected + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "Error(%r) in setting CacheWriteProtected for 0x%X-0x%X\n", + Status, + PcdGet32 (PcdFlashAreaBaseAddress), + PcdGet32 (PcdFlashAreaBaseAddress) + PcdGet32 (PcdFlashAreaSize) + )); + } + + MtrrDebugPrintAllMtrrs (); + return; +} + +/** + Update MTRR setting in EndOfPei phase. + This function will set the MTRR value as CacheUncacheable + for Flash address. + + @retval EFI_SUCCESS The function completes successfully. + @retval Others Some error occurs. +**/ +EFI_STATUS +EFIAPI +SetCacheMtrrAfterEndOfPei ( + VOID + ) +{ + EFI_STATUS Status; + + Status = MtrrSetMemoryAttribute ( + PcdGet32 (PcdFlashAreaBaseAddress), + PcdGet32 (PcdFlashAreaSize), + CacheUncacheable + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "Error(%r) in setting CacheUncacheable for 0x%X-0x%X\n", + Status, + PcdGet32 (PcdFlashAreaBaseAddress), + PcdGet32 (PcdFlashAreaBaseAddress) + PcdGet32 (PcdFlashAreaSize) + )); + } + + MtrrDebugPrintAllMtrrs (); + return EFI_SUCCESS; +} -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101305): https://edk2.groups.io/g/devel/message/101305 Mute This Topic: https://groups.io/mt/97667844/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=- From: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Adds maintainers for AMD/BoardPkg and AMD/PlatformPkg. Signed-off-by: Abdul Lateef Attar <abdattar@amd.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Abner Chang <abner.chang@amd.com Cc: Michael D Kinney <michael.d.kinney@intel.com> --- Maintainers.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Maintainers.txt b/Maintainers.txt index XXXXXXX..XXXXXXX 100644 --- a/Maintainers.txt +++ b/Maintainers.txt @@ -XXX,XX +XXX,XX @@ F: Silicon/AMD/Styx/ M: Ard Biesheuvel <ardb+tianocore@kernel.org> M: Leif Lindholm <quic_llindhol@quicinc.com> +AMD Platform +F: Platform/AMD/BoardPkg +F: Platform/AMD/PlatformPkg +M: Abner Chang <abner.chang@amd.com> +M: Abdul Lateef Attar <abdattar@amd.com> + Ampere Computing F: Platform/Ampere F: Silicon/Ampere -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101306): https://edk2.groups.io/g/devel/message/101306 Mute This Topic: https://groups.io/mt/97667845/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=- Resending with correct email Adds AMD/BoardPkg to support MinPlatformPkg framework. Adds AMD/PlatformPkg, which provide supporting modules and libraries for AMD based platform. PR: https://github.com/tianocore/edk2-platforms/pull/69 Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Abdul Lateef Attar (4): Platform/AMD: Adds BoardPkg and PlatformPkg Platform/AMD/PlatformPkg: Adds PciHotPlug init protocol implementation Platform/AMD/BoarkPkg: Adds SetCacheMtrrLib library Maintainers.txt: Adds AMD/BoardPkg and AMD/PlatformPkg maintainers Platform/AMD/BoardPkg/BoardPkg.dec | 18 + Platform/AMD/PlatformPkg/PlatformPkg.dec | 31 ++ Platform/AMD/BoardPkg/BoardPkg.dsc | 30 ++ Platform/AMD/PlatformPkg/PlatformPkg.dsc | 43 +++ .../SetCacheMtrrLib/SetCacheMtrrLib.inf | 37 ++ .../PlatformPkg/PciHotPlug/PciHotPlugInit.inf | 41 +++ .../Library/SetCacheMtrrLib/SetCacheMtrrLib.c | 132 +++++++ .../PlatformPkg/PciHotPlug/PciHotPlugInit.c | 340 ++++++++++++++++++ Maintainers.txt | 6 + 9 files changed, 678 insertions(+) create mode 100644 Platform/AMD/BoardPkg/BoardPkg.dec create mode 100644 Platform/AMD/PlatformPkg/PlatformPkg.dec create mode 100644 Platform/AMD/BoardPkg/BoardPkg.dsc create mode 100644 Platform/AMD/PlatformPkg/PlatformPkg.dsc create mode 100644 Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf create mode 100644 Platform/AMD/PlatformPkg/PciHotPlug/PciHotPlugInit.inf create mode 100644 Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c create mode 100644 Platform/AMD/PlatformPkg/PciHotPlug/PciHotPlugInit.c -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101310): https://edk2.groups.io/g/devel/message/101310 Mute This Topic: https://groups.io/mt/97667944/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=- Adds initial DEC and DSC file for BoardPkg and PlatformPkg packages, which supports AMD processor family based boards and platforms. Signed-off-by: Abdul Lateef Attar <abdattar@amd.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Abner Chang <abner.chang@amd.com> --- Platform/AMD/BoardPkg/BoardPkg.dec | 18 ++++++++++++++++++ Platform/AMD/PlatformPkg/PlatformPkg.dec | 15 +++++++++++++++ Platform/AMD/BoardPkg/BoardPkg.dsc | 20 ++++++++++++++++++++ Platform/AMD/PlatformPkg/PlatformPkg.dsc | 20 ++++++++++++++++++++ 4 files changed, 73 insertions(+) create mode 100644 Platform/AMD/BoardPkg/BoardPkg.dec create mode 100644 Platform/AMD/PlatformPkg/PlatformPkg.dec create mode 100644 Platform/AMD/BoardPkg/BoardPkg.dsc create mode 100644 Platform/AMD/PlatformPkg/PlatformPkg.dsc diff --git a/Platform/AMD/BoardPkg/BoardPkg.dec b/Platform/AMD/BoardPkg/BoardPkg.dec new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/AMD/BoardPkg/BoardPkg.dec @@ -XXX,XX +XXX,XX @@ +## @file BoardPkg.dec +# Declaration file for AMD's BoardPkg. +# +# This package supports AMD processor family based board as per the MinPlatform +# Arch specification. +# +# Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# @par Specification Reference: +# -https://tianocore-docs.github.io/edk2-MinimumPlatformSpecification/draft/ 0.7 +## + +[Defines] + DEC_SPECIFICATION = 1.27 + PACKAGE_NAME = BoardPkg + PACKAGE_GUID = 44F9D761-9ECB-43DD-A5AC-177E5048701B + PACKAGE_VERSION = 0.1 diff --git a/Platform/AMD/PlatformPkg/PlatformPkg.dec b/Platform/AMD/PlatformPkg/PlatformPkg.dec new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/AMD/PlatformPkg/PlatformPkg.dec @@ -XXX,XX +XXX,XX @@ +## @file PlatformPkg.dec +# Declaration file for AMD's PlatformPkg. +# +# This package supports AMD processory family based platform. +# +# Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + DEC_SPECIFICATION = 1.27 + PACKAGE_NAME = PlatformPkg + PACKAGE_GUID = 38FBA311-E2AA-4620-9A90-9A23753D1878 + PACKAGE_VERSION = 0.1 diff --git a/Platform/AMD/BoardPkg/BoardPkg.dsc b/Platform/AMD/BoardPkg/BoardPkg.dsc new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/AMD/BoardPkg/BoardPkg.dsc @@ -XXX,XX +XXX,XX @@ +## @file +# BoardPkg.dsc +# +# Description file for AMD BoardPkg +# +# Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + DSC_SPECIFICATION = 1.30 + PLATFORM_GUID = 88F8A9AE-2FA0-4D58-A6F9-05F635C05F4E + PLATFORM_NAME = BoardPkg + PLATFORM_VERSION = 0.1 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + BUILD_TARGETS = DEBUG | RELEASE | NOOPT + SUPPORTED_ARCHITECTURES = IA32 | X64 + +[Packages] + BoardPkg/BoardPkg.dec diff --git a/Platform/AMD/PlatformPkg/PlatformPkg.dsc b/Platform/AMD/PlatformPkg/PlatformPkg.dsc new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/AMD/PlatformPkg/PlatformPkg.dsc @@ -XXX,XX +XXX,XX @@ +## @file +# PlatformPkg.dsc +# +# Description file for AMD PlatformPkg +# +# Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + DSC_SPECIFICATION = 1.30 + PLATFORM_GUID = 2F7C29F2-7F35-4B49-B97D-F0E61BD42FC0 + PLATFORM_NAME = PlatformPkg + PLATFORM_VERSION = 0.1 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + BUILD_TARGETS = DEBUG | RELEASE | NOOPT + SUPPORTED_ARCHITECTURES = IA32 | X64 + +[Packages] + PlatformPkg/PlatformPkg.dec -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101308): https://edk2.groups.io/g/devel/message/101308 Mute This Topic: https://groups.io/mt/97667942/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=- Adds PCI hotplug init protocol implementation. Signed-off-by: Abdul Lateef Attar <abdattar@amd.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> --- Platform/AMD/PlatformPkg/PlatformPkg.dec | 16 + Platform/AMD/PlatformPkg/PlatformPkg.dsc | 23 ++ .../PlatformPkg/PciHotPlug/PciHotPlugInit.inf | 41 +++ .../PlatformPkg/PciHotPlug/PciHotPlugInit.c | 340 ++++++++++++++++++ 4 files changed, 420 insertions(+) create mode 100644 Platform/AMD/PlatformPkg/PciHotPlug/PciHotPlugInit.inf create mode 100644 Platform/AMD/PlatformPkg/PciHotPlug/PciHotPlugInit.c diff --git a/Platform/AMD/PlatformPkg/PlatformPkg.dec b/Platform/AMD/PlatformPkg/PlatformPkg.dec index XXXXXXX..XXXXXXX 100644 --- a/Platform/AMD/PlatformPkg/PlatformPkg.dec +++ b/Platform/AMD/PlatformPkg/PlatformPkg.dec @@ -XXX,XX +XXX,XX @@ [Defines] PACKAGE_NAME = PlatformPkg PACKAGE_GUID = 38FBA311-E2AA-4620-9A90-9A23753D1878 PACKAGE_VERSION = 0.1 + +[Guids] + gPlatformPkgTokenSpaceGuid = { 0x95ECA58D, 0x09B6, 0x4420, { 0xB4, 0xE7, 0x01, 0x7F, 0x6A, 0x5B, 0x26, 0x0F }} + +[PcdsDynamic, PcdsDynamicEx] + # + # PCI HotPlug Resource Padding + # + # IO Resource padding in bytes, default 4KB + gPlatformPkgTokenSpaceGuid.PcdPciHotPlugResourcePadIO|0x00001000|UINT64|0x10000000 + # PreFetch Memory padding in bytes, default 2MB + gPlatformPkgTokenSpaceGuid.PcdPciHotPlugResourcePadPMem|0x00200000|UINT64|0x10000001 + # Non-PreFetch Memory padding in bytes, default 1MB + gPlatformPkgTokenSpaceGuid.PcdPciHotPlugResourcePadMem|0x00100000|UINT64|0x10000002 + # PCI bus padding, number of bus to reserve, default 2 bus + gPlatformPkgTokenSpaceGuid.PcdPciHotPlugResourcePadBus|2|UINT8|0x10000003 diff --git a/Platform/AMD/PlatformPkg/PlatformPkg.dsc b/Platform/AMD/PlatformPkg/PlatformPkg.dsc index XXXXXXX..XXXXXXX 100644 --- a/Platform/AMD/PlatformPkg/PlatformPkg.dsc +++ b/Platform/AMD/PlatformPkg/PlatformPkg.dsc @@ -XXX,XX +XXX,XX @@ [Defines] BUILD_TARGETS = DEBUG | RELEASE | NOOPT SUPPORTED_ARCHITECTURES = IA32 | X64 + [Packages] PlatformPkg/PlatformPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses.Common] + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + RegisterFilterLib|MdePkg/Library/RegisterFilterLibNull/RegisterFilterLibNull.inf + SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf + PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf + PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf + +[Components.X64] + PlatformPkg/PciHotPlug/PciHotPlugInit.inf diff --git a/Platform/AMD/PlatformPkg/PciHotPlug/PciHotPlugInit.inf b/Platform/AMD/PlatformPkg/PciHotPlug/PciHotPlugInit.inf new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/AMD/PlatformPkg/PciHotPlug/PciHotPlugInit.inf @@ -XXX,XX +XXX,XX @@ +## @file +# This driver implements EFI_PCI_HOT_PLUG_INIT_PROTOCOL. +# Adds resource padding information, for PCIe hotplug purposes. +# +# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION = 1.29 + BASE_NAME = PciHotPlugInit + FILE_GUID = 8B67D95F-78B7-484F-8F16-5F22AB388B0C + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 0.1 + ENTRY_POINT = PciHotPlugInitialize + +[Sources] + PciHotPlugInit.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + PlatformPkg/PlatformPkg.dec + +[LibraryClasses] + UefiDriverEntryPoint + UefiBootServicesTableLib + DebugLib + MemoryAllocationLib + +[Protocols] + gEfiPciHotPlugInitProtocolGuid + +[Pcd] + gPlatformPkgTokenSpaceGuid.PcdPciHotPlugResourcePadIO + gPlatformPkgTokenSpaceGuid.PcdPciHotPlugResourcePadPMem + gPlatformPkgTokenSpaceGuid.PcdPciHotPlugResourcePadMem + gPlatformPkgTokenSpaceGuid.PcdPciHotPlugResourcePadBus + +[Depex] + TRUE diff --git a/Platform/AMD/PlatformPkg/PciHotPlug/PciHotPlugInit.c b/Platform/AMD/PlatformPkg/PciHotPlug/PciHotPlugInit.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/AMD/PlatformPkg/PciHotPlug/PciHotPlugInit.c @@ -XXX,XX +XXX,XX @@ +/** @file + This file declares EFI PCI Hot Plug Init Protocol. + + This protocol provides the necessary functionality to initialize the Hot Plug + Controllers (HPCs) and the buses that they control. This protocol also provides + information regarding resource padding. + + @par Note: + This source has the reference of OVMF PciHotPluginit.c and Intel platform PciHotPlug.c. + + This protocol is required only on platforms that support one or more PCI Hot + Plug* slots or CardBus sockets. + + The EFI_PCI_HOT_PLUG_INIT_PROTOCOL provides a mechanism for the PCI bus enumerator + to properly initialize the HPCs and CardBus sockets that require initialization. + The HPC initialization takes place before the PCI enumeration process is complete. + There cannot be more than one instance of this protocol in a system. This protocol + is installed on its own separate handle. + + Because the system may include multiple HPCs, one instance of this protocol + should represent all of them. The protocol functions use the device path of + the HPC to identify the HPC. When the PCI bus enumerator finds a root HPC, it + will call EFI_PCI_HOT_PLUG_INIT_PROTOCOL.InitializeRootHpc(). If InitializeRootHpc() + is unable to initialize a root HPC, the PCI enumerator will ignore that root HPC + and continue the enumeration process. If the HPC is not initialized, the devices + that it controls may not be initialized, and no resource padding will be provided. + + From the standpoint of the PCI bus enumerator, HPCs are divided into the following + two classes: + + - Root HPC: + These HPCs must be initialized by calling InitializeRootHpc() during the + enumeration process. These HPCs will also require resource padding. The + platform code must have a priori knowledge of these devices and must know + how to initialize them. There may not be any way to access their PCI + configuration space before the PCI enumerator programs all the upstream + bridges and thus enables the path to these devices. The PCI bus enumerator + is responsible for determining the PCI bus address of the HPC before it + calls InitializeRootHpc(). + - Nonroot HPC: + These HPCs will not need explicit initialization during enumeration process. + These HPCs will require resource padding. The platform code does not have + to have a priori knowledge of these devices. + + Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR> + Copyright (C) 2016, Red Hat, Inc.<BR> + Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is defined in UEFI Platform Initialization Specification 1.2 + Volume 5: Standards + +**/ + +#include <Uefi/UefiBaseType.h> +#include <Uefi/UefiSpec.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/DebugLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Protocol/PciHotPlugInit.h> + +// +// The protocol interface this driver produces. +// +STATIC EFI_PCI_HOT_PLUG_INIT_PROTOCOL mPciHotPlugInit; + +/** + Returns a list of root Hot Plug Controllers (HPCs) that require initialization + during the boot process. + + This procedure returns a list of root HPCs. The PCI bus driver must initialize + these controllers during the boot process. The PCI bus driver may or may not be + able to detect these HPCs. If the platform includes a PCI-to-CardBus bridge, it + can be included in this list if it requires initialization. The HpcList must be + self consistent. An HPC cannot control any of its parent buses. Only one HPC can + control a PCI bus. Because this list includes only root HPCs, no HPC in the list + can be a child of another HPC. This policy must be enforced by the + EFI_PCI_HOT_PLUG_INIT_PROTOCOL. The PCI bus driver may not check for such + invalid conditions. The callee allocates the buffer HpcList + + @param[in] This Pointer to the EFI_PCI_HOT_PLUG_INIT_PROTOCOL instance. + @param[out] HpcCount The number of root HPCs that were returned. + @param[out] HpcList The list of root HPCs. HpcCount defines the number of + elements in this list. + + @retval EFI_SUCCESS HpcList was returned. + @retval EFI_OUT_OF_RESOURCES HpcList was not returned due to insufficient + resources. + @retval EFI_INVALID_PARAMETER HpcCount is NULL or HpcList is NULL. + +**/ +EFI_STATUS +EFIAPI +GetRootHpcList ( + IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This, + OUT UINTN *HpcCount, + OUT EFI_HPC_LOCATION **HpcList + ) +{ + if ((HpcCount == NULL) || (HpcList == NULL)) { + return EFI_INVALID_PARAMETER; + } + + // + // Platform BIOS not doing any extra/special HPC initialization + // Hence returning the HpcCount as zero and HpcList as NULL + // + *HpcCount = 0; + *HpcList = NULL; + + return EFI_SUCCESS; +} + +/** + Initializes one root Hot Plug Controller (HPC). This process may causes + initialization of its subordinate buses. + + This function initializes the specified HPC. At the end of initialization, + the hot-plug slots or sockets (controlled by this HPC) are powered and are + connected to the bus. All the necessary registers in the HPC are set up. For + a Standard (PCI) Hot Plug Controller (SHPC), the registers that must be set + up are defined in the PCI Standard Hot Plug Controller and Subsystem + Specification. + + @param[in] This Pointer to the EFI_PCI_HOT_PLUG_INIT_PROTOCOL instance. + @param[in] HpcDevicePath The device path to the HPC that is being initialized. + @param[in] HpcPciAddress The address of the HPC function on the PCI bus. + @param[in] Event The event that should be signaled when the HPC + initialization is complete. Set to NULL if the + caller wants to wait until the entire initialization + process is complete. + @param[out] HpcState The state of the HPC hardware. The state is + EFI_HPC_STATE_INITIALIZED or EFI_HPC_STATE_ENABLED. + + @retval EFI_SUCCESS If Event is NULL, the specific HPC was successfully + initialized. If Event is not NULL, Event will be + signaled at a later time when initialization is complete. + @retval EFI_UNSUPPORTED This instance of EFI_PCI_HOT_PLUG_INIT_PROTOCOL + does not support the specified HPC. + @retval EFI_OUT_OF_RESOURCES Initialization failed due to insufficient + resources. + @retval EFI_INVALID_PARAMETER HpcState is NULL. + +**/ +EFI_STATUS +EFIAPI +InitializeRootHpc ( + IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This, + IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath, + IN UINT64 HpcPciAddress, + IN EFI_EVENT Event, OPTIONAL + OUT EFI_HPC_STATE *HpcState + ) +{ + if (HpcState == NULL) { + return EFI_INVALID_PARAMETER; + } + + // + // This Platform doesnt have any non-enumerated HPC. + // Hence no extra initialization required from Platform BIOS. + // + return EFI_UNSUPPORTED; +} + +/** + Returns the resource padding that is required by the PCI bus that is controlled + by the specified Hot Plug Controller (HPC). + + This function returns the resource padding that is required by the PCI bus that + is controlled by the specified HPC. This member function is called for all the + root HPCs and nonroot HPCs that are detected by the PCI bus enumerator. This + function will be called before PCI resource allocation is completed. This function + must be called after all the root HPCs, with the possible exception of a + PCI-to-CardBus bridge, have completed initialization. + + @param[in] This Pointer to the EFI_PCI_HOT_PLUG_INIT_PROTOCOL instance. + @param[in] HpcDevicePath The device path to the HPC. + @param[in] HpcPciAddress The address of the HPC function on the PCI bus. + @param[out] HpcState The state of the HPC hardware. + @param[out] Padding The amount of resource padding that is required by the + PCI bus under the control of the specified HPC. + @param[out] Attributes Describes how padding is accounted for. The padding + is returned in the form of ACPI 2.0 resource descriptors. + + @retval EFI_SUCCESS The resource padding was successfully returned. + @retval EFI_UNSUPPORTED This instance of the EFI_PCI_HOT_PLUG_INIT_PROTOCOL + does not support the specified HPC. + @retval EFI_NOT_READY This function was called before HPC initialization + is complete. + @retval EFI_INVALID_PARAMETER HpcState or Padding or Attributes is NULL. + @retval EFI_OUT_OF_RESOURCES ACPI 2.0 resource descriptors for Padding + cannot be allocated due to insufficient resources. + +**/ +EFI_STATUS +EFIAPI +GetResourcePadding ( + IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This, + IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath, + IN UINT64 HpcPciAddress, + OUT EFI_HPC_STATE *HpcState, + OUT VOID **Padding, + OUT EFI_HPC_PADDING_ATTRIBUTES *Attributes + ) +{ + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *PaddingResource; + + // + // Need total 5 resources + // 1 - IO resource + // 2 - Mem resource + // 3 - PMem resource + // 4 - Bus resource + // 5 - end tag resource + PaddingResource = AllocateZeroPool (4 * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)); + if (PaddingResource == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + *Padding = (VOID *)PaddingResource; + + // + // Padding for bus + // + *Attributes = EfiPaddingPciBus; + + PaddingResource->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR; + PaddingResource->Len = (UINT16)( + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - + OFFSET_OF ( + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR, + ResType + ) + ); + PaddingResource->ResType = ACPI_ADDRESS_SPACE_TYPE_BUS; + PaddingResource->GenFlag = 0x0; + PaddingResource->SpecificFlag = 0; + PaddingResource->AddrRangeMin = 0; + PaddingResource->AddrRangeMax = 0; + PaddingResource->AddrLen = PcdGet8 (PcdPciHotPlugResourcePadBus); + + // + // Padding for non-prefetchable memory + // + PaddingResource++; + PaddingResource->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR; + PaddingResource->Len = (UINT16)( + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - + OFFSET_OF ( + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR, + ResType + ) + ); + PaddingResource->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM; + PaddingResource->GenFlag = 0x0; + PaddingResource->AddrSpaceGranularity = 32; + PaddingResource->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_NON_CACHEABLE; + PaddingResource->AddrRangeMin = 0; + PaddingResource->AddrLen = PcdGet64 (PcdPciHotPlugResourcePadMem); + PaddingResource->AddrRangeMax = PaddingResource->AddrLen - 1; + + // + // Padding for prefetchable memory + // + PaddingResource++; + PaddingResource->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR; + PaddingResource->Len = (UINT16)( + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - + OFFSET_OF ( + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR, + ResType + ) + ); + PaddingResource->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM; + PaddingResource->GenFlag = 0x0; + PaddingResource->AddrSpaceGranularity = 32; + PaddingResource->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE; + PaddingResource->AddrLen = PcdGet64 (PcdPciHotPlugResourcePadPMem); + PaddingResource->AddrRangeMax = PaddingResource->AddrLen - 1; + + // + // Padding for I/O + // + PaddingResource++; + PaddingResource->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR; + PaddingResource->Len = (UINT16)( + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - + OFFSET_OF ( + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR, + ResType + ) + ); + PaddingResource->ResType = ACPI_ADDRESS_SPACE_TYPE_IO; + PaddingResource->GenFlag = 0x0; + PaddingResource->SpecificFlag = 0; + PaddingResource->AddrRangeMin = 0; + PaddingResource->AddrLen = PcdGet64 (PcdPciHotPlugResourcePadIO); + PaddingResource->AddrRangeMax = PaddingResource->AddrLen - 1; + + // + // Terminate the entries. + // + PaddingResource++; + ((EFI_ACPI_END_TAG_DESCRIPTOR *)PaddingResource)->Desc = ACPI_END_TAG_DESCRIPTOR; + ((EFI_ACPI_END_TAG_DESCRIPTOR *)PaddingResource)->Checksum = 0x0; + + *HpcState = EFI_HPC_STATE_INITIALIZED | EFI_HPC_STATE_ENABLED; + + return EFI_SUCCESS; +} + +/** + Entry point for this driver. + + @param[in] ImageHandle Image handle of this driver. + @param[in] SystemTable Pointer to SystemTable. + + @retval EFI_SUCESS Driver has loaded successfully. + @return Error codes from lower level functions. + +**/ +EFI_STATUS +EFIAPI +PciHotPlugInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + mPciHotPlugInit.GetRootHpcList = GetRootHpcList; + mPciHotPlugInit.InitializeRootHpc = InitializeRootHpc; + mPciHotPlugInit.GetResourcePadding = GetResourcePadding; + return gBS->InstallMultipleProtocolInterfaces ( + &ImageHandle, + &gEfiPciHotPlugInitProtocolGuid, + &mPciHotPlugInit, + NULL + ); +} -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101309): https://edk2.groups.io/g/devel/message/101309 Mute This Topic: https://groups.io/mt/97667943/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=- Adds SetCacheMtrrLib library for AMD processor based boards. This library sets MTRR value or various memory ranges. Signed-off-by: Abdul Lateef Attar <abdattar@amd.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> --- Platform/AMD/BoardPkg/BoardPkg.dsc | 10 ++ .../SetCacheMtrrLib/SetCacheMtrrLib.inf | 37 +++++ .../Library/SetCacheMtrrLib/SetCacheMtrrLib.c | 132 ++++++++++++++++++ 3 files changed, 179 insertions(+) create mode 100644 Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf create mode 100644 Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c diff --git a/Platform/AMD/BoardPkg/BoardPkg.dsc b/Platform/AMD/BoardPkg/BoardPkg.dsc index XXXXXXX..XXXXXXX 100644 --- a/Platform/AMD/BoardPkg/BoardPkg.dsc +++ b/Platform/AMD/BoardPkg/BoardPkg.dsc @@ -XXX,XX +XXX,XX @@ [Defines] [Packages] BoardPkg/BoardPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses.common.PEIM] + SetCacheMtrrLib|BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf + +[Components.IA32] + BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf + diff --git a/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf b/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf @@ -XXX,XX +XXX,XX @@ +## @file +# Component information file for Platform SetCacheMtrr Library. +# This library implementation is for AMD processor based platforms. +# +# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 1.29 + BASE_NAME = PeiSetCacheMtrrLib + FILE_GUID = 1E8468E0-5EB4-4088-9B52-BFDC6E4DAE87 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + LIBRARY_CLASS = SetCacheMtrrLib + +[LibraryClasses] + BaseLib + DebugLib + MtrrLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[Sources] + SetCacheMtrrLib.c + +[Guids] + +[Pcd] + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize + diff --git a/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c b/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c @@ -XXX,XX +XXX,XX @@ +/** @file + +SetCacheMtrr library functions. +This library implementation is for AMD processor based platforms. + +Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR> + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <Uefi.h> +#include <PiPei.h> +#include <Library/DebugLib.h> +#include <Library/MtrrLib.h> + +/** + This function sets the cache MTRR values for PEI phase. +**/ +VOID +EFIAPI +SetCacheMtrr ( + VOID + ) +{ + EFI_STATUS Status; + + Status = MtrrSetMemoryAttribute ( + 0, + 0xA0000, + CacheWriteBack + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "Error(%r) in setting CacheWriteBack for 0-0x9FFFF\n", + Status + )); + } + + Status = MtrrSetMemoryAttribute ( + 0xA0000, + 0x20000, + CacheUncacheable + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "Error(%r) in setting CacheUncacheable for 0xA0000-0xBFFFF\n", + Status + )); + } + + Status = MtrrSetMemoryAttribute ( + 0xC0000, + 0x40000, + CacheWriteProtected + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "Error(%r) in setting CacheWriteProtected for 0xC0000-0xFFFFF\n", + Status + )); + } + + Status = MtrrSetMemoryAttribute ( + 0x100000, + 0xAFF00000, + CacheWriteBack + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "Error(%r) in setting CacheWriteBack for 0x100000-0xAFFFFFFF\n", + Status + )); + } + + Status = MtrrSetMemoryAttribute ( + PcdGet32 (PcdFlashAreaBaseAddress), + PcdGet32 (PcdFlashAreaSize), + CacheWriteProtected + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "Error(%r) in setting CacheWriteProtected for 0x%X-0x%X\n", + Status, + PcdGet32 (PcdFlashAreaBaseAddress), + PcdGet32 (PcdFlashAreaBaseAddress) + PcdGet32 (PcdFlashAreaSize) + )); + } + + MtrrDebugPrintAllMtrrs (); + return; +} + +/** + Update MTRR setting in EndOfPei phase. + This function will set the MTRR value as CacheUncacheable + for Flash address. + + @retval EFI_SUCCESS The function completes successfully. + @retval Others Some error occurs. +**/ +EFI_STATUS +EFIAPI +SetCacheMtrrAfterEndOfPei ( + VOID + ) +{ + EFI_STATUS Status; + + Status = MtrrSetMemoryAttribute ( + PcdGet32 (PcdFlashAreaBaseAddress), + PcdGet32 (PcdFlashAreaSize), + CacheUncacheable + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "Error(%r) in setting CacheUncacheable for 0x%X-0x%X\n", + Status, + PcdGet32 (PcdFlashAreaBaseAddress), + PcdGet32 (PcdFlashAreaBaseAddress) + PcdGet32 (PcdFlashAreaSize) + )); + } + + MtrrDebugPrintAllMtrrs (); + return EFI_SUCCESS; +} -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101311): https://edk2.groups.io/g/devel/message/101311 Mute This Topic: https://groups.io/mt/97667945/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=- From: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Adds maintainers for AMD/BoardPkg and AMD/PlatformPkg. Signed-off-by: Abdul Lateef Attar <abdattar@amd.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> --- Maintainers.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Maintainers.txt b/Maintainers.txt index XXXXXXX..XXXXXXX 100644 --- a/Maintainers.txt +++ b/Maintainers.txt @@ -XXX,XX +XXX,XX @@ F: Silicon/AMD/Styx/ M: Ard Biesheuvel <ardb+tianocore@kernel.org> M: Leif Lindholm <quic_llindhol@quicinc.com> +AMD Platform +F: Platform/AMD/BoardPkg +F: Platform/AMD/PlatformPkg +M: Abner Chang <abner.chang@amd.com> +M: Abdul Lateef Attar <abdattar@amd.com> + Ampere Computing F: Platform/Ampere F: Silicon/Ampere -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101312): https://edk2.groups.io/g/devel/message/101312 Mute This Topic: https://groups.io/mt/97667946/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-