[edk2-devel] [PATCH] MdeModulePkg/BaseSerialPortLib16550: Fix Serial Port Ready

Ashish Singhal posted 1 patch 4 years, 2 months ago
Failed in applying to current master (apply log)
.../Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c     | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
[edk2-devel] [PATCH] MdeModulePkg/BaseSerialPortLib16550: Fix Serial Port Ready
Posted by Ashish Singhal 4 years, 2 months ago
Before writing data to FIFO, wait for the serial port to be ready,
to make sure both the transmit FIFO and shift register empty. Code
comment was saying the right thing but code was missing a check.

Signed-off-by: Ashish Singhal <ashishsingha@nvidia.com>
---
 .../Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c     | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c b/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
index bbae379887..9cb50dd80d 100644
--- a/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
+++ b/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
@@ -646,7 +646,7 @@ SerialPortWrite (
     // Wait for the serial port to be ready, to make sure both the transmit FIFO
     // and shift register empty.
     //
-    while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & B_UART_LSR_TEMT) == 0);
+    while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT | B_UART_LSR_TXRDY));
 
     //
     // Fill then entire Tx FIFO
-- 
2.17.1


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Re: [edk2-devel] [PATCH] MdeModulePkg/BaseSerialPortLib16550: Fix Serial Port Ready
Posted by Gao, Zhichao 4 years, 2 months ago
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>

Thanks,
Zhichao

> -----Original Message-----
> From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Ashish
> Singhal
> Sent: Tuesday, January 28, 2020 1:53 AM
> To: devel@edk2.groups.io; Wang, Jian J <jian.j.wang@intel.com>; Wu, Hao A
> <hao.a.wu@intel.com>; Gao, Zhichao <zhichao.gao@intel.com>; Ni, Ray
> <ray.ni@intel.com>
> Cc: Ashish Singhal <ashishsingha@nvidia.com>
> Subject: [edk2-devel] [PATCH] MdeModulePkg/BaseSerialPortLib16550: Fix
> Serial Port Ready
> 
> Before writing data to FIFO, wait for the serial port to be ready, to make sure
> both the transmit FIFO and shift register empty. Code comment was saying the
> right thing but code was missing a check.
> 
> Signed-off-by: Ashish Singhal <ashishsingha@nvidia.com>
> ---
>  .../Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c     | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git
> a/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
> b/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
> index bbae379887..9cb50dd80d 100644
> --- a/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
> +++ b/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550
> +++ .c
> @@ -646,7 +646,7 @@ SerialPortWrite (
>      // Wait for the serial port to be ready, to make sure both the transmit FIFO
>      // and shift register empty.
>      //
> -    while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) &
> B_UART_LSR_TEMT) == 0);
> +    while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) &
> + (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT |
> + B_UART_LSR_TXRDY));
> 
>      //
>      // Fill then entire Tx FIFO
> --
> 2.17.1
> 
> 
> 


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