From nobody Sun May 5 02:12:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+53487+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+53487+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=nvidia.com Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1580147570144847.2509533399747; Mon, 27 Jan 2020 09:52:50 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id PTFNYY1788612xMTESoOueOY; Mon, 27 Jan 2020 09:52:49 -0800 X-Received: from hqnvemgate25.nvidia.com (hqnvemgate25.nvidia.com [216.228.121.64]) by mx.groups.io with SMTP id smtpd.web10.12793.1580147568626259916 for ; Mon, 27 Jan 2020 09:52:48 -0800 X-Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 27 Jan 2020 09:52:29 -0800 X-Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 27 Jan 2020 09:52:48 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 27 Jan 2020 09:52:48 -0800 X-Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 27 Jan 2020 17:52:48 +0000 X-Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 27 Jan 2020 17:52:47 +0000 X-Received: from ashishsingha-lnx.nvidia.com (Not Verified[10.28.48.147]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Mon, 27 Jan 2020 09:52:47 -0800 From: "Ashish Singhal" To: , , , , CC: Ashish Singhal Subject: [edk2-devel] [PATCH] MdeModulePkg/BaseSerialPortLib16550: Fix Serial Port Ready Date: Mon, 27 Jan 2020 10:52:45 -0700 Message-ID: <5d9ffe00de052a95ac04319951d7466644cf78c1.1580147315.git.ashishsingha@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ashishsingha@nvidia.com X-Gm-Message-State: XO3IH4tJImtFp7Slt4fnkPRrx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1580147569; bh=2l2dScuyNtC5qc5GGKvAdXX+V4/YR1Urlyk7vNSq/Uo=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=t3F3cRsCe5p4I2oBZ1FxXrqwoDHj0nNXRc6W6PI3Nec8gMC+tBDe4gBCBHkDsS9j5ZM 5wBn/03T98IC/6d/LO2VYuYEwReaNSMtNS3nwI4DPgdBAa8aru29puYK/kKhqg8lXLK9+ GKkaZhi5fSVAm8hWk9c1VnXWG26pKbzBhAU= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Before writing data to FIFO, wait for the serial port to be ready, to make sure both the transmit FIFO and shift register empty. Code comment was saying the right thing but code was missing a check. Signed-off-by: Ashish Singhal Reviewed-by: Zhichao Gao --- .../Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib1= 6550.c b/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550= .c index bbae379887..9cb50dd80d 100644 --- a/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c +++ b/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c @@ -646,7 +646,7 @@ SerialPortWrite ( // Wait for the serial port to be ready, to make sure both the transmi= t FIFO // and shift register empty. // - while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & B_UA= RT_LSR_TEMT) =3D=3D 0); + while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & (B_U= ART_LSR_TEMT | B_UART_LSR_TXRDY)) !=3D (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)= ); =20 // // Fill then entire Tx FIFO --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#53487): https://edk2.groups.io/g/devel/message/53487 Mute This Topic: https://groups.io/mt/70161119/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-