ArmPlatformPkg/ArmPlatformPkg.dec | 2 ++ ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c | 4 ++++ ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf | 1 + 3 files changed, 7 insertions(+)
From: Irene Park <ipark@nvidia.com>
PL011UartLib determines its FIFO depth based on the PID2 value but
the register PID2 is not mandatory in the SBSA spec.
This change adds a new 32bit PCD reference to define a FIFO depth and
make PL011UartLib available for the custom UART which is compliant
to the SBSA spec but doesn't support the optional register of PID2.
* Available values for PL011UartFifoDepth: 0, 16, 32
Note that a FIFO depth will be determined based on PID2 when the PCD
reference is set to 0.
Signed-off-by: Irene Park <ipark@nvidia.com>
---
ArmPlatformPkg/ArmPlatformPkg.dec | 2 ++
ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c | 4 ++++
ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf | 1 +
3 files changed, 7 insertions(+)
diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatformPkg.dec
index 696d636..b4b950f 100644
--- a/ArmPlatformPkg/ArmPlatformPkg.dec
+++ b/ArmPlatformPkg/ArmPlatformPkg.dec
@@ -72,6 +72,8 @@
gArmPlatformTokenSpaceGuid.PL011UartFractional|0|UINT32|0x0000002D
gArmPlatformTokenSpaceGuid.PL011UartInterrupt|0x00000000|UINT32|0x0000002F
gArmPlatformTokenSpaceGuid.PL011UartRegOffsetVariant|0|UINT8|0x0000003E
+ ## FIFO Depth in 0/16/32 (0 to determine FIFO depth based on PID2)
+ gArmPlatformTokenSpaceGuid.PL011UartFifoDepth|0|UINT32|0x0000003F
## PL011 Serial Debug UART
gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x00000000|UINT64|0x00000030
diff --git a/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c b/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c
index 801990d..1aa6830 100644
--- a/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c
+++ b/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c
@@ -79,9 +79,13 @@ PL011UartInitializePort (
UINT32 Fractional;
UINT32 HardwareFifoDepth;
+ HardwareFifoDepth = FixedPcdGet8 (PL011UartFifoDepth);
+#if FixedPcdGet8 (PL011UartFifoDepth) == 0
HardwareFifoDepth = (PL011_UARTPID2_VER (MmioRead32 (UartBase + UARTPID2)) \
> PL011_VER_R1P4) \
? 32 : 16 ;
+#endif
+
// The PL011 supports a buffer of 1, 16 or 32 chars. Therefore we can accept
// 1 char buffer as the minimum FIFO size. Because everything can be rounded
// down, there is no maximum FIFO size.
diff --git a/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf b/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf
index d99e89f..3e5efc7 100644
--- a/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf
+++ b/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf
@@ -35,3 +35,4 @@
gArmPlatformTokenSpaceGuid.PL011UartInteger
gArmPlatformTokenSpaceGuid.PL011UartFractional
gArmPlatformTokenSpaceGuid.PL011UartRegOffsetVariant
+ gArmPlatformTokenSpaceGuid.PL011UartFifoDepth
--
2.7.4
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Hello Ard Biesheuvel, Would you please review this change? Thank you, Irene -----Original Message----- From: Irene Park <ipark@nvidia.com> Sent: Friday, June 5, 2020 11:23 PM To: devel@edk2.groups.io Cc: Irene Park <ipark@nvidia.com> Subject: [PATCH] ArmPlatformPkg/PL011UartLib: Add PCD for FIFO depth From: Irene Park <ipark@nvidia.com> PL011UartLib determines its FIFO depth based on the PID2 value but the register PID2 is not mandatory in the SBSA spec. This change adds a new 32bit PCD reference to define a FIFO depth and make PL011UartLib available for the custom UART which is compliant to the SBSA spec but doesn't support the optional register of PID2. * Available values for PL011UartFifoDepth: 0, 16, 32 Note that a FIFO depth will be determined based on PID2 when the PCD reference is set to 0. Signed-off-by: Irene Park <ipark@nvidia.com> --- ArmPlatformPkg/ArmPlatformPkg.dec | 2 ++ ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c | 4 ++++ ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf | 1 + 3 files changed, 7 insertions(+) diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatformPkg.dec index 696d636..b4b950f 100644 --- a/ArmPlatformPkg/ArmPlatformPkg.dec +++ b/ArmPlatformPkg/ArmPlatformPkg.dec @@ -72,6 +72,8 @@ gArmPlatformTokenSpaceGuid.PL011UartFractional|0|UINT32|0x0000002D gArmPlatformTokenSpaceGuid.PL011UartInterrupt|0x00000000|UINT32|0x0000002F gArmPlatformTokenSpaceGuid.PL011UartRegOffsetVariant|0|UINT8|0x0000003E + ## FIFO Depth in 0/16/32 (0 to determine FIFO depth based on PID2) + gArmPlatformTokenSpaceGuid.PL011UartFifoDepth|0|UINT32|0x0000003F ## PL011 Serial Debug UART gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x00000000|UINT64|0x00000030 diff --git a/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c b/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c index 801990d..1aa6830 100644 --- a/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c +++ b/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c @@ -79,9 +79,13 @@ PL011UartInitializePort ( UINT32 Fractional; UINT32 HardwareFifoDepth; + HardwareFifoDepth = FixedPcdGet8 (PL011UartFifoDepth); #if +FixedPcdGet8 (PL011UartFifoDepth) == 0 HardwareFifoDepth = (PL011_UARTPID2_VER (MmioRead32 (UartBase + UARTPID2)) \ > PL011_VER_R1P4) \ ? 32 : 16 ; +#endif + // The PL011 supports a buffer of 1, 16 or 32 chars. Therefore we can accept // 1 char buffer as the minimum FIFO size. Because everything can be rounded // down, there is no maximum FIFO size. diff --git a/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf b/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf index d99e89f..3e5efc7 100644 --- a/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf +++ b/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf @@ -35,3 +35,4 @@ gArmPlatformTokenSpaceGuid.PL011UartInteger gArmPlatformTokenSpaceGuid.PL011UartFractional gArmPlatformTokenSpaceGuid.PL011UartRegOffsetVariant + gArmPlatformTokenSpaceGuid.PL011UartFifoDepth -- 2.7.4 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#60827): https://edk2.groups.io/g/devel/message/60827 Mute This Topic: https://groups.io/mt/74707614/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
Hello Ard Biesheuvel, Would you please review this change? Thank you, Irene -----Original Message----- From: Irene Park <ipark@nvidia.com> Sent: Friday, June 5, 2020 11:23 PM To: devel@edk2.groups.io Cc: Irene Park <ipark@nvidia.com> Subject: [PATCH] ArmPlatformPkg/PL011UartLib: Add PCD for FIFO depth From: Irene Park <ipark@nvidia.com> PL011UartLib determines its FIFO depth based on the PID2 value but the register PID2 is not mandatory in the SBSA spec. This change adds a new 32bit PCD reference to define a FIFO depth and make PL011UartLib available for the custom UART which is compliant to the SBSA spec but doesn't support the optional register of PID2. * Available values for PL011UartFifoDepth: 0, 16, 32 Note that a FIFO depth will be determined based on PID2 when the PCD reference is set to 0. Signed-off-by: Irene Park <ipark@nvidia.com> --- ArmPlatformPkg/ArmPlatformPkg.dec | 2 ++ ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c | 4 ++++ ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf | 1 + 3 files changed, 7 insertions(+) diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatformPkg.dec index 696d636..b4b950f 100644 --- a/ArmPlatformPkg/ArmPlatformPkg.dec +++ b/ArmPlatformPkg/ArmPlatformPkg.dec @@ -72,6 +72,8 @@ gArmPlatformTokenSpaceGuid.PL011UartFractional|0|UINT32|0x0000002D gArmPlatformTokenSpaceGuid.PL011UartInterrupt|0x00000000|UINT32|0x0000002F gArmPlatformTokenSpaceGuid.PL011UartRegOffsetVariant|0|UINT8|0x0000003E + ## FIFO Depth in 0/16/32 (0 to determine FIFO depth based on PID2) + gArmPlatformTokenSpaceGuid.PL011UartFifoDepth|0|UINT32|0x0000003F ## PL011 Serial Debug UART gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x00000000|UINT64|0x00000030 diff --git a/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c b/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c index 801990d..1aa6830 100644 --- a/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c +++ b/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c @@ -79,9 +79,13 @@ PL011UartInitializePort ( UINT32 Fractional; UINT32 HardwareFifoDepth; + HardwareFifoDepth = FixedPcdGet8 (PL011UartFifoDepth); #if +FixedPcdGet8 (PL011UartFifoDepth) == 0 HardwareFifoDepth = (PL011_UARTPID2_VER (MmioRead32 (UartBase + UARTPID2)) \ > PL011_VER_R1P4) \ ? 32 : 16 ; +#endif + // The PL011 supports a buffer of 1, 16 or 32 chars. Therefore we can accept // 1 char buffer as the minimum FIFO size. Because everything can be rounded // down, there is no maximum FIFO size. diff --git a/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf b/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf index d99e89f..3e5efc7 100644 --- a/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf +++ b/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf @@ -35,3 +35,4 @@ gArmPlatformTokenSpaceGuid.PL011UartInteger gArmPlatformTokenSpaceGuid.PL011UartFractional gArmPlatformTokenSpaceGuid.PL011UartRegOffsetVariant + gArmPlatformTokenSpaceGuid.PL011UartFifoDepth -- 2.7.4 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#60850): https://edk2.groups.io/g/devel/message/60850 Mute This Topic: https://groups.io/mt/74707614/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
On 6/6/20 5:23 AM, Irene Park via groups.io wrote: > From: Irene Park <ipark@nvidia.com> > > PL011UartLib determines its FIFO depth based on the PID2 value but > the register PID2 is not mandatory in the SBSA spec. > This change adds a new 32bit PCD reference to define a FIFO depth and > make PL011UartLib available for the custom UART which is compliant > to the SBSA spec but doesn't support the optional register of PID2. > What does 'doesn't support' mean in this case? > * Available values for PL011UartFifoDepth: 0, 16, 32 > > Note that a FIFO depth will be determined based on PID2 when the PCD > reference is set to 0. > > Signed-off-by: Irene Park <ipark@nvidia.com> > --- > ArmPlatformPkg/ArmPlatformPkg.dec | 2 ++ > ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c | 4 ++++ > ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf | 1 + > 3 files changed, 7 insertions(+) > > diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatformPkg.dec > index 696d636..b4b950f 100644 > --- a/ArmPlatformPkg/ArmPlatformPkg.dec > +++ b/ArmPlatformPkg/ArmPlatformPkg.dec > @@ -72,6 +72,8 @@ > gArmPlatformTokenSpaceGuid.PL011UartFractional|0|UINT32|0x0000002D > gArmPlatformTokenSpaceGuid.PL011UartInterrupt|0x00000000|UINT32|0x0000002F > gArmPlatformTokenSpaceGuid.PL011UartRegOffsetVariant|0|UINT8|0x0000003E > + ## FIFO Depth in 0/16/32 (0 to determine FIFO depth based on PID2) > + gArmPlatformTokenSpaceGuid.PL011UartFifoDepth|0|UINT32|0x0000003F > > ## PL011 Serial Debug UART > gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x00000000|UINT64|0x00000030 > diff --git a/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c b/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c > index 801990d..1aa6830 100644 > --- a/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c > +++ b/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c > @@ -79,9 +79,13 @@ PL011UartInitializePort ( > UINT32 Fractional; > UINT32 HardwareFifoDepth; > > + HardwareFifoDepth = FixedPcdGet8 (PL011UartFifoDepth); > +#if FixedPcdGet8 (PL011UartFifoDepth) == 0 > HardwareFifoDepth = (PL011_UARTPID2_VER (MmioRead32 (UartBase + UARTPID2)) \ > > PL011_VER_R1P4) \ > ? 32 : 16 ; > +#endif > + > // The PL011 supports a buffer of 1, 16 or 32 chars. Therefore we can accept > // 1 char buffer as the minimum FIFO size. Because everything can be rounded > // down, there is no maximum FIFO size. > diff --git a/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf b/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf > index d99e89f..3e5efc7 100644 > --- a/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf > +++ b/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf > @@ -35,3 +35,4 @@ > gArmPlatformTokenSpaceGuid.PL011UartInteger > gArmPlatformTokenSpaceGuid.PL011UartFractional > gArmPlatformTokenSpaceGuid.PL011UartRegOffsetVariant > + gArmPlatformTokenSpaceGuid.PL011UartFifoDepth > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#60855): https://edk2.groups.io/g/devel/message/60855 Mute This Topic: https://groups.io/mt/74707614/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
Hi Ard, I feel bad that I confused you. I'll update the commit message later. SBSA spec doesn't "mandate" that the optional registers such as PID2 are present in a UART compliant to PL011. Therefore this register access to PID2 will generate a fault onto SOC when its UART doesn't provide such registers. PID2 is used to determine the FIFO depth in the library so I'd like to propose a new PCD to define a FIFO depth. Thank you, Irene -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#60870): https://edk2.groups.io/g/devel/message/60870 Mute This Topic: https://groups.io/mt/74707614/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
On 6/8/20 4:47 PM, Irene Park via Groups.Io wrote: > Hi Ard, > I feel bad that I confused you. I'll update the commit message later. > SBSA spec doesn't "mandate" that the optional registers such as PID2 are > present in a UART compliant to PL011. > Therefore this register access to PID2 will generate a fault onto SOC > when its UART doesn't provide such registers. > PID2 is used to determine the FIFO depth in the library so I'd like to > propose a new PCD to define a FIFO depth. I'd prefer it if we could change the existing code so that the register is never checked if gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth is set to a value > 0 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#60883): https://edk2.groups.io/g/devel/message/60883 Mute This Topic: https://groups.io/mt/74707614/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
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