From nobody Mon May 20 00:56:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+60826+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+60826+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=nvidia.com ARC-Seal: i=1; a=rsa-sha256; t=1591413811; cv=none; d=zohomail.com; s=zohoarc; b=LtrSh0UC4nrEAGMJ3yCGc6Plb+Hrbt6k56HFnHheI9gdpZ1JVibsbYFMlKx79YqN/IAPszSNnPz9iu3jGlI//CwuQAL+/mmijHLL2YA/zkLjNqNduxNhoKc9rcxygulIhSqd5jM8ZGE9JcAzl5aqeNggNO5zbB72KEls48D6E7E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1591413811; h=Content-Type:Cc:Date:From:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; bh=FWGuyjXLws0/sa6h0SUOGE9vWDJsLy562V1b9hgo8TY=; b=Uwd2bBYy4KIn+gq3DOmnCVqd2O/zy0++MYylyAYJ1Mb3S3v/HwAFUqYMQRk7KZZ4yuym9dRLpkAxu1DypQruu+SnKRaQgUX7i1u623us1qRSmMlx9xk4rVyF0IHSbbCXuUnMORo5yBizeWkwqL6/n5lLLs6F8pNQtVQoaA4UaIM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+60826+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1591413811311231.740893990539; Fri, 5 Jun 2020 20:23:31 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id OaVRYY1788612xaWRLZ7xKjM; Fri, 05 Jun 2020 20:23:30 -0700 X-Received: from hqnvemgate25.nvidia.com (hqnvemgate25.nvidia.com [216.228.121.64]) by mx.groups.io with SMTP id smtpd.web12.3772.1591413809374039597 for ; Fri, 05 Jun 2020 20:23:29 -0700 X-Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 05 Jun 2020 20:22:00 -0700 X-Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 05 Jun 2020 20:23:28 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 05 Jun 2020 20:23:28 -0700 X-Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sat, 6 Jun 2020 03:23:28 +0000 X-Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sat, 6 Jun 2020 03:23:28 +0000 X-Received: from ipark-ubuntu.nvidia.com (Not Verified[10.28.100.106]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Fri, 05 Jun 2020 20:23:28 -0700 From: "Irene Park" To: CC: Irene Park Subject: [edk2-devel] [PATCH] ArmPlatformPkg/PL011UartLib: Add PCD for FIFO depth Date: Fri, 5 Jun 2020 23:23:24 -0400 Message-ID: <5a94d7db2db04a22baa79c65d42feeea30bf81b8.1591413682.git.ipark@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ipark@nvidia.com X-Gm-Message-State: oiTkXM4o2ZA37v5sT9D73ytIx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1591413810; bh=rTjzEsHYupRKLt3esLMjV8ehHsf4dki3PPDX4jeZwnk=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=jPUTaLtMGhLsWWJgnf66/i2JCY1RkaxsDuQxoswyVhlcLjYY1WW9vlCRyewjmwdvXOB 4PLoVmuG0L93co956t83PhGZTA8VNT5Ui4PXBKkCMAcxtgpWb0KUchDd9V/r9Lil8mcOm S0e5cin07H5FwTSlDW1mfvGNUna0LYk+0Zo= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Irene Park PL011UartLib determines its FIFO depth based on the PID2 value but the register PID2 is not mandatory in the SBSA spec. This change adds a new 32bit PCD reference to define a FIFO depth and make PL011UartLib available for the custom UART which is compliant to the SBSA spec but doesn't support the optional register of PID2. * Available values for PL011UartFifoDepth: 0, 16, 32 Note that a FIFO depth will be determined based on PID2 when the PCD reference is set to 0. Signed-off-by: Irene Park --- ArmPlatformPkg/ArmPlatformPkg.dec | 2 ++ ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c | 4 ++++ ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf | 1 + 3 files changed, 7 insertions(+) diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatform= Pkg.dec index 696d636..b4b950f 100644 --- a/ArmPlatformPkg/ArmPlatformPkg.dec +++ b/ArmPlatformPkg/ArmPlatformPkg.dec @@ -72,6 +72,8 @@ gArmPlatformTokenSpaceGuid.PL011UartFractional|0|UINT32|0x0000002D gArmPlatformTokenSpaceGuid.PL011UartInterrupt|0x00000000|UINT32|0x000000= 2F gArmPlatformTokenSpaceGuid.PL011UartRegOffsetVariant|0|UINT8|0x0000003E + ## FIFO Depth in 0/16/32 (0 to determine FIFO depth based on PID2) + gArmPlatformTokenSpaceGuid.PL011UartFifoDepth|0|UINT32|0x0000003F =20 ## PL011 Serial Debug UART gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x00000000|UINT64|0x= 00000030 diff --git a/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c b/ArmPlatfo= rmPkg/Library/PL011UartLib/PL011UartLib.c index 801990d..1aa6830 100644 --- a/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c +++ b/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c @@ -79,9 +79,13 @@ PL011UartInitializePort ( UINT32 Fractional; UINT32 HardwareFifoDepth; =20 + HardwareFifoDepth =3D FixedPcdGet8 (PL011UartFifoDepth); +#if FixedPcdGet8 (PL011UartFifoDepth) =3D=3D 0 HardwareFifoDepth =3D (PL011_UARTPID2_VER (MmioRead32 (UartBase + UARTPI= D2)) \ > PL011_VER_R1P4) \ ? 32 : 16 ; +#endif + // The PL011 supports a buffer of 1, 16 or 32 chars. Therefore we can ac= cept // 1 char buffer as the minimum FIFO size. Because everything can be rou= nded // down, there is no maximum FIFO size. diff --git a/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf b/ArmPlat= formPkg/Library/PL011UartLib/PL011UartLib.inf index d99e89f..3e5efc7 100644 --- a/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf +++ b/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf @@ -35,3 +35,4 @@ gArmPlatformTokenSpaceGuid.PL011UartInteger gArmPlatformTokenSpaceGuid.PL011UartFractional gArmPlatformTokenSpaceGuid.PL011UartRegOffsetVariant + gArmPlatformTokenSpaceGuid.PL011UartFifoDepth --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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