From: Narinder Dhillon <ndhillon@marvell.com>
This patch adds helper library to initialize Odyssey SoC.
Signed-off-by: Narinder Dhillon <ndhillon@marvell.com>
---
.../OdysseyLib/AArch64/ArmPlatformHelper.S | 97 ++++++++++++
.../Library/OdysseyLib/OdysseyLib.c | 79 ++++++++++
.../Library/OdysseyLib/OdysseyLib.inf | 60 ++++++++
.../Library/OdysseyLib/OdysseyLibMem.c | 142 ++++++++++++++++++
4 files changed, 378 insertions(+)
create mode 100644 Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/AArch64/ArmPlatformHelper.S
create mode 100644 Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/OdysseyLib.c
create mode 100644 Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/OdysseyLib.inf
create mode 100644 Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/OdysseyLibMem.c
diff --git a/Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/AArch64/ArmPlatformHelper.S b/Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/AArch64/ArmPlatformHelper.S
new file mode 100644
index 0000000000..e816e6bd5a
--- /dev/null
+++ b/Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/AArch64/ArmPlatformHelper.S
@@ -0,0 +1,97 @@
+/** @file
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+* https://spdx.org/licenses
+*
+* Copyright (C) 2023 Marvell
+*
+* Source file for Marvell ARM Platform library
+* Based on ArmPlatformPkg/Library/ArmPlatformLibNull
+**/
+
+#include <AsmMacroIoLibV8.h>
+#include <Base.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+#include <AutoGen.h>
+#include <IndustryStandard/SmcLib.h>
+
+/* x1 - node number
+ */
+
+.text
+.align 2
+
+GCC_ASM_EXPORT(ArmPlatformPeiBootAction)
+GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)
+GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)
+GCC_ASM_EXPORT(ArmPlatformGetCorePosition)
+GCC_ASM_EXPORT(ArmGetCpuCountPerCluster)
+
+GCC_ASM_IMPORT(mDeviceTreeBaseAddress)
+GCC_ASM_IMPORT(mSystemMemoryEnd)
+
+ASM_FUNC(ArmPlatformPeiBootAction)
+ // Save the boot parameter to a global variable
+ adr x10, mDeviceTreeBaseAddress
+ str x1, [x10]
+
+ adr x1, PrimaryCoreMpid
+ str w0, [x1]
+ ldr x0, =MV_SMC_ID_DRAM_SIZE
+ mov x1, xzr
+ smc #0
+ sub x0, x0, #1 // Last valid address
+ // if mSystemMemoryEnd wasn't gethered from SMC call, get it from PCDs
+ cmp x0, #0xffffffffffffffff
+ bne done
+ // if mSystemMemoryEnd wasn't gethered from SMC call, get it from PCDs
+ MOV64 (x0, FixedPcdGet64(PcdSystemMemoryBase) + FixedPcdGet64(PcdSystemMemorySize) - 1)
+done:
+ adr x1, mSystemMemoryEnd
+ str x0, [x1] // Set mSystemMemoryEnd
+
+ ret
+
+
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+// VOID
+// );
+ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
+ MOV32(w0, FixedPcdGet32(PcdArmPrimaryCore))
+ ret
+
+//UINTN
+//ArmPlatformIsPrimaryCore (
+// IN UINTN MpId
+// );
+ASM_FUNC(ArmPlatformIsPrimaryCore)
+ MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCoreMask))
+ and x0, x0, x1
+ MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCore))
+ cmp w0, w1
+ mov x0, #1
+ mov x1, #0
+ csel x0, x0, x1, eq
+ ret
+
+//UINTN
+//ArmPlatformGetCorePosition (
+// IN UINTN MpId
+// );
+ASM_FUNC(ArmPlatformGetCorePosition)
+/*
+ Affinity Level 0: single thread 0
+ Affinity Level 1: clustering 0(
+ Affinity Level 2: number of clusters up to 64 (CN10K)/ 80 (Odyssey)/ 16 (Iliad)
+ Affinity Level 3: number of chip 0
+ LinearId = Aff2
+*/
+ and x0, x0, #ARM_CORE_AFF2
+ lsr x0, x0, #16
+ ret
+
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
+
+PrimaryCoreMpid: .word 0x0
diff --git a/Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/OdysseyLib.c b/Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/OdysseyLib.c
new file mode 100644
index 0000000000..ed48a00950
--- /dev/null
+++ b/Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/OdysseyLib.c
@@ -0,0 +1,79 @@
+/** @file
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+* https://spdx.org/licenses
+*
+* Copyright (C) 2022 Marvell
+*
+* Source file for Marvell ARM Platform library
+* Based on ArmPlatformPkg/Library/ArmPlatformLibNull
+**/
+
+#include <Uefi.h>
+#include <Pi/PiBootMode.h> // EFI_BOOT_MODE
+#include <Pi/PiPeiCis.h> // EFI_PEI_PPI_DESCRIPTOR
+#include <Library/DebugLib.h> // ASSERT
+#include <Library/ArmPlatformLib.h> // ArmPlatformIsPrimaryCore
+#include <Ppi/ArmMpCoreInfo.h> // ARM_MP_CORE_INFO_PPI
+
+/**
+ Return the current Boot Mode
+
+ This function returns the boot reason on the platform
+
+ @return Return the current Boot Mode of the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+ VOID
+ )
+{
+ return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+ Initialize controllers that must setup in the normal world
+
+ This function is called by the ArmPlatformPkg/PrePei or ArmPlatformPkg/Pei/PlatformPeim
+ in the PEI phase.
+
+**/
+RETURN_STATUS
+ArmPlatformInitialize (
+ IN UINTN MpId
+ )
+{
+ ASSERT(ArmPlatformIsPrimaryCore (MpId));
+
+ return RETURN_SUCCESS;
+}
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+ OUT UINTN *CoreCount,
+ OUT ARM_CORE_INFO **ArmCoreTable
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &gArmMpCoreInfoPpiGuid,
+ &mMpCoreInfoPpi
+ }
+};
+
+VOID
+ArmPlatformGetPlatformPpiList (
+ OUT UINTN *PpiListSize,
+ OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
+ )
+{
+ *PpiListSize = sizeof(gPlatformPpiTable);
+ *PpiList = gPlatformPpiTable;
+}
diff --git a/Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/OdysseyLib.inf b/Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/OdysseyLib.inf
new file mode 100644
index 0000000000..c47a19767b
--- /dev/null
+++ b/Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/OdysseyLib.inf
@@ -0,0 +1,60 @@
+#/** @file
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+# https://spdx.org/licenses
+#
+# Copyright (C) 2022 Marvell
+#
+# Marvell ARM Platform library
+# Based on ArmPlatformPkg/Library/ArmPlatformLibNull
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = OdysseyLib
+ FILE_GUID = 7ea0f45b-0e06-4e45-8353-9c28b091a11c
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = OdysseyLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec # Include ArmPlatformLib.h
+ EmbeddedPkg/EmbeddedPkg.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
+
+[LibraryClasses]
+ ArmLib
+ HobLib
+ DebugLib
+ MemoryAllocationLib
+ SmcLib
+ FdtLib
+
+[Sources]
+ OdysseyLib.c
+ OdysseyLibMem.c
+
+[Sources.AARCH64]
+ AArch64/ArmPlatformHelper.S
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdFdBaseAddress
+ gArmTokenSpaceGuid.PcdFdSize
+ gArmTokenSpaceGuid.PcdSystemMemoryBase
+ gArmTokenSpaceGuid.PcdSystemMemorySize
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+ gArmTokenSpaceGuid.PcdArmPrimaryCore
+
+ gMarvellSiliconTokenSpaceGuid.PcdNodeDramBase
+ gMarvellSiliconTokenSpaceGuid.PcdIoBaseAddress
+ gMarvellSiliconTokenSpaceGuid.PcdNodeIoBaseAddress
+ gMarvellSiliconTokenSpaceGuid.PcdIoSize
+
+[Ppis]
+ gArmMpCoreInfoPpiGuid
+
+[Guids]
+ gFdtHobGuid
diff --git a/Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/OdysseyLibMem.c b/Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/OdysseyLibMem.c
new file mode 100644
index 0000000000..bfec57952a
--- /dev/null
+++ b/Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/OdysseyLibMem.c
@@ -0,0 +1,142 @@
+/** @file
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+* https://spdx.org/licenses
+*
+* Copyright (C) 2022 Marvell
+*
+* Source file for Marvell ARM Platform library
+* Based on ArmPlatformPkg/Library/ArmPlatformLibNull
+**/
+
+#include <Uefi.h> // Basic UEFI types
+#include <Library/DebugLib.h> // DEBUG
+#include <Pi/PiBootMode.h> // EFI_BOOT_MODE required by PiHob.h
+#include <Pi/PiHob.h> // EFI_RESOURCE_ATTRIBUTE_TYPE
+#include <Library/HobLib.h> // BuildResourceDescriptorHob
+#include <Library/PcdLib.h> // PcdGet64
+#include <Library/ArmLib.h> // ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
+#include <IndustryStandard/SmcLib.h> // SmcGetRamSize
+#include <Library/MemoryAllocationLib.h> // AllocatePages
+#include <libfdt.h> // fdt_totalsize //
+
+// Number of Virtual Memory Map Descriptors
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 129
+#define MAX_NODES 1
+
+// DDR attributes
+#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
+#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
+
+UINT64 mDeviceTreeBaseAddress = 0;
+
+/**
+ Return the Virtual Memory Map of your platform
+
+ This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
+
+ @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
+ Virtual Memory mapping. This array must be ended by a zero-filled
+ entry
+
+**/
+VOID
+ArmPlatformGetVirtualMemoryMap (
+ IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
+ )
+{
+ ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;
+ ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
+ UINT64 VirtualMemoryTableSize;
+ UINT64 MemoryBase;
+ UINT64 MemorySize;
+ UINTN Index = 0;
+ UINTN Node;
+ EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
+
+ ASSERT (VirtualMemoryMap != NULL);
+
+ VirtualMemoryTableSize = sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS;
+ VirtualMemoryTable = AllocatePages (EFI_SIZE_TO_PAGES (VirtualMemoryTableSize));
+
+ if (VirtualMemoryTable == NULL) {
+ return;
+ }
+
+ CacheAttributes = DDR_ATTRIBUTES_CACHED;
+
+ ResourceAttributes =
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED;
+
+
+ VirtualMemoryTable[Index].PhysicalBase = PcdGet64(PcdFdBaseAddress);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64(PcdFdBaseAddress);
+ VirtualMemoryTable[Index].Length = PcdGet32(PcdFdSize);
+ VirtualMemoryTable[Index].Attributes = CacheAttributes;
+ Index++;
+
+ BuildResourceDescriptorHob (EFI_RESOURCE_SYSTEM_MEMORY,
+ ResourceAttributes,
+ PcdGet64 (PcdFdBaseAddress),
+ PcdGet32 (PcdFdSize));
+
+ for (Node = 0; Node < MAX_NODES; Node++) {
+ MemoryBase = Node * FixedPcdGet64(PcdNodeDramBase);
+ MemorySize = SmcGetRamSize(Node);
+
+ MemoryBase += (Node == 0) ? PcdGet64(PcdSystemMemoryBase) : 0;
+ MemorySize -= (Node == 0) ? PcdGet64(PcdSystemMemoryBase) : 0;
+
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ ResourceAttributes,
+ MemoryBase,
+ MemorySize);
+
+ DEBUG ((DEBUG_LOAD | DEBUG_INFO, "Memory %lx @ %lx\n", MemorySize, MemoryBase));
+ VirtualMemoryTable[Index].PhysicalBase = MemoryBase;
+ VirtualMemoryTable[Index].VirtualBase = MemoryBase;
+ VirtualMemoryTable[Index].Length = MemorySize;
+ VirtualMemoryTable[Index].Attributes = CacheAttributes;
+
+ Index++;
+ }
+
+ for (Node = 0; Node < MAX_NODES; Node++) {
+ VirtualMemoryTable[Index].PhysicalBase = FixedPcdGet64(PcdIoBaseAddress) +
+ Node * FixedPcdGet64(PcdNodeIoBaseAddress);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64(PcdIoBaseAddress) +
+ Node * FixedPcdGet64(PcdNodeIoBaseAddress);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64(PcdIoSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ DEBUG ((DEBUG_LOAD | DEBUG_INFO,
+ "IO %lx @ %lx\n",
+ VirtualMemoryTable[Index].Length,
+ VirtualMemoryTable[Index].PhysicalBase));
+
+ Index++;
+ }
+
+ // End of Table
+ VirtualMemoryTable[Index].PhysicalBase = 0;
+ VirtualMemoryTable[Index].VirtualBase = 0;
+ VirtualMemoryTable[Index].Length = 0;
+ VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
+
+ *VirtualMemoryMap = VirtualMemoryTable;
+
+ // Build the FDT HOB
+ ASSERT(fdt_check_header ((VOID *)mDeviceTreeBaseAddress) == 0);
+ DEBUG((DEBUG_INFO, "FDT address: %lx, size: %d\n",
+ mDeviceTreeBaseAddress,
+ fdt_totalsize((VOID *)mDeviceTreeBaseAddress)));
+
+ BuildGuidDataHob (&gFdtHobGuid, &mDeviceTreeBaseAddress, sizeof(mDeviceTreeBaseAddress));
+}
--
2.34.1
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