From nobody Mon Sep 16 19:24:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+113972+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+113972+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=marvell.com ARC-Seal: i=1; a=rsa-sha256; t=1705540710; cv=none; d=zohomail.com; s=zohoarc; b=Ugg7ddv5iCr4Wpg8DptTx0NmxdWweZAaE6+fIsK3MaLUsFltrVUZTL1ZPM1V6HkwxezbLpI1tMb35hL2xkZlLP1Gf37QsvcCXu9y/oiuTsF/VT8VCiOq790VdKmD9mxqpJ/j6Jun2kjcz6dpNWwdkngxxtsylGTX4C3uXvxoiN4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705540710; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=YW5U+8tQ4VfUNb2TumE9ZtSSJVGDbQiir2/Xp8yL2jw=; b=kHN0wcTNSR7LNsQKsAvT03dBVtcbxgVVBeLE9BzUKSrnpOb/atR6N+tgdzZRYjnQoTvl9aBhQkwNj//XqkMWzIbZP6qj+qzSm66Tjv1aphbKfqldz8qs3HnXqCl+BY7SwhS1//EvCmFYEDkJ2Akt5CZHIGqh3/wwg2HxcUaFuHM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+113972+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1705540710709931.5520259406343; Wed, 17 Jan 2024 17:18:30 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=5/SHgoeryQ5P7sdM76NfmWhz3XYEfT1fxndAnqmv5X8=; c=relaxed/simple; d=groups.io; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding:Content-Type; s=20140610; t=1705540710; v=1; b=CY8lx5a7kqO2NAYb8L+HkxwrdiFBbQ8VTSNx2H+LGfg5atHEkekAchFJ5Itv1WYDtYqHA17Q zDnMufItF+hHcL0be2ni0i9M46ccXNwY54fjB5DIXWeOqiiBcdAcRuACFx0msTByLaYrtCE+RgO K7VbZ1xSSJblxAFrP9zAs99E= X-Received: by 127.0.0.2 with SMTP id hF3wYY1788612xV5wjNzg7An; Wed, 17 Jan 2024 17:18:30 -0800 X-Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.148.174]) by mx.groups.io with SMTP id smtpd.web10.926.1705540709507118852 for ; Wed, 17 Jan 2024 17:18:29 -0800 X-Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 40HHSY3c029567; Wed, 17 Jan 2024 17:18:29 -0800 X-Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3vpaskb4ru-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 17 Jan 2024 17:18:28 -0800 (PST) X-Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 17 Jan 2024 17:18:27 -0800 X-Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 17 Jan 2024 17:18:27 -0800 X-Received: from MRVL-5Lp9he46Ey.marvell.com (unknown [10.85.176.100]) by maili.marvell.com (Postfix) with ESMTP id 12E093F7081; Wed, 17 Jan 2024 17:18:27 -0800 (PST) From: "Narinder Dhillon" To: CC: , , , Narinder Dhillon Subject: [edk2-devel] [edk2-platforms PATCH v3 1/7] Silicon/Marvell: New Marvell Odyssey processor Date: Wed, 17 Jan 2024 17:18:11 -0800 Message-ID: <20240118011817.4348-2-ndhillon@marvell.com> In-Reply-To: <20240118011817.4348-1-ndhillon@marvell.com> References: <20240118011817.4348-1-ndhillon@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: -WwX9O7afffreQqqqgIoL7sDjxc-j7Fh X-Proofpoint-GUID: -WwX9O7afffreQqqqgIoL7sDjxc-j7Fh Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ndhillon@marvell.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: oms24M8taEAlSvoUL0xaW1jvx1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1705540712782100016 Content-Type: text/plain; charset="utf-8" From: Narinder Dhillon This patch adds helper library to initialize Odyssey SoC. Signed-off-by: Narinder Dhillon --- .../OdysseyLib/AArch64/ArmPlatformHelper.S | 97 ++++++++++++ .../Library/OdysseyLib/OdysseyLib.c | 79 ++++++++++ .../Library/OdysseyLib/OdysseyLib.inf | 60 ++++++++ .../Library/OdysseyLib/OdysseyLibMem.c | 142 ++++++++++++++++++ 4 files changed, 378 insertions(+) create mode 100644 Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/AArch64/A= rmPlatformHelper.S create mode 100644 Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/OdysseyLi= b.c create mode 100644 Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/OdysseyLi= b.inf create mode 100644 Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/OdysseyLi= bMem.c diff --git a/Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/AArch64/ArmPlatf= ormHelper.S b/Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/AArch64/ArmPlat= formHelper.S new file mode 100644 index 0000000000..e816e6bd5a --- /dev/null +++ b/Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/AArch64/ArmPlatformHelp= er.S @@ -0,0 +1,97 @@ +/** @file +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* https://spdx.org/licenses +* +* Copyright (C) 2023 Marvell +* +* Source file for Marvell ARM Platform library +* Based on ArmPlatformPkg/Library/ArmPlatformLibNull +**/ + +#include +#include +#include +#include +#include +#include + +/* x1 - node number + */ + +.text +.align 2 + +GCC_ASM_EXPORT(ArmPlatformPeiBootAction) +GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore) +GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId) +GCC_ASM_EXPORT(ArmPlatformGetCorePosition) +GCC_ASM_EXPORT(ArmGetCpuCountPerCluster) + +GCC_ASM_IMPORT(mDeviceTreeBaseAddress) +GCC_ASM_IMPORT(mSystemMemoryEnd) + +ASM_FUNC(ArmPlatformPeiBootAction) + // Save the boot parameter to a global variable + adr x10, mDeviceTreeBaseAddress + str x1, [x10] + + adr x1, PrimaryCoreMpid + str w0, [x1] + ldr x0, =3DMV_SMC_ID_DRAM_SIZE + mov x1, xzr + smc #0 + sub x0, x0, #1 // Last valid address + // if mSystemMemoryEnd wasn't gethered from SMC call, get it from PCDs + cmp x0, #0xffffffffffffffff + bne done + // if mSystemMemoryEnd wasn't gethered from SMC call, get it from PCDs + MOV64 (x0, FixedPcdGet64(PcdSystemMemoryBase) + FixedPcdGet64(PcdSystemM= emorySize) - 1) +done: + adr x1, mSystemMemoryEnd + str x0, [x1] // Set mSystemMemoryEnd + + ret + + +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId) + MOV32(w0, FixedPcdGet32(PcdArmPrimaryCore)) + ret + +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_FUNC(ArmPlatformIsPrimaryCore) + MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCoreMask)) + and x0, x0, x1 + MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCore)) + cmp w0, w1 + mov x0, #1 + mov x1, #0 + csel x0, x0, x1, eq + ret + +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +ASM_FUNC(ArmPlatformGetCorePosition) +/* + Affinity Level 0: single thread 0 + Affinity Level 1: clustering 0( + Affinity Level 2: number of clusters up to 64 (CN10K)/ 80 (Odyssey)/ 16 = (Iliad) + Affinity Level 3: number of chip 0 + LinearId =3D Aff2 +*/ + and x0, x0, #ARM_CORE_AFF2 + lsr x0, x0, #16 + ret + +ASM_FUNCTION_REMOVE_IF_UNREFERENCED + +PrimaryCoreMpid: .word 0x0 diff --git a/Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/OdysseyLib.c b/S= ilicon/Marvell/OdysseyPkg/Library/OdysseyLib/OdysseyLib.c new file mode 100644 index 0000000000..ed48a00950 --- /dev/null +++ b/Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/OdysseyLib.c @@ -0,0 +1,79 @@ +/** @file +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* https://spdx.org/licenses +* +* Copyright (C) 2022 Marvell +* +* Source file for Marvell ARM Platform library +* Based on ArmPlatformPkg/Library/ArmPlatformLibNull +**/ + +#include +#include // EFI_BOOT_MODE +#include // EFI_PEI_PPI_DESCRIPTOR +#include // ASSERT +#include // ArmPlatformIsPrimaryCore +#include // ARM_MP_CORE_INFO_PPI + +/** + Return the current Boot Mode + + This function returns the boot reason on the platform + + @return Return the current Boot Mode of the platform + +**/ +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + +/** + Initialize controllers that must setup in the normal world + + This function is called by the ArmPlatformPkg/PrePei or ArmPlatformPkg/P= ei/PlatformPeim + in the PEI phase. + +**/ +RETURN_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + ASSERT(ArmPlatformIsPrimaryCore (MpId)); + + return RETURN_SUCCESS; +} + +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + return EFI_UNSUPPORTED; +} + +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi =3D { PrePeiCoreGetMpCoreInfo }; + +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + } +}; + +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + *PpiListSize =3D sizeof(gPlatformPpiTable); + *PpiList =3D gPlatformPpiTable; +} diff --git a/Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/OdysseyLib.inf b= /Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/OdysseyLib.inf new file mode 100644 index 0000000000..c47a19767b --- /dev/null +++ b/Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/OdysseyLib.inf @@ -0,0 +1,60 @@ +#/** @file +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# https://spdx.org/licenses +# +# Copyright (C) 2022 Marvell +# +# Marvell ARM Platform library +# Based on ArmPlatformPkg/Library/ArmPlatformLibNull +# +#**/ + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D OdysseyLib + FILE_GUID =3D 7ea0f45b-0e06-4e45-8353-9c28b091a11c + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D OdysseyLib + +[Packages] + MdePkg/MdePkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec # Include ArmPlatformLib.h + EmbeddedPkg/EmbeddedPkg.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec + +[LibraryClasses] + ArmLib + HobLib + DebugLib + MemoryAllocationLib + SmcLib + FdtLib + +[Sources] + OdysseyLib.c + OdysseyLibMem.c + +[Sources.AARCH64] + AArch64/ArmPlatformHelper.S + +[FixedPcd] + gArmTokenSpaceGuid.PcdFdBaseAddress + gArmTokenSpaceGuid.PcdFdSize + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + gArmTokenSpaceGuid.PcdArmPrimaryCore + + gMarvellSiliconTokenSpaceGuid.PcdNodeDramBase + gMarvellSiliconTokenSpaceGuid.PcdIoBaseAddress + gMarvellSiliconTokenSpaceGuid.PcdNodeIoBaseAddress + gMarvellSiliconTokenSpaceGuid.PcdIoSize + +[Ppis] + gArmMpCoreInfoPpiGuid + +[Guids] + gFdtHobGuid diff --git a/Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/OdysseyLibMem.c = b/Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/OdysseyLibMem.c new file mode 100644 index 0000000000..bfec57952a --- /dev/null +++ b/Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/OdysseyLibMem.c @@ -0,0 +1,142 @@ +/** @file +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* https://spdx.org/licenses +* +* Copyright (C) 2022 Marvell +* +* Source file for Marvell ARM Platform library +* Based on ArmPlatformPkg/Library/ArmPlatformLibNull +**/ + +#include // Basic UEFI types +#include // DEBUG +#include // EFI_BOOT_MODE required by PiH= ob.h +#include // EFI_RESOURCE_ATTRIBUTE_TYPE +#include // BuildResourceDescriptorHob +#include // PcdGet64 +#include // ARM_MEMORY_REGION_ATTRIBUTE_W= RITE_BACK +#include // SmcGetRamSize +#include // AllocatePages +#include // fdt_totalsize // + +// Number of Virtual Memory Map Descriptors +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 129 +#define MAX_NODES 1 + +// DDR attributes +#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_= BACK +#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACH= ED_UNBUFFERED + +UINT64 mDeviceTreeBaseAddress =3D 0; + +/** + Return the Virtual Memory Map of your platform + + This Virtual Memory Map is used by MemoryInitPei Module to initialize th= e MMU on your platform. + + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR = describing a Physical-to- + Virtual Memory mapping. This array mus= t be ended by a zero-filled + entry + +**/ +VOID +ArmPlatformGetVirtualMemoryMap ( + IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap + ) +{ + ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes; + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; + UINT64 VirtualMemoryTableSize; + UINT64 MemoryBase; + UINT64 MemorySize; + UINTN Index =3D 0; + UINTN Node; + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; + + ASSERT (VirtualMemoryMap !=3D NULL); + + VirtualMemoryTableSize =3D sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VI= RTUAL_MEMORY_MAP_DESCRIPTORS; + VirtualMemoryTable =3D AllocatePages (EFI_SIZE_TO_PAGES (VirtualMemoryTa= bleSize)); + + if (VirtualMemoryTable =3D=3D NULL) { + return; + } + + CacheAttributes =3D DDR_ATTRIBUTES_CACHED; + + ResourceAttributes =3D + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED; + + + VirtualMemoryTable[Index].PhysicalBase =3D PcdGet64(PcdFdBaseAddress); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64(PcdFdBaseAddress); + VirtualMemoryTable[Index].Length =3D PcdGet32(PcdFdSize); + VirtualMemoryTable[Index].Attributes =3D CacheAttributes; + Index++; + + BuildResourceDescriptorHob (EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + PcdGet64 (PcdFdBaseAddress), + PcdGet32 (PcdFdSize)); + + for (Node =3D 0; Node < MAX_NODES; Node++) { + MemoryBase =3D Node * FixedPcdGet64(PcdNodeDramBase); + MemorySize =3D SmcGetRamSize(Node); + + MemoryBase +=3D (Node =3D=3D 0) ? PcdGet64(PcdSystemMemoryBase) : 0; + MemorySize -=3D (Node =3D=3D 0) ? PcdGet64(PcdSystemMemoryBase) : 0; + + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + MemoryBase, + MemorySize); + + DEBUG ((DEBUG_LOAD | DEBUG_INFO, "Memory %lx @ %lx\n", MemorySize, = MemoryBase)); + VirtualMemoryTable[Index].PhysicalBase =3D MemoryBase; + VirtualMemoryTable[Index].VirtualBase =3D MemoryBase; + VirtualMemoryTable[Index].Length =3D MemorySize; + VirtualMemoryTable[Index].Attributes =3D CacheAttributes; + + Index++; + } + + for (Node =3D 0; Node < MAX_NODES; Node++) { + VirtualMemoryTable[Index].PhysicalBase =3D FixedPcdGet64(PcdIoBaseAdd= ress) + + Node * FixedPcdGet64(PcdNo= deIoBaseAddress); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64(PcdIoBaseAdd= ress) + + Node * FixedPcdGet64(PcdNo= deIoBaseAddress); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64(PcdIoSize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + + DEBUG ((DEBUG_LOAD | DEBUG_INFO, + "IO %lx @ %lx\n", + VirtualMemoryTable[Index].Length, + VirtualMemoryTable[Index].PhysicalBase)); + + Index++; + } + + // End of Table + VirtualMemoryTable[Index].PhysicalBase =3D 0; + VirtualMemoryTable[Index].VirtualBase =3D 0; + VirtualMemoryTable[Index].Length =3D 0; + VirtualMemoryTable[Index].Attributes =3D (ARM_MEMORY_REGION_ATTRIBUTES= )0; + + *VirtualMemoryMap =3D VirtualMemoryTable; + + // Build the FDT HOB + ASSERT(fdt_check_header ((VOID *)mDeviceTreeBaseAddress) =3D=3D 0); + DEBUG((DEBUG_INFO, "FDT address: %lx, size: %d\n", + mDeviceTreeBaseAddress, + fdt_totalsize((VOID *)mDeviceTreeBaseAddress))); + + BuildGuidDataHob (&gFdtHobGuid, &mDeviceTreeBaseAddress, sizeof(mDeviceT= reeBaseAddress)); +} --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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