UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-)
When creating smm page table, limit maximum
supported physical address bits returned by
CalculateMaximumSupportAddress() to 48 if
5-Level Paging is disabled.
When 5-Level Paging is disabled and the
PhysicalAddressBits retrived from CPU HOB or
CpuId is bigger than 48, only [0, 2^48 -1]
range in 52-bit physical address is mapped
in page table.
Signed-off-by: Dun Tan <dun.tan@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
---
UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 15 +++++++++++++--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
index ddd9be66b5..e6f174ca10 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
@@ -137,11 +137,13 @@ GetSubEntriesNum (
/**
Calculate the maximum support address.
+ @param[in] Is5LevelPagingNeeded If 5-level paging enabling is needed.
+
@return the maximum support address.
**/
UINT8
CalculateMaximumSupportAddress (
- VOID
+ BOOLEAN Is5LevelPagingNeeded
)
{
UINT32 RegEax;
@@ -164,6 +166,15 @@ CalculateMaximumSupportAddress (
}
}
+ //
+ // Only [0, 2^48 -1] in 52-bit physical addresses is mapped in page table
+ // when 5-Level Paging is disabled.
+ //
+ ASSERT (PhysicalAddressBits <= 52);
+ if (!Is5LevelPagingNeeded && (PhysicalAddressBits > 48)) {
+ PhysicalAddressBits = 48;
+ }
+
return PhysicalAddressBits;
}
@@ -197,7 +208,7 @@ SmmInitPageTable (
mCpuSmmRestrictedMemoryAccess = PcdGetBool (PcdCpuSmmRestrictedMemoryAccess);
m1GPageTableSupport = Is1GPageSupport ();
m5LevelPagingNeeded = Is5LevelPagingNeeded ();
- mPhysicalAddressBits = CalculateMaximumSupportAddress ();
+ mPhysicalAddressBits = CalculateMaximumSupportAddress (m5LevelPagingNeeded);
PatchInstructionX86 (gPatch5LevelPagingNeeded, m5LevelPagingNeeded, 1);
if (m5LevelPagingNeeded) {
mPagingMode = m1GPageTableSupport ? Paging5Level1GB : Paging5Level;
--
2.31.1.windows.1
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-=-=-=-=-=-=-=-=-=-=-=-On Wed, Jan 10, 2024 at 04:05:44PM +0800, Dun Tan wrote: > When creating smm page table, limit maximum > supported physical address bits returned by > CalculateMaximumSupportAddress() to 48 if > 5-Level Paging is disabled. > When 5-Level Paging is disabled and the > PhysicalAddressBits retrived from CPU HOB or > CpuId is bigger than 48, only [0, 2^48 -1] > range in 52-bit physical address is mapped > in page table. I think this is wrong. Virtual addresses are sign-extended, i.e. the virtual address space without 5-level paging is: 0x0000000000000000 -> 0x00007fffffffffff and 0xffff800000000000 -> 0xffffffffffffffff Therefore identity-mapping works for [0, 2^47-1] only. take care, Gerd -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#113523): https://edk2.groups.io/g/devel/message/113523 Mute This Topic: https://groups.io/mt/103637402/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
Hi Gerd, Thanks for your comments. I agree with your opinion. Will change the code and related comments in V2 patch. Thanks, Dun -----Original Message----- From: Gerd Hoffmann <kraxel@redhat.com> Sent: Wednesday, January 10, 2024 6:55 PM To: Tan, Dun <dun.tan@intel.com> Cc: devel@edk2.groups.io; Ni, Ray <ray.ni@intel.com>; Laszlo Ersek <lersek@redhat.com>; Kumar, Rahul R <rahul.r.kumar@intel.com> Subject: Re: [PATCH] UefiCpuPkg:Limit PhysicalAddressBits in speicial case On Wed, Jan 10, 2024 at 04:05:44PM +0800, Dun Tan wrote: > When creating smm page table, limit maximum supported physical address > bits returned by > CalculateMaximumSupportAddress() to 48 if 5-Level Paging is disabled. > When 5-Level Paging is disabled and the PhysicalAddressBits retrived > from CPU HOB or CpuId is bigger than 48, only [0, 2^48 -1] range in > 52-bit physical address is mapped in page table. I think this is wrong. Virtual addresses are sign-extended, i.e. the virtual address space without 5-level paging is: 0x0000000000000000 -> 0x00007fffffffffff and 0xffff800000000000 -> 0xffffffffffffffff Therefore identity-mapping works for [0, 2^47-1] only. take care, Gerd -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#113567): https://edk2.groups.io/g/devel/message/113567 Mute This Topic: https://groups.io/mt/103637402/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
On 1/10/24 11:54, Gerd Hoffmann wrote: > On Wed, Jan 10, 2024 at 04:05:44PM +0800, Dun Tan wrote: >> When creating smm page table, limit maximum >> supported physical address bits returned by >> CalculateMaximumSupportAddress() to 48 if >> 5-Level Paging is disabled. >> When 5-Level Paging is disabled and the >> PhysicalAddressBits retrived from CPU HOB or >> CpuId is bigger than 48, only [0, 2^48 -1] >> range in 52-bit physical address is mapped >> in page table. > > I think this is wrong. Virtual addresses are sign-extended, > i.e. the virtual address space without 5-level paging is: > > 0x0000000000000000 -> 0x00007fffffffffff and > 0xffff800000000000 -> 0xffffffffffffffff > > Therefore identity-mapping works for [0, 2^47-1] only. I'd have never noticed this. I'll happily defer reviewing this patch to you then! :) Thanks! Laszlo -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#113529): https://edk2.groups.io/g/devel/message/113529 Mute This Topic: https://groups.io/mt/103637402/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/leave/3901457/1787277/102458076/xyzzy [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
Reviewed-by: Ray Ni <ray.ni@intel.com>
Thanks,
Ray
> -----Original Message-----
> From: Tan, Dun <dun.tan@intel.com>
> Sent: Wednesday, January 10, 2024 4:06 PM
> To: devel@edk2.groups.io
> Cc: Ni, Ray <ray.ni@intel.com>; Laszlo Ersek <lersek@redhat.com>; Kumar,
> Rahul R <rahul.r.kumar@intel.com>; Gerd Hoffmann <kraxel@redhat.com>
> Subject: [PATCH] UefiCpuPkg:Limit PhysicalAddressBits in speicial case
>
> When creating smm page table, limit maximum
> supported physical address bits returned by
> CalculateMaximumSupportAddress() to 48 if
> 5-Level Paging is disabled.
> When 5-Level Paging is disabled and the
> PhysicalAddressBits retrived from CPU HOB or
> CpuId is bigger than 48, only [0, 2^48 -1]
> range in 52-bit physical address is mapped
> in page table.
>
> Signed-off-by: Dun Tan <dun.tan@intel.com>
> Cc: Ray Ni <ray.ni@intel.com>
> Cc: Laszlo Ersek <lersek@redhat.com>
> Cc: Rahul Kumar <rahul1.kumar@intel.com>
> Cc: Gerd Hoffmann <kraxel@redhat.com>
> ---
> UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 15 +++++++++++++--
> 1 file changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
> b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
> index ddd9be66b5..e6f174ca10 100644
> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
> @@ -137,11 +137,13 @@ GetSubEntriesNum (
> /**
> Calculate the maximum support address.
>
> + @param[in] Is5LevelPagingNeeded If 5-level paging enabling is needed.
> +
> @return the maximum support address.
> **/
> UINT8
> CalculateMaximumSupportAddress (
> - VOID
> + BOOLEAN Is5LevelPagingNeeded
> )
> {
> UINT32 RegEax;
> @@ -164,6 +166,15 @@ CalculateMaximumSupportAddress (
> }
> }
>
> + //
> + // Only [0, 2^48 -1] in 52-bit physical addresses is mapped in page table
> + // when 5-Level Paging is disabled.
> + //
> + ASSERT (PhysicalAddressBits <= 52);
> + if (!Is5LevelPagingNeeded && (PhysicalAddressBits > 48)) {
> + PhysicalAddressBits = 48;
> + }
> +
> return PhysicalAddressBits;
> }
>
> @@ -197,7 +208,7 @@ SmmInitPageTable (
> mCpuSmmRestrictedMemoryAccess = PcdGetBool
> (PcdCpuSmmRestrictedMemoryAccess);
> m1GPageTableSupport = Is1GPageSupport ();
> m5LevelPagingNeeded = Is5LevelPagingNeeded ();
> - mPhysicalAddressBits = CalculateMaximumSupportAddress ();
> + mPhysicalAddressBits = CalculateMaximumSupportAddress
> (m5LevelPagingNeeded);
> PatchInstructionX86 (gPatch5LevelPagingNeeded, m5LevelPagingNeeded,
> 1);
> if (m5LevelPagingNeeded) {
> mPagingMode = m1GPageTableSupport ? Paging5Level1GB : Paging5Level;
> --
> 2.31.1.windows.1
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