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[edk2-devel] [edk2-platforms PATCH 2/4] Marvell/Cn913xDb: Add ACPI MDIO description

Marcin Wojtas posted 4 patches 4 years, 8 months ago
[edk2-devel] [edk2-platforms PATCH 2/4] Marvell/Cn913xDb: Add ACPI MDIO description
Posted by Marcin Wojtas 4 years, 8 months ago 
As the MDIO ACPI binding in DSDT is now established,
add description for the SMI controller, along with the 1G PHYs.
Add also a missing 'managed' property to the 10G ports.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl |  1 +
 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl | 24 ++++++++++++++++++++
 2 files changed, 25 insertions(+)

diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl
index 691a709c18..8377b13763 100644
--- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl
@@ -91,6 +91,7 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU ", "CN9131", 3)
                     Package () { "port-id", 0 },
                     Package () { "gop-port-id", 0 },
                     Package () { "phy-mode", "10gbase-kr"},
+                    Package () { "managed", "in-band-status"},
                   }
               })
             }
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl
index 30de868907..d76a2a902b 100644
--- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl
@@ -185,6 +185,27 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
             })
         }
 
+        Device (SMI0)
+        {
+            Name (_HID, "MRVL0100")                             // _HID: Hardware ID
+            Name (_UID, 0x00)                                   // _UID: Unique ID
+            Name (_CRS, ResourceTemplate ()
+            {
+                Memory32Fixed (ReadWrite,
+                    0xf212a200,                                 // Address Base
+                    0x00000010,                                 // Address Length
+                    )
+            })
+            Device (PHY0)
+            {
+                Name (_ADR, 0x0)
+            }
+            Device (PHY1)
+            {
+                Name (_ADR, 0x1)
+            }
+        }
+
         Device (PP20)
         {
             Name (_HID, "MRVL0110")                             // _HID: Hardware ID
@@ -218,6 +239,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
                     Package () { "port-id", 0 },
                     Package () { "gop-port-id", 0 },
                     Package () { "phy-mode", "10gbase-kr"},
+                    Package () { "managed", "in-band-status"},
                   }
               })
             }
@@ -237,6 +259,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
                     Package () { "port-id", 1 },
                     Package () { "gop-port-id", 2 },
                     Package () { "phy-mode", "rgmii-id"},
+                    Package () { "phy-handle", \_SB.SMI0.PHY0},
                   }
               })
             }
@@ -256,6 +279,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
                     Package () { "port-id", 2 },
                     Package () { "gop-port-id", 3 },
                     Package () { "phy-mode", "rgmii-id"},
+                    Package () { "phy-handle", \_SB.SMI0.PHY1},
                   }
               })
             }
-- 
2.29.0



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Re: [edk2-devel] [edk2-platforms PATCH 2/4] Marvell/Cn913xDb: Add ACPI MDIO description
Posted by Grzegorz Bernacki 4 years, 7 months ago 
Tested-by: Grzegorz Bernacki <gjb@semihalf.com>

regards,
greg

niedz., 13 cze 2021 o 20:17 Marcin Wojtas <mw@semihalf.com> napisał(a):
>
> As the MDIO ACPI binding in DSDT is now established,
> add description for the SMI controller, along with the 1G PHYs.
> Add also a missing 'managed' property to the 10G ports.
>
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> ---
>  Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl |  1 +
>  Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl | 24 ++++++++++++++++++++
>  2 files changed, 25 insertions(+)
>
> diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl
> index 691a709c18..8377b13763 100644
> --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl
> +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl
> @@ -91,6 +91,7 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU ", "CN9131", 3)
>                      Package () { "port-id", 0 },
>                      Package () { "gop-port-id", 0 },
>                      Package () { "phy-mode", "10gbase-kr"},
> +                    Package () { "managed", "in-band-status"},
>                    }
>                })
>              }
> diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl
> index 30de868907..d76a2a902b 100644
> --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl
> +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl
> @@ -185,6 +185,27 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
>              })
>          }
>
> +        Device (SMI0)
> +        {
> +            Name (_HID, "MRVL0100")                             // _HID: Hardware ID
> +            Name (_UID, 0x00)                                   // _UID: Unique ID
> +            Name (_CRS, ResourceTemplate ()
> +            {
> +                Memory32Fixed (ReadWrite,
> +                    0xf212a200,                                 // Address Base
> +                    0x00000010,                                 // Address Length
> +                    )
> +            })
> +            Device (PHY0)
> +            {
> +                Name (_ADR, 0x0)
> +            }
> +            Device (PHY1)
> +            {
> +                Name (_ADR, 0x1)
> +            }
> +        }
> +
>          Device (PP20)
>          {
>              Name (_HID, "MRVL0110")                             // _HID: Hardware ID
> @@ -218,6 +239,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
>                      Package () { "port-id", 0 },
>                      Package () { "gop-port-id", 0 },
>                      Package () { "phy-mode", "10gbase-kr"},
> +                    Package () { "managed", "in-band-status"},
>                    }
>                })
>              }
> @@ -237,6 +259,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
>                      Package () { "port-id", 1 },
>                      Package () { "gop-port-id", 2 },
>                      Package () { "phy-mode", "rgmii-id"},
> +                    Package () { "phy-handle", \_SB.SMI0.PHY0},
>                    }
>                })
>              }
> @@ -256,6 +279,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
>                      Package () { "port-id", 2 },
>                      Package () { "gop-port-id", 3 },
>                      Package () { "phy-mode", "rgmii-id"},
> +                    Package () { "phy-handle", \_SB.SMI0.PHY1},
>                    }
>                })
>              }
> --
> 2.29.0
>


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