UefiPayloadPkg/Include/Guid/PldPciRootBridgeInfoHob.h | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h | 40 ++++++++++++++++++++++++++++++++++++++-- UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c | 41 ++++++++++++++++++++++++++++++++++++++--- UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf | 9 ++++++++- UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c | 81 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++- UefiPayloadPkg/UefiPayloadPkg.dec | 11 ++++++----- 6 files changed, 224 insertions(+), 12 deletions(-)
UefiPayload parse gPldPciRootBridgeInfoGuid Guid Hob to retrieve PCI root bridges
information. gPldPciRootBridgeInfoGuid Guid Hob should be created by Bootloader.
Cc: Guo Dong <guo.dong@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Signed-off-by: Aiden Park <aiden.park@intel.com>
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
---
UefiPayloadPkg/Include/Guid/PldPciRootBridgeInfoHob.h | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h | 40 ++++++++++++++++++++++++++++++++++++++--
UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c | 41 ++++++++++++++++++++++++++++++++++++++---
UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf | 9 ++++++++-
UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c | 81 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
UefiPayloadPkg/UefiPayloadPkg.dec | 11 ++++++-----
6 files changed, 224 insertions(+), 12 deletions(-)
diff --git a/UefiPayloadPkg/Include/Guid/PldPciRootBridgeInfoHob.h b/UefiPayloadPkg/Include/Guid/PldPciRootBridgeInfoHob.h
new file mode 100644
index 0000000000..47a9a7aeb2
--- /dev/null
+++ b/UefiPayloadPkg/Include/Guid/PldPciRootBridgeInfoHob.h
@@ -0,0 +1,54 @@
+/** @file
+ This file defines the hob structure for the PCI Root Bridge Info.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __PLD_PCI_ROOT_BRIDGE_INFO_HOB_H__
+#define __PLD_PCI_ROOT_BRIDGE_INFO_HOB_H__
+
+#include <IndustryStandard/Pci.h>
+#include <Library/PciHostBridgeLib.h>
+
+///
+/// Payload PCI Root Bridge Information HOB
+///
+typedef struct {
+ UINT32 Segment; ///< Segment number.
+ UINT64 Supports; ///< Supported attributes.
+ ///< Refer to EFI_PCI_ATTRIBUTE_xxx used by GetAttributes()
+ ///< and SetAttributes() in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ UINT64 Attributes; ///< Initial attributes.
+ ///< Refer to EFI_PCI_ATTRIBUTE_xxx used by GetAttributes()
+ ///< and SetAttributes() in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ BOOLEAN DmaAbove4G; ///< DMA above 4GB memory.
+ ///< Set to TRUE when root bridge supports DMA above 4GB memory.
+ BOOLEAN NoExtendedConfigSpace; ///< When FALSE, the root bridge supports
+ ///< Extended (4096-byte) Configuration Space.
+ ///< When TRUE, the root bridge supports
+ ///< 256-byte Configuration Space only.
+ BOOLEAN ResourceAssigned; ///< Resource assignment status of the root bridge.
+ ///< Set to TRUE if Bus/IO/MMIO resources for root bridge have been assigned.
+ UINT64 AllocationAttributes; ///< Allocation attributes.
+ ///< Refer to EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM and
+ ///< EFI_PCI_HOST_BRIDGE_MEM64_DECODE used by GetAllocAttributes()
+ ///< in EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.
+ PCI_ROOT_BRIDGE_APERTURE Bus; ///< Bus aperture which can be used by the root bridge.
+ PCI_ROOT_BRIDGE_APERTURE Io; ///< IO aperture which can be used by the root bridge.
+ PCI_ROOT_BRIDGE_APERTURE Mem; ///< MMIO aperture below 4GB which can be used by the root bridge.
+ PCI_ROOT_BRIDGE_APERTURE MemAbove4G; ///< MMIO aperture above 4GB which can be used by the root bridge.
+ PCI_ROOT_BRIDGE_APERTURE PMem; ///< Prefetchable MMIO aperture below 4GB which can be used by the root bridge.
+ PCI_ROOT_BRIDGE_APERTURE PMemAbove4G; ///< Prefetchable MMIO aperture above 4GB which can be used by the root bridge.
+ UINT32 HID;
+ UINT32 UID;
+} PLD_PCI_ROOT_BRIDGE;
+
+typedef struct {
+ UINT8 Revision;
+ UINT8 Count;
+ PLD_PCI_ROOT_BRIDGE RootBridge[0];
+} PLD_PCI_ROOT_BRIDGE_INFO_HOB;
+
+#endif // __PLD_PCI_ROOT_BRIDGE_INFO_HOB_H__
diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h
index c2961b3bee..f6cb2a25d9 100644
--- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h
+++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h
@@ -2,7 +2,7 @@
Header file of PciHostBridgeLib.
Copyright (C) 2016, Red Hat, Inc.
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -11,14 +11,38 @@
#ifndef _PCI_HOST_BRIDGE_H
#define _PCI_HOST_BRIDGE_H
+#include <Guid/PldPciRootBridgeInfoHob.h>
+
typedef struct {
ACPI_HID_DEVICE_PATH AcpiDevicePath;
EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
} CB_PCI_ROOT_BRIDGE_DEVICE_PATH;
+/**
+ Scan for all root bridges in platform.
+
+ @param[out] NumberOfRootBridges Number of root bridges detected
+
+ @retval Pointer to the allocated PCI_ROOT_BRIDGE structure array.
+**/
PCI_ROOT_BRIDGE *
ScanForRootBridges (
- UINTN *NumberOfRootBridges
+ OUT UINTN *NumberOfRootBridges
+);
+
+/**
+ Scan for all root bridges from PldPciRootBridgeInfoHob
+
+ @param[in] PciRootBridgeInfo Pointer of PLD PCI Root Bridge Info Hob
+ @param[out] NumberOfRootBridges Number of root bridges detected
+
+ @retval Pointer to the allocated PCI_ROOT_BRIDGE structure array.
+
+**/
+PCI_ROOT_BRIDGE *
+RetrieveRootBridgeInfoFromHob (
+ IN PLD_PCI_ROOT_BRIDGE_INFO_HOB *PciRootBridgeInfo,
+ OUT UINTN *NumberOfRootBridges
);
/**
@@ -77,4 +101,16 @@ InitRootBridge (
OUT PCI_ROOT_BRIDGE *RootBus
);
+/**
+ Initialize DevicePath for a PCI_ROOT_BRIDGE.
+ @param[in] HID HID for device path
+ @param[in] UID UID for device path
+
+ @retval A pointer to the new created device patch.
+**/
+EFI_DEVICE_PATH_PROTOCOL *
+CreateRootBridgeDevicePath (
+ IN UINT32 HID,
+ IN UINT32 UID
+);
#endif
diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
index 512c3127cc..8af98dc16a 100644
--- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
+++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
@@ -2,7 +2,7 @@
Library instance of PciHostBridgeLib library class for coreboot.
Copyright (C) 2016, Red Hat, Inc.
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -19,6 +19,7 @@
#include <Library/MemoryAllocationLib.h>
#include <Library/PciHostBridgeLib.h>
#include <Library/PciLib.h>
+#include <Library/HobLib.h>
#include "PciHostBridge.h"
@@ -48,7 +49,6 @@ CB_PCI_ROOT_BRIDGE_DEVICE_PATH mRootBridgeDevicePathTemplate = {
}
};
-
/**
Initialize a PCI_ROOT_BRIDGE structure.
@@ -145,6 +145,27 @@ InitRootBridge (
return EFI_SUCCESS;
}
+/**
+ Initialize DevicePath for a PCI_ROOT_BRIDGE.
+ @param[in] HID HID for device path
+ @param[in] UID UID for device path
+
+ @retval A pointer to the new created device patch.
+**/
+EFI_DEVICE_PATH_PROTOCOL *
+CreateRootBridgeDevicePath (
+ IN UINT32 HID,
+ IN UINT32 UID
+)
+{
+ CB_PCI_ROOT_BRIDGE_DEVICE_PATH *DevicePath;
+ DevicePath = AllocateCopyPool (sizeof (mRootBridgeDevicePathTemplate),
+ &mRootBridgeDevicePathTemplate);
+ ASSERT (DevicePath != NULL);
+ DevicePath->AcpiDevicePath.HID = HID;
+ DevicePath->AcpiDevicePath.UID = UID;
+ return (EFI_DEVICE_PATH_PROTOCOL *)DevicePath;
+}
/**
Return all the root bridge instances in an array.
@@ -161,10 +182,24 @@ PciHostBridgeGetRootBridges (
UINTN *Count
)
{
+ PLD_PCI_ROOT_BRIDGE_INFO_HOB *PciRootBridgeInfo;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ //
+ // Find PLD PCI Root Bridge Info hob
+ //
+ GuidHob = GetFirstGuidHob (&gPldPciRootBridgeInfoGuid);
+ if (GuidHob != NULL) {
+ PciRootBridgeInfo = (PLD_PCI_ROOT_BRIDGE_INFO_HOB *) GET_GUID_HOB_DATA (GuidHob);
+ //
+ // The count of Root Bridge must be not large than the maximum Root Bridge number that the Hob can carry
+ //
+ if (PciRootBridgeInfo->Count <= (GuidHob->Header.HobLength - sizeof(PLD_PCI_ROOT_BRIDGE_INFO_HOB)) / sizeof(PLD_PCI_ROOT_BRIDGE)) {
+ return RetrieveRootBridgeInfoFromHob (PciRootBridgeInfo, Count);
+ }
+ }
return ScanForRootBridges (Count);
}
-
/**
Free the root bridge instances array returned from
PciHostBridgeGetRootBridges().
diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
index 7896df2416..ba31d718b8 100644
--- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
@@ -2,7 +2,7 @@
# Library instance of PciHostBridgeLib library class for coreboot.
#
# Copyright (C) 2016, Red Hat, Inc.
-# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -32,6 +32,7 @@
[Packages]
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
+ UefiPayloadPkg/UefiPayloadPkg.dec
[LibraryClasses]
BaseMemoryLib
@@ -39,3 +40,9 @@
DevicePathLib
MemoryAllocationLib
PciLib
+
+[Guids]
+ gPldPciRootBridgeInfoGuid
+
+[Pcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration
diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
index fffbf04cad..eb2d54fedc 100644
--- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
+++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
@@ -1,7 +1,7 @@
/** @file
Scan the entire PCI bus for root bridges to support coreboot UEFI payload.
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -582,3 +582,82 @@ ScanForRootBridges (
return RootBridges;
}
+
+/**
+ Scan for all root bridges from PldPciRootBridgeInfoHob
+
+ @param[in] PciRootBridgeInfo Pointer of PLD PCI Root Bridge Info Hob
+ @param[out] NumberOfRootBridges Number of root bridges detected
+
+ @retval Pointer to the allocated PCI_ROOT_BRIDGE structure array.
+
+**/
+PCI_ROOT_BRIDGE *
+RetrieveRootBridgeInfoFromHob (
+ IN PLD_PCI_ROOT_BRIDGE_INFO_HOB *PciRootBridgeInfo,
+ OUT UINTN *NumberOfRootBridges
+)
+{
+ PCI_ROOT_BRIDGE *PciRootBridges;
+ UINTN Size;
+ UINT8 Index;
+ BOOLEAN ResourceAssigned;
+
+ ASSERT (PciRootBridgeInfo != NULL);
+ ASSERT (NumberOfRootBridges != NULL);
+ if (PciRootBridgeInfo == NULL) {
+ return NULL;
+ }
+ if (PciRootBridgeInfo->Count == 0) {
+ return NULL;
+ }
+ Size = PciRootBridgeInfo->Count * sizeof (PCI_ROOT_BRIDGE);
+ PciRootBridges = (PCI_ROOT_BRIDGE *) AllocatePool (Size);
+ ASSERT (PciRootBridges != NULL);
+ if (PciRootBridges == NULL) {
+ return NULL;
+ }
+ ZeroMem (PciRootBridges, PciRootBridgeInfo->Count * sizeof (PCI_ROOT_BRIDGE));
+
+ //
+ // Create all root bridges with PciRootBridgeInfoHob
+ //
+ for (Index = 0; Index < PciRootBridgeInfo->Count; Index++) {
+ PciRootBridges[Index].Segment = PciRootBridgeInfo->RootBridge[Index].Segment;
+ PciRootBridges[Index].Supports = PciRootBridgeInfo->RootBridge[Index].Supports;
+ PciRootBridges[Index].Attributes = PciRootBridgeInfo->RootBridge[Index].Attributes;
+ PciRootBridges[Index].DmaAbove4G = PciRootBridgeInfo->RootBridge[Index].DmaAbove4G;
+ PciRootBridges[Index].NoExtendedConfigSpace = PciRootBridgeInfo->RootBridge[Index].NoExtendedConfigSpace;
+ PciRootBridges[Index].ResourceAssigned = PciRootBridgeInfo->RootBridge[Index].ResourceAssigned;
+ PciRootBridges[Index].AllocationAttributes = PciRootBridgeInfo->RootBridge[Index].AllocationAttributes;
+ PciRootBridges[Index].DevicePath = CreateRootBridgeDevicePath(PciRootBridgeInfo->RootBridge[Index].HID, PciRootBridgeInfo->RootBridge[Index].UID);
+ CopyMem(&PciRootBridges[Index].Bus, &PciRootBridgeInfo->RootBridge[Index].Bus, sizeof(PCI_ROOT_BRIDGE_APERTURE));
+ CopyMem(&PciRootBridges[Index].Io, &PciRootBridgeInfo->RootBridge[Index].Io, sizeof(PCI_ROOT_BRIDGE_APERTURE));
+ CopyMem(&PciRootBridges[Index].Mem, &PciRootBridgeInfo->RootBridge[Index].Mem, sizeof(PCI_ROOT_BRIDGE_APERTURE));
+ CopyMem(&PciRootBridges[Index].MemAbove4G, &PciRootBridgeInfo->RootBridge[Index].MemAbove4G, sizeof(PCI_ROOT_BRIDGE_APERTURE));
+ CopyMem(&PciRootBridges[Index].PMem, &PciRootBridgeInfo->RootBridge[Index].PMem, sizeof(PCI_ROOT_BRIDGE_APERTURE));
+ CopyMem(&PciRootBridges[Index].PMemAbove4G, &PciRootBridgeInfo->RootBridge[Index].PMemAbove4G, sizeof(PCI_ROOT_BRIDGE_APERTURE));
+ }
+
+ *NumberOfRootBridges = PciRootBridgeInfo->Count;
+ ResourceAssigned = PciRootBridges[0].ResourceAssigned;
+ for (Index = 1; Index < PciRootBridgeInfo->Count; Index++) {
+ if (PciRootBridges[Index].ResourceAssigned != ResourceAssigned) {
+ DEBUG ((DEBUG_ERROR, "All root birdges' field ResourceAssigned should be the same\n"));
+ return NULL;
+ }
+ }
+
+ //
+ // Now, this library only supports RootBridge that ResourceAssigned is True
+ //
+ if (ResourceAssigned) {
+ PcdSetBoolS (PcdPciDisableBusEnumeration, TRUE);
+ } else {
+ DEBUG ((DEBUG_ERROR, "There is root bridge whose ResourceAssigned is FALSE\n"));
+ PcdSetBoolS (PcdPciDisableBusEnumeration, FALSE);
+ return NULL;
+ }
+
+ return PciRootBridges;
+}
diff --git a/UefiPayloadPkg/UefiPayloadPkg.dec b/UefiPayloadPkg/UefiPayloadPkg.dec
index 99cb3311a6..a655a374e1 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.dec
+++ b/UefiPayloadPkg/UefiPayloadPkg.dec
@@ -3,7 +3,7 @@
#
# Provides drivers and definitions to create uefi payload for bootloaders.
#
-# Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -29,10 +29,11 @@
#
gBmpImageGuid = { 0x878AC2CC, 0x5343, 0x46F2, { 0xB5, 0x63, 0x51, 0xF8, 0x9D, 0xAF, 0x56, 0xBA } }
- gUefiSystemTableInfoGuid = {0x16c8a6d0, 0xfe8a, 0x4082, {0xa2, 0x8, 0xcf, 0x89, 0xc4, 0x29, 0x4, 0x33}}
- gUefiAcpiBoardInfoGuid = {0xad3d31b, 0xb3d8, 0x4506, {0xae, 0x71, 0x2e, 0xf1, 0x10, 0x6, 0xd9, 0xf}}
- gUefiSerialPortInfoGuid = { 0x6c6872fe, 0x56a9, 0x4403, { 0xbb, 0x98, 0x95, 0x8d, 0x62, 0xde, 0x87, 0xf1 } }
- gLoaderMemoryMapInfoGuid = { 0xa1ff7424, 0x7a1a, 0x478e, { 0xa9, 0xe4, 0x92, 0xf3, 0x57, 0xd1, 0x28, 0x32 } }
+ gUefiSystemTableInfoGuid = { 0x16c8a6d0, 0xfe8a, 0x4082, { 0xa2, 0x08, 0xcf, 0x89, 0xc4, 0x29, 0x04, 0x33 }}
+ gUefiAcpiBoardInfoGuid = { 0x0ad3d31b, 0xb3d8, 0x4506, { 0xae, 0x71, 0x2e, 0xf1, 0x10, 0x06, 0xd9, 0x0f }}
+ gUefiSerialPortInfoGuid = { 0x6c6872fe, 0x56a9, 0x4403, { 0xbb, 0x98, 0x95, 0x8d, 0x62, 0xde, 0x87, 0xf1 }}
+ gLoaderMemoryMapInfoGuid = { 0xa1ff7424, 0x7a1a, 0x478e, { 0xa9, 0xe4, 0x92, 0xf3, 0x57, 0xd1, 0x28, 0x32 }}
+ gPldPciRootBridgeInfoGuid = { 0xec4ebacb, 0x2638, 0x416e, { 0xbe, 0x80, 0xe5, 0xfa, 0x4b, 0x51, 0x19, 0x01 }}
[Ppis]
gEfiPayLoadHobBasePpiGuid = { 0xdbe23aa1, 0xa342, 0x4b97, {0x85, 0xb6, 0xb2, 0x26, 0xf1, 0x61, 0x73, 0x89} }
--
2.30.0.windows.2
-=-=-=-=-=-=-=-=-=-=-=-
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-=-=-=-=-=-=-=-=-=-=-=-
Reviewed-by: Ray Ni <ray.ni@intel.com>
> -----Original Message-----
> From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of
> Zhiguang Liu
> Sent: Tuesday, March 30, 2021 4:45 PM
> To: devel@edk2.groups.io
> Cc: Dong, Guo <guo.dong@intel.com>; You, Benjamin
> <benjamin.you@intel.com>; Park, Aiden <aiden.park@intel.com>; Ma,
> Maurice <maurice.ma@intel.com>
> Subject: [edk2-devel] [PATCH] UefiPayloadPkg: UefiPayload retrieve PCI root
> bridge from Guid Hob
>
> UefiPayload parse gPldPciRootBridgeInfoGuid Guid Hob to retrieve PCI root
> bridges
> information. gPldPciRootBridgeInfoGuid Guid Hob should be created by
> Bootloader.
>
> Cc: Guo Dong <guo.dong@intel.com>
> Cc: Benjamin You <benjamin.you@intel.com>
> Signed-off-by: Aiden Park <aiden.park@intel.com>
> Signed-off-by: Maurice Ma <maurice.ma@intel.com>
> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
> ---
> UefiPayloadPkg/Include/Guid/PldPciRootBridgeInfoHob.h | 54
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++
> UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h | 40
> ++++++++++++++++++++++++++++++++++++++--
> UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c | 41
> ++++++++++++++++++++++++++++++++++++++---
> UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf | 9
> ++++++++-
> UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c | 81
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++-
> UefiPayloadPkg/UefiPayloadPkg.dec | 11 ++++++-----
> 6 files changed, 224 insertions(+), 12 deletions(-)
>
> diff --git a/UefiPayloadPkg/Include/Guid/PldPciRootBridgeInfoHob.h
> b/UefiPayloadPkg/Include/Guid/PldPciRootBridgeInfoHob.h
> new file mode 100644
> index 0000000000..47a9a7aeb2
> --- /dev/null
> +++ b/UefiPayloadPkg/Include/Guid/PldPciRootBridgeInfoHob.h
> @@ -0,0 +1,54 @@
> +/** @file
>
> + This file defines the hob structure for the PCI Root Bridge Info.
>
> +
>
> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +
>
> +**/
>
> +
>
> +#ifndef __PLD_PCI_ROOT_BRIDGE_INFO_HOB_H__
>
> +#define __PLD_PCI_ROOT_BRIDGE_INFO_HOB_H__
>
> +
>
> +#include <IndustryStandard/Pci.h>
>
> +#include <Library/PciHostBridgeLib.h>
>
> +
>
> +///
>
> +/// Payload PCI Root Bridge Information HOB
>
> +///
>
> +typedef struct {
>
> + UINT32 Segment; ///< Segment number.
>
> + UINT64 Supports; ///< Supported attributes.
>
> + ///< Refer to EFI_PCI_ATTRIBUTE_xxx used by
> GetAttributes()
>
> + ///< and SetAttributes() in
> EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
>
> + UINT64 Attributes; ///< Initial attributes.
>
> + ///< Refer to EFI_PCI_ATTRIBUTE_xxx used by
> GetAttributes()
>
> + ///< and SetAttributes() in
> EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
>
> + BOOLEAN DmaAbove4G; ///< DMA above 4GB memory.
>
> + ///< Set to TRUE when root bridge supports DMA
> above 4GB memory.
>
> + BOOLEAN NoExtendedConfigSpace; ///< When FALSE, the root
> bridge supports
>
> + ///< Extended (4096-byte) Configuration Space.
>
> + ///< When TRUE, the root bridge supports
>
> + ///< 256-byte Configuration Space only.
>
> + BOOLEAN ResourceAssigned; ///< Resource assignment status
> of the root bridge.
>
> + ///< Set to TRUE if Bus/IO/MMIO resources for
> root bridge have been assigned.
>
> + UINT64 AllocationAttributes; ///< Allocation attributes.
>
> + ///< Refer to
> EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM and
>
> + ///< EFI_PCI_HOST_BRIDGE_MEM64_DECODE
> used by GetAllocAttributes()
>
> + ///< in
> EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.
>
> + PCI_ROOT_BRIDGE_APERTURE Bus; ///< Bus aperture which can
> be used by the root bridge.
>
> + PCI_ROOT_BRIDGE_APERTURE Io; ///< IO aperture which can be
> used by the root bridge.
>
> + PCI_ROOT_BRIDGE_APERTURE Mem; ///< MMIO aperture below
> 4GB which can be used by the root bridge.
>
> + PCI_ROOT_BRIDGE_APERTURE MemAbove4G; ///< MMIO aperture
> above 4GB which can be used by the root bridge.
>
> + PCI_ROOT_BRIDGE_APERTURE PMem; ///< Prefetchable MMIO
> aperture below 4GB which can be used by the root bridge.
>
> + PCI_ROOT_BRIDGE_APERTURE PMemAbove4G; ///< Prefetchable
> MMIO aperture above 4GB which can be used by the root bridge.
>
> + UINT32 HID;
>
> + UINT32 UID;
>
> +} PLD_PCI_ROOT_BRIDGE;
>
> +
>
> +typedef struct {
>
> + UINT8 Revision;
>
> + UINT8 Count;
>
> + PLD_PCI_ROOT_BRIDGE RootBridge[0];
>
> +} PLD_PCI_ROOT_BRIDGE_INFO_HOB;
>
> +
>
> +#endif // __PLD_PCI_ROOT_BRIDGE_INFO_HOB_H__
>
> diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h
> b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h
> index c2961b3bee..f6cb2a25d9 100644
> --- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h
> +++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h
> @@ -2,7 +2,7 @@
> Header file of PciHostBridgeLib.
>
>
>
> Copyright (C) 2016, Red Hat, Inc.
>
> - Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
>
> + Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR>
>
>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
>
>
> @@ -11,14 +11,38 @@
> #ifndef _PCI_HOST_BRIDGE_H
>
> #define _PCI_HOST_BRIDGE_H
>
>
>
> +#include <Guid/PldPciRootBridgeInfoHob.h>
>
> +
>
> typedef struct {
>
> ACPI_HID_DEVICE_PATH AcpiDevicePath;
>
> EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
>
> } CB_PCI_ROOT_BRIDGE_DEVICE_PATH;
>
>
>
> +/**
>
> + Scan for all root bridges in platform.
>
> +
>
> + @param[out] NumberOfRootBridges Number of root bridges detected
>
> +
>
> + @retval Pointer to the allocated PCI_ROOT_BRIDGE structure array.
>
> +**/
>
> PCI_ROOT_BRIDGE *
>
> ScanForRootBridges (
>
> - UINTN *NumberOfRootBridges
>
> + OUT UINTN *NumberOfRootBridges
>
> +);
>
> +
>
> +/**
>
> + Scan for all root bridges from PldPciRootBridgeInfoHob
>
> +
>
> + @param[in] PciRootBridgeInfo Pointer of PLD PCI Root Bridge Info Hob
>
> + @param[out] NumberOfRootBridges Number of root bridges detected
>
> +
>
> + @retval Pointer to the allocated PCI_ROOT_BRIDGE structure array.
>
> +
>
> +**/
>
> +PCI_ROOT_BRIDGE *
>
> +RetrieveRootBridgeInfoFromHob (
>
> + IN PLD_PCI_ROOT_BRIDGE_INFO_HOB *PciRootBridgeInfo,
>
> + OUT UINTN *NumberOfRootBridges
>
> );
>
>
>
> /**
>
> @@ -77,4 +101,16 @@ InitRootBridge (
> OUT PCI_ROOT_BRIDGE *RootBus
>
> );
>
>
>
> +/**
>
> + Initialize DevicePath for a PCI_ROOT_BRIDGE.
>
> + @param[in] HID HID for device path
>
> + @param[in] UID UID for device path
>
> +
>
> + @retval A pointer to the new created device patch.
>
> +**/
>
> +EFI_DEVICE_PATH_PROTOCOL *
>
> +CreateRootBridgeDevicePath (
>
> + IN UINT32 HID,
>
> + IN UINT32 UID
>
> +);
>
> #endif
>
> diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
> b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
> index 512c3127cc..8af98dc16a 100644
> --- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
> +++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
> @@ -2,7 +2,7 @@
> Library instance of PciHostBridgeLib library class for coreboot.
>
>
>
> Copyright (C) 2016, Red Hat, Inc.
>
> - Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
>
> + Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR>
>
>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
>
>
> @@ -19,6 +19,7 @@
> #include <Library/MemoryAllocationLib.h>
>
> #include <Library/PciHostBridgeLib.h>
>
> #include <Library/PciLib.h>
>
> +#include <Library/HobLib.h>
>
>
>
> #include "PciHostBridge.h"
>
>
>
> @@ -48,7 +49,6 @@ CB_PCI_ROOT_BRIDGE_DEVICE_PATH
> mRootBridgeDevicePathTemplate = {
> }
>
> };
>
>
>
> -
>
> /**
>
> Initialize a PCI_ROOT_BRIDGE structure.
>
>
>
> @@ -145,6 +145,27 @@ InitRootBridge (
> return EFI_SUCCESS;
>
> }
>
>
>
> +/**
>
> + Initialize DevicePath for a PCI_ROOT_BRIDGE.
>
> + @param[in] HID HID for device path
>
> + @param[in] UID UID for device path
>
> +
>
> + @retval A pointer to the new created device patch.
>
> +**/
>
> +EFI_DEVICE_PATH_PROTOCOL *
>
> +CreateRootBridgeDevicePath (
>
> + IN UINT32 HID,
>
> + IN UINT32 UID
>
> +)
>
> +{
>
> + CB_PCI_ROOT_BRIDGE_DEVICE_PATH *DevicePath;
>
> + DevicePath = AllocateCopyPool (sizeof (mRootBridgeDevicePathTemplate),
>
> + &mRootBridgeDevicePathTemplate);
>
> + ASSERT (DevicePath != NULL);
>
> + DevicePath->AcpiDevicePath.HID = HID;
>
> + DevicePath->AcpiDevicePath.UID = UID;
>
> + return (EFI_DEVICE_PATH_PROTOCOL *)DevicePath;
>
> +}
>
>
>
> /**
>
> Return all the root bridge instances in an array.
>
> @@ -161,10 +182,24 @@ PciHostBridgeGetRootBridges (
> UINTN *Count
>
> )
>
> {
>
> + PLD_PCI_ROOT_BRIDGE_INFO_HOB *PciRootBridgeInfo;
>
> + EFI_HOB_GUID_TYPE *GuidHob;
>
> + //
>
> + // Find PLD PCI Root Bridge Info hob
>
> + //
>
> + GuidHob = GetFirstGuidHob (&gPldPciRootBridgeInfoGuid);
>
> + if (GuidHob != NULL) {
>
> + PciRootBridgeInfo = (PLD_PCI_ROOT_BRIDGE_INFO_HOB *)
> GET_GUID_HOB_DATA (GuidHob);
>
> + //
>
> + // The count of Root Bridge must be not large than the maximum Root
> Bridge number that the Hob can carry
>
> + //
>
> + if (PciRootBridgeInfo->Count <= (GuidHob->Header.HobLength -
> sizeof(PLD_PCI_ROOT_BRIDGE_INFO_HOB)) /
> sizeof(PLD_PCI_ROOT_BRIDGE)) {
>
> + return RetrieveRootBridgeInfoFromHob (PciRootBridgeInfo, Count);
>
> + }
>
> + }
>
> return ScanForRootBridges (Count);
>
> }
>
>
>
> -
>
> /**
>
> Free the root bridge instances array returned from
>
> PciHostBridgeGetRootBridges().
>
> diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> index 7896df2416..ba31d718b8 100644
> --- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> +++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> @@ -2,7 +2,7 @@
> # Library instance of PciHostBridgeLib library class for coreboot.
>
> #
>
> # Copyright (C) 2016, Red Hat, Inc.
>
> -# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
>
> +# Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR>
>
> #
>
> # SPDX-License-Identifier: BSD-2-Clause-Patent
>
> #
>
> @@ -32,6 +32,7 @@
> [Packages]
>
> MdeModulePkg/MdeModulePkg.dec
>
> MdePkg/MdePkg.dec
>
> + UefiPayloadPkg/UefiPayloadPkg.dec
>
>
>
> [LibraryClasses]
>
> BaseMemoryLib
>
> @@ -39,3 +40,9 @@
> DevicePathLib
>
> MemoryAllocationLib
>
> PciLib
>
> +
>
> +[Guids]
>
> + gPldPciRootBridgeInfoGuid
>
> +
>
> +[Pcd]
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration
>
> diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
> b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
> index fffbf04cad..eb2d54fedc 100644
> --- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
> +++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
> @@ -1,7 +1,7 @@
> /** @file
>
> Scan the entire PCI bus for root bridges to support coreboot UEFI payload.
>
>
>
> - Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
>
> + Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR>
>
>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
>
>
> @@ -582,3 +582,82 @@ ScanForRootBridges (
>
>
> return RootBridges;
>
> }
>
> +
>
> +/**
>
> + Scan for all root bridges from PldPciRootBridgeInfoHob
>
> +
>
> + @param[in] PciRootBridgeInfo Pointer of PLD PCI Root Bridge Info Hob
>
> + @param[out] NumberOfRootBridges Number of root bridges detected
>
> +
>
> + @retval Pointer to the allocated PCI_ROOT_BRIDGE structure array.
>
> +
>
> +**/
>
> +PCI_ROOT_BRIDGE *
>
> +RetrieveRootBridgeInfoFromHob (
>
> + IN PLD_PCI_ROOT_BRIDGE_INFO_HOB *PciRootBridgeInfo,
>
> + OUT UINTN *NumberOfRootBridges
>
> +)
>
> +{
>
> + PCI_ROOT_BRIDGE *PciRootBridges;
>
> + UINTN Size;
>
> + UINT8 Index;
>
> + BOOLEAN ResourceAssigned;
>
> +
>
> + ASSERT (PciRootBridgeInfo != NULL);
>
> + ASSERT (NumberOfRootBridges != NULL);
>
> + if (PciRootBridgeInfo == NULL) {
>
> + return NULL;
>
> + }
>
> + if (PciRootBridgeInfo->Count == 0) {
>
> + return NULL;
>
> + }
>
> + Size = PciRootBridgeInfo->Count * sizeof (PCI_ROOT_BRIDGE);
>
> + PciRootBridges = (PCI_ROOT_BRIDGE *) AllocatePool (Size);
>
> + ASSERT (PciRootBridges != NULL);
>
> + if (PciRootBridges == NULL) {
>
> + return NULL;
>
> + }
>
> + ZeroMem (PciRootBridges, PciRootBridgeInfo->Count * sizeof
> (PCI_ROOT_BRIDGE));
>
> +
>
> + //
>
> + // Create all root bridges with PciRootBridgeInfoHob
>
> + //
>
> + for (Index = 0; Index < PciRootBridgeInfo->Count; Index++) {
>
> + PciRootBridges[Index].Segment = PciRootBridgeInfo-
> >RootBridge[Index].Segment;
>
> + PciRootBridges[Index].Supports = PciRootBridgeInfo-
> >RootBridge[Index].Supports;
>
> + PciRootBridges[Index].Attributes = PciRootBridgeInfo-
> >RootBridge[Index].Attributes;
>
> + PciRootBridges[Index].DmaAbove4G = PciRootBridgeInfo-
> >RootBridge[Index].DmaAbove4G;
>
> + PciRootBridges[Index].NoExtendedConfigSpace = PciRootBridgeInfo-
> >RootBridge[Index].NoExtendedConfigSpace;
>
> + PciRootBridges[Index].ResourceAssigned = PciRootBridgeInfo-
> >RootBridge[Index].ResourceAssigned;
>
> + PciRootBridges[Index].AllocationAttributes = PciRootBridgeInfo-
> >RootBridge[Index].AllocationAttributes;
>
> + PciRootBridges[Index].DevicePath =
> CreateRootBridgeDevicePath(PciRootBridgeInfo->RootBridge[Index].HID,
> PciRootBridgeInfo->RootBridge[Index].UID);
>
> + CopyMem(&PciRootBridges[Index].Bus, &PciRootBridgeInfo-
> >RootBridge[Index].Bus, sizeof(PCI_ROOT_BRIDGE_APERTURE));
>
> + CopyMem(&PciRootBridges[Index].Io, &PciRootBridgeInfo-
> >RootBridge[Index].Io, sizeof(PCI_ROOT_BRIDGE_APERTURE));
>
> + CopyMem(&PciRootBridges[Index].Mem, &PciRootBridgeInfo-
> >RootBridge[Index].Mem, sizeof(PCI_ROOT_BRIDGE_APERTURE));
>
> + CopyMem(&PciRootBridges[Index].MemAbove4G, &PciRootBridgeInfo-
> >RootBridge[Index].MemAbove4G, sizeof(PCI_ROOT_BRIDGE_APERTURE));
>
> + CopyMem(&PciRootBridges[Index].PMem, &PciRootBridgeInfo-
> >RootBridge[Index].PMem, sizeof(PCI_ROOT_BRIDGE_APERTURE));
>
> + CopyMem(&PciRootBridges[Index].PMemAbove4G, &PciRootBridgeInfo-
> >RootBridge[Index].PMemAbove4G, sizeof(PCI_ROOT_BRIDGE_APERTURE));
>
> + }
>
> +
>
> + *NumberOfRootBridges = PciRootBridgeInfo->Count;
>
> + ResourceAssigned = PciRootBridges[0].ResourceAssigned;
>
> + for (Index = 1; Index < PciRootBridgeInfo->Count; Index++) {
>
> + if (PciRootBridges[Index].ResourceAssigned != ResourceAssigned) {
>
> + DEBUG ((DEBUG_ERROR, "All root birdges' field ResourceAssigned
> should be the same\n"));
>
> + return NULL;
>
> + }
>
> + }
>
> +
>
> + //
>
> + // Now, this library only supports RootBridge that ResourceAssigned is
> True
>
> + //
>
> + if (ResourceAssigned) {
>
> + PcdSetBoolS (PcdPciDisableBusEnumeration, TRUE);
>
> + } else {
>
> + DEBUG ((DEBUG_ERROR, "There is root bridge whose ResourceAssigned
> is FALSE\n"));
>
> + PcdSetBoolS (PcdPciDisableBusEnumeration, FALSE);
>
> + return NULL;
>
> + }
>
> +
>
> + return PciRootBridges;
>
> +}
>
> diff --git a/UefiPayloadPkg/UefiPayloadPkg.dec
> b/UefiPayloadPkg/UefiPayloadPkg.dec
> index 99cb3311a6..a655a374e1 100644
> --- a/UefiPayloadPkg/UefiPayloadPkg.dec
> +++ b/UefiPayloadPkg/UefiPayloadPkg.dec
> @@ -3,7 +3,7 @@
> #
>
> # Provides drivers and definitions to create uefi payload for bootloaders.
>
> #
>
> -# Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>
>
> +# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>
>
> # SPDX-License-Identifier: BSD-2-Clause-Patent
>
> #
>
> ##
>
> @@ -29,10 +29,11 @@
> #
>
> gBmpImageGuid = { 0x878AC2CC, 0x5343, 0x46F2, { 0xB5, 0x63,
> 0x51, 0xF8, 0x9D, 0xAF, 0x56, 0xBA } }
>
>
>
> - gUefiSystemTableInfoGuid = {0x16c8a6d0, 0xfe8a, 0x4082, {0xa2, 0x8, 0xcf,
> 0x89, 0xc4, 0x29, 0x4, 0x33}}
>
> - gUefiAcpiBoardInfoGuid = {0xad3d31b, 0xb3d8, 0x4506, {0xae, 0x71, 0x2e,
> 0xf1, 0x10, 0x6, 0xd9, 0xf}}
>
> - gUefiSerialPortInfoGuid = { 0x6c6872fe, 0x56a9, 0x4403, { 0xbb, 0x98, 0x95,
> 0x8d, 0x62, 0xde, 0x87, 0xf1 } }
>
> - gLoaderMemoryMapInfoGuid = { 0xa1ff7424, 0x7a1a, 0x478e, { 0xa9, 0xe4,
> 0x92, 0xf3, 0x57, 0xd1, 0x28, 0x32 } }
>
> + gUefiSystemTableInfoGuid = { 0x16c8a6d0, 0xfe8a, 0x4082, { 0xa2, 0x08,
> 0xcf, 0x89, 0xc4, 0x29, 0x04, 0x33 }}
>
> + gUefiAcpiBoardInfoGuid = { 0x0ad3d31b, 0xb3d8, 0x4506, { 0xae, 0x71,
> 0x2e, 0xf1, 0x10, 0x06, 0xd9, 0x0f }}
>
> + gUefiSerialPortInfoGuid = { 0x6c6872fe, 0x56a9, 0x4403, { 0xbb, 0x98, 0x95,
> 0x8d, 0x62, 0xde, 0x87, 0xf1 }}
>
> + gLoaderMemoryMapInfoGuid = { 0xa1ff7424, 0x7a1a, 0x478e, { 0xa9, 0xe4,
> 0x92, 0xf3, 0x57, 0xd1, 0x28, 0x32 }}
>
> + gPldPciRootBridgeInfoGuid = { 0xec4ebacb, 0x2638, 0x416e, { 0xbe, 0x80,
> 0xe5, 0xfa, 0x4b, 0x51, 0x19, 0x01 }}
>
>
>
> [Ppis]
>
> gEfiPayLoadHobBasePpiGuid = { 0xdbe23aa1, 0xa342, 0x4b97, {0x85, 0xb6,
> 0xb2, 0x26, 0xf1, 0x61, 0x73, 0x89} }
>
> --
> 2.30.0.windows.2
>
>
>
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