From nobody Thu Apr 25 19:47:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+73524+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+73524+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1617093893; cv=none; d=zohomail.com; s=zohoarc; b=Ux6FR9Jj0F/jfCdQ2zamBK7iZCaHrTMhY1UziYMKpzZkcJIJ0jmb5iWx7ZUICiF96qXp11OpgQCZpdwSzKe83CZuuDm6aConAPPnpIgPuA+Lp7z+AmCgns1QOl+80Rr6USvcaQFTW3BVUrcBsKA/OxT3IHy4LmL/Hz03MaAgU40= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1617093893; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; bh=Nc7AXgUrizcOMIE5M9bEeC721jobvtzbCBMSL78Psx0=; b=Kahtprp4nOHzosYxGHkJvespJb/VomovfkwGq/LaDb0j7yFQEWKliomCUeSwsZdp5DPgLkndGsEMsx/CeIO3BfNgoSttNKDEoPFFaMCYaUlORhLJZRqWWaKiClgro0R7EUQtPonRnXr4EEKUoy5e7IvqOdyyk/mVbuWayr+JkH0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+73524+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1617093893876829.5831470176248; Tue, 30 Mar 2021 01:44:53 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id bMO7YY1788612xSqizSS0Ig4; Tue, 30 Mar 2021 01:44:53 -0700 X-Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web11.1764.1617093887341270266 for ; Tue, 30 Mar 2021 01:44:47 -0700 IronPort-SDR: gIiw7EzEFs3cDnAaJwtbR4yXAwwYoD7Om8HNu3WdbOXXvJMymGjVRQb4Lkzro6thXFTvCNZRQi TDbS6Maq2uyA== X-IronPort-AV: E=McAfee;i="6000,8403,9938"; a="189475595" X-IronPort-AV: E=Sophos;i="5.81,290,1610438400"; d="scan'208";a="189475595" X-Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2021 01:44:46 -0700 IronPort-SDR: joGTcFywVPuygZb1WfwGZmFLMLxLMlB4L9U42VxHMyE0gqCvUZwMczCCG66So1ia1BIl+VzAr1 jUN5ypGRUI2Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,290,1610438400"; d="scan'208";a="411508904" X-Received: from fieedk002.ccr.corp.intel.com ([10.239.158.144]) by fmsmga008.fm.intel.com with ESMTP; 30 Mar 2021 01:44:44 -0700 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: Guo Dong , Benjamin You , Aiden Park , Maurice Ma Subject: [edk2-devel] [PATCH] UefiPayloadPkg: UefiPayload retrieve PCI root bridge from Guid Hob Date: Tue, 30 Mar 2021 16:44:31 +0800 Message-Id: <20210330084431.1352-1-zhiguang.liu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,zhiguang.liu@intel.com X-Gm-Message-State: 6hK9bWeh3EuyjiSQeAH8OkBmx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1617093893; bh=EUab5EnmalgSs6yAY4ypYzgJgoYwMyDOWtHzdlpzYVk=; h=Cc:Date:From:Reply-To:Subject:To; b=K5tiAGsiJ1OoV0MHFlzztcHZYiT9sYg6MPB3GdeRoGQjbMm2WKfoFBs25NcNKkH1peI B9jSMoyYlf5iUptc3r9SqB9pq9f+NKUnuzMKZ2UwEO3Gdp84aC5BDBaWYSl3ijfST5r6O 2O6U+jEGM18s37SH8ilQV8Koiqe0yjVwOwo= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" UefiPayload parse gPldPciRootBridgeInfoGuid Guid Hob to retrieve PCI root b= ridges information. gPldPciRootBridgeInfoGuid Guid Hob should be created by Bootlo= ader. Cc: Guo Dong Cc: Benjamin You Signed-off-by: Aiden Park Signed-off-by: Maurice Ma Signed-off-by: Zhiguang Liu Reviewed-by: Ray Ni --- UefiPayloadPkg/Include/Guid/PldPciRootBridgeInfoHob.h | 54 ++++++= ++++++++++++++++++++++++++++++++++++++++++++++++ UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h | 40 ++++++= ++++++++++++++++++++++++++++++++-- UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c | 41 ++++++= ++++++++++++++++++++++++++++++++--- UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf | 9 ++++++= ++- UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c | 81 ++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++- UefiPayloadPkg/UefiPayloadPkg.dec | 11 ++++++= ----- 6 files changed, 224 insertions(+), 12 deletions(-) diff --git a/UefiPayloadPkg/Include/Guid/PldPciRootBridgeInfoHob.h b/UefiPa= yloadPkg/Include/Guid/PldPciRootBridgeInfoHob.h new file mode 100644 index 0000000000..47a9a7aeb2 --- /dev/null +++ b/UefiPayloadPkg/Include/Guid/PldPciRootBridgeInfoHob.h @@ -0,0 +1,54 @@ +/** @file + This file defines the hob structure for the PCI Root Bridge Info. + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PLD_PCI_ROOT_BRIDGE_INFO_HOB_H__ +#define __PLD_PCI_ROOT_BRIDGE_INFO_HOB_H__ + +#include +#include + +/// +/// Payload PCI Root Bridge Information HOB +/// +typedef struct { + UINT32 Segment; ///< Segment number. + UINT64 Supports; ///< Supported attribute= s. + ///< Refer to EFI_PCI_AT= TRIBUTE_xxx used by GetAttributes() + ///< and SetAttributes()= in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + UINT64 Attributes; ///< Initial attributes. + ///< Refer to EFI_PCI_AT= TRIBUTE_xxx used by GetAttributes() + ///< and SetAttributes()= in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + BOOLEAN DmaAbove4G; ///< DMA above 4GB memor= y. + ///< Set to TRUE when ro= ot bridge supports DMA above 4GB memory. + BOOLEAN NoExtendedConfigSpace; ///< When FALSE, the roo= t bridge supports + ///< Extended (4096-byte= ) Configuration Space. + ///< When TRUE, the root= bridge supports + ///< 256-byte Configurat= ion Space only. + BOOLEAN ResourceAssigned; ///< Resource assignment= status of the root bridge. + ///< Set to TRUE if Bus/= IO/MMIO resources for root bridge have been assigned. + UINT64 AllocationAttributes; ///< Allocation attribut= es. + ///< Refer to EFI_PCI_HO= ST_BRIDGE_COMBINE_MEM_PMEM and + ///< EFI_PCI_HOST_BRIDGE= _MEM64_DECODE used by GetAllocAttributes() + ///< in EFI_PCI_HOST_BRI= DGE_RESOURCE_ALLOCATION_PROTOCOL. + PCI_ROOT_BRIDGE_APERTURE Bus; ///< Bus aperture which = can be used by the root bridge. + PCI_ROOT_BRIDGE_APERTURE Io; ///< IO aperture which c= an be used by the root bridge. + PCI_ROOT_BRIDGE_APERTURE Mem; ///< MMIO aperture below= 4GB which can be used by the root bridge. + PCI_ROOT_BRIDGE_APERTURE MemAbove4G; ///< MMIO aperture above= 4GB which can be used by the root bridge. + PCI_ROOT_BRIDGE_APERTURE PMem; ///< Prefetchable MMIO a= perture below 4GB which can be used by the root bridge. + PCI_ROOT_BRIDGE_APERTURE PMemAbove4G; ///< Prefetchable MMIO a= perture above 4GB which can be used by the root bridge. + UINT32 HID; + UINT32 UID; +} PLD_PCI_ROOT_BRIDGE; + +typedef struct { + UINT8 Revision; + UINT8 Count; + PLD_PCI_ROOT_BRIDGE RootBridge[0]; +} PLD_PCI_ROOT_BRIDGE_INFO_HOB; + +#endif // __PLD_PCI_ROOT_BRIDGE_INFO_HOB_H__ diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h b/Uefi= PayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h index c2961b3bee..f6cb2a25d9 100644 --- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h +++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h @@ -2,7 +2,7 @@ Header file of PciHostBridgeLib. =20 Copyright (C) 2016, Red Hat, Inc. - Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -11,14 +11,38 @@ #ifndef _PCI_HOST_BRIDGE_H #define _PCI_HOST_BRIDGE_H =20 +#include + typedef struct { ACPI_HID_DEVICE_PATH AcpiDevicePath; EFI_DEVICE_PATH_PROTOCOL EndDevicePath; } CB_PCI_ROOT_BRIDGE_DEVICE_PATH; =20 +/** + Scan for all root bridges in platform. + + @param[out] NumberOfRootBridges Number of root bridges detected + + @retval Pointer to the allocated PCI_ROOT_BRIDGE structure array. +**/ PCI_ROOT_BRIDGE * ScanForRootBridges ( - UINTN *NumberOfRootBridges + OUT UINTN *NumberOfRootBridges +); + +/** + Scan for all root bridges from PldPciRootBridgeInfoHob + + @param[in] PciRootBridgeInfo Pointer of PLD PCI Root Bridge Info Hob + @param[out] NumberOfRootBridges Number of root bridges detected + + @retval Pointer to the allocated PCI_ROOT_BRIDGE structure array. + +**/ +PCI_ROOT_BRIDGE * +RetrieveRootBridgeInfoFromHob ( + IN PLD_PCI_ROOT_BRIDGE_INFO_HOB *PciRootBridgeInfo, + OUT UINTN *NumberOfRootBridges ); =20 /** @@ -77,4 +101,16 @@ InitRootBridge ( OUT PCI_ROOT_BRIDGE *RootBus ); =20 +/** + Initialize DevicePath for a PCI_ROOT_BRIDGE. + @param[in] HID HID for device path + @param[in] UID UID for device path + + @retval A pointer to the new created device patch. +**/ +EFI_DEVICE_PATH_PROTOCOL * +CreateRootBridgeDevicePath ( + IN UINT32 HID, + IN UINT32 UID +); #endif diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c b/U= efiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c index 512c3127cc..8af98dc16a 100644 --- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c +++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c @@ -2,7 +2,7 @@ Library instance of PciHostBridgeLib library class for coreboot. =20 Copyright (C) 2016, Red Hat, Inc. - Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -19,6 +19,7 @@ #include #include #include +#include =20 #include "PciHostBridge.h" =20 @@ -48,7 +49,6 @@ CB_PCI_ROOT_BRIDGE_DEVICE_PATH mRootBridgeDevicePathTempl= ate =3D { } }; =20 - /** Initialize a PCI_ROOT_BRIDGE structure. =20 @@ -145,6 +145,27 @@ InitRootBridge ( return EFI_SUCCESS; } =20 +/** + Initialize DevicePath for a PCI_ROOT_BRIDGE. + @param[in] HID HID for device path + @param[in] UID UID for device path + + @retval A pointer to the new created device patch. +**/ +EFI_DEVICE_PATH_PROTOCOL * +CreateRootBridgeDevicePath ( + IN UINT32 HID, + IN UINT32 UID +) +{ + CB_PCI_ROOT_BRIDGE_DEVICE_PATH *DevicePath; + DevicePath =3D AllocateCopyPool (sizeof (mRootBridgeDevicePathTemplate), + &mRootBridgeDevicePathTemplate); + ASSERT (DevicePath !=3D NULL); + DevicePath->AcpiDevicePath.HID =3D HID; + DevicePath->AcpiDevicePath.UID =3D UID; + return (EFI_DEVICE_PATH_PROTOCOL *)DevicePath; +} =20 /** Return all the root bridge instances in an array. @@ -161,10 +182,24 @@ PciHostBridgeGetRootBridges ( UINTN *Count ) { + PLD_PCI_ROOT_BRIDGE_INFO_HOB *PciRootBridgeInfo; + EFI_HOB_GUID_TYPE *GuidHob; + // + // Find PLD PCI Root Bridge Info hob + // + GuidHob =3D GetFirstGuidHob (&gPldPciRootBridgeInfoGuid); + if (GuidHob !=3D NULL) { + PciRootBridgeInfo =3D (PLD_PCI_ROOT_BRIDGE_INFO_HOB *) GET_GUID_HOB_DA= TA (GuidHob); + // + // The count of Root Bridge must be not large than the maximum Root Br= idge number that the Hob can carry + // + if (PciRootBridgeInfo->Count <=3D (GuidHob->Header.HobLength - sizeof(= PLD_PCI_ROOT_BRIDGE_INFO_HOB)) / sizeof(PLD_PCI_ROOT_BRIDGE)) { + return RetrieveRootBridgeInfoFromHob (PciRootBridgeInfo, Count); + } + } return ScanForRootBridges (Count); } =20 - /** Free the root bridge instances array returned from PciHostBridgeGetRootBridges(). diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf b= /UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf index 7896df2416..ba31d718b8 100644 --- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf +++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf @@ -2,7 +2,7 @@ # Library instance of PciHostBridgeLib library class for coreboot. # # Copyright (C) 2016, Red Hat, Inc. -# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -32,6 +32,7 @@ [Packages] MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec + UefiPayloadPkg/UefiPayloadPkg.dec =20 [LibraryClasses] BaseMemoryLib @@ -39,3 +40,9 @@ DevicePathLib MemoryAllocationLib PciLib + +[Guids] + gPldPciRootBridgeInfoGuid + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c= b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c index fffbf04cad..eb2d54fedc 100644 --- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c +++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c @@ -1,7 +1,7 @@ /** @file Scan the entire PCI bus for root bridges to support coreboot UEFI payloa= d. =20 - Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -582,3 +582,82 @@ ScanForRootBridges ( =20 return RootBridges; } + +/** + Scan for all root bridges from PldPciRootBridgeInfoHob + + @param[in] PciRootBridgeInfo Pointer of PLD PCI Root Bridge Info Hob + @param[out] NumberOfRootBridges Number of root bridges detected + + @retval Pointer to the allocated PCI_ROOT_BRIDGE structure array. + +**/ +PCI_ROOT_BRIDGE * +RetrieveRootBridgeInfoFromHob ( + IN PLD_PCI_ROOT_BRIDGE_INFO_HOB *PciRootBridgeInfo, + OUT UINTN *NumberOfRootBridges +) +{ + PCI_ROOT_BRIDGE *PciRootBridges; + UINTN Size; + UINT8 Index; + BOOLEAN ResourceAssigned; + + ASSERT (PciRootBridgeInfo !=3D NULL); + ASSERT (NumberOfRootBridges !=3D NULL); + if (PciRootBridgeInfo =3D=3D NULL) { + return NULL; + } + if (PciRootBridgeInfo->Count =3D=3D 0) { + return NULL; + } + Size =3D PciRootBridgeInfo->Count * sizeof (PCI_ROOT_BRIDGE); + PciRootBridges =3D (PCI_ROOT_BRIDGE *) AllocatePool (Size); + ASSERT (PciRootBridges !=3D NULL); + if (PciRootBridges =3D=3D NULL) { + return NULL; + } + ZeroMem (PciRootBridges, PciRootBridgeInfo->Count * sizeof (PCI_ROOT_BRI= DGE)); + + // + // Create all root bridges with PciRootBridgeInfoHob + // + for (Index =3D 0; Index < PciRootBridgeInfo->Count; Index++) { + PciRootBridges[Index].Segment =3D PciRootBridgeInfo->Roo= tBridge[Index].Segment; + PciRootBridges[Index].Supports =3D PciRootBridgeInfo->Roo= tBridge[Index].Supports; + PciRootBridges[Index].Attributes =3D PciRootBridgeInfo->Roo= tBridge[Index].Attributes; + PciRootBridges[Index].DmaAbove4G =3D PciRootBridgeInfo->Roo= tBridge[Index].DmaAbove4G; + PciRootBridges[Index].NoExtendedConfigSpace =3D PciRootBridgeInfo->Roo= tBridge[Index].NoExtendedConfigSpace; + PciRootBridges[Index].ResourceAssigned =3D PciRootBridgeInfo->Roo= tBridge[Index].ResourceAssigned; + PciRootBridges[Index].AllocationAttributes =3D PciRootBridgeInfo->Roo= tBridge[Index].AllocationAttributes; + PciRootBridges[Index].DevicePath =3D CreateRootBridgeDevice= Path(PciRootBridgeInfo->RootBridge[Index].HID, PciRootBridgeInfo->RootBridg= e[Index].UID); + CopyMem(&PciRootBridges[Index].Bus, &PciRootBridgeInfo->RootBr= idge[Index].Bus, sizeof(PCI_ROOT_BRIDGE_APERTURE)); + CopyMem(&PciRootBridges[Index].Io, &PciRootBridgeInfo->RootBr= idge[Index].Io, sizeof(PCI_ROOT_BRIDGE_APERTURE)); + CopyMem(&PciRootBridges[Index].Mem, &PciRootBridgeInfo->RootBr= idge[Index].Mem, sizeof(PCI_ROOT_BRIDGE_APERTURE)); + CopyMem(&PciRootBridges[Index].MemAbove4G, &PciRootBridgeInfo->RootBr= idge[Index].MemAbove4G, sizeof(PCI_ROOT_BRIDGE_APERTURE)); + CopyMem(&PciRootBridges[Index].PMem, &PciRootBridgeInfo->RootBr= idge[Index].PMem, sizeof(PCI_ROOT_BRIDGE_APERTURE)); + CopyMem(&PciRootBridges[Index].PMemAbove4G, &PciRootBridgeInfo->RootBr= idge[Index].PMemAbove4G, sizeof(PCI_ROOT_BRIDGE_APERTURE)); + } + + *NumberOfRootBridges =3D PciRootBridgeInfo->Count; + ResourceAssigned =3D PciRootBridges[0].ResourceAssigned; + for (Index =3D 1; Index < PciRootBridgeInfo->Count; Index++) { + if (PciRootBridges[Index].ResourceAssigned !=3D ResourceAssigned) { + DEBUG ((DEBUG_ERROR, "All root birdges' field ResourceAssigned shoul= d be the same\n")); + return NULL; + } + } + + // + // Now, this library only supports RootBridge that ResourceAssigned is T= rue + // + if (ResourceAssigned) { + PcdSetBoolS (PcdPciDisableBusEnumeration, TRUE); + } else { + DEBUG ((DEBUG_ERROR, "There is root bridge whose ResourceAssigned is F= ALSE\n")); + PcdSetBoolS (PcdPciDisableBusEnumeration, FALSE); + return NULL; + } + + return PciRootBridges; +} diff --git a/UefiPayloadPkg/UefiPayloadPkg.dec b/UefiPayloadPkg/UefiPayload= Pkg.dec index 99cb3311a6..a655a374e1 100644 --- a/UefiPayloadPkg/UefiPayloadPkg.dec +++ b/UefiPayloadPkg/UefiPayloadPkg.dec @@ -3,7 +3,7 @@ # # Provides drivers and definitions to create uefi payload for bootloaders. # -# Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -29,10 +29,11 @@ # gBmpImageGuid =3D { 0x878AC2CC, 0x5343, 0x46F2= , { 0xB5, 0x63, 0x51, 0xF8, 0x9D, 0xAF, 0x56, 0xBA } } =20 - gUefiSystemTableInfoGuid =3D {0x16c8a6d0, 0xfe8a, 0x4082, {0xa2, 0x8, 0x= cf, 0x89, 0xc4, 0x29, 0x4, 0x33}} - gUefiAcpiBoardInfoGuid =3D {0xad3d31b, 0xb3d8, 0x4506, {0xae, 0x71, 0x= 2e, 0xf1, 0x10, 0x6, 0xd9, 0xf}} - gUefiSerialPortInfoGuid =3D { 0x6c6872fe, 0x56a9, 0x4403, { 0xbb, 0x98,= 0x95, 0x8d, 0x62, 0xde, 0x87, 0xf1 } } - gLoaderMemoryMapInfoGuid =3D { 0xa1ff7424, 0x7a1a, 0x478e, { 0xa9, 0xe4,= 0x92, 0xf3, 0x57, 0xd1, 0x28, 0x32 } } + gUefiSystemTableInfoGuid =3D { 0x16c8a6d0, 0xfe8a, 0x4082, { 0xa2, 0x08= , 0xcf, 0x89, 0xc4, 0x29, 0x04, 0x33 }} + gUefiAcpiBoardInfoGuid =3D { 0x0ad3d31b, 0xb3d8, 0x4506, { 0xae, 0x71= , 0x2e, 0xf1, 0x10, 0x06, 0xd9, 0x0f }} + gUefiSerialPortInfoGuid =3D { 0x6c6872fe, 0x56a9, 0x4403, { 0xbb, 0x98= , 0x95, 0x8d, 0x62, 0xde, 0x87, 0xf1 }} + gLoaderMemoryMapInfoGuid =3D { 0xa1ff7424, 0x7a1a, 0x478e, { 0xa9, 0xe4= , 0x92, 0xf3, 0x57, 0xd1, 0x28, 0x32 }} + gPldPciRootBridgeInfoGuid =3D { 0xec4ebacb, 0x2638, 0x416e, { 0xbe, 0x80= , 0xe5, 0xfa, 0x4b, 0x51, 0x19, 0x01 }} =20 [Ppis] gEfiPayLoadHobBasePpiGuid =3D { 0xdbe23aa1, 0xa342, 0x4b97, {0x85, 0xb6,= 0xb2, 0x26, 0xf1, 0x61, 0x73, 0x89} } --=20 2.30.0.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#73524): https://edk2.groups.io/g/devel/message/73524 Mute This Topic: https://groups.io/mt/81717538/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-