REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3224

- Fix the Teton Glacier Endpoint entry in mPciDeviceTable

Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Heng Luo <heng.luo@intel.com>
Signed-off-by: Takuto Naito <naitaku@gmail.com>
---

Notes:
    v2:
    - Split the v1 patch into 2 patches,
      One is for Platform/Intel/TigerlakeOpenBoardPkg,
      another one is for edk2-platforms\Silicon\Intel\TigerlakeSiliconPkg.

 .../DxePchPcieRpPolicyLib/DxePchPcieRpPolicyLib.c               | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/DxePchPcieRpPolicyLib/DxePchPcieRpPolicyLib.c b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/DxePchPcieRpPolicyLib/DxePchPcieRpPolicyLib.c
index 577e436e32..1553d2e2aa 100644
--- a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/DxePchPcieRpPolicyLib/DxePchPcieRpPolicyLib.c
+++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/DxePchPcieRpPolicyLib/DxePchPcieRpPolicyLib.c
@@ -98,7 +98,7 @@ GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[] = {
   //
   // Teton Glacier Endpoint
   //
-  { 0x8086, 0x0975, 0xff, 0, 0, 0, PchPcieL1SubstatesOverride, 0, 0xff, 0x3C, 0, 5, 0, 0, 0, 0 },
+  { 0x8086, 0x0975, 0xff, 0, 0, 0, PchPcieL1SubstatesOverride, 0, 0xff, 0x3C, 0, 5, 0, 0 },
 
   //
   // End of Table
-- 
2.30.1



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Reviewed-by: Heng Luo <heng.luo@intel.com>

> -----Original Message-----
> From: Takuto Naito <naitaku@gmail.com>
> Sent: Sunday, February 21, 2021 11:10 PM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone,
> Nathaniel L <nathaniel.l.desimone@intel.com>; Luo, Heng <heng.luo@intel.com>
> Subject: [PATCH v2 2/2] TigerlakeSiliconPkg/IpBlock: Fix build errors with GCC5
> 
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3224
> 
> - Fix the Teton Glacier Endpoint entry in mPciDeviceTable
> 
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Heng Luo <heng.luo@intel.com>
> Signed-off-by: Takuto Naito <naitaku@gmail.com>
> ---
> 
> Notes:
>     v2:
>     - Split the v1 patch into 2 patches,
>       One is for Platform/Intel/TigerlakeOpenBoardPkg,
>       another one is for edk2-platforms\Silicon\Intel\TigerlakeSiliconPkg.
> 
>  .../DxePchPcieRpPolicyLib/DxePchPcieRpPolicyLib.c               | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git
> a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/DxePchPcieRp
> PolicyLib/DxePchPcieRpPolicyLib.c
> b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/DxePchPcieRp
> PolicyLib/DxePchPcieRpPolicyLib.c
> index 577e436e32..1553d2e2aa 100644
> ---
> a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/DxePchPcieRp
> PolicyLib/DxePchPcieRpPolicyLib.c
> +++
> b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/DxePchPcieRp
> PolicyLib/DxePchPcieRpPolicyLib.c
> @@ -98,7 +98,7 @@ GLOBAL_REMOVE_IF_UNREFERENCED
> PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[] = {
>    //
>    // Teton Glacier Endpoint
>    //
> -  { 0x8086, 0x0975, 0xff, 0, 0, 0, PchPcieL1SubstatesOverride, 0, 0xff, 0x3C, 0, 5,
> 0, 0, 0, 0 },
> +  { 0x8086, 0x0975, 0xff, 0, 0, 0, PchPcieL1SubstatesOverride, 0, 0xff, 0x3C, 0, 5,
> 0, 0 },
> 
>    //
>    // End of Table
> --
> 2.30.1



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