IntelFsp2Pkg/Include/Guid/FspHeaderFile.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-)
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2698
To enhance FSP silicon initialization flexibility an
optional Multi-Phase API is introduced and FSP header
needs update for new API offset.
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
IntelFsp2Pkg/Include/Guid/FspHeaderFile.h | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h b/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h
index 16f43a1273..3474bac1de 100644
--- a/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h
+++ b/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h
@@ -1,8 +1,8 @@
/** @file
Intel FSP Header File definition from Intel Firmware Support Package External
- Architecture Specification v2.0.
+ Architecture Specification v2.0 and above.
- Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -110,6 +110,12 @@ typedef struct {
/// Byte 0x44: The offset for the API to initialize the CPU and chipset.
///
UINT32 FspSiliconInitEntryOffset;
+ ///
+ /// Byte 0x48: Offset for the API for the optional Multi-Phase processor and chipset initialization.
+ /// This value is only valid if FSP HeaderRevision is >= 5.
+ /// If the value is set to 0x00000000, then this API is not available in this component.
+ ///
+ UINT32 FspMultiPhaseSiInitEntryOffset;
} FSP_INFO_HEADER;
///
--
2.13.3.windows.1
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Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> -----Original Message----- From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Chiu, Chasel Sent: Wednesday, April 29, 2020 6:38 PM To: devel@edk2.groups.io Cc: Ma, Maurice <maurice.ma@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Zeng, Star <star.zeng@intel.com> Subject: [edk2-devel] [PATCH] IntelFsp2Pkg: Support Multi-Phase silicon initialization. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2698 To enhance FSP silicon initialization flexibility an optional Multi-Phase API is introduced and FSP header needs update for new API offset. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> --- IntelFsp2Pkg/Include/Guid/FspHeaderFile.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h b/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h index 16f43a1273..3474bac1de 100644 --- a/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h +++ b/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h @@ -1,8 +1,8 @@ /** @file Intel FSP Header File definition from Intel Firmware Support Package External - Architecture Specification v2.0. + Architecture Specification v2.0 and above. - Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR> + Copyright (c) 2014 - 2020, Intel Corporation. All rights + reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -110,6 +110,12 @@ typedef struct { /// Byte 0x44: The offset for the API to initialize the CPU and chipset. /// UINT32 FspSiliconInitEntryOffset; + /// + /// Byte 0x48: Offset for the API for the optional Multi-Phase processor and chipset initialization. + /// This value is only valid if FSP HeaderRevision is >= 5. + /// If the value is set to 0x00000000, then this API is not available in this component. + /// + UINT32 FspMultiPhaseSiInitEntryOffset; } FSP_INFO_HEADER; /// -- 2.13.3.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#58480): https://edk2.groups.io/g/devel/message/58480 Mute This Topic: https://groups.io/mt/73367408/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
Reviewed-by: Star Zeng <star.zeng@intel.com> > -----Original Message----- > From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com> > Sent: Friday, May 1, 2020 5:59 AM > To: devel@edk2.groups.io; Chiu, Chasel <chasel.chiu@intel.com> > Cc: Ma, Maurice <maurice.ma@intel.com>; Zeng, Star <star.zeng@intel.com> > Subject: RE: [edk2-devel] [PATCH] IntelFsp2Pkg: Support Multi-Phase silicon > initialization. > > Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> > > -----Original Message----- > From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Chiu, > Chasel > Sent: Wednesday, April 29, 2020 6:38 PM > To: devel@edk2.groups.io > Cc: Ma, Maurice <maurice.ma@intel.com>; Desimone, Nathaniel L > <nathaniel.l.desimone@intel.com>; Zeng, Star <star.zeng@intel.com> > Subject: [edk2-devel] [PATCH] IntelFsp2Pkg: Support Multi-Phase silicon > initialization. > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2698 > > To enhance FSP silicon initialization flexibility an optional Multi-Phase API is > introduced and FSP header needs update for new API offset. > > Cc: Maurice Ma <maurice.ma@intel.com> > Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> > Cc: Star Zeng <star.zeng@intel.com> > Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> > --- > IntelFsp2Pkg/Include/Guid/FspHeaderFile.h | 10 ++++++++-- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h > b/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h > index 16f43a1273..3474bac1de 100644 > --- a/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h > +++ b/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h > @@ -1,8 +1,8 @@ > /** @file > Intel FSP Header File definition from Intel Firmware Support Package > External > - Architecture Specification v2.0. > + Architecture Specification v2.0 and above. > > - Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR> > + Copyright (c) 2014 - 2020, Intel Corporation. All rights > + reserved.<BR> > SPDX-License-Identifier: BSD-2-Clause-Patent > > **/ > @@ -110,6 +110,12 @@ typedef struct { > /// Byte 0x44: The offset for the API to initialize the CPU and chipset. > /// > UINT32 FspSiliconInitEntryOffset; > + /// > + /// Byte 0x48: Offset for the API for the optional Multi-Phase processor > and chipset initialization. > + /// This value is only valid if FSP HeaderRevision is >= 5. > + /// If the value is set to 0x00000000, then this API is not > available in this component. > + /// > + UINT32 FspMultiPhaseSiInitEntryOffset; > } FSP_INFO_HEADER; > > /// > -- > 2.13.3.windows.1 > > > > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#58487): https://edk2.groups.io/g/devel/message/58487 Mute This Topic: https://groups.io/mt/73367408/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
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