From nobody Sat May 4 07:05:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+58351+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+58351+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1588210685; cv=none; d=zohomail.com; s=zohoarc; b=k5041X1l3EI6P/QjRQ1799IaPpN9V0f4liDoQHEgRcNpZqbOxTzqzk0zZstFu4V5DKmPsH6sxijOhXqRuCHPZvfreMR9k6kLvxeUOo84a+BapMoMRRRMQk+n5Z+T885qIwrEU8rPcmtuiV42ekQ/Pf89550qBo0BxLThC0WjFxI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588210685; h=Cc:Date:From:List-Id:List-Unsubscribe:Message-ID:Reply-To:Sender:Subject:To; bh=dntGtZxid83YTVMolzXfP9K1BY9BMZCA+mJaxwDmv3Y=; b=Z5Mmbuy8A/2Mgvtw+AXqT/BmAT7/FLZ3JM9ggl6xQC0o1gluBAVx8NupegATVxqKtVG1tjjVDyjyAeuuJTnk2G4HQjybWa8QS3v23b0BpRRn7xJZ3I38bAKQEwvvhhdMj5ub0knORFXanFI7bAJMUeP1X+ctelWtTYAbm6AXyyk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+58351+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1588210685649947.8204498784553; Wed, 29 Apr 2020 18:38:05 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id X99gYY1788612xF0IE7BadiS; Wed, 29 Apr 2020 18:38:05 -0700 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web11.2024.1588210683909188472 for ; Wed, 29 Apr 2020 18:38:04 -0700 IronPort-SDR: aBRwayfr/26aKdbpgKcwJZWJzX05f5ENRDGSR+k+j3D4Ogul5GLIX1nVvIoUol56huSUZhpsdQ FGRtsQ8SDsjA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2020 18:38:02 -0700 IronPort-SDR: GbOAdHRx48QBF2I9a9wOGZVdg+vjevErCOs3sHV/CJV9ByF5H9isMP+8D2PSd6M0rfaatlmBYh b4RAOcK9GAoQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,333,1583222400"; d="scan'208";a="261611817" X-Received: from cchiu4-mobl1.gar.corp.intel.com ([10.215.151.72]) by orsmga006.jf.intel.com with ESMTP; 29 Apr 2020 18:38:00 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: Maurice Ma , Nate DeSimone , Star Zeng Subject: [edk2-devel] [PATCH] IntelFsp2Pkg: Support Multi-Phase silicon initialization. Date: Thu, 30 Apr 2020 09:37:45 +0800 Message-Id: <20200430013745.18528-1-chasel.chiu@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: <27952.devel.edk2.groups.io> Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chasel.chiu@intel.com X-Gm-Message-State: RZXCfzaBEfzHaJrY95T1SmY9x1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1588210685; bh=Bx298g5+t4Lbdd9N/fsVolHjzE++3btthcZiFfv5uqg=; h=Cc:Date:From:Reply-To:Subject:To; b=fKObS3mCnRdr5K9wxyVvvLAnxd+zeaks9xg2Kujxi0jUBEiGm2N1qqMyQs4aygzJWN2 UvXb81j1GEVU5VmRfwaVpeq4B1uA8MaXxK33b/YWRwvpcWvVC27tA9W/4qKuJv28L3Kj0 7YRbHWZNHGSZU8Swo7oPo35YquyeebrM71I= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2698 To enhance FSP silicon initialization flexibility an optional Multi-Phase API is introduced and FSP header needs update for new API offset. Cc: Maurice Ma Cc: Nate DeSimone Cc: Star Zeng Signed-off-by: Chasel Chiu Reviewed-by: Nate DeSimone Reviewed-by: Star Zeng --- IntelFsp2Pkg/Include/Guid/FspHeaderFile.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h b/IntelFsp2Pkg/Inclu= de/Guid/FspHeaderFile.h index 16f43a1273..3474bac1de 100644 --- a/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h +++ b/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h @@ -1,8 +1,8 @@ /** @file Intel FSP Header File definition from Intel Firmware Support Package Ext= ernal - Architecture Specification v2.0. + Architecture Specification v2.0 and above. =20 - Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -110,6 +110,12 @@ typedef struct { /// Byte 0x44: The offset for the API to initialize the CPU and chipset. /// UINT32 FspSiliconInitEntryOffset; + /// + /// Byte 0x48: Offset for the API for the optional Multi-Phase processor= and chipset initialization. + /// This value is only valid if FSP HeaderRevision is >=3D 5. + /// If the value is set to 0x00000000, then this API is not a= vailable in this component. + /// + UINT32 FspMultiPhaseSiInitEntryOffset; } FSP_INFO_HEADER; =20 /// --=20 2.13.3.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#58351): https://edk2.groups.io/g/devel/message/58351 Mute This Topic: https://groups.io/mt/73367408/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-