Add RISC-V architecture on RISC-V EDK2 CI testing.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Daniel Helmut Schaefer <daniel.schaefer@hpe.com>
---
.pytool/CISettings.py | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/.pytool/CISettings.py b/.pytool/CISettings.py
index 79593d9dc5..0111565ef8 100644
--- a/.pytool/CISettings.py
+++ b/.pytool/CISettings.py
@@ -1,6 +1,7 @@
# @file
#
# Copyright (c) Microsoft Corporation.
+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
##
import os
@@ -54,10 +55,12 @@ class Settings(CiBuildSettingsManager, UpdateSettingsManager, SetupSettingsManag
def GetArchitecturesSupported(self):
''' return iterable of edk2 architectures supported by this build '''
- return ("IA32",
+ return (
+ "IA32",
"X64",
"ARM",
- "AARCH64")
+ "AARCH64",
+ "RISCV64")
def GetTargetsSupported(self):
''' return iterable of edk2 target tags supported by this build '''
@@ -130,6 +133,8 @@ class Settings(CiBuildSettingsManager, UpdateSettingsManager, SetupSettingsManag
scopes += ("gcc_aarch64_linux",)
if "ARM" in self.ActualArchitectures:
scopes += ("gcc_arm_linux",)
+ if "RISCV64" in self.ActualArchitectures:
+ scopes += ("gcc_riscv64_unknown",)
return scopes
--
2.25.0
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