BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2598

All registers definition of DVSEC are defined as per the PCI Express Base
Specification 4.0 chapter 7.9.6.

Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>

V2: fixed the comment section description for DVSEC definitions
---
 MdePkg/Include/IndustryStandard/PciExpress40.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/MdePkg/Include/IndustryStandard/PciExpress40.h b/MdePkg/Include/IndustryStandard/PciExpress40.h
index 02c30a7757..0564d72861 100644
--- a/MdePkg/Include/IndustryStandard/PciExpress40.h
+++ b/MdePkg/Include/IndustryStandard/PciExpress40.h
@@ -77,7 +77,11 @@ typedef struct {
   UINT32                                                        Reserved;
   PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1];
 } PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0;
+///@}
 
+/// The Designated Vendor Specific Capability definitions
+/// Based on section 7.9.6 of PCI Express Base Specification 4.0.
+///@{
 typedef union {
   struct {
     UINT32 DvsecVendorId                                        : 16; //bit 0..15
-- 
2.21.0.windows.1


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