From nobody Sun Feb 8 07:32:59 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+55920+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55920+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1584431549; cv=none; d=zohomail.com; s=zohoarc; b=T/4ibOuS6cUfbOfOiXTY6FPC/j6lAt4kfpsj3tMqvqgtmFNIifNqrpMQe6UY/5xJmh+HH2iatmwaqJyfJKv1BN6/t4BGkuxoR9/S3dkAyRYwl8Nt14M4XUxhZV4pkT57C5z+LNQvtLgewyxLKiyHZFMEb7woXEADaVefzuwzAqE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1584431549; h=Content-Transfer-Encoding:Cc:Date:From:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; bh=wNAqmTX7x6rFZ2JJemFKAVkJ9Qs+KKiU26k1AusMlrA=; b=CMyAt5mlkd9umy8PBWEoiERZWm/ffBEx1AqA5liq0jM/Ns9gtUgiXZnv6/wjG0h1dNF9vLzo2pr3RIqS3rC8xE2pVLXFQXLCiQxRFbkEolv+npUqjJz4hB5RoL0EdKGgiP/DfIdMGg2ZuVItWrLTbkz+IonpDoeGf//saTKWeVQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55920+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1584431549517978.2416151333979; Tue, 17 Mar 2020 00:52:29 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 1p6PYY1788612xYisdjiLMmu; Tue, 17 Mar 2020 00:52:29 -0700 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web11.1005.1584431548336664528 for ; Tue, 17 Mar 2020 00:52:28 -0700 IronPort-SDR: Fnyac1fkUVBfsQeV46pgaaya58KG6nviK+TUsCGM96Ir+2KG5+2NQKSsskf8cPUolen694ym5q KORwlErw0VDw== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Mar 2020 00:52:27 -0700 IronPort-SDR: oFLwAVtmGEw+vMhFs4sYSAvzzSEJbyhMr0UmoW7356fb5PBlffBy+1iqHsDqFNbD5DwEvpA7Wh vJmou+Z1rS4Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,563,1574150400"; d="scan'208";a="236255993" X-Received: from unknown (HELO PIDSBABIOS005.gar.corp.intel.com) ([10.223.9.183]) by fmsmga007.fm.intel.com with ESMTP; 17 Mar 2020 00:52:25 -0700 From: "Javeed, Ashraf" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu Subject: [edk2-devel] [PATCH V2] MdePkg-PciExpress40.h: DVSEC definition missing Date: Tue, 17 Mar 2020 13:22:22 +0530 Message-Id: <20200317075222.2960-1-ashraf.javeed@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ashraf.javeed@intel.com X-Gm-Message-State: 70FnDWBmBMfz6tCLiEl8miigx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1584431549; bh=cxnMCgdVaFIbTNpsm+JQ/Gdy5WjoEgHiKHcINLXO5F4=; h=Cc:Date:From:Reply-To:Subject:To; b=KGSuTYYsutJeKwsjwFaOwwzqydn9Xy0T0+7E02mCL7Wmjw8HB8F943j7v0s/hMQB3S1 L7AgSAU+dnE0QkMSr9IJJm/aGpOwOD1xav7RXxjWB8PMZ9tDAdxU7baw9PGfWY2+DDcV/ 90NljRdUXsUTBcZ0uzHW7o+d9WXoo3wkQ3U= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2598 All registers definition of DVSEC are defined as per the PCI Express Base Specification 4.0 chapter 7.9.6. Signed-off-by: Ashraf Javeed Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu V2: fixed the comment section description for DVSEC definitions --- MdePkg/Include/IndustryStandard/PciExpress40.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/MdePkg/Include/IndustryStandard/PciExpress40.h b/MdePkg/Includ= e/IndustryStandard/PciExpress40.h index 02c30a7757..0564d72861 100644 --- a/MdePkg/Include/IndustryStandard/PciExpress40.h +++ b/MdePkg/Include/IndustryStandard/PciExpress40.h @@ -77,7 +77,11 @@ typedef struct { UINT32 Reserved; PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL LaneEquali= zationControl[1]; } PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0; +///@} =20 +/// The Designated Vendor Specific Capability definitions +/// Based on section 7.9.6 of PCI Express Base Specification 4.0. +///@{ typedef union { struct { UINT32 DvsecVendorId : 16; //bi= t 0..15 --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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