Initial version of SiFive RISC-V core libraries. Library of each core
creates processor core SMBIOS data hob for building SMBIOS
records in DXE phase.
Signed-off-by: Gilbert Chen <gilbert.chen@hpe.com>
---
.../E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c | 242 +++++++++++++++++
.../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 51 ++++
.../U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c | 294 +++++++++++++++++++++
.../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 51 ++++
.../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 185 +++++++++++++
.../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 50 ++++
6 files changed, 873 insertions(+)
create mode 100644 Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c
create mode 100644 Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
create mode 100644 Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c
create mode 100644 Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
create mode 100644 Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob.c
create mode 100644 Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
diff --git a/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c b/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c
new file mode 100644
index 00000000..b7140b53
--- /dev/null
+++ b/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c
@@ -0,0 +1,242 @@
+/**@file
+ Build up platform processor information.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include <PiPei.h>
+
+//
+// The Library classes this module consumes
+//
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/ResourcePublicationLib.h>
+
+#include <SmbiosProcessorSpecificData.h>
+
+#include <RiscV.h>
+#include <ProcessorSpecificDataHob.h>
+#include <sbi/sbi_hart.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi/sbi_platform.h>
+#include <sbi/sbi.h>
+#include <sbi/SbiFirmwareContext.h>
+#include <Library/FirmwareContextProcessorSpecificLib.h>
+
+/**
+ Function to build core specific information HOB. RISC-V SMBIOS DXE driver collect
+ this information and build SMBIOS Type44.
+
+ @param ParentProcessorGuid Parent processor od this core. ParentProcessorGuid
+ could be the same as CoreGuid if one processor has
+ only one core.
+ @param ParentProcessorUid Unique ID of pysical processor which owns this core.
+ @param HartId Hart ID of this core.
+ @param IsBootHart TRUE means this is the boot HART.
+ @param GuidHobData Pointer to receive EFI_HOB_GUID_TYPE.
+
+ @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateE51CoreProcessorSpecificDataHob (
+ IN EFI_GUID *ParentProcessorGuid,
+ IN UINTN ParentProcessorUid,
+ IN UINTN HartId,
+ IN BOOLEAN IsBootHart,
+ OUT RISC_V_PROCESSOR_SPECIFIC_DATA_HOB **GuidHobData
+ )
+{
+ RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *CoreGuidHob;
+ EFI_GUID *ProcessorSpecDataHobGuid;
+ RISC_V_PROCESSOR_SPECIFIC_DATA_HOB ProcessorSpecDataHob;
+ struct sbi_scratch *ThisHartSbiScratch;
+ struct sbi_platform *ThisHartSbiPlatform;
+ EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
+ EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *FirmwareContextHartSpecific;
+
+ DEBUG ((DEBUG_INFO, "%a: Entry.\n", __FUNCTION__));
+
+ if (GuidHobData == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ ThisHartSbiScratch = sbi_hart_id_to_scratch (sbi_scratch_thishart_ptr(), (UINT32)HartId);
+ DEBUG ((DEBUG_INFO, " SBI Scratch is at 0x%x.\n", ThisHartSbiScratch));
+ ThisHartSbiPlatform = (struct sbi_platform *)sbi_platform_ptr(ThisHartSbiScratch);
+ DEBUG ((DEBUG_INFO, " SBI platform is at 0x%x.\n", ThisHartSbiPlatform));
+ FirmwareContext = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)ThisHartSbiPlatform->firmware_context;
+ DEBUG ((DEBUG_INFO, " Firmware Context is at 0x%x.\n", FirmwareContext));
+ FirmwareContextHartSpecific = FirmwareContext->HartSpecific[HartId];
+ DEBUG ((DEBUG_INFO, " Firmware Context Hart specific is at 0x%x.\n", FirmwareContextHartSpecific));
+
+ //
+ // Build up RISC_V_PROCESSOR_SPECIFIC_DATA_HOB.
+ //
+ CommonFirmwareContextHartSpecificInfo (
+ FirmwareContextHartSpecific,
+ ParentProcessorGuid,
+ ParentProcessorUid,
+ (EFI_GUID *)PcdGetPtr (PcdSiFiveE51CoreGuid),
+ HartId,
+ IsBootHart,
+ &ProcessorSpecDataHob
+ );
+ ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_L = TO_BE_FILLED;
+ ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_H = TO_BE_FILLED;
+ ProcessorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Value64_L = TO_BE_FILLED;
+ ProcessorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Value64_H = TO_BE_FILLED;
+ ProcessorSpecDataHob.ProcessorSpecificData.HartXlen = RegisterLen64;
+ ProcessorSpecDataHob.ProcessorSpecificData.MachineModeXlen = RegisterLen64;
+ ProcessorSpecDataHob.ProcessorSpecificData.SupervisorModeXlen = RegisterUnsupported;
+ ProcessorSpecDataHob.ProcessorSpecificData.UserModeXlen = RegisterLen64;
+
+ DEBUG ((DEBUG_INFO, " *HartId = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.HartId.Value64_L));
+ DEBUG ((DEBUG_INFO, " *Is Boot Hart? = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.BootHartId));
+ DEBUG ((DEBUG_INFO, " *PrivilegeModeSupported = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.PrivilegeModeSupported));
+ DEBUG ((DEBUG_INFO, " *MModeExcepDelegation = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_L));
+ DEBUG ((DEBUG_INFO, " *MModeInterruptDelegation = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Value64_L));
+ DEBUG ((DEBUG_INFO, " *HartXlen = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.HartXlen ));
+ DEBUG ((DEBUG_INFO, " *MachineModeXlen = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.MachineModeXlen));
+ DEBUG ((DEBUG_INFO, " *SupervisorModeXlen = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.SupervisorModeXlen));
+ DEBUG ((DEBUG_INFO, " *UserModeXlen = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.UserModeXlen));
+ DEBUG ((DEBUG_INFO, " *InstSetSupported = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.InstSetSupported));
+ DEBUG ((DEBUG_INFO, " *MachineVendorId = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.MachineVendorId.Value64_L));
+ DEBUG ((DEBUG_INFO, " *MachineArchId = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.MachineArchId.Value64_L));
+ DEBUG ((DEBUG_INFO, " *MachineImplId = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.MachineImplId.Value64_L));
+
+ //
+ // Build GUID HOB for E51 core, this is for SMBIOS type 44
+ //
+ ProcessorSpecDataHobGuid = PcdGetPtr (PcdProcessorSpecificDataGuidHobGuid);
+ CoreGuidHob = (RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *)BuildGuidDataHob (ProcessorSpecDataHobGuid, (VOID *)&ProcessorSpecDataHob, sizeof (RISC_V_PROCESSOR_SPECIFIC_DATA_HOB));
+ if (CoreGuidHob == NULL) {
+ DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive E51 core.\n"));
+ ASSERT (FALSE);
+ }
+ *GuidHobData = CoreGuidHob;
+ return EFI_SUCCESS;
+}
+
+/**
+ Function to build processor related SMBIOS information. RISC-V SMBIOS DXE driver collect
+ this information and build SMBIOS Type4 and Type7 record.
+
+ @param ProcessorUid Unique ID of pysical processor which owns this core.
+ @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_DATA_HOB. The pointers
+ maintained in this structure is only valid before memory is discovered.
+ Access to those pointers after memory is installed will cause unexpected issues.
+
+ @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateE51ProcessorSmbiosDataHob (
+ IN UINTN ProcessorUid,
+ OUT RISC_V_PROCESSOR_SMBIOS_DATA_HOB **SmbiosHobPtr
+ )
+{
+ EFI_GUID *GuidPtr;
+ RISC_V_PROCESSOR_TYPE4_DATA_HOB ProcessorDataHob;
+ RISC_V_PROCESSOR_TYPE7_DATA_HOB L1InstCacheDataHob;
+ RISC_V_PROCESSOR_SMBIOS_DATA_HOB SmbiosDataHob;
+ RISC_V_PROCESSOR_TYPE4_DATA_HOB *ProcessorDataHobPtr;
+ RISC_V_PROCESSOR_TYPE7_DATA_HOB *L1InstCacheDataHobPtr;
+ RISC_V_PROCESSOR_SMBIOS_DATA_HOB *SmbiosDataHobPtr;
+
+ if (SmbiosHobPtr == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+ //
+ // Build up SMBIOS type 7 L1 instruction cache record.
+ //
+ ZeroMem((VOID *)&L1InstCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_DATA_HOB));
+ CopyGuid (&L1InstCacheDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSiFiveE51CoreGuid));
+ L1InstCacheDataHob.ProcessorUid = ProcessorUid;
+ L1InstCacheDataHob.SmbiosType7Cache.SocketDesignation = TO_BE_FILLED_BY_VENDOR;
+ L1InstCacheDataHob.SmbiosType7Cache.CacheConfiguration = RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1 | \
+ RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL | \
+ RISC_V_CACHE_CONFIGURATION_ENABLED | \
+ RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN;
+ L1InstCacheDataHob.SmbiosType7Cache.MaximumCacheSize = TO_BE_FILLED_BY_VENDOR;
+ L1InstCacheDataHob.SmbiosType7Cache.InstalledSize = TO_BE_FILLED_BY_VENDOR;
+ L1InstCacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown = 1;
+ L1InstCacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown = 1;
+ L1InstCacheDataHob.SmbiosType7Cache.CacheSpeed = TO_BE_FILLED_BY_VENDOR;
+ L1InstCacheDataHob.SmbiosType7Cache.ErrorCorrectionType = TO_BE_FILLED_BY_VENDOR;
+ L1InstCacheDataHob.SmbiosType7Cache.SystemCacheType = CacheTypeInstruction;
+ L1InstCacheDataHob.SmbiosType7Cache.Associativity = TO_BE_FILLED_BY_VENDOR;
+ GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid);
+ L1InstCacheDataHobPtr = (RISC_V_PROCESSOR_TYPE7_DATA_HOB *)BuildGuidDataHob (GuidPtr, (VOID *)&L1InstCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_DATA_HOB));
+ if (L1InstCacheDataHobPtr == NULL) {
+ DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive E51 core L1 instruction cache RISC_V_PROCESSOR_TYPE7_DATA_HOB.\n"));
+ ASSERT (FALSE);
+ }
+
+ //
+ // Build up SMBIOS type 4 record.
+ //
+ ZeroMem((VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_DATA_HOB));
+ CopyGuid (&ProcessorDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSiFiveE51CoreGuid));
+ ProcessorDataHob.ProcessorUid = ProcessorUid;
+ ProcessorDataHob.SmbiosType4Processor.Socket = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.ProcessorType = CentralProcessor;
+ ProcessorDataHob.SmbiosType4Processor.ProcessorFamily = ProcessorFamilyIndicatorFamily2;
+ ProcessorDataHob.SmbiosType4Processor.ProcessorManufacture = TO_BE_FILLED_BY_VENDOR;
+ SetMem ((VOID *)&ProcessorDataHob.SmbiosType4Processor.ProcessorId, sizeof (PROCESSOR_ID_DATA), TO_BE_FILLED_BY_CODE);
+ ProcessorDataHob.SmbiosType4Processor.ProcessorVersion = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.Voltage.ProcessorVoltageCapability3_3V = 1;
+ ProcessorDataHob.SmbiosType4Processor.ExternalClock = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.MaxSpeed = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.CurrentSpeed = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.Status = TO_BE_FILLED_BY_CODE;
+ ProcessorDataHob.SmbiosType4Processor.ProcessorUpgrade = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.L1CacheHandle = TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER;
+ ProcessorDataHob.SmbiosType4Processor.L2CacheHandle = 0xffff;
+ ProcessorDataHob.SmbiosType4Processor.L3CacheHandle = 0xffff;
+ ProcessorDataHob.SmbiosType4Processor.SerialNumber = TO_BE_FILLED_BY_CODE;
+ ProcessorDataHob.SmbiosType4Processor.AssetTag = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.PartNumber = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.CoreCount = 1;
+ ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount = 1;
+ ProcessorDataHob.SmbiosType4Processor.ThreadCount = 1;
+ ProcessorDataHob.SmbiosType4Processor.ProcessorCharacteristics = (UINT16)(1 << 2); // 64-bit capable
+ ProcessorDataHob.SmbiosType4Processor.ProcessorFamily2 = ProcessorFamilyRiscVRV64;
+ ProcessorDataHob.SmbiosType4Processor.CoreCount2 = 0;
+ ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount2 = 0;
+ ProcessorDataHob.SmbiosType4Processor.ThreadCount2 = 0;
+ GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType4GuidHobGuid);
+ ProcessorDataHobPtr = (RISC_V_PROCESSOR_TYPE4_DATA_HOB *)BuildGuidDataHob (GuidPtr, (VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_DATA_HOB));
+ if (ProcessorDataHobPtr == NULL) {
+ DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive E51 core RISC_V_PROCESSOR_TYPE4_DATA_HOB.\n"));
+ ASSERT (FALSE);
+ }
+
+ ZeroMem((VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_DATA_HOB));
+ SmbiosDataHob.Processor = ProcessorDataHobPtr;
+ SmbiosDataHob.L1InstCache = L1InstCacheDataHobPtr;
+ SmbiosDataHob.L1DataCache = NULL;
+ SmbiosDataHob.L2Cache = NULL;
+ SmbiosDataHob.L3Cache = NULL;
+ GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosGuidHobGuid);
+ SmbiosDataHobPtr = (RISC_V_PROCESSOR_SMBIOS_DATA_HOB *)BuildGuidDataHob (GuidPtr, (VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_DATA_HOB));
+ if (SmbiosDataHobPtr == NULL) {
+ DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive E51 core RISC_V_PROCESSOR_SMBIOS_DATA_HOB.\n"));
+ ASSERT (FALSE);
+ }
+ *SmbiosHobPtr = SmbiosDataHobPtr;
+ return EFI_SUCCESS;
+}
+
+
diff --git a/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf b/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
new file mode 100644
index 00000000..003ad5ae
--- /dev/null
+++ b/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
@@ -0,0 +1,51 @@
+## @file
+# Library instance to create core information HOB
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SiliconSiFiveE51CoreInfoLib
+ FILE_GUID = 80A59B85-1245-4309-AC58-2CFA4199B46C
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SiliconSiFiveE51CoreInfoLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV
+#
+
+[Sources]
+ CoreInfoHob.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ RiscVPkg/RiscVPkg.dec
+ Silicon/SiFive/SiFive.dec
+ Platform/RiscV/RiscVPlatformPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+ MemoryAllocationLib
+ PrintLib
+ FirmwareContextProcessorSpecificLib
+
+[Guids]
+
+[Ppis]
+
+[FixedPcd]
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSpecificDataGuidHobGuid
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid
+ gEfiSiFiveSiliconSpaceGuid.PcdSiFiveE51CoreGuid
+
diff --git a/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c b/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c
new file mode 100644
index 00000000..295e020a
--- /dev/null
+++ b/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c
@@ -0,0 +1,294 @@
+/**@file
+ Build up platform processor information.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include <PiPei.h>
+
+//
+// The Library classes this module consumes
+//
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/BaseMemoryLib.h>
+
+#include <SmbiosProcessorSpecificData.h>
+
+#include <RiscV.h>
+#include <ProcessorSpecificDataHob.h>
+#include <sbi/sbi_hart.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi/sbi_platform.h>
+#include <sbi/sbi.h>
+#include <sbi/SbiFirmwareContext.h>
+#include <Library/FirmwareContextProcessorSpecificLib.h>
+
+/**
+ Function to build core specific information HOB.
+
+ @param ParentProcessorGuid Parent processor od this core. ParentProcessorGuid
+ could be the same as CoreGuid if one processor has
+ only one core.
+ @param ParentProcessorUid Unique ID of pysical processor which owns this core.
+ @param HartId Hart ID of this core.
+ @param IsBootHart TRUE means this is the boot HART.
+ @param GuidHobdata Pointer to RISC_V_PROCESSOR_SPECIFIC_DATA_HOB.
+
+ @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateU54CoreProcessorSpecificDataHob (
+ IN EFI_GUID *ParentProcessorGuid,
+ IN UINTN ParentProcessorUid,
+ IN UINTN HartId,
+ IN BOOLEAN IsBootHart,
+ OUT RISC_V_PROCESSOR_SPECIFIC_DATA_HOB **GuidHobdata
+ )
+{
+ RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *CoreGuidHob;
+ EFI_GUID *ProcessorSpecDataHobGuid;
+ RISC_V_PROCESSOR_SPECIFIC_DATA_HOB ProcessorSpecDataHob;
+ struct sbi_scratch *ThisHartSbiScratch;
+ struct sbi_platform *ThisHartSbiPlatform;
+ EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
+ EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *FirmwareContextHartSpecific;
+
+ DEBUG ((DEBUG_INFO, "%a: Entry.\n", __FUNCTION__));
+
+ if (GuidHobdata == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ ThisHartSbiScratch = sbi_hart_id_to_scratch (sbi_scratch_thishart_ptr(), (UINT32)HartId);
+ DEBUG ((DEBUG_INFO, " SBI Scratch is at 0x%x.\n", ThisHartSbiScratch));
+ ThisHartSbiPlatform = (struct sbi_platform *)sbi_platform_ptr(ThisHartSbiScratch);
+ DEBUG ((DEBUG_INFO, " SBI platform is at 0x%x.\n", ThisHartSbiPlatform));
+ FirmwareContext = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)ThisHartSbiPlatform->firmware_context;
+ DEBUG ((DEBUG_INFO, " Firmware Context is at 0x%x.\n", FirmwareContext));
+ FirmwareContextHartSpecific = FirmwareContext->HartSpecific[HartId];
+ DEBUG ((DEBUG_INFO, " Firmware Context Hart specific is at 0x%x.\n", FirmwareContextHartSpecific));
+
+ //
+ // Build up RISC_V_PROCESSOR_SPECIFIC_DATA_HOB.
+ //
+ CommonFirmwareContextHartSpecificInfo (
+ FirmwareContextHartSpecific,
+ ParentProcessorGuid,
+ ParentProcessorUid,
+ (EFI_GUID *)PcdGetPtr (PcdSiFiveU54CoreGuid),
+ HartId,
+ IsBootHart,
+ &ProcessorSpecDataHob
+ );
+ ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_L = TO_BE_FILLED;
+ ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_H = TO_BE_FILLED;
+ ProcessorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Value64_L = TO_BE_FILLED;
+ ProcessorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Value64_H = TO_BE_FILLED;
+ ProcessorSpecDataHob.ProcessorSpecificData.HartXlen = RegisterLen64;
+ ProcessorSpecDataHob.ProcessorSpecificData.MachineModeXlen = RegisterLen64;
+ ProcessorSpecDataHob.ProcessorSpecificData.SupervisorModeXlen = RegisterUnsupported;
+ ProcessorSpecDataHob.ProcessorSpecificData.UserModeXlen = RegisterLen64;
+
+ DEBUG ((DEBUG_INFO, " *HartId = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.HartId.Value64_L));
+ DEBUG ((DEBUG_INFO, " *Is Boot Hart? = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.BootHartId));
+ DEBUG ((DEBUG_INFO, " *PrivilegeModeSupported = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.PrivilegeModeSupported));
+ DEBUG ((DEBUG_INFO, " *MModeExcepDelegation = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_L));
+ DEBUG ((DEBUG_INFO, " *MModeInterruptDelegation = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Value64_L));
+ DEBUG ((DEBUG_INFO, " *HartXlen = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.HartXlen ));
+ DEBUG ((DEBUG_INFO, " *MachineModeXlen = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.MachineModeXlen));
+ DEBUG ((DEBUG_INFO, " *SupervisorModeXlen = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.SupervisorModeXlen));
+ DEBUG ((DEBUG_INFO, " *UserModeXlen = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.UserModeXlen));
+ DEBUG ((DEBUG_INFO, " *InstSetSupported = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.InstSetSupported));
+ DEBUG ((DEBUG_INFO, " *MachineVendorId = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.MachineVendorId.Value64_L));
+ DEBUG ((DEBUG_INFO, " *MachineArchId = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.MachineArchId.Value64_L));
+ DEBUG ((DEBUG_INFO, " *MachineImplId = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.MachineImplId.Value64_L));
+
+ //
+ // Build GUID HOB for U54 core.
+ //
+ ProcessorSpecDataHobGuid = PcdGetPtr (PcdProcessorSpecificDataGuidHobGuid);
+ CoreGuidHob = (RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *)BuildGuidDataHob (ProcessorSpecDataHobGuid, (VOID *)&ProcessorSpecDataHob, sizeof (RISC_V_PROCESSOR_SPECIFIC_DATA_HOB));
+ if (CoreGuidHob == NULL) {
+ DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive E51 core.\n"));
+ ASSERT (FALSE);
+ }
+ *GuidHobdata = CoreGuidHob;
+ return EFI_SUCCESS;
+}
+
+/**
+ Function to build processor related SMBIOS information. RISC-V SMBIOS DXE driver collect
+ this information and build SMBIOS Type4 and Type7 record.
+
+ @param ProcessorUid Unique ID of pysical processor which owns this core.
+ @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_DATA_HOB. The pointers
+ maintained in this structure is only valid before memory is discovered.
+ Access to those pointers after memory is installed will cause unexpected issues.
+
+ @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateU54ProcessorSmbiosDataHob (
+ IN UINTN ProcessorUid,
+ IN RISC_V_PROCESSOR_SMBIOS_DATA_HOB **SmbiosHobPtr
+ )
+{
+ EFI_GUID *GuidPtr;
+ RISC_V_PROCESSOR_TYPE4_DATA_HOB ProcessorDataHob;
+ RISC_V_PROCESSOR_TYPE7_DATA_HOB L1InstCacheDataHob;
+ RISC_V_PROCESSOR_TYPE7_DATA_HOB L1DataCacheDataHob;
+ RISC_V_PROCESSOR_TYPE7_DATA_HOB L2CacheDataHob;
+ RISC_V_PROCESSOR_SMBIOS_DATA_HOB SmbiosDataHob;
+ RISC_V_PROCESSOR_TYPE4_DATA_HOB *ProcessorDataHobPtr;
+ RISC_V_PROCESSOR_TYPE7_DATA_HOB *L1InstCacheDataHobPtr;
+ RISC_V_PROCESSOR_TYPE7_DATA_HOB *L1DataCacheDataHobPtr;
+ RISC_V_PROCESSOR_TYPE7_DATA_HOB *L2CacheDataHobPtr;
+ RISC_V_PROCESSOR_SMBIOS_DATA_HOB *SmbiosDataHobPtr;
+
+ if (SmbiosHobPtr == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+ //
+ // Build up SMBIOS type 7 L1 instruction cache record.
+ //
+ ZeroMem((VOID *)&L1InstCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_DATA_HOB));
+ CopyGuid (&L1InstCacheDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSiFiveU54CoreGuid));
+ L1InstCacheDataHob.ProcessorUid = ProcessorUid;
+ L1InstCacheDataHob.SmbiosType7Cache.SocketDesignation = TO_BE_FILLED_BY_VENDOR;
+ L1InstCacheDataHob.SmbiosType7Cache.CacheConfiguration = RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1 | \
+ RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL | \
+ RISC_V_CACHE_CONFIGURATION_ENABLED | \
+ RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN;
+ L1InstCacheDataHob.SmbiosType7Cache.MaximumCacheSize = TO_BE_FILLED_BY_VENDOR;
+ L1InstCacheDataHob.SmbiosType7Cache.InstalledSize = TO_BE_FILLED_BY_VENDOR;
+ L1InstCacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown = 1;
+ L1InstCacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown = 1;
+ L1InstCacheDataHob.SmbiosType7Cache.CacheSpeed = TO_BE_FILLED_BY_VENDOR;
+ L1InstCacheDataHob.SmbiosType7Cache.ErrorCorrectionType = TO_BE_FILLED_BY_VENDOR;
+ L1InstCacheDataHob.SmbiosType7Cache.SystemCacheType = CacheTypeInstruction;
+ L1InstCacheDataHob.SmbiosType7Cache.Associativity = TO_BE_FILLED_BY_VENDOR;
+ GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid);
+ L1InstCacheDataHobPtr = (RISC_V_PROCESSOR_TYPE7_DATA_HOB *)BuildGuidDataHob (GuidPtr, (VOID *)&L1InstCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_DATA_HOB));
+ if (L1InstCacheDataHobPtr == NULL) {
+ DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 core L1 instruction cache RISC_V_PROCESSOR_TYPE7_DATA_HOB.\n"));
+ ASSERT (FALSE);
+ }
+
+ //
+ // Build up SMBIOS type 7 L1 data cache record.
+ //
+ ZeroMem((VOID *)&L1DataCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_DATA_HOB));
+ CopyGuid (&L1DataCacheDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSiFiveU54CoreGuid));
+ L1DataCacheDataHob.ProcessorUid = ProcessorUid;
+ L1DataCacheDataHob.SmbiosType7Cache.SocketDesignation = TO_BE_FILLED_BY_VENDOR;
+ L1DataCacheDataHob.SmbiosType7Cache.CacheConfiguration = RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1 | \
+ RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL | \
+ RISC_V_CACHE_CONFIGURATION_ENABLED | \
+ RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN;
+ L1DataCacheDataHob.SmbiosType7Cache.MaximumCacheSize = TO_BE_FILLED_BY_VENDOR;
+ L1DataCacheDataHob.SmbiosType7Cache.InstalledSize = TO_BE_FILLED_BY_VENDOR;
+ L1DataCacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown = 1;
+ L1DataCacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown = 1;
+ L1DataCacheDataHob.SmbiosType7Cache.CacheSpeed = TO_BE_FILLED_BY_VENDOR;
+ L1DataCacheDataHob.SmbiosType7Cache.ErrorCorrectionType = TO_BE_FILLED_BY_VENDOR;
+ L1DataCacheDataHob.SmbiosType7Cache.SystemCacheType = CacheTypeData;
+ L1DataCacheDataHob.SmbiosType7Cache.Associativity = TO_BE_FILLED_BY_VENDOR;
+ GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid);
+ L1DataCacheDataHobPtr = (RISC_V_PROCESSOR_TYPE7_DATA_HOB *)BuildGuidDataHob (GuidPtr, (VOID *)&L1DataCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_DATA_HOB));
+ if (L1DataCacheDataHobPtr == NULL) {
+ DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 core L1 data cache RISC_V_PROCESSOR_TYPE7_DATA_HOB.\n"));
+ ASSERT (FALSE);
+ }
+
+ //
+ // Build up SMBIOS type 7 L2 cache record.
+ //
+ ZeroMem((VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_DATA_HOB));
+ CopyGuid (&L2CacheDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSiFiveU54CoreGuid));
+ L2CacheDataHob.ProcessorUid = ProcessorUid;
+ L2CacheDataHob.SmbiosType7Cache.SocketDesignation = TO_BE_FILLED_BY_VENDOR;
+ L2CacheDataHob.SmbiosType7Cache.CacheConfiguration = RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2 | \
+ RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL | \
+ RISC_V_CACHE_CONFIGURATION_ENABLED | \
+ RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN;
+ L2CacheDataHob.SmbiosType7Cache.MaximumCacheSize = TO_BE_FILLED_BY_VENDOR;
+ L2CacheDataHob.SmbiosType7Cache.InstalledSize = TO_BE_FILLED_BY_VENDOR;
+ L2CacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown = 1;
+ L2CacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown = 1;
+ L2CacheDataHob.SmbiosType7Cache.CacheSpeed = TO_BE_FILLED_BY_VENDOR;
+ L2CacheDataHob.SmbiosType7Cache.ErrorCorrectionType = TO_BE_FILLED_BY_VENDOR;
+ L2CacheDataHob.SmbiosType7Cache.SystemCacheType = CacheTypeUnified;
+ L2CacheDataHob.SmbiosType7Cache.Associativity = TO_BE_FILLED_BY_VENDOR;
+ GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid);
+ L2CacheDataHobPtr = (RISC_V_PROCESSOR_TYPE7_DATA_HOB *)BuildGuidDataHob (GuidPtr, (VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_DATA_HOB));
+ if (L2CacheDataHobPtr == NULL) {
+ DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 core L2 cache RISC_V_PROCESSOR_TYPE7_DATA_HOB.\n"));
+ ASSERT (FALSE);
+ }
+
+ //
+ // Build up SMBIOS type 4 record.
+ //
+ ZeroMem((VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_DATA_HOB));
+ CopyGuid (&ProcessorDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSiFiveU54CoreGuid));
+ ProcessorDataHob.ProcessorUid = ProcessorUid;
+ ProcessorDataHob.SmbiosType4Processor.Socket = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.ProcessorType = CentralProcessor;
+ ProcessorDataHob.SmbiosType4Processor.ProcessorFamily = ProcessorFamilyIndicatorFamily2;
+ ProcessorDataHob.SmbiosType4Processor.ProcessorManufacture = TO_BE_FILLED_BY_VENDOR;
+ SetMem ((VOID *)&ProcessorDataHob.SmbiosType4Processor.ProcessorId, sizeof (PROCESSOR_ID_DATA), TO_BE_FILLED_BY_CODE);
+ ProcessorDataHob.SmbiosType4Processor.ProcessorVersion = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.Voltage.ProcessorVoltageCapability3_3V = 1;
+ ProcessorDataHob.SmbiosType4Processor.ExternalClock = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.MaxSpeed = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.CurrentSpeed = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.Status = TO_BE_FILLED_BY_CODE;
+ ProcessorDataHob.SmbiosType4Processor.ProcessorUpgrade = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.L1CacheHandle = TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER;
+ ProcessorDataHob.SmbiosType4Processor.L2CacheHandle = TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER;
+ ProcessorDataHob.SmbiosType4Processor.L3CacheHandle = 0xffff;
+ ProcessorDataHob.SmbiosType4Processor.SerialNumber = TO_BE_FILLED_BY_CODE;
+ ProcessorDataHob.SmbiosType4Processor.AssetTag = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.PartNumber = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.CoreCount = 1;
+ ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount = 1;
+ ProcessorDataHob.SmbiosType4Processor.ThreadCount = 1;
+ ProcessorDataHob.SmbiosType4Processor.ProcessorCharacteristics = (UINT16)(1 << 2); // 64-bit capable
+ ProcessorDataHob.SmbiosType4Processor.ProcessorFamily2 = ProcessorFamilyRiscVRV64;
+ ProcessorDataHob.SmbiosType4Processor.CoreCount2 = 0;
+ ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount2 = 0;
+ ProcessorDataHob.SmbiosType4Processor.ThreadCount2 = 0;
+ GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType4GuidHobGuid);
+ ProcessorDataHobPtr = (RISC_V_PROCESSOR_TYPE4_DATA_HOB *)BuildGuidDataHob (GuidPtr, (VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_DATA_HOB));
+ if (ProcessorDataHobPtr == NULL) {
+ DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 core RISC_V_PROCESSOR_TYPE4_DATA_HOB.\n"));
+ ASSERT (FALSE);
+ }
+
+ ZeroMem((VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_DATA_HOB));
+ SmbiosDataHob.Processor = ProcessorDataHobPtr;
+ SmbiosDataHob.L1InstCache = L1InstCacheDataHobPtr;
+ SmbiosDataHob.L1DataCache = L1DataCacheDataHobPtr;
+ SmbiosDataHob.L2Cache = L2CacheDataHobPtr;
+ SmbiosDataHob.L3Cache = NULL;
+ GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosGuidHobGuid);
+ SmbiosDataHobPtr = (RISC_V_PROCESSOR_SMBIOS_DATA_HOB *)BuildGuidDataHob (GuidPtr, (VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_DATA_HOB));
+ if (SmbiosDataHobPtr == NULL) {
+ DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 core RISC_V_PROCESSOR_SMBIOS_DATA_HOB.\n"));
+ ASSERT (FALSE);
+ }
+ *SmbiosHobPtr = SmbiosDataHobPtr;
+ return EFI_SUCCESS;
+}
+
diff --git a/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf b/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
new file mode 100644
index 00000000..8efee93b
--- /dev/null
+++ b/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
@@ -0,0 +1,51 @@
+## @file
+# Library instance to create core information HOB
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SiliconSiFiveU54CoreInfoLib
+ FILE_GUID = 483DE090-267E-4278-A0A1-15D9836780EA
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SiliconSiFiveU54CoreInfoLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV
+#
+
+[Sources]
+ CoreInfoHob.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ RiscVPkg/RiscVPkg.dec
+ Platform/RiscV/RiscVPlatformPkg.dec
+ Silicon/SiFive/SiFive.dec
+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+ MemoryAllocationLib
+ PrintLib
+ FirmwareContextProcessorSpecificLib
+
+[Guids]
+
+[Ppis]
+
+[FixedPcd]
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSpecificDataGuidHobGuid
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid
+ gEfiSiFiveSiliconSpaceGuid.PcdSiFiveU54CoreGuid
+
diff --git a/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob.c b/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob.c
new file mode 100644
index 00000000..e14b5977
--- /dev/null
+++ b/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob.c
@@ -0,0 +1,185 @@
+/**@file
+ Build up platform processor information.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include <PiPei.h>
+
+//
+// The Library classes this module consumes
+//
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/BaseMemoryLib.h>
+
+#include <Library/SiFiveU54MCCoreplex.h>
+#include <Library/SiFiveE51.h>
+#include <Library/SiFiveU54.h>
+
+/**
+ Build up processor-specific HOB for U54MC Coreplex
+
+ @param UniqueId Unique ID of this U54MC Coreplex processor
+
+ @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateU54MCCoreplexProcessorSpecificDataHob (
+ IN UINTN UniqueId
+ )
+{
+ EFI_STATUS Status;
+ RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *ThisGuidHobData;
+ EFI_GUID *ParentProcessorGuid;
+
+ DEBUG ((DEBUG_INFO, "%a: Entry.\n", __FUNCTION__));
+
+ ParentProcessorGuid = PcdGetPtr (PcdSiFiveU54MCCoreplexGuid);
+ Status = CreateE51CoreProcessorSpecificDataHob (ParentProcessorGuid, UniqueId, SIFIVE_U54MC_COREPLEX_E51_HART_ID, FALSE, &ThisGuidHobData);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: Faile to build E51 core information HOB for U54 Coreplex.\n", __FUNCTION__));
+ return Status;
+ }
+ Status = CreateU54CoreProcessorSpecificDataHob (ParentProcessorGuid, UniqueId, SIFIVE_U54_COREPLEX_U54MC_0_HART_ID, TRUE, &ThisGuidHobData);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: Faile to build U54 core information HOB for U54 Coreplex.\n", __FUNCTION__));
+ return Status;
+ }
+ Status = CreateU54CoreProcessorSpecificDataHob (ParentProcessorGuid, UniqueId, SIFIVE_U54_COREPLEX_U54MC_1_HART_ID, FALSE, &ThisGuidHobData);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: Faile to build U54 core information HOB for U54 Coreplex.\n", __FUNCTION__));
+ return Status;
+ }
+ Status = CreateU54CoreProcessorSpecificDataHob (ParentProcessorGuid, UniqueId, SIFIVE_U54_COREPLEX_U54MC_2_HART_ID, FALSE, &ThisGuidHobData);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: Faile to build U54 core information HOB for U54 Coreplex.\n", __FUNCTION__));
+ return Status;
+ }
+ Status = CreateU54CoreProcessorSpecificDataHob (ParentProcessorGuid, UniqueId, SIFIVE_U54_COREPLEX_U54MC_3_HART_ID, FALSE, &ThisGuidHobData);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: Faile to build U54 core information HOB for U54 Coreplex.\n", __FUNCTION__));
+ return Status;
+ }
+ return Status;
+}
+
+/**
+ Function to build processor related SMBIOS information. RISC-V SMBIOS DXE driver collect
+ this information and build SMBIOS Type4 and Type7 record.
+
+ @param ProcessorUid Unique ID of pysical processor which owns this core.
+ @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_DATA_HOB. The pointers
+ maintained in this structure is only valid before memory is discovered.
+ Access to those pointers after memory is installed will cause unexpected issues.
+
+ @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateU54MCProcessorSmbiosDataHob (
+ IN UINTN ProcessorUid,
+ IN RISC_V_PROCESSOR_SMBIOS_DATA_HOB **SmbiosHobPtr
+ )
+{
+ EFI_GUID *GuidPtr;
+ RISC_V_PROCESSOR_TYPE4_DATA_HOB ProcessorDataHob;
+ RISC_V_PROCESSOR_TYPE7_DATA_HOB L2CacheDataHob;
+ RISC_V_PROCESSOR_SMBIOS_DATA_HOB SmbiosDataHob;
+ RISC_V_PROCESSOR_TYPE4_DATA_HOB *ProcessorDataHobPtr;
+ RISC_V_PROCESSOR_TYPE7_DATA_HOB *L2CacheDataHobPtr;
+ RISC_V_PROCESSOR_SMBIOS_DATA_HOB *SmbiosDataHobPtr;
+
+ if (SmbiosHobPtr == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Build up SMBIOS type 7 L2 cache record.
+ //
+ ZeroMem((VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_DATA_HOB));
+ L2CacheDataHob.PrcessorGuid = *((EFI_GUID *)PcdGetPtr (PcdSiFiveU54MCCoreplexGuid));
+ L2CacheDataHob.ProcessorUid = ProcessorUid;
+ L2CacheDataHob.SmbiosType7Cache.SocketDesignation = TO_BE_FILLED_BY_VENDOR;
+ L2CacheDataHob.SmbiosType7Cache.CacheConfiguration = RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2 | \
+ RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL | \
+ RISC_V_CACHE_CONFIGURATION_ENABLED | \
+ RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN;
+ L2CacheDataHob.SmbiosType7Cache.MaximumCacheSize = TO_BE_FILLED_BY_VENDOR;
+ L2CacheDataHob.SmbiosType7Cache.InstalledSize = TO_BE_FILLED_BY_VENDOR;
+ L2CacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown = 1;
+ L2CacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown = 1;
+ L2CacheDataHob.SmbiosType7Cache.CacheSpeed = TO_BE_FILLED_BY_VENDOR;
+ L2CacheDataHob.SmbiosType7Cache.ErrorCorrectionType = TO_BE_FILLED_BY_VENDOR;
+ L2CacheDataHob.SmbiosType7Cache.SystemCacheType = CacheTypeUnified;
+ L2CacheDataHob.SmbiosType7Cache.Associativity = TO_BE_FILLED_BY_VENDOR;
+ GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid);
+ L2CacheDataHobPtr = (RISC_V_PROCESSOR_TYPE7_DATA_HOB *)BuildGuidDataHob (GuidPtr, (VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_DATA_HOB));
+ if (L2CacheDataHobPtr == NULL) {
+ DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 MC Coreplex L2 cache RISC_V_PROCESSOR_TYPE7_DATA_HOB.\n"));
+ ASSERT (FALSE);
+ }
+
+ //
+ // Build up SMBIOS type 4 record.
+ //
+ ZeroMem((VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_DATA_HOB));
+ ProcessorDataHob.PrcessorGuid = *((EFI_GUID *)PcdGetPtr (PcdSiFiveU54MCCoreplexGuid));
+ ProcessorDataHob.ProcessorUid = ProcessorUid;
+ ProcessorDataHob.SmbiosType4Processor.Socket = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.ProcessorType = CentralProcessor;
+ ProcessorDataHob.SmbiosType4Processor.ProcessorFamily = ProcessorFamilyIndicatorFamily2;
+ ProcessorDataHob.SmbiosType4Processor.ProcessorManufacture = TO_BE_FILLED_BY_VENDOR;
+ SetMem ((VOID *)&ProcessorDataHob.SmbiosType4Processor.ProcessorId, sizeof (PROCESSOR_ID_DATA), TO_BE_FILLED_BY_CODE);
+ ProcessorDataHob.SmbiosType4Processor.ProcessorVersion = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.Voltage.ProcessorVoltageCapability3_3V = 1;
+ ProcessorDataHob.SmbiosType4Processor.ExternalClock = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.MaxSpeed = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.CurrentSpeed = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.Status = TO_BE_FILLED_BY_CODE;
+ ProcessorDataHob.SmbiosType4Processor.ProcessorUpgrade = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.L1CacheHandle = TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER;
+ ProcessorDataHob.SmbiosType4Processor.L2CacheHandle = TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER;
+ ProcessorDataHob.SmbiosType4Processor.L3CacheHandle = 0xffff;
+ ProcessorDataHob.SmbiosType4Processor.SerialNumber = TO_BE_FILLED_BY_CODE;
+ ProcessorDataHob.SmbiosType4Processor.AssetTag = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.PartNumber = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.CoreCount = 5;
+ ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount = 5;
+ ProcessorDataHob.SmbiosType4Processor.ThreadCount = 5;
+ ProcessorDataHob.SmbiosType4Processor.ProcessorCharacteristics = (UINT16)(1 << 2); // 64-bit capable
+ ProcessorDataHob.SmbiosType4Processor.ProcessorFamily2 = ProcessorFamilyRiscVRV64;
+ ProcessorDataHob.SmbiosType4Processor.CoreCount2 = 0;
+ ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount2 = 0;
+ ProcessorDataHob.SmbiosType4Processor.ThreadCount2 = 0;
+ GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType4GuidHobGuid);
+ ProcessorDataHobPtr = (RISC_V_PROCESSOR_TYPE4_DATA_HOB *)BuildGuidDataHob (GuidPtr, (VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_DATA_HOB));
+ if (ProcessorDataHobPtr == NULL) {
+ DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 MC Coreplex RISC_V_PROCESSOR_TYPE4_DATA_HOB.\n"));
+ ASSERT (FALSE);
+ }
+
+ ZeroMem((VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_DATA_HOB));
+ SmbiosDataHob.Processor = ProcessorDataHobPtr;
+ SmbiosDataHob.L1InstCache = NULL;
+ SmbiosDataHob.L1DataCache = NULL;
+ SmbiosDataHob.L2Cache = L2CacheDataHobPtr;
+ SmbiosDataHob.L3Cache = NULL;
+ GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosGuidHobGuid);
+ SmbiosDataHobPtr = (RISC_V_PROCESSOR_SMBIOS_DATA_HOB *)BuildGuidDataHob (GuidPtr, (VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_DATA_HOB));
+ if (SmbiosDataHobPtr == NULL) {
+ DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54MC Coreplex RISC_V_PROCESSOR_SMBIOS_DATA_HOB.\n"));
+ ASSERT (FALSE);
+ }
+ *SmbiosHobPtr = SmbiosDataHobPtr;
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf b/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
new file mode 100644
index 00000000..a5714a20
--- /dev/null
+++ b/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
@@ -0,0 +1,50 @@
+## @file
+# Library instance to create core information HOB
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SiliconSiFiveU54MCCoreplexInfoLib
+ FILE_GUID = 483DE090-267E-4278-A0A1-15D9836780EA
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SiliconSiFiveU54MCCoreplexInfoLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV
+#
+
+[Sources]
+ CoreInfoHob.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ RiscVPkg/RiscVPkg.dec
+ Silicon/SiFive/SiFive.dec
+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+ MemoryAllocationLib
+ PrintLib
+ SiliconSiFiveE51CoreInfoLib
+ SiliconSiFiveU54CoreInfoLib
+
+[Guids]
+
+[Ppis]
+
+[FixedPcd]
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid
+ gEfiSiFiveSiliconSpaceGuid.PcdSiFiveU54MCCoreplexGuid
+
--
2.12.0.windows.1
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On Thu, Sep 19, 2019 at 11:51:19AM +0800, Gilbert Chen wrote:
> Initial version of SiFive RISC-V core libraries. Library of each core
> creates processor core SMBIOS data hob for building SMBIOS
> records in DXE phase.
So yes, this implementation needs to change.
These should all implement the same LibraryClass.
Also, U54 appears to be a simple superset of U51.
What I would suggest is creating a
Silicon/SiFive/Library/SiFiveCoreInfoLib, which calls into a
SiFiveSoCCoreInfoLib in Silicon/SiFive/<SoC>/Library, providing the
acual SoC-specific bits.
/
Leif
> Signed-off-by: Gilbert Chen <gilbert.chen@hpe.com>
> ---
> .../E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c | 242 +++++++++++++++++
> .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 51 ++++
> .../U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c | 294 +++++++++++++++++++++
> .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 51 ++++
> .../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 185 +++++++++++++
> .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 50 ++++
> 6 files changed, 873 insertions(+)
> create mode 100644 Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c
> create mode 100644 Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
> create mode 100644 Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c
> create mode 100644 Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
> create mode 100644 Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob.c
> create mode 100644 Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
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> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Leif Lindholm
> Sent: Wednesday, October 2, 2019 5:15 AM
> To: devel@edk2.groups.io; Chen, Gilbert <gilbert.chen@hpe.com>
> Subject: Re: [edk2-devel] [plaforms/devel-riscv-v2 PATCHv2 02/14]
> Silicon/SiFive: Add library module of SiFive RISC-V cores
>
> On Thu, Sep 19, 2019 at 11:51:19AM +0800, Gilbert Chen wrote:
> > Initial version of SiFive RISC-V core libraries. Library of each core
> > creates processor core SMBIOS data hob for building SMBIOS records in
> > DXE phase.
>
> So yes, this implementation needs to change.
> These should all implement the same LibraryClass.
No. It shouldn't be the same library class (If you were saying the same LibraryClass). RISC-V SoC could be the combination of different RISC-V cores, or even the cores from different vendors. This depends on how SoC vendor combine those IPs.
Either U54 or E51 could be a standalone SoC, while U54MC is the combination of 4 x U54 core and one E51 core.
U5MC under Platform/SiFive could be 1-8 U5 core and optionally support E5 core. This is the special case for U500 VC707 platform because the core number could be customized.
> Also, U54 appears to be a simple superset of U51.
U54 is a single core.
>
> What I would suggest is creating a
> Silicon/SiFive/Library/SiFiveCoreInfoLib, which calls into a
> SiFiveSoCCoreInfoLib in Silicon/SiFive/<SoC>/Library, providing the acual SoC-
> specific bits.
Platform system firmware integrator just pull in the necessary core libraries from Silicon/{vendor} and invoke the function to create specific core bits.
I think this implementation is well and flexible which has no need to change.
>
> /
> Leif
>
> > Signed-off-by: Gilbert Chen <gilbert.chen@hpe.com>
> > ---
> > .../E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c | 242
> +++++++++++++++++
> > .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 51 ++++
> > .../U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c | 294
> +++++++++++++++++++++
> > .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 51 ++++
> > .../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 185 +++++++++++++
> > .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 50 ++++
> > 6 files changed, 873 insertions(+)
> > create mode 100644
> > Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c
> > create mode 100644
> > Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
> > create mode 100644
> > Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c
> > create mode 100644
> > Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
> > create mode 100644
> > Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob.c
> > create mode 100644
> >
> Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/PeiCoreInfoHobL
> > ib.inf
>
>
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On Wed, Oct 16, 2019 at 01:36:07AM +0000, Chang, Abner (HPS SW/FW Technologist) wrote:
> > -----Original Message-----
> > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> > Leif Lindholm
> > Sent: Wednesday, October 2, 2019 5:15 AM
> > To: devel@edk2.groups.io; Chen, Gilbert <gilbert.chen@hpe.com>
> > Subject: Re: [edk2-devel] [plaforms/devel-riscv-v2 PATCHv2 02/14]
> > Silicon/SiFive: Add library module of SiFive RISC-V cores
> >
> > On Thu, Sep 19, 2019 at 11:51:19AM +0800, Gilbert Chen wrote:
> > > Initial version of SiFive RISC-V core libraries. Library of each core
> > > creates processor core SMBIOS data hob for building SMBIOS records in
> > > DXE phase.
> >
> > So yes, this implementation needs to change.
> > These should all implement the same LibraryClass.
>
> No. It shouldn't be the same library class (If you were saying the
> same LibraryClass). RISC-V SoC could be the combination of different
> RISC-V cores, or even the cores from different vendors. This depends
> on how SoC vendor combine those IPs.
Ah, OK. Sorry, did not realise this aspect.
> Either U54 or E51 could be a standalone SoC, while U54MC is the
> combination of 4 x U54 core and one E51 core.
>
> U5MC under Platform/SiFive could be 1-8 U5 core and optionally
> support E5 core. This is the special case for U500 VC707 platform
> because the core number could be customized.
>
> > Also, U54 appears to be a simple superset of U51.
> U54 is a single core.
>
> >
> > What I would suggest is creating a
> > Silicon/SiFive/Library/SiFiveCoreInfoLib, which calls into a
> > SiFiveSoCCoreInfoLib in Silicon/SiFive/<SoC>/Library, providing the acual SoC-
> > specific bits.
>
> Platform system firmware integrator just pull in the necessary core
> libraries from Silicon/{vendor} and invoke the function to create
> specific core bits.
>
> I think this implementation is well and flexible which has no need to change.
Oh, my criticism was that it was *too* flexible (with resulting code
overhead). I still feel the very small source differences, especially
between E51/U54, indicate that these could be implemented by the same
source file but different .inf files.
But this is not something that needs to be addressed before this patch
goes into -staging.
Regards,
Leif
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