From nobody Sun Feb 8 14:22:53 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47535+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47535+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1568865100; cv=none; d=zoho.com; s=zohoarc; b=E7AdgbqzPz7iIh7AzEzSQEVG459B/H5jsI2i5yAGxVqiaOoBfEKIOFxrd3L25crJBOL0i40zH+U3DC6E1Yv62I4n9XWp8lTS19PDvgK4BBkEi09K8C9zyeOyztRmwdbC2NHkpO/R60pqbysOO5Z4l9uV4BqDKGC25xRXrVGGKsw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1568865100; h=Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=l1pZadZG6APHwWtdqogXF36CRTXOxsCqVoq3ReecJ28=; b=leZudklo7gRTsadbEoxsiFKp+2agzXeYWb+GG6ozWIbl0hkpB2E1BJxm6FchxXuWcm4hB+zbVp4Jwx3jPK7og36dJ6c0i6thT8ur+Zv5B8wHQloDmgWr1qJLdz9Xr3zirAON+scsW32HjE+yTw8NF5aICzuXENShnXfJ/zJs3S8= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47535+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1568865100201221.7025875012888; Wed, 18 Sep 2019 20:51:40 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id Iu0sYY1788612xXq5op0U64P; Wed, 18 Sep 2019 20:51:38 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by groups.io with SMTP; Wed, 18 Sep 2019 20:51:38 -0700 X-Received: from pps.filterd (m0150241.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8J3pJw3021123 for ; Thu, 19 Sep 2019 03:51:37 GMT X-Received: from g4t3425.houston.hpe.com (g4t3425.houston.hpe.com [15.241.140.78]) by mx0a-002e3701.pphosted.com with ESMTP id 2v3vaqnkax-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 19 Sep 2019 03:51:37 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3425.houston.hpe.com (Postfix) with ESMTP id 6F74492 for ; Thu, 19 Sep 2019 03:51:36 +0000 (UTC) X-Received: from ARBDN0VRAE.asiapacific.hpqcorp.net (arbdn0vrae.asiapacific.hpqcorp.net [10.43.41.0]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id A148047 for ; Thu, 19 Sep 2019 03:51:35 +0000 (UTC) From: "Gilbert Chen" To: devel@edk2.groups.io Subject: [edk2-devel] [plaforms/devel-riscv-v2 PATCHv2 02/14] Silicon/SiFive: Add library module of SiFive RISC-V cores Date: Thu, 19 Sep 2019 11:51:19 +0800 Message-Id: <20190919035131.4700-3-gilbert.chen@hpe.com> In-Reply-To: <20190919035131.4700-1-gilbert.chen@hpe.com> References: <20190919035131.4700-1-gilbert.chen@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,gilbert.chen@hpe.com X-Gm-Message-State: pJmEcU2Fd3dBHQ1nbunZiVfwx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1568865098; bh=UoKK04z3BviIw1uuCVaVJIGcRr6Y8KuJHOY96bqRPZ8=; h=Date:From:Reply-To:Subject:To; b=NHGkvYrfwCKv+9N19Z0LZ0l9266taO8pfktm+qmkubF3xVAlexU9FtjJtBPPfVgnSdr gXF0bmpRXrYWlOYFkpK/oZr43dgnf0vZx5FMaCwB/iLRrkYAUl0R35XYTkpwKz9orggVr EAcXJspBFNXbRn1IwlX6TAYpM5KHbuWL02o= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Initial version of SiFive RISC-V core libraries. Library of each core creates processor core SMBIOS data hob for building SMBIOS records in DXE phase. Signed-off-by: Gilbert Chen --- .../E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c | 242 +++++++++++++++++ .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 51 ++++ .../U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c | 294 +++++++++++++++++= ++++ .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 51 ++++ .../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 185 +++++++++++++ .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 50 ++++ 6 files changed, 873 insertions(+) create mode 100644 Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHo= b.c create mode 100644 Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInf= oHobLib.inf create mode 100644 Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHo= b.c create mode 100644 Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInf= oHobLib.inf create mode 100644 Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/= CoreInfoHob.c create mode 100644 Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/= PeiCoreInfoHobLib.inf diff --git a/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c b/S= ilicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c new file mode 100644 index 00000000..b7140b53 --- /dev/null +++ b/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c @@ -0,0 +1,242 @@ +/**@file + Build up platform processor information. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +// The package level header files this module uses +// +#include + +// +// The Library classes this module consumes +// +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Function to build core specific information HOB. RISC-V SMBIOS DXE drive= r collect + this information and build SMBIOS Type44. + + @param ParentProcessorGuid Parent processor od this core. ParentProc= essorGuid + could be the same as CoreGuid if one proc= essor has + only one core. + @param ParentProcessorUid Unique ID of pysical processor which owns= this core. + @param HartId Hart ID of this core. + @param IsBootHart TRUE means this is the boot HART. + @param GuidHobData Pointer to receive EFI_HOB_GUID_TYPE. + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +EFIAPI +CreateE51CoreProcessorSpecificDataHob ( + IN EFI_GUID *ParentProcessorGuid, + IN UINTN ParentProcessorUid, + IN UINTN HartId, + IN BOOLEAN IsBootHart, + OUT RISC_V_PROCESSOR_SPECIFIC_DATA_HOB **GuidHobData + ) +{ + RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *CoreGuidHob; + EFI_GUID *ProcessorSpecDataHobGuid; + RISC_V_PROCESSOR_SPECIFIC_DATA_HOB ProcessorSpecDataHob; + struct sbi_scratch *ThisHartSbiScratch; + struct sbi_platform *ThisHartSbiPlatform; + EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext; + EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *FirmwareContextHartSpecific; + + DEBUG ((DEBUG_INFO, "%a: Entry.\n", __FUNCTION__)); + + if (GuidHobData =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + ThisHartSbiScratch =3D sbi_hart_id_to_scratch (sbi_scratch_thishart_ptr(= ), (UINT32)HartId); + DEBUG ((DEBUG_INFO, " SBI Scratch is at 0x%x.\n", ThisHartSbiScratch)= ); + ThisHartSbiPlatform =3D (struct sbi_platform *)sbi_platform_ptr(ThisHart= SbiScratch); + DEBUG ((DEBUG_INFO, " SBI platform is at 0x%x.\n", ThisHartSbiPlatfor= m)); + FirmwareContext =3D (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)ThisHartSbiPla= tform->firmware_context; + DEBUG ((DEBUG_INFO, " Firmware Context is at 0x%x.\n", FirmwareContex= t)); + FirmwareContextHartSpecific =3D FirmwareContext->HartSpecific[HartId]; + DEBUG ((DEBUG_INFO, " Firmware Context Hart specific is at 0x%x.\n", = FirmwareContextHartSpecific)); + + // + // Build up RISC_V_PROCESSOR_SPECIFIC_DATA_HOB. + // + CommonFirmwareContextHartSpecificInfo ( + FirmwareContextHartSpecific, + ParentProcessorGuid, + ParentProcessorUid, + (EFI_GUID *)PcdGetPtr (PcdSiFiveE51CoreGuid), + HartId, + IsBootHart, + &ProcessorSpecDataHob + ); + ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_= L =3D TO_BE_FILLED; + ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_= H =3D TO_BE_FILLED; + ProcessorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Valu= e64_L =3D TO_BE_FILLED; + ProcessorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Valu= e64_H =3D TO_BE_FILLED; + ProcessorSpecDataHob.ProcessorSpecificData.HartXlen =3D = RegisterLen64; + ProcessorSpecDataHob.ProcessorSpecificData.MachineModeXlen =3D = RegisterLen64; + ProcessorSpecDataHob.ProcessorSpecificData.SupervisorModeXlen =3D = RegisterUnsupported; + ProcessorSpecDataHob.ProcessorSpecificData.UserModeXlen =3D = RegisterLen64; + + DEBUG ((DEBUG_INFO, " *HartId =3D 0x%x\n", ProcessorSpecDataHob.P= rocessorSpecificData.HartId.Value64_L)); + DEBUG ((DEBUG_INFO, " *Is Boot Hart? =3D 0x%x\n", ProcessorSpecDa= taHob.ProcessorSpecificData.BootHartId)); + DEBUG ((DEBUG_INFO, " *PrivilegeModeSupported =3D 0x%x\n", Proces= sorSpecDataHob.ProcessorSpecificData.PrivilegeModeSupported)); + DEBUG ((DEBUG_INFO, " *MModeExcepDelegation =3D 0x%x\n", Processo= rSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_L)); + DEBUG ((DEBUG_INFO, " *MModeInterruptDelegation =3D 0x%x\n", Proc= essorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Value64_L)); + DEBUG ((DEBUG_INFO, " *HartXlen =3D 0x%x\n", ProcessorSpecDataHob= .ProcessorSpecificData.HartXlen )); + DEBUG ((DEBUG_INFO, " *MachineModeXlen =3D 0x%x\n", ProcessorSpec= DataHob.ProcessorSpecificData.MachineModeXlen)); + DEBUG ((DEBUG_INFO, " *SupervisorModeXlen =3D 0x%x\n", ProcessorS= pecDataHob.ProcessorSpecificData.SupervisorModeXlen)); + DEBUG ((DEBUG_INFO, " *UserModeXlen =3D 0x%x\n", ProcessorSpecDat= aHob.ProcessorSpecificData.UserModeXlen)); + DEBUG ((DEBUG_INFO, " *InstSetSupported =3D 0x%x\n", ProcessorSpe= cDataHob.ProcessorSpecificData.InstSetSupported)); + DEBUG ((DEBUG_INFO, " *MachineVendorId =3D 0x%x\n", ProcessorSpec= DataHob.ProcessorSpecificData.MachineVendorId.Value64_L)); + DEBUG ((DEBUG_INFO, " *MachineArchId =3D 0x%x\n", ProcessorSpecDa= taHob.ProcessorSpecificData.MachineArchId.Value64_L)); + DEBUG ((DEBUG_INFO, " *MachineImplId =3D 0x%x\n", ProcessorSpecDa= taHob.ProcessorSpecificData.MachineImplId.Value64_L)); + + // + // Build GUID HOB for E51 core, this is for SMBIOS type 44 + // + ProcessorSpecDataHobGuid =3D PcdGetPtr (PcdProcessorSpecificDataGuidHobG= uid); + CoreGuidHob =3D (RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *)BuildGuidDataHob (= ProcessorSpecDataHobGuid, (VOID *)&ProcessorSpecDataHob, sizeof (RISC_V_PRO= CESSOR_SPECIFIC_DATA_HOB)); + if (CoreGuidHob =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive E51 core.\n")); + ASSERT (FALSE); + } + *GuidHobData =3D CoreGuidHob; + return EFI_SUCCESS; +} + +/** + Function to build processor related SMBIOS information. RISC-V SMBIOS DX= E driver collect + this information and build SMBIOS Type4 and Type7 record. + + @param ProcessorUid Unique ID of pysical processor which owns this c= ore. + @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_DATA_= HOB. The pointers + maintained in this structure is only valid befor= e memory is discovered. + Access to those pointers after memory is install= ed will cause unexpected issues. + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +EFIAPI +CreateE51ProcessorSmbiosDataHob ( + IN UINTN ProcessorUid, + OUT RISC_V_PROCESSOR_SMBIOS_DATA_HOB **SmbiosHobPtr + ) +{ + EFI_GUID *GuidPtr; + RISC_V_PROCESSOR_TYPE4_DATA_HOB ProcessorDataHob; + RISC_V_PROCESSOR_TYPE7_DATA_HOB L1InstCacheDataHob; + RISC_V_PROCESSOR_SMBIOS_DATA_HOB SmbiosDataHob; + RISC_V_PROCESSOR_TYPE4_DATA_HOB *ProcessorDataHobPtr; + RISC_V_PROCESSOR_TYPE7_DATA_HOB *L1InstCacheDataHobPtr; + RISC_V_PROCESSOR_SMBIOS_DATA_HOB *SmbiosDataHobPtr; + + if (SmbiosHobPtr =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + // + // Build up SMBIOS type 7 L1 instruction cache record. + // + ZeroMem((VOID *)&L1InstCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_DATA= _HOB)); + CopyGuid (&L1InstCacheDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSi= FiveE51CoreGuid)); + L1InstCacheDataHob.ProcessorUid =3D ProcessorUid; + L1InstCacheDataHob.SmbiosType7Cache.SocketDesignation =3D TO_BE_FILLED_B= Y_VENDOR; + L1InstCacheDataHob.SmbiosType7Cache.CacheConfiguration =3D RISC_V_CACHE_= CONFIGURATION_CACHE_LEVEL_1 | \ + RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL | \ + RISC_V_CACHE_CONFIGURATION_ENABLED | \ + RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN; + L1InstCacheDataHob.SmbiosType7Cache.MaximumCacheSize =3D TO_BE_FILLED_BY= _VENDOR; + L1InstCacheDataHob.SmbiosType7Cache.InstalledSize =3D TO_BE_FILLED_BY_VE= NDOR; + L1InstCacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown =3D 1; + L1InstCacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown =3D 1; + L1InstCacheDataHob.SmbiosType7Cache.CacheSpeed =3D TO_BE_FILLED_BY_VENDO= R; + L1InstCacheDataHob.SmbiosType7Cache.ErrorCorrectionType =3D TO_BE_FILLED= _BY_VENDOR; + L1InstCacheDataHob.SmbiosType7Cache.SystemCacheType =3D CacheTypeInstruc= tion; + L1InstCacheDataHob.SmbiosType7Cache.Associativity =3D TO_BE_FILLED_BY_VE= NDOR; + GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid); + L1InstCacheDataHobPtr =3D (RISC_V_PROCESSOR_TYPE7_DATA_HOB *)BuildGuidDa= taHob (GuidPtr, (VOID *)&L1InstCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7= _DATA_HOB)); + if (L1InstCacheDataHobPtr =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive E51 core L1 in= struction cache RISC_V_PROCESSOR_TYPE7_DATA_HOB.\n")); + ASSERT (FALSE); + } + + // + // Build up SMBIOS type 4 record. + // + ZeroMem((VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_DATA_H= OB)); + CopyGuid (&ProcessorDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSiFi= veE51CoreGuid)); + ProcessorDataHob.ProcessorUid =3D ProcessorUid; + ProcessorDataHob.SmbiosType4Processor.Socket =3D TO_BE_FILLED_BY_VENDOR; + ProcessorDataHob.SmbiosType4Processor.ProcessorType =3D CentralProcessor; + ProcessorDataHob.SmbiosType4Processor.ProcessorFamily =3D ProcessorFamil= yIndicatorFamily2; + ProcessorDataHob.SmbiosType4Processor.ProcessorManufacture =3D TO_BE_FIL= LED_BY_VENDOR; + SetMem ((VOID *)&ProcessorDataHob.SmbiosType4Processor.ProcessorId, size= of (PROCESSOR_ID_DATA), TO_BE_FILLED_BY_CODE); + ProcessorDataHob.SmbiosType4Processor.ProcessorVersion =3D TO_BE_FILLED_= BY_VENDOR; + ProcessorDataHob.SmbiosType4Processor.Voltage.ProcessorVoltageCapability= 3_3V =3D 1; + ProcessorDataHob.SmbiosType4Processor.ExternalClock =3D TO_BE_FILLED_BY_= VENDOR; + ProcessorDataHob.SmbiosType4Processor.MaxSpeed =3D TO_BE_FILLED_BY_VENDO= R; + ProcessorDataHob.SmbiosType4Processor.CurrentSpeed =3D TO_BE_FILLED_BY_V= ENDOR; + ProcessorDataHob.SmbiosType4Processor.Status =3D TO_BE_FILLED_BY_CODE; + ProcessorDataHob.SmbiosType4Processor.ProcessorUpgrade =3D TO_BE_FILLED_= BY_VENDOR; + ProcessorDataHob.SmbiosType4Processor.L1CacheHandle =3D TO_BE_FILLED_BY_= RISC_V_SMBIOS_DXE_DRIVER; + ProcessorDataHob.SmbiosType4Processor.L2CacheHandle =3D 0xffff; + ProcessorDataHob.SmbiosType4Processor.L3CacheHandle =3D 0xffff; + ProcessorDataHob.SmbiosType4Processor.SerialNumber =3D TO_BE_FILLED_BY_C= ODE; + ProcessorDataHob.SmbiosType4Processor.AssetTag =3D TO_BE_FILLED_BY_VENDO= R; + ProcessorDataHob.SmbiosType4Processor.PartNumber =3D TO_BE_FILLED_BY_VEN= DOR; + ProcessorDataHob.SmbiosType4Processor.CoreCount =3D 1; + ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount =3D 1; + ProcessorDataHob.SmbiosType4Processor.ThreadCount =3D 1; + ProcessorDataHob.SmbiosType4Processor.ProcessorCharacteristics =3D (UINT= 16)(1 << 2); // 64-bit capable + ProcessorDataHob.SmbiosType4Processor.ProcessorFamily2 =3D ProcessorFami= lyRiscVRV64; + ProcessorDataHob.SmbiosType4Processor.CoreCount2 =3D 0; + ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount2 =3D 0; + ProcessorDataHob.SmbiosType4Processor.ThreadCount2 =3D 0; + GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType4GuidHobGuid); + ProcessorDataHobPtr =3D (RISC_V_PROCESSOR_TYPE4_DATA_HOB *)BuildGuidData= Hob (GuidPtr, (VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_DAT= A_HOB)); + if (ProcessorDataHobPtr =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive E51 core RISC_= V_PROCESSOR_TYPE4_DATA_HOB.\n")); + ASSERT (FALSE); + } + + ZeroMem((VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_DATA_HOB= )); + SmbiosDataHob.Processor =3D ProcessorDataHobPtr; + SmbiosDataHob.L1InstCache =3D L1InstCacheDataHobPtr; + SmbiosDataHob.L1DataCache =3D NULL; + SmbiosDataHob.L2Cache =3D NULL; + SmbiosDataHob.L3Cache =3D NULL; + GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosGuidHobGuid); + SmbiosDataHobPtr =3D (RISC_V_PROCESSOR_SMBIOS_DATA_HOB *)BuildGuidDataHo= b (GuidPtr, (VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_DATA_HO= B)); + if (SmbiosDataHobPtr =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive E51 core RISC_= V_PROCESSOR_SMBIOS_DATA_HOB.\n")); + ASSERT (FALSE); + } + *SmbiosHobPtr =3D SmbiosDataHobPtr; + return EFI_SUCCESS; +} + + diff --git a/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib= .inf b/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf new file mode 100644 index 00000000..003ad5ae --- /dev/null +++ b/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf @@ -0,0 +1,51 @@ +## @file +# Library instance to create core information HOB +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SiliconSiFiveE51CoreInfoLib + FILE_GUID =3D 80A59B85-1245-4309-AC58-2CFA4199B46C + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SiliconSiFiveE51CoreInfoLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV +# + +[Sources] + CoreInfoHob.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + RiscVPkg/RiscVPkg.dec + Silicon/SiFive/SiFive.dec + Platform/RiscV/RiscVPlatformPkg.dec + +[LibraryClasses] + BaseLib + PcdLib + MemoryAllocationLib + PrintLib + FirmwareContextProcessorSpecificLib + +[Guids] + +[Ppis] + +[FixedPcd] + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSpecificDataGuidHobGuid + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid + gEfiSiFiveSiliconSpaceGuid.PcdSiFiveE51CoreGuid + diff --git a/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c b/S= ilicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c new file mode 100644 index 00000000..295e020a --- /dev/null +++ b/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c @@ -0,0 +1,294 @@ +/**@file + Build up platform processor information. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +// The package level header files this module uses +// +#include + +// +// The Library classes this module consumes +// +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Function to build core specific information HOB. + + @param ParentProcessorGuid Parent processor od this core. ParentProc= essorGuid + could be the same as CoreGuid if one proc= essor has + only one core. + @param ParentProcessorUid Unique ID of pysical processor which owns= this core. + @param HartId Hart ID of this core. + @param IsBootHart TRUE means this is the boot HART. + @param GuidHobdata Pointer to RISC_V_PROCESSOR_SPECIFIC_DATA= _HOB. + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +EFIAPI +CreateU54CoreProcessorSpecificDataHob ( + IN EFI_GUID *ParentProcessorGuid, + IN UINTN ParentProcessorUid, + IN UINTN HartId, + IN BOOLEAN IsBootHart, + OUT RISC_V_PROCESSOR_SPECIFIC_DATA_HOB **GuidHobdata + ) +{ + RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *CoreGuidHob; + EFI_GUID *ProcessorSpecDataHobGuid; + RISC_V_PROCESSOR_SPECIFIC_DATA_HOB ProcessorSpecDataHob; + struct sbi_scratch *ThisHartSbiScratch; + struct sbi_platform *ThisHartSbiPlatform; + EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext; + EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *FirmwareContextHartSpecific; + + DEBUG ((DEBUG_INFO, "%a: Entry.\n", __FUNCTION__)); + + if (GuidHobdata =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + ThisHartSbiScratch =3D sbi_hart_id_to_scratch (sbi_scratch_thishart_ptr(= ), (UINT32)HartId); + DEBUG ((DEBUG_INFO, " SBI Scratch is at 0x%x.\n", ThisHartSbiScratch)= ); + ThisHartSbiPlatform =3D (struct sbi_platform *)sbi_platform_ptr(ThisHart= SbiScratch); + DEBUG ((DEBUG_INFO, " SBI platform is at 0x%x.\n", ThisHartSbiPlatfor= m)); + FirmwareContext =3D (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)ThisHartSbiPla= tform->firmware_context; + DEBUG ((DEBUG_INFO, " Firmware Context is at 0x%x.\n", FirmwareContex= t)); + FirmwareContextHartSpecific =3D FirmwareContext->HartSpecific[HartId]; + DEBUG ((DEBUG_INFO, " Firmware Context Hart specific is at 0x%x.\n", = FirmwareContextHartSpecific)); + + // + // Build up RISC_V_PROCESSOR_SPECIFIC_DATA_HOB. + // + CommonFirmwareContextHartSpecificInfo ( + FirmwareContextHartSpecific, + ParentProcessorGuid, + ParentProcessorUid, + (EFI_GUID *)PcdGetPtr (PcdSiFiveU54CoreGuid), + HartId, + IsBootHart, + &ProcessorSpecDataHob + ); + ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_= L =3D TO_BE_FILLED; + ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_= H =3D TO_BE_FILLED; + ProcessorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Valu= e64_L =3D TO_BE_FILLED; + ProcessorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Valu= e64_H =3D TO_BE_FILLED; + ProcessorSpecDataHob.ProcessorSpecificData.HartXlen =3D = RegisterLen64; + ProcessorSpecDataHob.ProcessorSpecificData.MachineModeXlen =3D = RegisterLen64; + ProcessorSpecDataHob.ProcessorSpecificData.SupervisorModeXlen =3D = RegisterUnsupported; + ProcessorSpecDataHob.ProcessorSpecificData.UserModeXlen =3D = RegisterLen64; + + DEBUG ((DEBUG_INFO, " *HartId =3D 0x%x\n", ProcessorSpecDataHob.P= rocessorSpecificData.HartId.Value64_L)); + DEBUG ((DEBUG_INFO, " *Is Boot Hart? =3D 0x%x\n", ProcessorSpecDa= taHob.ProcessorSpecificData.BootHartId)); + DEBUG ((DEBUG_INFO, " *PrivilegeModeSupported =3D 0x%x\n", Proces= sorSpecDataHob.ProcessorSpecificData.PrivilegeModeSupported)); + DEBUG ((DEBUG_INFO, " *MModeExcepDelegation =3D 0x%x\n", Processo= rSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_L)); + DEBUG ((DEBUG_INFO, " *MModeInterruptDelegation =3D 0x%x\n", Proc= essorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Value64_L)); + DEBUG ((DEBUG_INFO, " *HartXlen =3D 0x%x\n", ProcessorSpecDataHob= .ProcessorSpecificData.HartXlen )); + DEBUG ((DEBUG_INFO, " *MachineModeXlen =3D 0x%x\n", ProcessorSpec= DataHob.ProcessorSpecificData.MachineModeXlen)); + DEBUG ((DEBUG_INFO, " *SupervisorModeXlen =3D 0x%x\n", ProcessorS= pecDataHob.ProcessorSpecificData.SupervisorModeXlen)); + DEBUG ((DEBUG_INFO, " *UserModeXlen =3D 0x%x\n", ProcessorSpecDat= aHob.ProcessorSpecificData.UserModeXlen)); + DEBUG ((DEBUG_INFO, " *InstSetSupported =3D 0x%x\n", ProcessorSpe= cDataHob.ProcessorSpecificData.InstSetSupported)); + DEBUG ((DEBUG_INFO, " *MachineVendorId =3D 0x%x\n", ProcessorSpec= DataHob.ProcessorSpecificData.MachineVendorId.Value64_L)); + DEBUG ((DEBUG_INFO, " *MachineArchId =3D 0x%x\n", ProcessorSpecDa= taHob.ProcessorSpecificData.MachineArchId.Value64_L)); + DEBUG ((DEBUG_INFO, " *MachineImplId =3D 0x%x\n", ProcessorSpecDa= taHob.ProcessorSpecificData.MachineImplId.Value64_L)); + + // + // Build GUID HOB for U54 core. + // + ProcessorSpecDataHobGuid =3D PcdGetPtr (PcdProcessorSpecificDataGuidHobG= uid); + CoreGuidHob =3D (RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *)BuildGuidDataHob (= ProcessorSpecDataHobGuid, (VOID *)&ProcessorSpecDataHob, sizeof (RISC_V_PRO= CESSOR_SPECIFIC_DATA_HOB)); + if (CoreGuidHob =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive E51 core.\n")); + ASSERT (FALSE); + } + *GuidHobdata =3D CoreGuidHob; + return EFI_SUCCESS; +} + +/** + Function to build processor related SMBIOS information. RISC-V SMBIOS DX= E driver collect + this information and build SMBIOS Type4 and Type7 record. + + @param ProcessorUid Unique ID of pysical processor which owns this c= ore. + @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_DATA_= HOB. The pointers + maintained in this structure is only valid befor= e memory is discovered. + Access to those pointers after memory is install= ed will cause unexpected issues. + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +EFIAPI +CreateU54ProcessorSmbiosDataHob ( + IN UINTN ProcessorUid, + IN RISC_V_PROCESSOR_SMBIOS_DATA_HOB **SmbiosHobPtr + ) +{ + EFI_GUID *GuidPtr; + RISC_V_PROCESSOR_TYPE4_DATA_HOB ProcessorDataHob; + RISC_V_PROCESSOR_TYPE7_DATA_HOB L1InstCacheDataHob; + RISC_V_PROCESSOR_TYPE7_DATA_HOB L1DataCacheDataHob; + RISC_V_PROCESSOR_TYPE7_DATA_HOB L2CacheDataHob; + RISC_V_PROCESSOR_SMBIOS_DATA_HOB SmbiosDataHob; + RISC_V_PROCESSOR_TYPE4_DATA_HOB *ProcessorDataHobPtr; + RISC_V_PROCESSOR_TYPE7_DATA_HOB *L1InstCacheDataHobPtr; + RISC_V_PROCESSOR_TYPE7_DATA_HOB *L1DataCacheDataHobPtr; + RISC_V_PROCESSOR_TYPE7_DATA_HOB *L2CacheDataHobPtr; + RISC_V_PROCESSOR_SMBIOS_DATA_HOB *SmbiosDataHobPtr; + + if (SmbiosHobPtr =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + // + // Build up SMBIOS type 7 L1 instruction cache record. + // + ZeroMem((VOID *)&L1InstCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_DATA= _HOB)); + CopyGuid (&L1InstCacheDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSi= FiveU54CoreGuid)); + L1InstCacheDataHob.ProcessorUid =3D ProcessorUid; + L1InstCacheDataHob.SmbiosType7Cache.SocketDesignation =3D TO_BE_FILLED_B= Y_VENDOR; + L1InstCacheDataHob.SmbiosType7Cache.CacheConfiguration =3D RISC_V_CACHE_= CONFIGURATION_CACHE_LEVEL_1 | \ + RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL | \ + RISC_V_CACHE_CONFIGURATION_ENABLED | \ + RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN; + L1InstCacheDataHob.SmbiosType7Cache.MaximumCacheSize =3D TO_BE_FILLED_BY= _VENDOR; + L1InstCacheDataHob.SmbiosType7Cache.InstalledSize =3D TO_BE_FILLED_BY_VE= NDOR; + L1InstCacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown =3D 1; + L1InstCacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown =3D 1; + L1InstCacheDataHob.SmbiosType7Cache.CacheSpeed =3D TO_BE_FILLED_BY_VENDO= R; + L1InstCacheDataHob.SmbiosType7Cache.ErrorCorrectionType =3D TO_BE_FILLED= _BY_VENDOR; + L1InstCacheDataHob.SmbiosType7Cache.SystemCacheType =3D CacheTypeInstruc= tion; + L1InstCacheDataHob.SmbiosType7Cache.Associativity =3D TO_BE_FILLED_BY_VE= NDOR; + GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid); + L1InstCacheDataHobPtr =3D (RISC_V_PROCESSOR_TYPE7_DATA_HOB *)BuildGuidDa= taHob (GuidPtr, (VOID *)&L1InstCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7= _DATA_HOB)); + if (L1InstCacheDataHobPtr =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 core L1 in= struction cache RISC_V_PROCESSOR_TYPE7_DATA_HOB.\n")); + ASSERT (FALSE); + } + + // + // Build up SMBIOS type 7 L1 data cache record. + // + ZeroMem((VOID *)&L1DataCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_DATA= _HOB)); + CopyGuid (&L1DataCacheDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSi= FiveU54CoreGuid)); + L1DataCacheDataHob.ProcessorUid =3D ProcessorUid; + L1DataCacheDataHob.SmbiosType7Cache.SocketDesignation =3D TO_BE_FILLED_B= Y_VENDOR; + L1DataCacheDataHob.SmbiosType7Cache.CacheConfiguration =3D RISC_V_CACHE_= CONFIGURATION_CACHE_LEVEL_1 | \ + RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL | \ + RISC_V_CACHE_CONFIGURATION_ENABLED | \ + RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN; + L1DataCacheDataHob.SmbiosType7Cache.MaximumCacheSize =3D TO_BE_FILLED_BY= _VENDOR; + L1DataCacheDataHob.SmbiosType7Cache.InstalledSize =3D TO_BE_FILLED_BY_VE= NDOR; + L1DataCacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown =3D 1; + L1DataCacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown =3D 1; + L1DataCacheDataHob.SmbiosType7Cache.CacheSpeed =3D TO_BE_FILLED_BY_VENDO= R; + L1DataCacheDataHob.SmbiosType7Cache.ErrorCorrectionType =3D TO_BE_FILLED= _BY_VENDOR; + L1DataCacheDataHob.SmbiosType7Cache.SystemCacheType =3D CacheTypeData; + L1DataCacheDataHob.SmbiosType7Cache.Associativity =3D TO_BE_FILLED_BY_VE= NDOR; + GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid); + L1DataCacheDataHobPtr =3D (RISC_V_PROCESSOR_TYPE7_DATA_HOB *)BuildGuidDa= taHob (GuidPtr, (VOID *)&L1DataCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7= _DATA_HOB)); + if (L1DataCacheDataHobPtr =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 core L1 da= ta cache RISC_V_PROCESSOR_TYPE7_DATA_HOB.\n")); + ASSERT (FALSE); + } + + // + // Build up SMBIOS type 7 L2 cache record. + // + ZeroMem((VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_DATA_HOB= )); + CopyGuid (&L2CacheDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSiFive= U54CoreGuid)); + L2CacheDataHob.ProcessorUid =3D ProcessorUid; + L2CacheDataHob.SmbiosType7Cache.SocketDesignation =3D TO_BE_FILLED_BY_VE= NDOR; + L2CacheDataHob.SmbiosType7Cache.CacheConfiguration =3D RISC_V_CACHE_CONF= IGURATION_CACHE_LEVEL_2 | \ + RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL | \ + RISC_V_CACHE_CONFIGURATION_ENABLED | \ + RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN; + L2CacheDataHob.SmbiosType7Cache.MaximumCacheSize =3D TO_BE_FILLED_BY_VEN= DOR; + L2CacheDataHob.SmbiosType7Cache.InstalledSize =3D TO_BE_FILLED_BY_VENDOR; + L2CacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown =3D 1; + L2CacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown =3D 1; + L2CacheDataHob.SmbiosType7Cache.CacheSpeed =3D TO_BE_FILLED_BY_VENDOR; + L2CacheDataHob.SmbiosType7Cache.ErrorCorrectionType =3D TO_BE_FILLED_BY_= VENDOR; + L2CacheDataHob.SmbiosType7Cache.SystemCacheType =3D CacheTypeUnified; + L2CacheDataHob.SmbiosType7Cache.Associativity =3D TO_BE_FILLED_BY_VENDOR; + GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid); + L2CacheDataHobPtr =3D (RISC_V_PROCESSOR_TYPE7_DATA_HOB *)BuildGuidDataHo= b (GuidPtr, (VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_DATA_HO= B)); + if (L2CacheDataHobPtr =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 core L2 ca= che RISC_V_PROCESSOR_TYPE7_DATA_HOB.\n")); + ASSERT (FALSE); + } + + // + // Build up SMBIOS type 4 record. + // + ZeroMem((VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_DATA_H= OB)); + CopyGuid (&ProcessorDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSiFi= veU54CoreGuid)); + ProcessorDataHob.ProcessorUid =3D ProcessorUid; + ProcessorDataHob.SmbiosType4Processor.Socket =3D TO_BE_FILLED_BY_VENDOR; + ProcessorDataHob.SmbiosType4Processor.ProcessorType =3D CentralProcessor; + ProcessorDataHob.SmbiosType4Processor.ProcessorFamily =3D ProcessorFamil= yIndicatorFamily2; + ProcessorDataHob.SmbiosType4Processor.ProcessorManufacture =3D TO_BE_FIL= LED_BY_VENDOR; + SetMem ((VOID *)&ProcessorDataHob.SmbiosType4Processor.ProcessorId, size= of (PROCESSOR_ID_DATA), TO_BE_FILLED_BY_CODE); + ProcessorDataHob.SmbiosType4Processor.ProcessorVersion =3D TO_BE_FILLED_= BY_VENDOR; + ProcessorDataHob.SmbiosType4Processor.Voltage.ProcessorVoltageCapability= 3_3V =3D 1; + ProcessorDataHob.SmbiosType4Processor.ExternalClock =3D TO_BE_FILLED_BY_= VENDOR; + ProcessorDataHob.SmbiosType4Processor.MaxSpeed =3D TO_BE_FILLED_BY_VENDO= R; + ProcessorDataHob.SmbiosType4Processor.CurrentSpeed =3D TO_BE_FILLED_BY_V= ENDOR; + ProcessorDataHob.SmbiosType4Processor.Status =3D TO_BE_FILLED_BY_CODE; + ProcessorDataHob.SmbiosType4Processor.ProcessorUpgrade =3D TO_BE_FILLED_= BY_VENDOR; + ProcessorDataHob.SmbiosType4Processor.L1CacheHandle =3D TO_BE_FILLED_BY_= RISC_V_SMBIOS_DXE_DRIVER; + ProcessorDataHob.SmbiosType4Processor.L2CacheHandle =3D TO_BE_FILLED_BY_= RISC_V_SMBIOS_DXE_DRIVER; + ProcessorDataHob.SmbiosType4Processor.L3CacheHandle =3D 0xffff; + ProcessorDataHob.SmbiosType4Processor.SerialNumber =3D TO_BE_FILLED_BY_C= ODE; + ProcessorDataHob.SmbiosType4Processor.AssetTag =3D TO_BE_FILLED_BY_VENDO= R; + ProcessorDataHob.SmbiosType4Processor.PartNumber =3D TO_BE_FILLED_BY_VEN= DOR; + ProcessorDataHob.SmbiosType4Processor.CoreCount =3D 1; + ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount =3D 1; + ProcessorDataHob.SmbiosType4Processor.ThreadCount =3D 1; + ProcessorDataHob.SmbiosType4Processor.ProcessorCharacteristics =3D (UINT= 16)(1 << 2); // 64-bit capable + ProcessorDataHob.SmbiosType4Processor.ProcessorFamily2 =3D ProcessorFami= lyRiscVRV64; + ProcessorDataHob.SmbiosType4Processor.CoreCount2 =3D 0; + ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount2 =3D 0; + ProcessorDataHob.SmbiosType4Processor.ThreadCount2 =3D 0; + GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType4GuidHobGuid); + ProcessorDataHobPtr =3D (RISC_V_PROCESSOR_TYPE4_DATA_HOB *)BuildGuidData= Hob (GuidPtr, (VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_DAT= A_HOB)); + if (ProcessorDataHobPtr =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 core RISC_= V_PROCESSOR_TYPE4_DATA_HOB.\n")); + ASSERT (FALSE); + } + + ZeroMem((VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_DATA_HOB= )); + SmbiosDataHob.Processor =3D ProcessorDataHobPtr; + SmbiosDataHob.L1InstCache =3D L1InstCacheDataHobPtr; + SmbiosDataHob.L1DataCache =3D L1DataCacheDataHobPtr; + SmbiosDataHob.L2Cache =3D L2CacheDataHobPtr; + SmbiosDataHob.L3Cache =3D NULL; + GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosGuidHobGuid); + SmbiosDataHobPtr =3D (RISC_V_PROCESSOR_SMBIOS_DATA_HOB *)BuildGuidDataHo= b (GuidPtr, (VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_DATA_HO= B)); + if (SmbiosDataHobPtr =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 core RISC_= V_PROCESSOR_SMBIOS_DATA_HOB.\n")); + ASSERT (FALSE); + } + *SmbiosHobPtr =3D SmbiosDataHobPtr; + return EFI_SUCCESS; +} + diff --git a/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib= .inf b/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf new file mode 100644 index 00000000..8efee93b --- /dev/null +++ b/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf @@ -0,0 +1,51 @@ +## @file +# Library instance to create core information HOB +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SiliconSiFiveU54CoreInfoLib + FILE_GUID =3D 483DE090-267E-4278-A0A1-15D9836780EA + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SiliconSiFiveU54CoreInfoLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV +# + +[Sources] + CoreInfoHob.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + RiscVPkg/RiscVPkg.dec + Platform/RiscV/RiscVPlatformPkg.dec + Silicon/SiFive/SiFive.dec + +[LibraryClasses] + BaseLib + PcdLib + MemoryAllocationLib + PrintLib + FirmwareContextProcessorSpecificLib + +[Guids] + +[Ppis] + +[FixedPcd] + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSpecificDataGuidHobGuid + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid + gEfiSiFiveSiliconSpaceGuid.PcdSiFiveU54CoreGuid + diff --git a/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInf= oHob.c b/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob= .c new file mode 100644 index 00000000..e14b5977 --- /dev/null +++ b/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob.c @@ -0,0 +1,185 @@ +/**@file + Build up platform processor information. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +// The package level header files this module uses +// +#include + +// +// The Library classes this module consumes +// +#include +#include +#include + +#include +#include +#include + +/** + Build up processor-specific HOB for U54MC Coreplex + + @param UniqueId Unique ID of this U54MC Coreplex processor + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +EFIAPI +CreateU54MCCoreplexProcessorSpecificDataHob ( + IN UINTN UniqueId + ) +{ + EFI_STATUS Status; + RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *ThisGuidHobData; + EFI_GUID *ParentProcessorGuid; + + DEBUG ((DEBUG_INFO, "%a: Entry.\n", __FUNCTION__)); + + ParentProcessorGuid =3D PcdGetPtr (PcdSiFiveU54MCCoreplexGuid); + Status =3D CreateE51CoreProcessorSpecificDataHob (ParentProcessorGuid, U= niqueId, SIFIVE_U54MC_COREPLEX_E51_HART_ID, FALSE, &ThisGuidHobData); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "%a: Faile to build E51 core information HOB for = U54 Coreplex.\n", __FUNCTION__)); + return Status; + } + Status =3D CreateU54CoreProcessorSpecificDataHob (ParentProcessorGuid, U= niqueId, SIFIVE_U54_COREPLEX_U54MC_0_HART_ID, TRUE, &ThisGuidHobData); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "%a: Faile to build U54 core information HOB for = U54 Coreplex.\n", __FUNCTION__)); + return Status; + } + Status =3D CreateU54CoreProcessorSpecificDataHob (ParentProcessorGuid, U= niqueId, SIFIVE_U54_COREPLEX_U54MC_1_HART_ID, FALSE, &ThisGuidHobData); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "%a: Faile to build U54 core information HOB for = U54 Coreplex.\n", __FUNCTION__)); + return Status; + } + Status =3D CreateU54CoreProcessorSpecificDataHob (ParentProcessorGuid, U= niqueId, SIFIVE_U54_COREPLEX_U54MC_2_HART_ID, FALSE, &ThisGuidHobData); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "%a: Faile to build U54 core information HOB for = U54 Coreplex.\n", __FUNCTION__)); + return Status; + } + Status =3D CreateU54CoreProcessorSpecificDataHob (ParentProcessorGuid, U= niqueId, SIFIVE_U54_COREPLEX_U54MC_3_HART_ID, FALSE, &ThisGuidHobData); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "%a: Faile to build U54 core information HOB for = U54 Coreplex.\n", __FUNCTION__)); + return Status; + } + return Status; +} + +/** + Function to build processor related SMBIOS information. RISC-V SMBIOS DX= E driver collect + this information and build SMBIOS Type4 and Type7 record. + + @param ProcessorUid Unique ID of pysical processor which owns this c= ore. + @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_DATA_= HOB. The pointers + maintained in this structure is only valid befor= e memory is discovered. + Access to those pointers after memory is install= ed will cause unexpected issues. + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +EFIAPI +CreateU54MCProcessorSmbiosDataHob ( + IN UINTN ProcessorUid, + IN RISC_V_PROCESSOR_SMBIOS_DATA_HOB **SmbiosHobPtr + ) +{ + EFI_GUID *GuidPtr; + RISC_V_PROCESSOR_TYPE4_DATA_HOB ProcessorDataHob; + RISC_V_PROCESSOR_TYPE7_DATA_HOB L2CacheDataHob; + RISC_V_PROCESSOR_SMBIOS_DATA_HOB SmbiosDataHob; + RISC_V_PROCESSOR_TYPE4_DATA_HOB *ProcessorDataHobPtr; + RISC_V_PROCESSOR_TYPE7_DATA_HOB *L2CacheDataHobPtr; + RISC_V_PROCESSOR_SMBIOS_DATA_HOB *SmbiosDataHobPtr; + + if (SmbiosHobPtr =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + // + // Build up SMBIOS type 7 L2 cache record. + // + ZeroMem((VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_DATA_HOB= )); + L2CacheDataHob.PrcessorGuid =3D *((EFI_GUID *)PcdGetPtr (PcdSiFiveU54MCC= oreplexGuid)); + L2CacheDataHob.ProcessorUid =3D ProcessorUid; + L2CacheDataHob.SmbiosType7Cache.SocketDesignation =3D TO_BE_FILLED_BY_VE= NDOR; + L2CacheDataHob.SmbiosType7Cache.CacheConfiguration =3D RISC_V_CACHE_CONF= IGURATION_CACHE_LEVEL_2 | \ + RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL | \ + RISC_V_CACHE_CONFIGURATION_ENABLED | \ + RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN; + L2CacheDataHob.SmbiosType7Cache.MaximumCacheSize =3D TO_BE_FILLED_BY_VEN= DOR; + L2CacheDataHob.SmbiosType7Cache.InstalledSize =3D TO_BE_FILLED_BY_VENDOR; + L2CacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown =3D 1; + L2CacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown =3D 1; + L2CacheDataHob.SmbiosType7Cache.CacheSpeed =3D TO_BE_FILLED_BY_VENDOR; + L2CacheDataHob.SmbiosType7Cache.ErrorCorrectionType =3D TO_BE_FILLED_BY_= VENDOR; + L2CacheDataHob.SmbiosType7Cache.SystemCacheType =3D CacheTypeUnified; + L2CacheDataHob.SmbiosType7Cache.Associativity =3D TO_BE_FILLED_BY_VENDOR; + GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid); + L2CacheDataHobPtr =3D (RISC_V_PROCESSOR_TYPE7_DATA_HOB *)BuildGuidDataHo= b (GuidPtr, (VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_DATA_HO= B)); + if (L2CacheDataHobPtr =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 MC Coreple= x L2 cache RISC_V_PROCESSOR_TYPE7_DATA_HOB.\n")); + ASSERT (FALSE); + } + + // + // Build up SMBIOS type 4 record. + // + ZeroMem((VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_DATA_H= OB)); + ProcessorDataHob.PrcessorGuid =3D *((EFI_GUID *)PcdGetPtr (PcdSiFiveU54M= CCoreplexGuid)); + ProcessorDataHob.ProcessorUid =3D ProcessorUid; + ProcessorDataHob.SmbiosType4Processor.Socket =3D TO_BE_FILLED_BY_VENDOR; + ProcessorDataHob.SmbiosType4Processor.ProcessorType =3D CentralProcessor; + ProcessorDataHob.SmbiosType4Processor.ProcessorFamily =3D ProcessorFamil= yIndicatorFamily2; + ProcessorDataHob.SmbiosType4Processor.ProcessorManufacture =3D TO_BE_FIL= LED_BY_VENDOR; + SetMem ((VOID *)&ProcessorDataHob.SmbiosType4Processor.ProcessorId, size= of (PROCESSOR_ID_DATA), TO_BE_FILLED_BY_CODE); + ProcessorDataHob.SmbiosType4Processor.ProcessorVersion =3D TO_BE_FILLED_= BY_VENDOR; + ProcessorDataHob.SmbiosType4Processor.Voltage.ProcessorVoltageCapability= 3_3V =3D 1; + ProcessorDataHob.SmbiosType4Processor.ExternalClock =3D TO_BE_FILLED_BY_= VENDOR; + ProcessorDataHob.SmbiosType4Processor.MaxSpeed =3D TO_BE_FILLED_BY_VENDO= R; + ProcessorDataHob.SmbiosType4Processor.CurrentSpeed =3D TO_BE_FILLED_BY_V= ENDOR; + ProcessorDataHob.SmbiosType4Processor.Status =3D TO_BE_FILLED_BY_CODE; + ProcessorDataHob.SmbiosType4Processor.ProcessorUpgrade =3D TO_BE_FILLED_= BY_VENDOR; + ProcessorDataHob.SmbiosType4Processor.L1CacheHandle =3D TO_BE_FILLED_BY_= RISC_V_SMBIOS_DXE_DRIVER; + ProcessorDataHob.SmbiosType4Processor.L2CacheHandle =3D TO_BE_FILLED_BY_= RISC_V_SMBIOS_DXE_DRIVER; + ProcessorDataHob.SmbiosType4Processor.L3CacheHandle =3D 0xffff; + ProcessorDataHob.SmbiosType4Processor.SerialNumber =3D TO_BE_FILLED_BY_C= ODE; + ProcessorDataHob.SmbiosType4Processor.AssetTag =3D TO_BE_FILLED_BY_VENDO= R; + ProcessorDataHob.SmbiosType4Processor.PartNumber =3D TO_BE_FILLED_BY_VEN= DOR; + ProcessorDataHob.SmbiosType4Processor.CoreCount =3D 5; + ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount =3D 5; + ProcessorDataHob.SmbiosType4Processor.ThreadCount =3D 5; + ProcessorDataHob.SmbiosType4Processor.ProcessorCharacteristics =3D (UINT= 16)(1 << 2); // 64-bit capable + ProcessorDataHob.SmbiosType4Processor.ProcessorFamily2 =3D ProcessorFami= lyRiscVRV64; + ProcessorDataHob.SmbiosType4Processor.CoreCount2 =3D 0; + ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount2 =3D 0; + ProcessorDataHob.SmbiosType4Processor.ThreadCount2 =3D 0; + GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType4GuidHobGuid); + ProcessorDataHobPtr =3D (RISC_V_PROCESSOR_TYPE4_DATA_HOB *)BuildGuidData= Hob (GuidPtr, (VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_DAT= A_HOB)); + if (ProcessorDataHobPtr =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 MC Coreple= x RISC_V_PROCESSOR_TYPE4_DATA_HOB.\n")); + ASSERT (FALSE); + } + + ZeroMem((VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_DATA_HOB= )); + SmbiosDataHob.Processor =3D ProcessorDataHobPtr; + SmbiosDataHob.L1InstCache =3D NULL; + SmbiosDataHob.L1DataCache =3D NULL; + SmbiosDataHob.L2Cache =3D L2CacheDataHobPtr; + SmbiosDataHob.L3Cache =3D NULL; + GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosGuidHobGuid); + SmbiosDataHobPtr =3D (RISC_V_PROCESSOR_SMBIOS_DATA_HOB *)BuildGuidDataHo= b (GuidPtr, (VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_DATA_HO= B)); + if (SmbiosDataHobPtr =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54MC Coreplex= RISC_V_PROCESSOR_SMBIOS_DATA_HOB.\n")); + ASSERT (FALSE); + } + *SmbiosHobPtr =3D SmbiosDataHobPtr; + return EFI_SUCCESS; +} diff --git a/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/PeiCore= InfoHobLib.inf b/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/Pei= CoreInfoHobLib.inf new file mode 100644 index 00000000..a5714a20 --- /dev/null +++ b/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/PeiCoreInfoHob= Lib.inf @@ -0,0 +1,50 @@ +## @file +# Library instance to create core information HOB +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SiliconSiFiveU54MCCoreplexInfoLib + FILE_GUID =3D 483DE090-267E-4278-A0A1-15D9836780EA + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SiliconSiFiveU54MCCoreplexInfoLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV +# + +[Sources] + CoreInfoHob.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + RiscVPkg/RiscVPkg.dec + Silicon/SiFive/SiFive.dec + +[LibraryClasses] + BaseLib + PcdLib + MemoryAllocationLib + PrintLib + SiliconSiFiveE51CoreInfoLib + SiliconSiFiveU54CoreInfoLib + +[Guids] + +[Ppis] + +[FixedPcd] + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid + gEfiSiFiveSiliconSpaceGuid.PcdSiFiveU54MCCoreplexGuid + --=20 2.12.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47535): https://edk2.groups.io/g/devel/message/47535 Mute This Topic: https://groups.io/mt/34196349/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-