Today's code defines macros like CR0_PG, CR0_WP, CR4_PSE, CR4_PAE
when checking whether individual bits are set in CR0 or CR4 register.
The patch changes the code to use IA32_CR0 and IA32_CR4 structure
defined in MdePkg/Include/Library/BaseLib.h so that the module
local macros can be removed.
There is no functionality impact to this change.
Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
---
UefiCpuPkg/CpuDxe/CpuPageTable.c | 43 ++++++++++++++++++--------------
1 file changed, 24 insertions(+), 19 deletions(-)
diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.c b/UefiCpuPkg/CpuDxe/CpuPageTable.c
index c369b44f12..16a2528b55 100644
--- a/UefiCpuPkg/CpuDxe/CpuPageTable.c
+++ b/UefiCpuPkg/CpuDxe/CpuPageTable.c
@@ -1,7 +1,7 @@
/** @file
Page table management support.
- Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -21,14 +21,6 @@
#include "CpuDxe.h"
#include "CpuPageTable.h"
-///
-/// Paging registers
-///
-#define CR0_WP BIT16
-#define CR0_PG BIT31
-#define CR4_PSE BIT4
-#define CR4_PAE BIT5
-
///
/// Page Table Entry
///
@@ -161,6 +153,8 @@ GetCurrentPagingContext (
UINT32 RegEax;
CPUID_EXTENDED_CPU_SIG_EDX RegEdx;
MSR_IA32_EFER_REGISTER MsrEfer;
+ IA32_CR4 Cr4;
+ IA32_CR0 Cr0;
//
// Don't retrieve current paging context from processor if in SMM mode.
@@ -172,21 +166,24 @@ GetCurrentPagingContext (
} else {
mPagingContext.MachineType = IMAGE_FILE_MACHINE_I386;
}
- if ((AsmReadCr0 () & CR0_PG) != 0) {
+
+ Cr0.UintN = AsmReadCr0 ();
+ Cr4.UintN = AsmReadCr4 ();
+
+ if (Cr0.Bits.PG != 0) {
mPagingContext.ContextData.X64.PageTableBase = (AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64);
} else {
mPagingContext.ContextData.X64.PageTableBase = 0;
}
-
- if ((AsmReadCr4 () & CR4_PSE) != 0) {
+ if (Cr0.Bits.WP != 0) {
+ mPagingContext.ContextData.Ia32.Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_WP_ENABLE;
+ }
+ if (Cr4.Bits.PSE != 0) {
mPagingContext.ContextData.Ia32.Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PSE;
}
- if ((AsmReadCr4 () & CR4_PAE) != 0) {
+ if (Cr4.Bits.PAE != 0) {
mPagingContext.ContextData.Ia32.Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE;
}
- if ((AsmReadCr0 () & CR0_WP) != 0) {
- mPagingContext.ContextData.Ia32.Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_WP_ENABLE;
- }
AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);
if (RegEax >= CPUID_EXTENDED_CPU_SIG) {
@@ -581,12 +578,14 @@ IsReadOnlyPageWriteProtected (
VOID
)
{
+ IA32_CR0 Cr0;
//
// To avoid unforseen consequences, don't touch paging settings in SMM mode
// in this driver.
//
if (!IsInSmm ()) {
- return ((AsmReadCr0 () & CR0_WP) != 0);
+ Cr0.UintN = AsmReadCr0 ();
+ return (BOOLEAN) (Cr0.Bits.WP != 0);
}
return FALSE;
}
@@ -599,12 +598,15 @@ DisableReadOnlyPageWriteProtect (
VOID
)
{
+ IA32_CR0 Cr0;
//
// To avoid unforseen consequences, don't touch paging settings in SMM mode
// in this driver.
//
if (!IsInSmm ()) {
- AsmWriteCr0 (AsmReadCr0 () & ~CR0_WP);
+ Cr0.UintN = AsmReadCr0 ();
+ Cr0.Bits.WP = 0;
+ AsmWriteCr0 (Cr0.UintN);
}
}
@@ -616,12 +618,15 @@ EnableReadOnlyPageWriteProtect (
VOID
)
{
+ IA32_CR0 Cr0;
//
// To avoid unforseen consequences, don't touch paging settings in SMM mode
// in this driver.
//
if (!IsInSmm ()) {
- AsmWriteCr0 (AsmReadCr0 () | CR0_WP);
+ Cr0.UintN = AsmReadCr0 ();
+ Cr0.Bits.WP = 1;
+ AsmWriteCr0 (Cr0.UintN);
}
}
--
2.21.0.windows.1
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Reviewed-by: Eric Dong <eric.dong@intel.com>
> -----Original Message-----
> From: Ni, Ray
> Sent: Thursday, August 1, 2019 5:58 PM
> To: devel@edk2.groups.io
> Cc: Yao, Jiewen <jiewen.yao@intel.com>; Dong, Eric <eric.dong@intel.com>;
> Laszlo Ersek <lersek@redhat.com>
> Subject: [PATCH v4 2/8] UefiCpuPkg/CpuDxe: Remove unnecessary macros
>
> Today's code defines macros like CR0_PG, CR0_WP, CR4_PSE, CR4_PAE when
> checking whether individual bits are set in CR0 or CR4 register.
>
> The patch changes the code to use IA32_CR0 and IA32_CR4 structure defined
> in MdePkg/Include/Library/BaseLib.h so that the module local macros can be
> removed.
>
> There is no functionality impact to this change.
>
> Signed-off-by: Ray Ni <ray.ni@intel.com>
> Cc: Jiewen Yao <jiewen.yao@intel.com>
> Cc: Eric Dong <eric.dong@intel.com>
> Cc: Laszlo Ersek <lersek@redhat.com>
> ---
> UefiCpuPkg/CpuDxe/CpuPageTable.c | 43 ++++++++++++++++++------------
> --
> 1 file changed, 24 insertions(+), 19 deletions(-)
>
> diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.c
> b/UefiCpuPkg/CpuDxe/CpuPageTable.c
> index c369b44f12..16a2528b55 100644
> --- a/UefiCpuPkg/CpuDxe/CpuPageTable.c
> +++ b/UefiCpuPkg/CpuDxe/CpuPageTable.c
> @@ -1,7 +1,7 @@
> /** @file
> Page table management support.
>
> - Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> + Copyright (c) 2017 - 2019, Intel Corporation. All rights
> + reserved.<BR>
> Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent @@ -21,14 +21,6 @@
> #include "CpuDxe.h"
> #include "CpuPageTable.h"
>
> -///
> -/// Paging registers
> -///
> -#define CR0_WP BIT16
> -#define CR0_PG BIT31
> -#define CR4_PSE BIT4
> -#define CR4_PAE BIT5
> -
> ///
> /// Page Table Entry
> ///
> @@ -161,6 +153,8 @@ GetCurrentPagingContext (
> UINT32 RegEax;
> CPUID_EXTENDED_CPU_SIG_EDX RegEdx;
> MSR_IA32_EFER_REGISTER MsrEfer;
> + IA32_CR4 Cr4;
> + IA32_CR0 Cr0;
>
> //
> // Don't retrieve current paging context from processor if in SMM mode.
> @@ -172,21 +166,24 @@ GetCurrentPagingContext (
> } else {
> mPagingContext.MachineType = IMAGE_FILE_MACHINE_I386;
> }
> - if ((AsmReadCr0 () & CR0_PG) != 0) {
> +
> + Cr0.UintN = AsmReadCr0 ();
> + Cr4.UintN = AsmReadCr4 ();
> +
> + if (Cr0.Bits.PG != 0) {
> mPagingContext.ContextData.X64.PageTableBase = (AsmReadCr3 () &
> PAGING_4K_ADDRESS_MASK_64);
> } else {
> mPagingContext.ContextData.X64.PageTableBase = 0;
> }
> -
> - if ((AsmReadCr4 () & CR4_PSE) != 0) {
> + if (Cr0.Bits.WP != 0) {
> + mPagingContext.ContextData.Ia32.Attributes |=
> PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_WP_ENABLE;
> + }
> + if (Cr4.Bits.PSE != 0) {
> mPagingContext.ContextData.Ia32.Attributes |=
> PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PSE;
> }
> - if ((AsmReadCr4 () & CR4_PAE) != 0) {
> + if (Cr4.Bits.PAE != 0) {
> mPagingContext.ContextData.Ia32.Attributes |=
> PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE;
> }
> - if ((AsmReadCr0 () & CR0_WP) != 0) {
> - mPagingContext.ContextData.Ia32.Attributes |=
> PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_WP_ENABLE;
> - }
>
> AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);
> if (RegEax >= CPUID_EXTENDED_CPU_SIG) { @@ -581,12 +578,14 @@
> IsReadOnlyPageWriteProtected (
> VOID
> )
> {
> + IA32_CR0 Cr0;
> //
> // To avoid unforseen consequences, don't touch paging settings in SMM
> mode
> // in this driver.
> //
> if (!IsInSmm ()) {
> - return ((AsmReadCr0 () & CR0_WP) != 0);
> + Cr0.UintN = AsmReadCr0 ();
> + return (BOOLEAN) (Cr0.Bits.WP != 0);
> }
> return FALSE;
> }
> @@ -599,12 +598,15 @@ DisableReadOnlyPageWriteProtect (
> VOID
> )
> {
> + IA32_CR0 Cr0;
> //
> // To avoid unforseen consequences, don't touch paging settings in SMM
> mode
> // in this driver.
> //
> if (!IsInSmm ()) {
> - AsmWriteCr0 (AsmReadCr0 () & ~CR0_WP);
> + Cr0.UintN = AsmReadCr0 ();
> + Cr0.Bits.WP = 0;
> + AsmWriteCr0 (Cr0.UintN);
> }
> }
>
> @@ -616,12 +618,15 @@ EnableReadOnlyPageWriteProtect (
> VOID
> )
> {
> + IA32_CR0 Cr0;
> //
> // To avoid unforseen consequences, don't touch paging settings in SMM
> mode
> // in this driver.
> //
> if (!IsInSmm ()) {
> - AsmWriteCr0 (AsmReadCr0 () | CR0_WP);
> + Cr0.UintN = AsmReadCr0 ();
> + Cr0.Bits.WP = 1;
> + AsmWriteCr0 (Cr0.UintN);
> }
> }
>
> --
> 2.21.0.windows.1
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