From nobody Mon Feb 9 02:12:12 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+44780+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+44780+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1564653563; cv=none; d=zoho.com; s=zohoarc; b=Dieo7KsVgFXNV/IlaPGfWJTIc4tAj0F9gVpYfp9FR38axYKqKDZB57ttG9ldf12zvSWVsYvk4W3bEPTufTkcX9uJe2bOFqyN5OdrESddaewqofTYIeqiOjAFN/JU2A/LSiu1J8+vE6bNLk733bNcUkuaq7rs5tTtxKzhCjTtSd0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1564653563; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=vCbreXyqnLhkHc1lqOHXdxpDJbPfmm4WRbwolam9U90=; b=c5SY0wEvVrAI/vkrS7fUxFX5dtRNVr+AgGCSldMzCzpKp/XIdC5AQmXcg8W3vVQ011tcTBRYkKFcLis/cJkRJ6EqJEZUTAbO9JuAgHg8vJENBPVow6hkjmWN727S0RAnD0nPYeweleOW5vMg0qDPAHI3ORCtv/G01Ttb5WzKdW0= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+44780+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1564653563120767.2953245282175; Thu, 1 Aug 2019 02:59:23 -0700 (PDT) Return-Path: X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by groups.io with SMTP; Thu, 01 Aug 2019 02:59:22 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Aug 2019 02:59:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,333,1559545200"; d="scan'208";a="175203229" X-Received: from ray-dev.ccr.corp.intel.com ([10.239.9.9]) by orsmga003.jf.intel.com with ESMTP; 01 Aug 2019 02:59:14 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Jiewen Yao , Eric Dong , Laszlo Ersek Subject: [edk2-devel] [PATCH v4 2/8] UefiCpuPkg/CpuDxe: Remove unnecessary macros Date: Thu, 1 Aug 2019 17:58:25 +0800 Message-Id: <20190801095831.274356-3-ray.ni@intel.com> In-Reply-To: <20190801095831.274356-1-ray.ni@intel.com> References: <20190801095831.274356-1-ray.ni@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ray.ni@intel.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1564653562; bh=eG8WmgSyVmdE6FmwgQw4FqfKQH9KBtlLvevQ5ff46ns=; h=Cc:Date:From:Reply-To:Subject:To; b=lq6A2JGp7gYk2wAcfFXW3wtO5a2O95UeVqfyXdgELhig3oap1XUdvMhi0CXg/xZtZlf Fm4Sj0rccy9cSN9sTbTloiawOTDsiKs3hxdIkUMXZVXPeEwbGRpiGhax1nLK/K2s7FRtO LpbJtYDtYipz6+KVd4xfedOEfCeZiarRntQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Today's code defines macros like CR0_PG, CR0_WP, CR4_PSE, CR4_PAE when checking whether individual bits are set in CR0 or CR4 register. The patch changes the code to use IA32_CR0 and IA32_CR4 structure defined in MdePkg/Include/Library/BaseLib.h so that the module local macros can be removed. There is no functionality impact to this change. Signed-off-by: Ray Ni Cc: Jiewen Yao Cc: Eric Dong Cc: Laszlo Ersek Reviewed-by: Eric Dong --- UefiCpuPkg/CpuDxe/CpuPageTable.c | 43 ++++++++++++++++++-------------- 1 file changed, 24 insertions(+), 19 deletions(-) diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.c b/UefiCpuPkg/CpuDxe/CpuPageTa= ble.c index c369b44f12..16a2528b55 100644 --- a/UefiCpuPkg/CpuDxe/CpuPageTable.c +++ b/UefiCpuPkg/CpuDxe/CpuPageTable.c @@ -1,7 +1,7 @@ /** @file Page table management support. =20 - Copyright (c) 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent @@ -21,14 +21,6 @@ #include "CpuDxe.h" #include "CpuPageTable.h" =20 -/// -/// Paging registers -/// -#define CR0_WP BIT16 -#define CR0_PG BIT31 -#define CR4_PSE BIT4 -#define CR4_PAE BIT5 - /// /// Page Table Entry /// @@ -161,6 +153,8 @@ GetCurrentPagingContext ( UINT32 RegEax; CPUID_EXTENDED_CPU_SIG_EDX RegEdx; MSR_IA32_EFER_REGISTER MsrEfer; + IA32_CR4 Cr4; + IA32_CR0 Cr0; =20 // // Don't retrieve current paging context from processor if in SMM mode. @@ -172,21 +166,24 @@ GetCurrentPagingContext ( } else { mPagingContext.MachineType =3D IMAGE_FILE_MACHINE_I386; } - if ((AsmReadCr0 () & CR0_PG) !=3D 0) { + + Cr0.UintN =3D AsmReadCr0 (); + Cr4.UintN =3D AsmReadCr4 (); + + if (Cr0.Bits.PG !=3D 0) { mPagingContext.ContextData.X64.PageTableBase =3D (AsmReadCr3 () & PA= GING_4K_ADDRESS_MASK_64); } else { mPagingContext.ContextData.X64.PageTableBase =3D 0; } - - if ((AsmReadCr4 () & CR4_PSE) !=3D 0) { + if (Cr0.Bits.WP !=3D 0) { + mPagingContext.ContextData.Ia32.Attributes |=3D PAGE_TABLE_LIB_PAGIN= G_CONTEXT_IA32_X64_ATTRIBUTES_WP_ENABLE; + } + if (Cr4.Bits.PSE !=3D 0) { mPagingContext.ContextData.Ia32.Attributes |=3D PAGE_TABLE_LIB_PAGIN= G_CONTEXT_IA32_X64_ATTRIBUTES_PSE; } - if ((AsmReadCr4 () & CR4_PAE) !=3D 0) { + if (Cr4.Bits.PAE !=3D 0) { mPagingContext.ContextData.Ia32.Attributes |=3D PAGE_TABLE_LIB_PAGIN= G_CONTEXT_IA32_X64_ATTRIBUTES_PAE; } - if ((AsmReadCr0 () & CR0_WP) !=3D 0) { - mPagingContext.ContextData.Ia32.Attributes |=3D PAGE_TABLE_LIB_PAGIN= G_CONTEXT_IA32_X64_ATTRIBUTES_WP_ENABLE; - } =20 AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL); if (RegEax >=3D CPUID_EXTENDED_CPU_SIG) { @@ -581,12 +578,14 @@ IsReadOnlyPageWriteProtected ( VOID ) { + IA32_CR0 Cr0; // // To avoid unforseen consequences, don't touch paging settings in SMM m= ode // in this driver. // if (!IsInSmm ()) { - return ((AsmReadCr0 () & CR0_WP) !=3D 0); + Cr0.UintN =3D AsmReadCr0 (); + return (BOOLEAN) (Cr0.Bits.WP !=3D 0); } return FALSE; } @@ -599,12 +598,15 @@ DisableReadOnlyPageWriteProtect ( VOID ) { + IA32_CR0 Cr0; // // To avoid unforseen consequences, don't touch paging settings in SMM m= ode // in this driver. // if (!IsInSmm ()) { - AsmWriteCr0 (AsmReadCr0 () & ~CR0_WP); + Cr0.UintN =3D AsmReadCr0 (); + Cr0.Bits.WP =3D 0; + AsmWriteCr0 (Cr0.UintN); } } =20 @@ -616,12 +618,15 @@ EnableReadOnlyPageWriteProtect ( VOID ) { + IA32_CR0 Cr0; // // To avoid unforseen consequences, don't touch paging settings in SMM m= ode // in this driver. // if (!IsInSmm ()) { - AsmWriteCr0 (AsmReadCr0 () | CR0_WP); + Cr0.UintN =3D AsmReadCr0 (); + Cr0.Bits.WP =3D 1; + AsmWriteCr0 (Cr0.UintN); } } =20 --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#44780): https://edk2.groups.io/g/devel/message/44780 Mute This Topic: https://groups.io/mt/32677228/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-