From: Girish Pathak <girish.pathak at arm.com>

This change uses two PCDs, PcdArmLcdFrameBufferBase and
PcdArmLcdFrameBufferSize introduced in correspondiong EDK2 patch to
reserve framebuffer in DRAM if these values are defined in platform
specific DSC file, avoiding the need to allocate dynamically.
This allows the framebuffer to appear as "I/O memory" outside of the
normal RAM map, which is similar to the "VRAM" case.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Girish Pathak <girish.pathak@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
---

Notes:
    v3:
    - Move PcdArmLcdDdrFrameBufferBase and
      PcdArmLcdDdrFrameBufferSize to VExpressPkg.                 [Ard]
    
      These PCDs are also used for the Juno platform hence these
      PCDs are defined for the ArmPlatformPkg so that both
      platform can use it.                                        [Girish]
    
    - Could you please add an ASSERT() so that System Memory
      and PcdArmLcdDdrFrameBufferBase do not overlap              [Ard]
    
      Done                                                        [Girish]

 Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf |  4 +-
 Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c          | 41 ++++++++++++++------
 2 files changed, 32 insertions(+), 13 deletions(-)

diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf
index 8c6291c42f8a599591d00d7afcb2ff3399417034..b025abd98b5e654323b7821ac353ad920e2e6421 100644
--- a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf
+++ b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf
@@ -1,5 +1,5 @@
 #/* @file
-#  Copyright (c) 2011-2014, ARM Limited. All rights reserved.
+#  Copyright (c) 2011-2018, ARM Limited. All rights reserved.
 #
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD License
@@ -54,6 +54,8 @@ [FixedPcd]
   gArmTokenSpaceGuid.PcdArmPrimaryCore
 
   gArmPlatformTokenSpaceGuid.PcdCoreCount
+  gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferBase
+  gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferSize
 
 [Ppis]
   gArmMpCoreInfoPpiGuid
diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c
index 9fb0803d31ad0dbab59875bae99fd8a381d484b7..1d5fefc21726ba1b05d90e0e47677575d7fa2034 100644
--- a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c
+++ b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c
@@ -1,6 +1,6 @@
 /** @file
 *
-*  Copyright (c) 2011-2016, ARM Limited. All rights reserved.
+*  Copyright (c) 2011-2018, ARM Limited. All rights reserved.
 *
 *  This program and the accompanying materials
 *  are licensed and made available under the terms and conditions of the BSD License
@@ -128,17 +128,34 @@ ArmPlatformGetVirtualMemoryMap (
   VirtualMemoryTable[Index].Length = 2 * ARM_VE_SMB_PERIPH_SZ;
   VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
 
-  // VRAM
-  VirtualMemoryTable[++Index].PhysicalBase = PL111_CLCD_VRAM_MOTHERBOARD_BASE;
-  VirtualMemoryTable[Index].VirtualBase = PL111_CLCD_VRAM_MOTHERBOARD_BASE;
-  VirtualMemoryTable[Index].Length = PL111_CLCD_VRAM_MOTHERBOARD_SIZE;
-  //
-  // Map the VRAM region as Normal Non-Cacheable memory and not device memory,
-  // so that we can use the accelerated string routines that may use unaligned
-  // accesses or DC ZVA instructions. The enum identifier is slightly awkward
-  // here, but it maps to a memory type that allows buffering and reordering.
-  //
-  VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+  // Map region for the framebuffer in the system RAM if no VRAM present
+  if (FixedPcdGet32 (PcdArmLcdDdrFrameBufferBase) == 0) {
+    // VRAM
+    VirtualMemoryTable[++Index].PhysicalBase = PL111_CLCD_VRAM_MOTHERBOARD_BASE;
+    VirtualMemoryTable[Index].VirtualBase = PL111_CLCD_VRAM_MOTHERBOARD_BASE;
+    VirtualMemoryTable[Index].Length = PL111_CLCD_VRAM_MOTHERBOARD_SIZE;
+    //
+    // Map the VRAM region as Normal Non-Cacheable memory and not device memory,
+    // so that we can use the accelerated string routines that may use unaligned
+    // accesses or DC ZVA instructions. The enum identifier is slightly awkward
+    // here, but it maps to a memory type that allows buffering and reordering.
+    //
+    VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+
+  } else {
+    ASSERT ((ARM_VE_DRAM_BASE + ARM_VE_DRAM_SZ - 1) <
+            FixedPcdGet64 (PcdArmLcdDdrFrameBufferBase));
+    VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdArmLcdDdrFrameBufferBase);
+    VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdArmLcdDdrFrameBufferBase);
+    VirtualMemoryTable[Index].Length = FixedPcdGet32 (PcdArmLcdDdrFrameBufferSize);
+    // Map as Normal Non-Cacheable memory, so that we can use the accelerated
+    // SetMem/CopyMem routines that may use unaligned accesses or
+    // DC ZVA instructions. If mapped as device memory, these routine may cause
+    // alignment faults.
+    // NOTE: The attribute value is misleading, it indicates memory map type as
+    // an un-cached, un-buffered but allows buffering and reordering.
+    VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+  }
 
   // Map sparse memory region if present
   if (HasSparseMemory) {
-- 
'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)'


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