Even though the ARM ARM quite clearly states that the CNTFRQ field of
each MMIO timer frame should be a read-only alias of the CNTFRQ field
of the base frame, the SynQuacer SoC implements it as a register that
is programmable separately.
So let's program it from the hardware rather than overriding the
frequency using a DT property.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 1 -
Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 18 ++++++++++++++++++
Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h | 1 +
Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf | 2 ++
Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h | 3 +++
5 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
index 12b90a64da8b..3db3c5ed1c50 100644
--- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
+++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
@@ -368,7 +368,6 @@
mmio-timer@2a810000 {
compatible = "arm,armv7-timer-mem";
reg = <0x0 0x2a810000 0x0 0x10000>;
- clock-frequency = <100000000>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c
index 7d7d2ec80e8e..aab830dc3a5a 100644
--- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c
+++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c
@@ -174,6 +174,23 @@ SmmuEnableCoherentDma (
SMMU_SCR0_SHCFG_INNER | SMMU_SCR0_MTCFG | SMMU_SCR0_MEMATTR_INNER_OUTER_WB);
}
+#define MMIO_TIMER_CNTFRQ_OFFSET 0x10
+
+STATIC
+VOID
+SetMmioTimerFrequency (
+ VOID
+ )
+{
+ //
+ // Initialize the CNTFRQ field of the first non-secure MMIO timer frame.
+ // This field should be a read-only alias of the global frequency register
+ // but in reality, it is a separate field that needs to be set explicitly.
+ //
+ MmioWrite32 (SYNQUACER_MMIO_TIMER_CNT_BASE0 + MMIO_TIMER_CNTFRQ_OFFSET,
+ ArmGenericTimerGetTimerFreq ());
+}
+
STATIC
EFI_STATUS
InstallHiiPages (
@@ -297,6 +314,7 @@ PlatformDxeEntryPoint (
ASSERT_EFI_ERROR (Status);
SmmuEnableCoherentDma ();
+ SetMmioTimerFrequency ();
Status = RegisterPcieNotifier ();
ASSERT_EFI_ERROR (Status);
diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h
index b109bd359e13..a391d2f67c29 100644
--- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h
+++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h
@@ -18,6 +18,7 @@
#include <PiDxe.h>
#include <Guid/SynQuacerPlatformFormSet.h>
#include <IndustryStandard/Pci.h>
+#include <Library/ArmGenericTimerCounterLib.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf
index e13e16f3da6b..49d9deee57ea 100644
--- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf
+++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf
@@ -30,6 +30,7 @@ [Sources]
PlatformDxeHii.vfr
[Packages]
+ ArmPkg/ArmPkg.dec
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
@@ -38,6 +39,7 @@ [Packages]
Silicon/Socionext/SynQuacer/SynQuacer.dec
[LibraryClasses]
+ ArmGenericTimerCounterLib
BaseLib
BaseMemoryLib
DebugLib
diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h
index f43adcc8607f..fff760477488 100644
--- a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h
+++ b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h
@@ -69,4 +69,7 @@
#define SYNQUACER_SCB_SMMU_BASE 0x52E00000
#define SYNQUACER_SCB_SMMU_SIZE SIZE_64KB
+#define SYNQUACER_MMIO_TIMER_CTL_BASE 0x2A810000
+#define SYNQUACER_MMIO_TIMER_CNT_BASE0 0x2A830000
+
#endif
--
2.11.0
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