From nobody Fri Nov 1 12:29:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1517240694859692.9647092852629; Mon, 29 Jan 2018 07:44:54 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 3EF5221E25682; Mon, 29 Jan 2018 07:39:19 -0800 (PST) Received: from mail-wr0-x242.google.com (mail-wr0-x242.google.com [IPv6:2a00:1450:400c:c0c::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 683772215BDAE for ; Mon, 29 Jan 2018 07:39:17 -0800 (PST) Received: by mail-wr0-x242.google.com with SMTP id d9so7738197wre.3 for ; Mon, 29 Jan 2018 07:44:51 -0800 (PST) Received: from localhost.localdomain ([160.90.205.229]) by smtp.gmail.com with ESMTPSA id m191sm8670928wma.42.2018.01.29.07.44.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 29 Jan 2018 07:44:49 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::242; helo=mail-wr0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=AFeDLG6uQ5ZHPY762BrnIGCSc7+LwxeXOVQWYuWHVsY=; b=RbS9iq3SRoZOuBEil+YjEn6/G9A+u6yKZskSrg5rlHuwsaZ7YGO3uts9qGuKXEZnKu lECc5P9DQp5bToyplO0kyNXKq6pjgQ6FR35T9cVB2Pel26KG81Ze7MW+3FK0gGCRG+2B LLqBmGnV9izLNfpp4wbzXouk8AAeXAohrzoVg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AFeDLG6uQ5ZHPY762BrnIGCSc7+LwxeXOVQWYuWHVsY=; b=thsfKREnJ9VeaEPyTXbDk6hcuwnxvPJpMYhkKnS4Ql2l2mXPn499le70DL7NXmoR0o AlUHRHY2U+eR0bOJ/mtQ+LA983ADa+KNtXtC8sTPt+qb1HxBGpKGQZ2JB6jHnqhLNaPS zrbMUCq6iYw6k5DWqUN61FwaibosPT8ncVPvv7Q3T7fqsY+Kzh3c8qSLDRYMsOGcI2K7 SFjhrg/eVxFHTJN0XO2ySf5rWrZjIqp2r5CLWjJD3nBlCA7f5xTsrnlho6gngwVUtiq3 XLYhyItH6fyTxauqrgSxs704m99tjfPlmjFoEv39a7s5MNGBgpaxI0bLrL6DoVmNgliR NIrQ== X-Gm-Message-State: AKwxytdW3EU0UIfJTavck/uDy/gv6KjBE6ldOxwI1iH5i6E7fpyA70Eq LUrtLj1ByhT3h+e4urglaxYVPoxqk4M= X-Google-Smtp-Source: AH8x227B0C5PtZNkYSv2TqU64Yhsy2DoN4LqjENojMLwN1U6j6NOcNUJNZxJf22jyG/gPF1Ki/TzbQ== X-Received: by 10.223.187.72 with SMTP id x8mr21518181wrg.179.1517240689813; Mon, 29 Jan 2018 07:44:49 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Mon, 29 Jan 2018 15:44:15 +0000 Message-Id: <20180129154416.3622-4-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180129154416.3622-1-ard.biesheuvel@linaro.org> References: <20180129154416.3622-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 3/4] Silicon/SynQuacer: set CNTFRQ field of MMIO timer frame X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Even though the ARM ARM quite clearly states that the CNTFRQ field of each MMIO timer frame should be a read-only alias of the CNTFRQ field of the base frame, the SynQuacer SoC implements it as a register that is programmable separately. So let's program it from the hardware rather than overriding the frequency using a DT property. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 1 - Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 18 +++++= +++++++++++++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h | 1 + Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf | 2 ++ Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h | 3 +++ 5 files changed, 24 insertions(+), 1 deletion(-) diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silico= n/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index 12b90a64da8b..3db3c5ed1c50 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -368,7 +368,6 @@ mmio-timer@2a810000 { compatible =3D "arm,armv7-timer-mem"; reg =3D <0x0 0x2a810000 0x0 0x10000>; - clock-frequency =3D <100000000>; #address-cells =3D <2>; #size-cells =3D <2>; ranges; diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c = b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c index 7d7d2ec80e8e..aab830dc3a5a 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c @@ -174,6 +174,23 @@ SmmuEnableCoherentDma ( SMMU_SCR0_SHCFG_INNER | SMMU_SCR0_MTCFG | SMMU_SCR0_MEMATTR_INNER_OUTE= R_WB); } =20 +#define MMIO_TIMER_CNTFRQ_OFFSET 0x10 + +STATIC +VOID +SetMmioTimerFrequency ( + VOID + ) +{ + // + // Initialize the CNTFRQ field of the first non-secure MMIO timer frame. + // This field should be a read-only alias of the global frequency regist= er + // but in reality, it is a separate field that needs to be set explicitl= y. + // + MmioWrite32 (SYNQUACER_MMIO_TIMER_CNT_BASE0 + MMIO_TIMER_CNTFRQ_OFFSET, + ArmGenericTimerGetTimerFreq ()); +} + STATIC EFI_STATUS InstallHiiPages ( @@ -297,6 +314,7 @@ PlatformDxeEntryPoint ( ASSERT_EFI_ERROR (Status); =20 SmmuEnableCoherentDma (); + SetMmioTimerFrequency (); =20 Status =3D RegisterPcieNotifier (); ASSERT_EFI_ERROR (Status); diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h = b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h index b109bd359e13..a391d2f67c29 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.in= f b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf index e13e16f3da6b..49d9deee57ea 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf @@ -30,6 +30,7 @@ [Sources] PlatformDxeHii.vfr =20 [Packages] + ArmPkg/ArmPkg.dec EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec @@ -38,6 +39,7 @@ [Packages] Silicon/Socionext/SynQuacer/SynQuacer.dec =20 [LibraryClasses] + ArmGenericTimerCounterLib BaseLib BaseMemoryLib DebugLib diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h b/Sil= icon/Socionext/SynQuacer/Include/Platform/MemoryMap.h index f43adcc8607f..fff760477488 100644 --- a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h +++ b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h @@ -69,4 +69,7 @@ #define SYNQUACER_SCB_SMMU_BASE 0x52E00000 #define SYNQUACER_SCB_SMMU_SIZE SIZE_64KB =20 +#define SYNQUACER_MMIO_TIMER_CTL_BASE 0x2A810000 +#define SYNQUACER_MMIO_TIMER_CNT_BASE0 0x2A830000 + #endif --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel