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[edk2-devel] [edk2-platforms v3 5/6] Silicon/NXP/LS1046A: Apply USB errata workarounds

Meenakshi Aggarwal posted 6 patches 5 years, 4 months ago
Only 3 patches received!
[edk2-devel] [edk2-platforms v3 5/6] Silicon/NXP/LS1046A: Apply USB errata workarounds
Posted by Meenakshi Aggarwal 5 years, 4 months ago 
Apply USB errata workarounds for LS1046A SoC and
make SATA, USB and SEC snoopable.

Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
 Silicon/NXP/LS1046A/LS1046A.dsc.inc           |  1 +
 Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf |  1 +
 Silicon/NXP/LS1046A/Include/Soc.h             |  2 +
 Silicon/NXP/LS1046A/Library/SocLib/SocLib.c   | 65 +++++++++++++++++++++++++++
 4 files changed, 69 insertions(+)

diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
index db110553605f..4e1d6a7ae7a2 100644
--- a/Silicon/NXP/LS1046A/LS1046A.dsc.inc
+++ b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
@@ -34,6 +34,7 @@ [PcdsFixedAtBuild.common]
 
 [PcdsFeatureFlag]
   gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
+  gNxpQoriqLsTokenSpaceGuid.PcdScfgBigEndian|TRUE
   gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerBigEndian|TRUE
 
 ################################################################################
diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
index 01ed0f6592d2..36c09778b134 100644
--- a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
+++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
@@ -14,6 +14,7 @@ [Defines]
   LIBRARY_CLASS                  = SocLib
 
 [Packages]
+  ArmPkg/ArmPkg.dec
   MdePkg/MdePkg.dec
   Silicon/NXP/Chassis2/Chassis2.dec
   Silicon/NXP/LS1046A/LS1046A.dec
diff --git a/Silicon/NXP/LS1046A/Include/Soc.h b/Silicon/NXP/LS1046A/Include/Soc.h
index 84f433d5cb94..e1d97e531263 100644
--- a/Silicon/NXP/LS1046A/Include/Soc.h
+++ b/Silicon/NXP/LS1046A/Include/Soc.h
@@ -25,6 +25,7 @@
 #define LS1046A_QSPI0_SIZE           (SIZE_512MB)
 
 #define LS1046A_DCFG_ADDRESS         NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS
+#define LS1046A_SCFG_ADDRESS         NXP_LAYERSCAPE_CHASSIS2_SCFG_ADDRESS
 
 /**
   Reset Control Word (RCW) Bits
@@ -59,5 +60,6 @@ Bit(s) | Field Name  | Description                  | Notes/comments
 #define SYS_PLL_RAT(x)  (((x) >> 25) & 0x1f) // Bits 2-6
 
 typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG LS1046A_DEVICE_CONFIG;
+typedef NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG LS1046A_SUPPLEMENTAL_CONFIG;
 
 #endif // SOC_H__
diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
index 3b15aee6ecae..7726faf748cb 100644
--- a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
+++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
@@ -11,6 +11,7 @@
 #include <Library/ChassisLib.h>
 #include <Library/DebugLib.h>
 #include <Library/SocLib.h>
+
 #include <Soc.h>
 
 /**
@@ -65,6 +66,47 @@ SocGetClock (
 }
 
 /**
+   Function to select pins depending upon pcd using supplemental
+   configuration unit(SCFG) extended RCW controlled pinmux control
+   register which contains the bits to provide pin multiplexing control.
+   This register is reset on HRESET.
+ **/
+STATIC
+VOID
+ConfigScfgMux (VOID)
+{
+  LS1046A_SUPPLEMENTAL_CONFIG  *Scfg;
+  UINT32 UsbPwrFault;
+
+  Scfg = (LS1046A_SUPPLEMENTAL_CONFIG *)LS1046A_SCFG_ADDRESS;
+  // Configures functionality of the IIC3_SCL to USB2_DRVVBUS
+  // Configures functionality of the IIC3_SDA to USB2_PWRFAULT
+  // USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA
+  ScfgWrite32 ((UINTN)&Scfg->RcwPMuxCr0, SCFG_RCWPMUXCRO_NOT_SELCR_USB);
+
+  ScfgWrite32 ((UINTN)&Scfg->UsbDrvVBusSelCr, SCFG_USBDRVVBUS_SELCR_USB1);
+  UsbPwrFault = (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
+                (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
+                (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
+  ScfgWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault);
+  ScfgWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault);
+}
+
+STATIC
+VOID
+ApplyErrata (
+  VOID
+  )
+{
+  ErratumA008997 ();
+  ErratumA009007 ();
+  ErratumA009008 ();
+  ErratumA009798 ();
+}
+
+
+
+/**
   Function to initialize SoC specific constructs
  **/
 VOID
@@ -72,7 +114,30 @@ SocInit (
   VOID
   )
 {
+  LS1046A_SUPPLEMENTAL_CONFIG  *Scfg;
+
+  Scfg = (LS1046A_SUPPLEMENTAL_CONFIG *)LS1046A_SCFG_ADDRESS;
+
+  /* Make SEC, SATA and USB reads and writes snoopable */
+  ScfgOr32((UINTN)&Scfg->SnpCnfgCr, SCFG_SNPCNFGCR_SECRDSNP |
+    SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
+    SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
+    SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
+    SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
+    SCFG_SNPCNFGCR_SATAWRSNP);
+
+  ApplyErrata ();
   ChassisInit ();
 
+  //
+  // Due to the extensive functionality present on the chip and the limited number of external
+  // signals available, several functional blocks share signal resources through multiplexing.
+  // In this case when there is alternate functionality between multiple functional blocks,
+  // the signal's function is determined at the chip level (rather than at the block level)
+  // typically by a reset configuration word (RCW) option. Some of the signals' function are
+  // determined externel to RCW at Power-on Reset Sequence.
+  //
+  ConfigScfgMux ();
+
   return;
 }
-- 
1.9.1



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Re: [edk2-devel] [edk2-platforms v3 5/6] Silicon/NXP/LS1046A: Apply USB errata workarounds
Posted by Leif Lindholm 5 years, 4 months ago 
On Fri, Oct 09, 2020 at 20:49:03 +0530, Meenakshi Aggarwal wrote:
> Apply USB errata workarounds for LS1046A SoC and
> make SATA, USB and SEC snoopable.
> 
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
>  Silicon/NXP/LS1046A/LS1046A.dsc.inc           |  1 +
>  Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf |  1 +
>  Silicon/NXP/LS1046A/Include/Soc.h             |  2 +
>  Silicon/NXP/LS1046A/Library/SocLib/SocLib.c   | 65 +++++++++++++++++++++++++++
>  4 files changed, 69 insertions(+)
> 
> diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
> index db110553605f..4e1d6a7ae7a2 100644
> --- a/Silicon/NXP/LS1046A/LS1046A.dsc.inc
> +++ b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
> @@ -34,6 +34,7 @@ [PcdsFixedAtBuild.common]
>  
>  [PcdsFeatureFlag]
>    gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
> +  gNxpQoriqLsTokenSpaceGuid.PcdScfgBigEndian|TRUE
>    gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerBigEndian|TRUE
>  
>  ################################################################################
> diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
> index 01ed0f6592d2..36c09778b134 100644
> --- a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
> +++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
> @@ -14,6 +14,7 @@ [Defines]
>    LIBRARY_CLASS                  = SocLib
>  
>  [Packages]
> +  ArmPkg/ArmPkg.dec
>    MdePkg/MdePkg.dec
>    Silicon/NXP/Chassis2/Chassis2.dec
>    Silicon/NXP/LS1046A/LS1046A.dec
> diff --git a/Silicon/NXP/LS1046A/Include/Soc.h b/Silicon/NXP/LS1046A/Include/Soc.h
> index 84f433d5cb94..e1d97e531263 100644
> --- a/Silicon/NXP/LS1046A/Include/Soc.h
> +++ b/Silicon/NXP/LS1046A/Include/Soc.h
> @@ -25,6 +25,7 @@
>  #define LS1046A_QSPI0_SIZE           (SIZE_512MB)
>  
>  #define LS1046A_DCFG_ADDRESS         NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS
> +#define LS1046A_SCFG_ADDRESS         NXP_LAYERSCAPE_CHASSIS2_SCFG_ADDRESS
>  
>  /**
>    Reset Control Word (RCW) Bits
> @@ -59,5 +60,6 @@ Bit(s) | Field Name  | Description                  | Notes/comments
>  #define SYS_PLL_RAT(x)  (((x) >> 25) & 0x1f) // Bits 2-6
>  
>  typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG LS1046A_DEVICE_CONFIG;
> +typedef NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG LS1046A_SUPPLEMENTAL_CONFIG;
>  
>  #endif // SOC_H__
> diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
> index 3b15aee6ecae..7726faf748cb 100644
> --- a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
> +++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
> @@ -11,6 +11,7 @@
>  #include <Library/ChassisLib.h>
>  #include <Library/DebugLib.h>
>  #include <Library/SocLib.h>
> +

Please take the time to look through the generated patches before
sending. I will delete this spurious blank line addition when pushing,
but it shouldn't have been there in the first place.

/
    Leif

>  #include <Soc.h>
>  
>  /**
> @@ -65,6 +66,47 @@ SocGetClock (
>  }
>  
>  /**
> +   Function to select pins depending upon pcd using supplemental
> +   configuration unit(SCFG) extended RCW controlled pinmux control
> +   register which contains the bits to provide pin multiplexing control.
> +   This register is reset on HRESET.
> + **/
> +STATIC
> +VOID
> +ConfigScfgMux (VOID)
> +{
> +  LS1046A_SUPPLEMENTAL_CONFIG  *Scfg;
> +  UINT32 UsbPwrFault;
> +
> +  Scfg = (LS1046A_SUPPLEMENTAL_CONFIG *)LS1046A_SCFG_ADDRESS;
> +  // Configures functionality of the IIC3_SCL to USB2_DRVVBUS
> +  // Configures functionality of the IIC3_SDA to USB2_PWRFAULT
> +  // USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA
> +  ScfgWrite32 ((UINTN)&Scfg->RcwPMuxCr0, SCFG_RCWPMUXCRO_NOT_SELCR_USB);
> +
> +  ScfgWrite32 ((UINTN)&Scfg->UsbDrvVBusSelCr, SCFG_USBDRVVBUS_SELCR_USB1);
> +  UsbPwrFault = (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
> +                (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
> +                (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
> +  ScfgWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault);
> +  ScfgWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault);
> +}
> +
> +STATIC
> +VOID
> +ApplyErrata (
> +  VOID
> +  )
> +{
> +  ErratumA008997 ();
> +  ErratumA009007 ();
> +  ErratumA009008 ();
> +  ErratumA009798 ();
> +}
> +
> +
> +
> +/**
>    Function to initialize SoC specific constructs
>   **/
>  VOID
> @@ -72,7 +114,30 @@ SocInit (
>    VOID
>    )
>  {
> +  LS1046A_SUPPLEMENTAL_CONFIG  *Scfg;
> +
> +  Scfg = (LS1046A_SUPPLEMENTAL_CONFIG *)LS1046A_SCFG_ADDRESS;
> +
> +  /* Make SEC, SATA and USB reads and writes snoopable */
> +  ScfgOr32((UINTN)&Scfg->SnpCnfgCr, SCFG_SNPCNFGCR_SECRDSNP |
> +    SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
> +    SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
> +    SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
> +    SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
> +    SCFG_SNPCNFGCR_SATAWRSNP);
> +
> +  ApplyErrata ();
>    ChassisInit ();
>  
> +  //
> +  // Due to the extensive functionality present on the chip and the limited number of external
> +  // signals available, several functional blocks share signal resources through multiplexing.
> +  // In this case when there is alternate functionality between multiple functional blocks,
> +  // the signal's function is determined at the chip level (rather than at the block level)
> +  // typically by a reset configuration word (RCW) option. Some of the signals' function are
> +  // determined externel to RCW at Power-on Reset Sequence.
> +  //
> +  ConfigScfgMux ();
> +
>    return;
>  }
> -- 
> 1.9.1
> 


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