From nobody Tue Feb 10 21:41:27 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+66069+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+66069+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=oss.nxp.com ARC-Seal: i=1; a=rsa-sha256; t=1602244927; cv=none; d=zohomail.com; s=zohoarc; b=gYdt2RiTIx6uE1nbqTB/PaBfrMLBBnL4jx1MkDnsgK18xSVbYofxoFZI+XIn1UqVF4y1AqqgQXbQA8sOD6LU+ng4qKc8trRIA6Lognl8q4i+tU2CAtNKmwVzRqHAphD3OPjeGIaJjtRTunlRIbZv0NwYgeoHGFnKx1fXvSgJK1M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1602244927; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=hpOV1dJ7GwiSASEUvT+brN0zCFzRjSQBhyjssiSrygw=; b=PfDYrYAeY3hBnQbsTzjrdzoLpiqV9oaY7VCXugLw9UlwQ3eNmlQiNS020HXYSsD17xOTYBkbgO/qeJvP6OWcHoIWnKRAsy/rAnn9SSj3JFxuVkRKtGwXlrVF1R0vmaxsMqfyid2I8F0tHk8/tyDDnTAyniZxRcpkQyIEquMjp4A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+66069+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1602244927131842.3644328587515; Fri, 9 Oct 2020 05:02:07 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id ikMIYY1788612xEjkyi2DdLM; Fri, 09 Oct 2020 05:02:06 -0700 X-Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by mx.groups.io with SMTP id smtpd.web10.9966.1602236269568902944 for ; Fri, 09 Oct 2020 02:37:50 -0700 X-Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 239CB1A0D9F; Fri, 9 Oct 2020 11:37:48 +0200 (CEST) X-Received: from inv0113.in-blr01.nxp.com (inv0113.in-blr01.nxp.com [165.114.116.118]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id BDBE01A0D54; Fri, 9 Oct 2020 11:37:47 +0200 (CEST) X-Received: from uefi-OptiPlex-790.ap.freescale.net (unknown [10.232.132.78]) by inv0113.in-blr01.nxp.com (Postfix) with ESMTP id 7CF9A35E; Fri, 9 Oct 2020 15:07:46 +0530 (IST) From: Meenakshi Aggarwal To: ard.biesheuvel@arm.com, leif@nuviainc.com, michael.d.kinney@intel.com, devel@edk2.groups.io Cc: v.sethi@nxp.com, Meenakshi Aggarwal , Meenakshi Aggarwal Subject: [edk2-devel] [edk2-platforms v3 5/6] Silicon/NXP/LS1046A: Apply USB errata workarounds Date: Fri, 9 Oct 2020 20:49:03 +0530 Message-Id: <1602256744-12582-3-git-send-email-meenakshi.aggarwal@oss.nxp.com> In-Reply-To: <1602256744-12582-1-git-send-email-meenakshi.aggarwal@oss.nxp.com> References: <1602087041-8009-7-git-send-email-meenakshi.aggarwal@oss.nxp.com> <1602256744-12582-1-git-send-email-meenakshi.aggarwal@oss.nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,meenakshi.aggarwal@oss.nxp.com X-Gm-Message-State: Q0Qq3NnSHPwtBzekYOxFxT2sx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1602244926; bh=1bopVuHaoYCpoyiJXFeKknSzFZjCVWXhU/Wfvad24y0=; h=Cc:Date:From:Reply-To:Subject:To; b=cpAbG+4c9vw7Zog3XTpzq0bU3tMg8a+b6SqvUC2aCmhrS4DPPGyClGUVFEWj6s8n30Y 3tI1I9q6qLa/E1fXyueCmKCHa90qAt7sy1j9gBKyufLh9AkhJg1rsLtdgeUjvPG95InHx 3srAFcw9ffZpowQlK1jjNcUia11Ulby9RbI= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Apply USB errata workarounds for LS1046A SoC and make SATA, USB and SEC snoopable. Signed-off-by: Meenakshi Aggarwal --- Silicon/NXP/LS1046A/LS1046A.dsc.inc | 1 + Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf | 1 + Silicon/NXP/LS1046A/Include/Soc.h | 2 + Silicon/NXP/LS1046A/Library/SocLib/SocLib.c | 65 +++++++++++++++++++++++= ++++ 4 files changed, 69 insertions(+) diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc b/Silicon/NXP/LS1046A/LS10= 46A.dsc.inc index db110553605f..4e1d6a7ae7a2 100644 --- a/Silicon/NXP/LS1046A/LS1046A.dsc.inc +++ b/Silicon/NXP/LS1046A/LS1046A.dsc.inc @@ -34,6 +34,7 @@ [PcdsFixedAtBuild.common] =20 [PcdsFeatureFlag] gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE + gNxpQoriqLsTokenSpaceGuid.PcdScfgBigEndian|TRUE gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerBigEndian|TRUE =20 ##########################################################################= ###### diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf b/Silicon/NXP/LS= 1046A/Library/SocLib/SocLib.inf index 01ed0f6592d2..36c09778b134 100644 --- a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf +++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf @@ -14,6 +14,7 @@ [Defines] LIBRARY_CLASS =3D SocLib =20 [Packages] + ArmPkg/ArmPkg.dec MdePkg/MdePkg.dec Silicon/NXP/Chassis2/Chassis2.dec Silicon/NXP/LS1046A/LS1046A.dec diff --git a/Silicon/NXP/LS1046A/Include/Soc.h b/Silicon/NXP/LS1046A/Includ= e/Soc.h index 84f433d5cb94..e1d97e531263 100644 --- a/Silicon/NXP/LS1046A/Include/Soc.h +++ b/Silicon/NXP/LS1046A/Include/Soc.h @@ -25,6 +25,7 @@ #define LS1046A_QSPI0_SIZE (SIZE_512MB) =20 #define LS1046A_DCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS +#define LS1046A_SCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS2_SCFG_ADDRESS =20 /** Reset Control Word (RCW) Bits @@ -59,5 +60,6 @@ Bit(s) | Field Name | Description | Not= es/comments #define SYS_PLL_RAT(x) (((x) >> 25) & 0x1f) // Bits 2-6 =20 typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG LS1046A_DEVICE_CONFIG; +typedef NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG LS1046A_SUPPLEMENTAL_C= ONFIG; =20 #endif // SOC_H__ diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c b/Silicon/NXP/LS10= 46A/Library/SocLib/SocLib.c index 3b15aee6ecae..7726faf748cb 100644 --- a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c +++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c @@ -11,6 +11,7 @@ #include #include #include + #include =20 /** @@ -65,6 +66,47 @@ SocGetClock ( } =20 /** + Function to select pins depending upon pcd using supplemental + configuration unit(SCFG) extended RCW controlled pinmux control + register which contains the bits to provide pin multiplexing control. + This register is reset on HRESET. + **/ +STATIC +VOID +ConfigScfgMux (VOID) +{ + LS1046A_SUPPLEMENTAL_CONFIG *Scfg; + UINT32 UsbPwrFault; + + Scfg =3D (LS1046A_SUPPLEMENTAL_CONFIG *)LS1046A_SCFG_ADDRESS; + // Configures functionality of the IIC3_SCL to USB2_DRVVBUS + // Configures functionality of the IIC3_SDA to USB2_PWRFAULT + // USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA + ScfgWrite32 ((UINTN)&Scfg->RcwPMuxCr0, SCFG_RCWPMUXCRO_NOT_SELCR_USB); + + ScfgWrite32 ((UINTN)&Scfg->UsbDrvVBusSelCr, SCFG_USBDRVVBUS_SELCR_USB1); + UsbPwrFault =3D (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHI= FT) | + (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT= ) | + (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT); + ScfgWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault); + ScfgWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault); +} + +STATIC +VOID +ApplyErrata ( + VOID + ) +{ + ErratumA008997 (); + ErratumA009007 (); + ErratumA009008 (); + ErratumA009798 (); +} + + + +/** Function to initialize SoC specific constructs **/ VOID @@ -72,7 +114,30 @@ SocInit ( VOID ) { + LS1046A_SUPPLEMENTAL_CONFIG *Scfg; + + Scfg =3D (LS1046A_SUPPLEMENTAL_CONFIG *)LS1046A_SCFG_ADDRESS; + + /* Make SEC, SATA and USB reads and writes snoopable */ + ScfgOr32((UINTN)&Scfg->SnpCnfgCr, SCFG_SNPCNFGCR_SECRDSNP | + SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP | + SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP | + SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP | + SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP | + SCFG_SNPCNFGCR_SATAWRSNP); + + ApplyErrata (); ChassisInit (); =20 + // + // Due to the extensive functionality present on the chip and the limite= d number of external + // signals available, several functional blocks share signal resources t= hrough multiplexing. + // In this case when there is alternate functionality between multiple f= unctional blocks, + // the signal's function is determined at the chip level (rather than at= the block level) + // typically by a reset configuration word (RCW) option. Some of the sig= nals' function are + // determined externel to RCW at Power-on Reset Sequence. + // + ConfigScfgMux (); + return; } --=20 1.9.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#66069): https://edk2.groups.io/g/devel/message/66069 Mute This Topic: https://groups.io/mt/77402668/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-