Silicon/NXP/NxpQoriqLs.dec | 9 + Silicon/NXP/LS1046A/LS1046A.dsc.inc | 9 + Silicon/NXP/NxpQoriqLs.dsc.inc | 2 + Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc | 2 + Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf | 13 ++ .../Library/ArmPlatformLib/ArmPlatformLib.inf | 1 + .../NXP/Chassis2/Library/ChassisLib/ChassisLib.inf | 2 + Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf | 2 + Silicon/NXP/Library/GpioLib/GpioLib.inf | 39 ++++ Silicon/NXP/Chassis2/Include/Chassis.h | 112 ++++++++++ Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h | 23 ++ Silicon/NXP/Include/Library/ChassisLib.h | 62 ++++++ Silicon/NXP/Include/Library/GpioLib.h | 110 ++++++++++ Silicon/NXP/LS1046A/Include/Soc.h | 2 + .../Library/ArmPlatformLib/ArmPlatformLib.c | 17 ++ .../NXP/Chassis2/Library/ChassisLib/ChassisLib.c | 63 ++++++ Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c | 159 ++++++++++++++ Silicon/NXP/LS1046A/Library/SocLib/SocLib.c | 66 ++++++ Silicon/NXP/Library/GpioLib/GpioLib.c | 242 +++++++++++++++++++++ 19 files changed, 935 insertions(+) mode change 100644 => 100755 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc mode change 100644 => 100755 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf create mode 100644 Silicon/NXP/Library/GpioLib/GpioLib.inf create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h create mode 100644 Silicon/NXP/Include/Library/GpioLib.h create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c create mode 100644 Silicon/NXP/Library/GpioLib/GpioLib.c
This patch set adds GPIO Library. Gpio Library is required to set muxing to enable USB controller. Meenakshi Aggarwal (4): Silicon/NXP: Add GPIO driver support. Platform/NXP/LS1046aFrwyPkg: GPIO mux changes for USB Silicon/NXP: Implement USB Errata LS1046aFrwy: Enable USB support for LS1046AFRWY board. Silicon/NXP/NxpQoriqLs.dec | 9 + Silicon/NXP/LS1046A/LS1046A.dsc.inc | 9 + Silicon/NXP/NxpQoriqLs.dsc.inc | 2 + Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc | 2 + Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf | 13 ++ .../Library/ArmPlatformLib/ArmPlatformLib.inf | 1 + .../NXP/Chassis2/Library/ChassisLib/ChassisLib.inf | 2 + Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf | 2 + Silicon/NXP/Library/GpioLib/GpioLib.inf | 39 ++++ Silicon/NXP/Chassis2/Include/Chassis.h | 112 ++++++++++ Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h | 23 ++ Silicon/NXP/Include/Library/ChassisLib.h | 62 ++++++ Silicon/NXP/Include/Library/GpioLib.h | 110 ++++++++++ Silicon/NXP/LS1046A/Include/Soc.h | 2 + .../Library/ArmPlatformLib/ArmPlatformLib.c | 17 ++ .../NXP/Chassis2/Library/ChassisLib/ChassisLib.c | 63 ++++++ Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c | 159 ++++++++++++++ Silicon/NXP/LS1046A/Library/SocLib/SocLib.c | 66 ++++++ Silicon/NXP/Library/GpioLib/GpioLib.c | 242 +++++++++++++++++++++ 19 files changed, 935 insertions(+) mode change 100644 => 100755 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc mode change 100644 => 100755 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf create mode 100644 Silicon/NXP/Library/GpioLib/GpioLib.inf create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h create mode 100644 Silicon/NXP/Include/Library/GpioLib.h create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c create mode 100644 Silicon/NXP/Library/GpioLib/GpioLib.c -- 1.9.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#65265): https://edk2.groups.io/g/devel/message/65265 Mute This Topic: https://groups.io/mt/76840692/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
This patch set adds GPIO Library. Gpio Library is required to set muxing to enable USB controller. Changes in v2: - Modified GpioLib as per review comments - Prepared separate patch for SCFG enablement - Prepared sepaarte patch for USB errata implementation Meenakshi Aggarwal (6): Silicon/NXP: Add GPIO Library support. Platform/NXP/LS1046aFrwyPkg: MUX changes for USB Silicon/NXP: Add SCFG support for Chassis2 Silicon/NXP: Implement USB Errata Workarounds Silicon/NXP/LS1046A: Apply USB errata workarounds LS1046aFrwy: Enable USB support for LS1046AFRWY board. Silicon/NXP/NxpQoriqLs.dec | 9 + Silicon/NXP/LS1046A/LS1046A.dsc.inc | 9 + Silicon/NXP/NxpQoriqLs.dsc.inc | 2 + Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc | 2 + Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf | 13 ++ .../Library/ArmPlatformLib/ArmPlatformLib.inf | 1 + .../NXP/Chassis2/Library/ChassisLib/ChassisLib.inf | 2 + Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf | 2 + Silicon/NXP/Library/GpioLib/GpioLib.inf | 39 ++++ Silicon/NXP/Chassis2/Include/Chassis.h | 112 +++++++++++ Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h | 23 +++ Silicon/NXP/Include/Library/ChassisLib.h | 62 ++++++ Silicon/NXP/Include/Library/GpioLib.h | 110 +++++++++++ Silicon/NXP/LS1046A/Include/Soc.h | 2 + .../Library/ArmPlatformLib/ArmPlatformLib.c | 21 ++ .../NXP/Chassis2/Library/ChassisLib/ChassisLib.c | 63 ++++++ Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c | 165 ++++++++++++++++ Silicon/NXP/LS1046A/Library/SocLib/SocLib.c | 66 +++++++ Silicon/NXP/Library/GpioLib/GpioLib.c | 219 +++++++++++++++++++++ 19 files changed, 922 insertions(+) mode change 100644 => 100755 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc mode change 100644 => 100755 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf create mode 100644 Silicon/NXP/Library/GpioLib/GpioLib.inf create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h create mode 100644 Silicon/NXP/Include/Library/GpioLib.h create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c create mode 100644 Silicon/NXP/Library/GpioLib/GpioLib.c -- 1.9.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#65968): https://edk2.groups.io/g/devel/message/65968 Mute This Topic: https://groups.io/mt/77359490/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
Hi Meenakshi,
Can you please resubmit patches 4-5/6 only, addressing the feedback.
This will then be ready to merge.
/
Leif
On Wed, Oct 07, 2020 at 21:40:35 +0530, Meenakshi Aggarwal wrote:
> This patch set adds GPIO Library.
> Gpio Library is required to set muxing to enable USB controller.
>
>
> Changes in v2:
> - Modified GpioLib as per review comments
> - Prepared separate patch for SCFG enablement
> - Prepared sepaarte patch for USB errata implementation
>
>
> Meenakshi Aggarwal (6):
> Silicon/NXP: Add GPIO Library support.
> Platform/NXP/LS1046aFrwyPkg: MUX changes for USB
> Silicon/NXP: Add SCFG support for Chassis2
> Silicon/NXP: Implement USB Errata Workarounds
> Silicon/NXP/LS1046A: Apply USB errata workarounds
> LS1046aFrwy: Enable USB support for LS1046AFRWY board.
>
> Silicon/NXP/NxpQoriqLs.dec | 9 +
> Silicon/NXP/LS1046A/LS1046A.dsc.inc | 9 +
> Silicon/NXP/NxpQoriqLs.dsc.inc | 2 +
> Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc | 2 +
> Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf | 13 ++
> .../Library/ArmPlatformLib/ArmPlatformLib.inf | 1 +
> .../NXP/Chassis2/Library/ChassisLib/ChassisLib.inf | 2 +
> Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf | 2 +
> Silicon/NXP/Library/GpioLib/GpioLib.inf | 39 ++++
> Silicon/NXP/Chassis2/Include/Chassis.h | 112 +++++++++++
> Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h | 23 +++
> Silicon/NXP/Include/Library/ChassisLib.h | 62 ++++++
> Silicon/NXP/Include/Library/GpioLib.h | 110 +++++++++++
> Silicon/NXP/LS1046A/Include/Soc.h | 2 +
> .../Library/ArmPlatformLib/ArmPlatformLib.c | 21 ++
> .../NXP/Chassis2/Library/ChassisLib/ChassisLib.c | 63 ++++++
> Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c | 165 ++++++++++++++++
> Silicon/NXP/LS1046A/Library/SocLib/SocLib.c | 66 +++++++
> Silicon/NXP/Library/GpioLib/GpioLib.c | 219 +++++++++++++++++++++
> 19 files changed, 922 insertions(+)
> mode change 100644 => 100755 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
> mode change 100644 => 100755 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
> create mode 100644 Silicon/NXP/Library/GpioLib/GpioLib.inf
> create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h
> create mode 100644 Silicon/NXP/Include/Library/GpioLib.h
> create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c
> create mode 100644 Silicon/NXP/Library/GpioLib/GpioLib.c
>
> --
> 1.9.1
>
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General-purpose I/O (GPIO) module is integrated on chip.
In general, the GPIO module supports up to 32 general-purpose
I/O ports. Each port can be configured as an input or as an
output. However, some implementations may restrict specific ports to
input-only, output-only, or reserved (unimplemented).
Co-authored-by: Pramod Kumar <pramod.kumar_1@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Silicon/NXP/Library/GpioLib/GpioLib.inf | 39 ++++++
Silicon/NXP/Include/Library/GpioLib.h | 110 ++++++++++++++++
Silicon/NXP/Library/GpioLib/GpioLib.c | 219 ++++++++++++++++++++++++++++++++
3 files changed, 368 insertions(+)
create mode 100644 Silicon/NXP/Library/GpioLib/GpioLib.inf
create mode 100644 Silicon/NXP/Include/Library/GpioLib.h
create mode 100644 Silicon/NXP/Library/GpioLib/GpioLib.c
diff --git a/Silicon/NXP/Library/GpioLib/GpioLib.inf b/Silicon/NXP/Library/GpioLib/GpioLib.inf
new file mode 100644
index 000000000000..0c11a5f00a12
--- /dev/null
+++ b/Silicon/NXP/Library/GpioLib/GpioLib.inf
@@ -0,0 +1,39 @@
+/** @file
+
+ Copyright 2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = GpioLib
+ FILE_GUID = addec2b8-d2e0-43c0-a277-41a8d42f3f4f
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = GpioLib
+
+[Sources.common]
+ GpioLib.c
+
+[LibraryClasses]
+ ArmLib
+ BaseLib
+ BaseMemoryLib
+ IoAccessLib
+ IoLib
+
+[Packages]
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[Pcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdNumGpioController
+ gNxpQoriqLsTokenSpaceGuid.PcdGpioModuleBaseAddress
+ gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerOffset
+
+[FeaturePcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerBigEndian
diff --git a/Silicon/NXP/Include/Library/GpioLib.h b/Silicon/NXP/Include/Library/GpioLib.h
new file mode 100644
index 000000000000..0345aa66de7e
--- /dev/null
+++ b/Silicon/NXP/Include/Library/GpioLib.h
@@ -0,0 +1,110 @@
+/** @file
+
+ Copyright 2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef GPIO_H__
+#define GPIO_H__
+
+#include <Uefi.h>
+
+/* enum for GPIO number */
+typedef enum _GPIO_BLOCK {
+ GPIO1,
+ GPIO2,
+ GPIO3,
+ GPIO4,
+ GPIO_MAX
+} GPIO_BLOCK;
+
+/* enum for GPIO direction */
+typedef enum _GPIO_DIRECTION {
+ INPUT,
+ OUTPUT
+} GPIO_DIRECTION;
+
+/* enum for GPIO state */
+typedef enum _GPIO_STATE {
+ LOW,
+ HIGH
+} GPIO_VAL;
+
+/**
+ GpioSetDiriection: Set GPIO direction as INPUT or OUTPUT
+
+ @param[in] Id GPIO controller number
+ @param[in] Bit GPIO number
+ @param[in] Dir GPIO Direction as INPUT or OUTPUT
+
+ @retval EFI_SUCCESS
+ **/
+EFI_STATUS
+GpioSetDirection (
+ IN UINT8 Id,
+ IN UINT32 Bit,
+ IN BOOLEAN Dir
+ );
+
+/**
+ GpioGetDirection: Retrieve GPIO direction
+
+ @param[in] Id GPIO controller number
+ @param[in] Bit GPIO number
+
+ @retval GPIO Direction as INPUT or OUTPUT
+ **/
+UINT32
+GpioGetDirection (
+ IN UINT8 Id,
+ IN UINT32 Bit
+ );
+
+ /**
+ GpioGetData: Retrieve GPIO Value
+
+ @param[in] Id GPIO controller number
+ @param[in] Bit GPIO number
+
+ @retval GPIO value as HIGH or LOW
+ **/
+UINT32
+GpioGetData (
+ IN UINT8 Id,
+ IN UINT32 Bit
+ );
+
+/**
+ GpioSetData: Set GPIO data Value
+
+ @param[in] Id GPIO controller number
+ @param[in] Bit GPIO number
+ @param[in] Data GPIO data value to set
+
+ @retval GPIO value as HIGH or LOW
+ **/
+EFI_STATUS
+GpioSetData (
+ IN UINT8 Id,
+ IN UINT32 Bit,
+ IN BOOLEAN Data
+ );
+
+/**
+ GpioSetOpenDrain: Set GPIO as Open drain
+
+ @param[in] Id GPIO controller number
+ @param[in] Bit GPIO number
+ @param[in] OpenDrain Set as open drain
+
+ @retval EFI_SUCCESS
+ **/
+EFI_STATUS
+GpioSetOpenDrain (
+ IN UINT8 Id,
+ IN UINT32 Bit,
+ IN BOOLEAN OpenDrain
+ );
+
+#endif
diff --git a/Silicon/NXP/Library/GpioLib/GpioLib.c b/Silicon/NXP/Library/GpioLib/GpioLib.c
new file mode 100644
index 000000000000..9dd48b812a82
--- /dev/null
+++ b/Silicon/NXP/Library/GpioLib/GpioLib.c
@@ -0,0 +1,219 @@
+/** @file
+
+ GPIO controller Library inmplements the functions
+ which will be used by other library/drivers to
+ get/set GPIO pin direction and get/set data on
+ GPIO pins.
+
+ Copyright 2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/GpioLib.h>
+#include <Library/IoAccessLib.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+
+STATIC MMIO_OPERATIONS *mGpioOps;
+
+/**
+ Structure for GPIO Regsters
+
+ GpDir GPIO direction register
+ GpOdr GPIO open drain register
+ GpData GPIO data register
+ GpIer GPIO interrupt event register
+ GpImr GPIO interrupt mask register
+ GpIcr GPIO interrupt control register
+
+ **/
+typedef struct GpioRegs {
+ UINT32 GpDir;
+ UINT32 GpOdr;
+ UINT32 GpData;
+ UINT32 GpIer;
+ UINT32 GpImr;
+ UINT32 GpIcr;
+} GPIO_REGS;
+
+/**
+ GetBaseAddr GPIO controller Base Address
+
+ @param[in] Id GPIO controller number
+
+ @retval GPIO controller Base Address, if found
+ @retval NULL, if not a valid controller number
+
+ **/
+STATIC
+VOID *
+GetBaseAddr (
+ IN UINT8 Id
+ )
+{
+
+ UINTN GpioBaseAddr;
+ UINTN MaxGpioController;
+
+ mGpioOps = GetMmioOperations (FeaturePcdGet (PcdGpioControllerBigEndian));
+
+ MaxGpioController = PcdGet32 (PcdNumGpioController);
+
+ if (Id < MaxGpioController) {
+ GpioBaseAddr = PcdGet64 (PcdGpioModuleBaseAddress) +
+ (Id * PcdGet64 (PcdGpioControllerOffset));
+ return (VOID *)GpioBaseAddr;
+ } else {
+ DEBUG((DEBUG_ERROR, "Invalid Gpio Controller Id %d, Allowed Ids are %d-%d",
+ Id, GPIO1, MaxGpioController));
+ return NULL;
+ }
+}
+
+/**
+ GpioSetDirection: Set GPIO direction as INPUT or OUTPUT
+
+ @param[in] Id GPIO controller number
+ @param[in] Bit GPIO number
+ @param[in] Dir GPIO Direction as INPUT or OUTPUT
+
+ @retval EFI_SUCCESS
+ **/
+EFI_STATUS
+GpioSetDirection (
+ IN UINT8 Id,
+ IN UINT32 Bit,
+ IN BOOLEAN Dir
+ )
+{
+ GPIO_REGS *Regs;
+ UINT32 DirectionBitMask;
+
+ Regs = GetBaseAddr (Id);
+ DirectionBitMask = 1 << Bit;
+
+ if (Dir) {
+ mGpioOps->Or32 ((UINTN)&Regs->GpDir, DirectionBitMask);
+ }
+ else {
+ mGpioOps->And32 ((UINTN)&Regs->GpDir, ~DirectionBitMask);
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ GpioGetDiriection: Retrieve GPIO direction
+
+ @param[in] Id GPIO controller number
+ @param[in] Bit GPIO number
+
+ @retval GPIO Direction as INPUT or OUTPUT
+ **/
+UINT32
+GpioGetDirection (
+ IN UINT8 Id,
+ IN UINT32 Bit
+ )
+{
+ GPIO_REGS *Regs;
+ UINT32 Value;
+ UINT32 DirectionBitMask;
+
+ Regs = GetBaseAddr (Id);
+ DirectionBitMask = 1 << Bit;
+
+ Value = mGpioOps->Read32 ((UINTN)&Regs->GpDir);
+
+ return (Value & DirectionBitMask);
+}
+
+/**
+ GpioGetData: Retrieve GPIO Value
+
+ @param[in] Id GPIO controller number
+ @param[in] Bit GPIO number
+
+ @retval GPIO value as HIGH or LOW
+ **/
+UINT32
+GpioGetData (
+ IN UINT8 Id,
+ IN UINT32 Bit
+ )
+{
+ GPIO_REGS *Regs;
+ UINT32 Value;
+ UINT32 DataBitMask;
+
+ Regs = (VOID *)GetBaseAddr (Id);
+ DataBitMask = 1 << Bit;
+
+ Value = mGpioOps->Read32 ((UINTN)&Regs->GpData);
+
+ return (Value & DataBitMask);
+}
+
+/**
+ GpioSetData: Set GPIO data Value
+
+ @param[in] Id GPIO controller number
+ @param[in] Bit GPIO number
+ @param[in] Data GPIO data value to set
+
+ @retval GPIO value as HIGH or LOW
+ **/
+EFI_STATUS
+GpioSetData (
+ IN UINT8 Id,
+ IN UINT32 Bit,
+ IN BOOLEAN Data
+ )
+{
+ GPIO_REGS *Regs;
+ UINT32 DataBitMask;
+
+ Regs = GetBaseAddr (Id);
+ DataBitMask = 1 << Bit;
+
+ if (Data) {
+ mGpioOps->Or32 ((UINTN)&Regs->GpData, DataBitMask);
+ } else {
+ mGpioOps->And32 ((UINTN)&Regs->GpData, ~DataBitMask);
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ GpioSetOpenDrain: Set GPIO as Open drain
+
+ @param[in] Id GPIO controller number
+ @param[in] Bit GPIO number
+ @param[in] OpenDrain Set as open drain
+
+ @retval EFI_SUCCESS
+ **/
+EFI_STATUS
+GpioSetOpenDrain (
+ IN UINT8 Id,
+ IN UINT32 Bit,
+ IN BOOLEAN OpenDrain
+ )
+{
+ GPIO_REGS *Regs;
+ UINT32 OpenDrainBitMask;
+
+ Regs = GetBaseAddr (Id);
+ OpenDrainBitMask = 1 << Bit;
+
+ if (OpenDrain) {
+ mGpioOps->Or32 ((UINTN)&Regs->GpOdr, OpenDrainBitMask);
+ } else {
+ mGpioOps->And32 ((UINTN)&Regs->GpOdr, ~OpenDrainBitMask);
+ }
+
+ return EFI_SUCCESS;
+}
--
1.9.1
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On Wed, Oct 07, 2020 at 21:40:36 +0530, Meenakshi Aggarwal wrote:
> General-purpose I/O (GPIO) module is integrated on chip.
>
> In general, the GPIO module supports up to 32 general-purpose
> I/O ports. Each port can be configured as an input or as an
> output. However, some implementations may restrict specific ports to
> input-only, output-only, or reserved (unimplemented).
>
> Co-authored-by: Pramod Kumar <pramod.kumar_1@nxp.com>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
> ---
> Silicon/NXP/Library/GpioLib/GpioLib.inf | 39 ++++++
> Silicon/NXP/Include/Library/GpioLib.h | 110 ++++++++++++++++
> Silicon/NXP/Library/GpioLib/GpioLib.c | 219 ++++++++++++++++++++++++++++++++
> 3 files changed, 368 insertions(+)
> create mode 100644 Silicon/NXP/Library/GpioLib/GpioLib.inf
> create mode 100644 Silicon/NXP/Include/Library/GpioLib.h
> create mode 100644 Silicon/NXP/Library/GpioLib/GpioLib.c
>
> diff --git a/Silicon/NXP/Library/GpioLib/GpioLib.inf b/Silicon/NXP/Library/GpioLib/GpioLib.inf
> new file mode 100644
> index 000000000000..0c11a5f00a12
> --- /dev/null
> +++ b/Silicon/NXP/Library/GpioLib/GpioLib.inf
> @@ -0,0 +1,39 @@
> +/** @file
> +
> + Copyright 2020 NXP
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = GpioLib
> + FILE_GUID = addec2b8-d2e0-43c0-a277-41a8d42f3f4f
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = GpioLib
> +
> +[Sources.common]
> + GpioLib.c
> +
> +[LibraryClasses]
> + ArmLib
> + BaseLib
> + BaseMemoryLib
> + IoAccessLib
> + IoLib
> +
> +[Packages]
> + ArmPlatformPkg/ArmPlatformPkg.dec
> + EmbeddedPkg/EmbeddedPkg.dec
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[Pcd]
> + gNxpQoriqLsTokenSpaceGuid.PcdNumGpioController
> + gNxpQoriqLsTokenSpaceGuid.PcdGpioModuleBaseAddress
> + gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerOffset
> +
> +[FeaturePcd]
> + gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerBigEndian
> diff --git a/Silicon/NXP/Include/Library/GpioLib.h b/Silicon/NXP/Include/Library/GpioLib.h
> new file mode 100644
> index 000000000000..0345aa66de7e
> --- /dev/null
> +++ b/Silicon/NXP/Include/Library/GpioLib.h
> @@ -0,0 +1,110 @@
> +/** @file
> +
> + Copyright 2020 NXP
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef GPIO_H__
> +#define GPIO_H__
> +
> +#include <Uefi.h>
> +
> +/* enum for GPIO number */
> +typedef enum _GPIO_BLOCK {
> + GPIO1,
> + GPIO2,
> + GPIO3,
> + GPIO4,
> + GPIO_MAX
> +} GPIO_BLOCK;
> +
> +/* enum for GPIO direction */
> +typedef enum _GPIO_DIRECTION {
> + INPUT,
> + OUTPUT
> +} GPIO_DIRECTION;
> +
> +/* enum for GPIO state */
> +typedef enum _GPIO_STATE {
> + LOW,
> + HIGH
> +} GPIO_VAL;
> +
> +/**
> + GpioSetDiriection: Set GPIO direction as INPUT or OUTPUT
> +
> + @param[in] Id GPIO controller number
> + @param[in] Bit GPIO number
> + @param[in] Dir GPIO Direction as INPUT or OUTPUT
> +
> + @retval EFI_SUCCESS
> + **/
> +EFI_STATUS
> +GpioSetDirection (
> + IN UINT8 Id,
> + IN UINT32 Bit,
> + IN BOOLEAN Dir
> + );
> +
> +/**
> + GpioGetDirection: Retrieve GPIO direction
> +
> + @param[in] Id GPIO controller number
> + @param[in] Bit GPIO number
> +
> + @retval GPIO Direction as INPUT or OUTPUT
> + **/
> +UINT32
> +GpioGetDirection (
> + IN UINT8 Id,
> + IN UINT32 Bit
> + );
> +
> + /**
> + GpioGetData: Retrieve GPIO Value
> +
> + @param[in] Id GPIO controller number
> + @param[in] Bit GPIO number
> +
> + @retval GPIO value as HIGH or LOW
> + **/
> +UINT32
> +GpioGetData (
> + IN UINT8 Id,
> + IN UINT32 Bit
> + );
> +
> +/**
> + GpioSetData: Set GPIO data Value
> +
> + @param[in] Id GPIO controller number
> + @param[in] Bit GPIO number
> + @param[in] Data GPIO data value to set
> +
> + @retval GPIO value as HIGH or LOW
> + **/
> +EFI_STATUS
> +GpioSetData (
> + IN UINT8 Id,
> + IN UINT32 Bit,
> + IN BOOLEAN Data
> + );
> +
> +/**
> + GpioSetOpenDrain: Set GPIO as Open drain
> +
> + @param[in] Id GPIO controller number
> + @param[in] Bit GPIO number
> + @param[in] OpenDrain Set as open drain
> +
> + @retval EFI_SUCCESS
> + **/
> +EFI_STATUS
> +GpioSetOpenDrain (
> + IN UINT8 Id,
> + IN UINT32 Bit,
> + IN BOOLEAN OpenDrain
> + );
> +
> +#endif
> diff --git a/Silicon/NXP/Library/GpioLib/GpioLib.c b/Silicon/NXP/Library/GpioLib/GpioLib.c
> new file mode 100644
> index 000000000000..9dd48b812a82
> --- /dev/null
> +++ b/Silicon/NXP/Library/GpioLib/GpioLib.c
> @@ -0,0 +1,219 @@
> +/** @file
> +
> + GPIO controller Library inmplements the functions
> + which will be used by other library/drivers to
> + get/set GPIO pin direction and get/set data on
> + GPIO pins.
> +
> + Copyright 2020 NXP
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <Library/GpioLib.h>
> +#include <Library/IoAccessLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/BaseLib.h>
> +
> +STATIC MMIO_OPERATIONS *mGpioOps;
> +
> +/**
> + Structure for GPIO Regsters
> +
> + GpDir GPIO direction register
> + GpOdr GPIO open drain register
> + GpData GPIO data register
> + GpIer GPIO interrupt event register
> + GpImr GPIO interrupt mask register
> + GpIcr GPIO interrupt control register
> +
> + **/
> +typedef struct GpioRegs {
> + UINT32 GpDir;
> + UINT32 GpOdr;
> + UINT32 GpData;
> + UINT32 GpIer;
> + UINT32 GpImr;
> + UINT32 GpIcr;
> +} GPIO_REGS;
> +
> +/**
> + GetBaseAddr GPIO controller Base Address
> +
> + @param[in] Id GPIO controller number
> +
> + @retval GPIO controller Base Address, if found
> + @retval NULL, if not a valid controller number
> +
> + **/
> +STATIC
> +VOID *
> +GetBaseAddr (
> + IN UINT8 Id
> + )
> +{
> +
> + UINTN GpioBaseAddr;
> + UINTN MaxGpioController;
> +
> + mGpioOps = GetMmioOperations (FeaturePcdGet (PcdGpioControllerBigEndian));
> +
> + MaxGpioController = PcdGet32 (PcdNumGpioController);
> +
> + if (Id < MaxGpioController) {
> + GpioBaseAddr = PcdGet64 (PcdGpioModuleBaseAddress) +
> + (Id * PcdGet64 (PcdGpioControllerOffset));
> + return (VOID *)GpioBaseAddr;
> + } else {
> + DEBUG((DEBUG_ERROR, "Invalid Gpio Controller Id %d, Allowed Ids are %d-%d",
> + Id, GPIO1, MaxGpioController));
> + return NULL;
> + }
> +}
> +
> +/**
> + GpioSetDirection: Set GPIO direction as INPUT or OUTPUT
> +
> + @param[in] Id GPIO controller number
> + @param[in] Bit GPIO number
> + @param[in] Dir GPIO Direction as INPUT or OUTPUT
> +
> + @retval EFI_SUCCESS
> + **/
> +EFI_STATUS
> +GpioSetDirection (
> + IN UINT8 Id,
> + IN UINT32 Bit,
> + IN BOOLEAN Dir
> + )
> +{
> + GPIO_REGS *Regs;
> + UINT32 DirectionBitMask;
> +
> + Regs = GetBaseAddr (Id);
> + DirectionBitMask = 1 << Bit;
> +
> + if (Dir) {
> + mGpioOps->Or32 ((UINTN)&Regs->GpDir, DirectionBitMask);
> + }
> + else {
> + mGpioOps->And32 ((UINTN)&Regs->GpDir, ~DirectionBitMask);
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + GpioGetDiriection: Retrieve GPIO direction
> +
> + @param[in] Id GPIO controller number
> + @param[in] Bit GPIO number
> +
> + @retval GPIO Direction as INPUT or OUTPUT
> + **/
> +UINT32
> +GpioGetDirection (
> + IN UINT8 Id,
> + IN UINT32 Bit
> + )
> +{
> + GPIO_REGS *Regs;
> + UINT32 Value;
> + UINT32 DirectionBitMask;
> +
> + Regs = GetBaseAddr (Id);
> + DirectionBitMask = 1 << Bit;
> +
> + Value = mGpioOps->Read32 ((UINTN)&Regs->GpDir);
> +
> + return (Value & DirectionBitMask);
> +}
> +
> +/**
> + GpioGetData: Retrieve GPIO Value
> +
> + @param[in] Id GPIO controller number
> + @param[in] Bit GPIO number
> +
> + @retval GPIO value as HIGH or LOW
> + **/
> +UINT32
> +GpioGetData (
> + IN UINT8 Id,
> + IN UINT32 Bit
> + )
> +{
> + GPIO_REGS *Regs;
> + UINT32 Value;
> + UINT32 DataBitMask;
> +
> + Regs = (VOID *)GetBaseAddr (Id);
> + DataBitMask = 1 << Bit;
> +
> + Value = mGpioOps->Read32 ((UINTN)&Regs->GpData);
> +
> + return (Value & DataBitMask);
> +}
> +
> +/**
> + GpioSetData: Set GPIO data Value
> +
> + @param[in] Id GPIO controller number
> + @param[in] Bit GPIO number
> + @param[in] Data GPIO data value to set
> +
> + @retval GPIO value as HIGH or LOW
> + **/
> +EFI_STATUS
> +GpioSetData (
> + IN UINT8 Id,
> + IN UINT32 Bit,
> + IN BOOLEAN Data
> + )
> +{
> + GPIO_REGS *Regs;
> + UINT32 DataBitMask;
> +
> + Regs = GetBaseAddr (Id);
> + DataBitMask = 1 << Bit;
> +
> + if (Data) {
> + mGpioOps->Or32 ((UINTN)&Regs->GpData, DataBitMask);
> + } else {
> + mGpioOps->And32 ((UINTN)&Regs->GpData, ~DataBitMask);
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + GpioSetOpenDrain: Set GPIO as Open drain
> +
> + @param[in] Id GPIO controller number
> + @param[in] Bit GPIO number
> + @param[in] OpenDrain Set as open drain
> +
> + @retval EFI_SUCCESS
> + **/
> +EFI_STATUS
> +GpioSetOpenDrain (
> + IN UINT8 Id,
> + IN UINT32 Bit,
> + IN BOOLEAN OpenDrain
> + )
> +{
> + GPIO_REGS *Regs;
> + UINT32 OpenDrainBitMask;
> +
> + Regs = GetBaseAddr (Id);
> + OpenDrainBitMask = 1 << Bit;
> +
> + if (OpenDrain) {
> + mGpioOps->Or32 ((UINTN)&Regs->GpOdr, OpenDrainBitMask);
> + } else {
> + mGpioOps->And32 ((UINTN)&Regs->GpOdr, ~OpenDrainBitMask);
> + }
> +
> + return EFI_SUCCESS;
> +}
> --
> 1.9.1
>
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Second USB controller is muxed with I2c through GPIO.
Setting GPIO bit to configure for second USB controller.
Co-authored-by: Pramod Kumar <pramod.kumar_1@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Silicon/NXP/NxpQoriqLs.dec | 8 ++++++++
Silicon/NXP/LS1046A/LS1046A.dsc.inc | 5 +++++
Silicon/NXP/NxpQoriqLs.dsc.inc | 2 ++
.../Library/ArmPlatformLib/ArmPlatformLib.inf | 1 +
.../Library/ArmPlatformLib/ArmPlatformLib.c | 21 +++++++++++++++++++++
5 files changed, 37 insertions(+)
diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index 0c3608696569..3a568c0437e7 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -29,6 +29,7 @@ [PcdsFeatureFlag]
gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|FALSE|BOOLEAN|0x00000316
gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x00000317
gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA009185|FALSE|BOOLEAN|0x00000318
+ gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerBigEndian|FALSE|BOOLEAN|0x00000319
[PcdsFixedAtBuild.common]
# Pcds for PCI Express
@@ -48,6 +49,13 @@ [PcdsFixedAtBuild.common]
gNxpQoriqLsTokenSpaceGuid.PcdSataSize|0x0|UINT32|0x00000351
gNxpQoriqLsTokenSpaceGuid.PcdNumSataController|0x0|UINT32|0x00000352
+ #
+ # Pcds for Gpio
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdNumGpioController|0|UINT32|0x00000355
+ gNxpQoriqLsTokenSpaceGuid.PcdGpioModuleBaseAddress|0|UINT64|0x00000356
+ gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerOffset|0|UINT64|0x00000357
+
[PcdsDynamic.common]
gNxpQoriqLsTokenSpaceGuid.PcdPciCfgShiftEnable|FALSE|BOOLEAN|0x00000600
gNxpQoriqLsTokenSpaceGuid.PcdPciLsGen4Ctrl|FALSE|BOOLEAN|0x00000601
diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
index dbe7f408fce9..db110553605f 100644
--- a/Silicon/NXP/LS1046A/LS1046A.dsc.inc
+++ b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
@@ -27,9 +27,14 @@ [PcdsDynamicDefault.common]
[PcdsFixedAtBuild.common]
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
+ gNxpQoriqLsTokenSpaceGuid.PcdNumGpioController|0x04
+ gNxpQoriqLsTokenSpaceGuid.PcdGpioModuleBaseAddress|0x02300000
+ gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerOffset|0x10000
+
[PcdsFeatureFlag]
gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
+ gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerBigEndian|TRUE
################################################################################
#
diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
index fc600de01d74..21c87df73220 100644
--- a/Silicon/NXP/NxpQoriqLs.dsc.inc
+++ b/Silicon/NXP/NxpQoriqLs.dsc.inc
@@ -103,6 +103,8 @@ [LibraryClasses.common]
MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+ GpioLib|Silicon/NXP/Library/GpioLib/GpioLib.inf
+
[LibraryClasses.common.SEC]
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
DebugAgentLib|ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.inf
diff --git a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
index 7802696bf39b..2e755842a714 100644
--- a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
+++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
@@ -25,6 +25,7 @@ [Packages]
[LibraryClasses]
ArmLib
DebugLib
+ GpioLib
SocLib
[Sources.common]
diff --git a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
index e1f20da09337..ef404991add8 100644
--- a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
+++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
@@ -8,11 +8,18 @@
#include <Library/ArmLib.h>
#include <Library/ArmPlatformLib.h>
+#include <Library/GpioLib.h>
#include <Library/SocLib.h>
#include <Ppi/ArmMpCoreInfo.h>
#include <Ppi/NxpPlatformGetClock.h>
+/**
+ Documents use bit number as per Power PC notation,
+ so need to convert it to support ARMv8 architecture
+**/
+#define USB2_MUX_SEL_GPIO (31 - 23)
+
ARM_CORE_INFO mLS1046aMpCoreInfoTable[] = {
{
// Cluster 0, Core 0
@@ -89,6 +96,19 @@ NxpPlatformGetClock(
}
/**
+ FRWY-LS1046A GPIO 23 use for USB2
+ mux seclection
+**/
+STATIC VOID MuxSelectUsb2 (VOID)
+{
+
+ GpioSetDirection (GPIO3, USB2_MUX_SEL_GPIO, OUTPUT);
+ GpioSetData (GPIO3, USB2_MUX_SEL_GPIO, HIGH);
+
+ return;
+}
+
+/**
Initialize controllers that must setup in the normal world
This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
@@ -101,6 +121,7 @@ ArmPlatformInitialize (
)
{
SocInit ();
+ MuxSelectUsb2 ();
return EFI_SUCCESS;
}
--
1.9.1
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On Wed, Oct 07, 2020 at 21:40:37 +0530, Meenakshi Aggarwal wrote:
> Second USB controller is muxed with I2c through GPIO.
> Setting GPIO bit to configure for second USB controller.
>
> Co-authored-by: Pramod Kumar <pramod.kumar_1@nxp.com>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
> ---
> Silicon/NXP/NxpQoriqLs.dec | 8 ++++++++
> Silicon/NXP/LS1046A/LS1046A.dsc.inc | 5 +++++
> Silicon/NXP/NxpQoriqLs.dsc.inc | 2 ++
> .../Library/ArmPlatformLib/ArmPlatformLib.inf | 1 +
> .../Library/ArmPlatformLib/ArmPlatformLib.c | 21 +++++++++++++++++++++
> 5 files changed, 37 insertions(+)
(But please remember --stat=1000 --stat-graph-width=20 on git
format-patch command line to get rid of ...)
> diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
> index 0c3608696569..3a568c0437e7 100644
> --- a/Silicon/NXP/NxpQoriqLs.dec
> +++ b/Silicon/NXP/NxpQoriqLs.dec
> @@ -29,6 +29,7 @@ [PcdsFeatureFlag]
> gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|FALSE|BOOLEAN|0x00000316
> gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x00000317
> gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA009185|FALSE|BOOLEAN|0x00000318
> + gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerBigEndian|FALSE|BOOLEAN|0x00000319
>
> [PcdsFixedAtBuild.common]
> # Pcds for PCI Express
> @@ -48,6 +49,13 @@ [PcdsFixedAtBuild.common]
> gNxpQoriqLsTokenSpaceGuid.PcdSataSize|0x0|UINT32|0x00000351
> gNxpQoriqLsTokenSpaceGuid.PcdNumSataController|0x0|UINT32|0x00000352
>
> + #
> + # Pcds for Gpio
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdNumGpioController|0|UINT32|0x00000355
> + gNxpQoriqLsTokenSpaceGuid.PcdGpioModuleBaseAddress|0|UINT64|0x00000356
> + gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerOffset|0|UINT64|0x00000357
> +
> [PcdsDynamic.common]
> gNxpQoriqLsTokenSpaceGuid.PcdPciCfgShiftEnable|FALSE|BOOLEAN|0x00000600
> gNxpQoriqLsTokenSpaceGuid.PcdPciLsGen4Ctrl|FALSE|BOOLEAN|0x00000601
> diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
> index dbe7f408fce9..db110553605f 100644
> --- a/Silicon/NXP/LS1046A/LS1046A.dsc.inc
> +++ b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
> @@ -27,9 +27,14 @@ [PcdsDynamicDefault.common]
>
> [PcdsFixedAtBuild.common]
> gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
> + gNxpQoriqLsTokenSpaceGuid.PcdNumGpioController|0x04
> + gNxpQoriqLsTokenSpaceGuid.PcdGpioModuleBaseAddress|0x02300000
> + gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerOffset|0x10000
> +
>
> [PcdsFeatureFlag]
> gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
> + gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerBigEndian|TRUE
>
> ################################################################################
> #
> diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
> index fc600de01d74..21c87df73220 100644
> --- a/Silicon/NXP/NxpQoriqLs.dsc.inc
> +++ b/Silicon/NXP/NxpQoriqLs.dsc.inc
> @@ -103,6 +103,8 @@ [LibraryClasses.common]
> MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
> UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
>
> + GpioLib|Silicon/NXP/Library/GpioLib/GpioLib.inf
> +
> [LibraryClasses.common.SEC]
> PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> DebugAgentLib|ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.inf
> diff --git a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> index 7802696bf39b..2e755842a714 100644
> --- a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> +++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> @@ -25,6 +25,7 @@ [Packages]
> [LibraryClasses]
> ArmLib
> DebugLib
> + GpioLib
> SocLib
>
> [Sources.common]
> diff --git a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> index e1f20da09337..ef404991add8 100644
> --- a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> +++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> @@ -8,11 +8,18 @@
>
> #include <Library/ArmLib.h>
> #include <Library/ArmPlatformLib.h>
> +#include <Library/GpioLib.h>
> #include <Library/SocLib.h>
>
> #include <Ppi/ArmMpCoreInfo.h>
> #include <Ppi/NxpPlatformGetClock.h>
>
> +/**
> + Documents use bit number as per Power PC notation,
> + so need to convert it to support ARMv8 architecture
> +**/
> +#define USB2_MUX_SEL_GPIO (31 - 23)
> +
> ARM_CORE_INFO mLS1046aMpCoreInfoTable[] = {
> {
> // Cluster 0, Core 0
> @@ -89,6 +96,19 @@ NxpPlatformGetClock(
> }
>
> /**
> + FRWY-LS1046A GPIO 23 use for USB2
> + mux seclection
> +**/
> +STATIC VOID MuxSelectUsb2 (VOID)
> +{
> +
> + GpioSetDirection (GPIO3, USB2_MUX_SEL_GPIO, OUTPUT);
> + GpioSetData (GPIO3, USB2_MUX_SEL_GPIO, HIGH);
> +
> + return;
> +}
> +
> +/**
> Initialize controllers that must setup in the normal world
>
> This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
> @@ -101,6 +121,7 @@ ArmPlatformInitialize (
> )
> {
> SocInit ();
> + MuxSelectUsb2 ();
>
> return EFI_SUCCESS;
> }
> --
> 1.9.1
>
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Add support for SCFG (Supplemental Configuration Unit)
register space and helper functions to R/W SCFG registers
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Silicon/NXP/NxpQoriqLs.dec | 1 +
Silicon/NXP/Chassis2/Include/Chassis.h | 108 +++++++++++++++++++++
Silicon/NXP/Include/Library/ChassisLib.h | 42 ++++++++
.../NXP/Chassis2/Library/ChassisLib/ChassisLib.c | 63 ++++++++++++
4 files changed, 214 insertions(+)
diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index 3a568c0437e7..90dce69fd472 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -30,6 +30,7 @@ [PcdsFeatureFlag]
gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x00000317
gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA009185|FALSE|BOOLEAN|0x00000318
gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerBigEndian|FALSE|BOOLEAN|0x00000319
+ gNxpQoriqLsTokenSpaceGuid.PcdScfgBigEndian|FALSE|BOOLEAN|0x00000320
[PcdsFixedAtBuild.common]
# Pcds for PCI Express
diff --git a/Silicon/NXP/Chassis2/Include/Chassis.h b/Silicon/NXP/Chassis2/Include/Chassis.h
index 7e8bf224884b..6dfce425a0b0 100644
--- a/Silicon/NXP/Chassis2/Include/Chassis.h
+++ b/Silicon/NXP/Chassis2/Include/Chassis.h
@@ -11,6 +11,7 @@
#include <Uefi.h>
#define NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS 0x1EE0000
+#define NXP_LAYERSCAPE_CHASSIS2_SCFG_ADDRESS 0x1570000
#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFE)
#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
@@ -45,4 +46,111 @@ typedef struct {
} NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG;
#pragma pack()
+/* Supplemental Configuration Unit (SCFG) */
+typedef struct {
+ UINT8 Res000[0x070-0x000];
+ UINT32 Usb1Prm1Cr;
+ UINT32 Usb1Prm2Cr;
+ UINT32 Usb1Prm3Cr;
+ UINT32 Usb2Prm1Cr;
+ UINT32 Usb2Prm2Cr;
+ UINT32 Usb2Prm3Cr;
+ UINT32 Usb3Prm1Cr;
+ UINT32 Usb3Prm2Cr;
+ UINT32 Usb3Prm3Cr;
+ UINT8 Res094[0x100-0x094];
+ UINT32 Usb2Icid;
+ UINT32 Usb3Icid;
+ UINT8 Res108[0x114-0x108];
+ UINT32 DmaIcid;
+ UINT32 SataIcid;
+ UINT32 Usb1Icid;
+ UINT32 QeIcid;
+ UINT32 SdhcIcid;
+ UINT32 EdmaIcid;
+ UINT32 EtrIcid;
+ UINT32 Core0SftRst;
+ UINT32 Core1SftRst;
+ UINT32 Core2SftRst;
+ UINT32 Core3SftRst;
+ UINT8 Res140[0x158-0x140];
+ UINT32 AltCBar;
+ UINT32 QspiCfg;
+ UINT8 Res160[0x180-0x160];
+ UINT32 DmaMcr;
+ UINT8 Res184[0x188-0x184];
+ UINT32 GicAlign;
+ UINT32 DebugIcid;
+ UINT8 Res190[0x1a4-0x190];
+ UINT32 SnpCnfgCr;
+#define SCFG_SNPCNFGCR_SECRDSNP BIT31
+#define SCFG_SNPCNFGCR_SECWRSNP BIT30
+#define SCFG_SNPCNFGCR_SATARDSNP BIT23
+#define SCFG_SNPCNFGCR_SATAWRSNP BIT22
+#define SCFG_SNPCNFGCR_USB1RDSNP BIT21
+#define SCFG_SNPCNFGCR_USB1WRSNP BIT20
+#define SCFG_SNPCNFGCR_USB2RDSNP BIT15
+#define SCFG_SNPCNFGCR_USB2WRSNP BIT16
+#define SCFG_SNPCNFGCR_USB3RDSNP BIT13
+#define SCFG_SNPCNFGCR_USB3WRSNP BIT14
+ UINT8 Res1a8[0x1ac-0x1a8];
+ UINT32 IntpCr;
+ UINT8 Res1b0[0x204-0x1b0];
+ UINT32 CoreSrEnCr;
+ UINT8 Res208[0x220-0x208];
+ UINT32 RvBar00;
+ UINT32 RvBar01;
+ UINT32 RvBar10;
+ UINT32 RvBar11;
+ UINT32 RvBar20;
+ UINT32 RvBar21;
+ UINT32 RvBar30;
+ UINT32 RvBar31;
+ UINT32 LpmCsr;
+ UINT8 Res244[0x400-0x244];
+ UINT32 QspIdQScr;
+ UINT32 EcgTxcMcr;
+ UINT32 SdhcIoVSelCr;
+ UINT32 RcwPMuxCr0;
+ /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
+ Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
+ Setting RCW PinMux Register bits 25-27 to select USB3_DRVVBUS
+ Setting RCW PinMux Register bits 29-31 to select USB3_DRVVBUS
+ **/
+#define SCFG_RCWPMUXCRO_SELCR_USB 0x3333
+ /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
+ Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
+ Setting RCW PinMux Register bits 25-27 to select IIC4_SCL
+ Setting RCW PinMux Register bits 29-31 to select IIC4_SDA
+ **/
+#define SCFG_RCWPMUXCRO_NOT_SELCR_USB 0x3300
+ UINT32 UsbDrvVBusSelCr;
+#define SCFG_USBDRVVBUS_SELCR_USB1 0x00000000
+#define SCFG_USBDRVVBUS_SELCR_USB2 0x00000001
+#define SCFG_USBDRVVBUS_SELCR_USB3 0x00000003
+ UINT32 UsbPwrFaultSelCr;
+#define SCFG_USBPWRFAULT_INACTIVE 0x00000000
+#define SCFG_USBPWRFAULT_SHARED 0x00000001
+#define SCFG_USBPWRFAULT_DEDICATED 0x00000002
+#define SCFG_USBPWRFAULT_USB3_SHIFT 4
+#define SCFG_USBPWRFAULT_USB2_SHIFT 2
+#define SCFG_USBPWRFAULT_USB1_SHIFT 0
+ UINT32 UsbRefclkSelcr1;
+ UINT32 UsbRefclkSelcr2;
+ UINT32 UsbRefclkSelcr3;
+ UINT8 Res424[0x600-0x424];
+ UINT32 ScratchRw[4];
+ UINT8 Res610[0x680-0x610];
+ UINT32 CoreBCr;
+ UINT8 Res684[0x1000-0x684];
+ UINT32 Pex1MsiIr;
+ UINT32 Pex1MsiR;
+ UINT8 Res1008[0x2000-0x1008];
+ UINT32 Pex2;
+ UINT32 Pex2MsiR;
+ UINT8 Res2008[0x3000-0x2008];
+ UINT32 Pex3MsiIr;
+ UINT32 Pex3MsiR;
+} NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG;
+
#endif // CHASSIS_H__
diff --git a/Silicon/NXP/Include/Library/ChassisLib.h b/Silicon/NXP/Include/Library/ChassisLib.h
index 89992a4b6fd5..a038d8e5ce31 100644
--- a/Silicon/NXP/Include/Library/ChassisLib.h
+++ b/Silicon/NXP/Include/Library/ChassisLib.h
@@ -13,6 +13,48 @@
#include <Chassis.h>
/**
+ Or Scfg register
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+**/
+UINT32
+EFIAPI
+ScfgOr32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ );
+
+/**
+ Read Scfg register
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+**/
+UINT32
+EFIAPI
+ScfgRead32 (
+ IN UINTN Address
+ );
+
+/**
+ Write Scfg register
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+ @return Value.
+**/
+UINT32
+EFIAPI
+ScfgWrite32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ );
+
+/**
Read Dcfg register
@param Address The MMIO register to read.
diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
index 91b19f832f00..e6410a53f480 100644
--- a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
+++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
@@ -15,6 +15,69 @@
#include <Library/SerialPortLib.h>
/**
+ Or Scfg register
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+**/
+UINT32
+EFIAPI
+ScfgOr32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ )
+{
+ MMIO_OPERATIONS *ScfgOps;
+
+ ScfgOps = GetMmioOperations (FeaturePcdGet (PcdScfgBigEndian));
+
+ return ScfgOps->Or32 (Address, Value);
+}
+
+/**
+ Read Scfg register
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+**/
+UINT32
+EFIAPI
+ScfgRead32 (
+ IN UINTN Address
+ )
+{
+ MMIO_OPERATIONS *ScfgOps;
+
+ ScfgOps = GetMmioOperations (FeaturePcdGet (PcdScfgBigEndian));
+
+ return ScfgOps->Read32 (Address);
+}
+
+/**
+ Write Scfg register
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+ @return Value.
+**/
+UINT32
+EFIAPI
+ScfgWrite32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ )
+{
+ MMIO_OPERATIONS *ScfgOps;
+
+ ScfgOps = GetMmioOperations (FeaturePcdGet (PcdScfgBigEndian));
+
+ return ScfgOps->Write32 (Address, Value);
+}
+
+/**
Read Dcfg register
@param Address The MMIO register to read.
--
1.9.1
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On Wed, Oct 07, 2020 at 21:40:38 +0530, Meenakshi Aggarwal wrote:
> Add support for SCFG (Supplemental Configuration Unit)
> register space and helper functions to R/W SCFG registers
>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
> ---
> Silicon/NXP/NxpQoriqLs.dec | 1 +
> Silicon/NXP/Chassis2/Include/Chassis.h | 108 +++++++++++++++++++++
> Silicon/NXP/Include/Library/ChassisLib.h | 42 ++++++++
> .../NXP/Chassis2/Library/ChassisLib/ChassisLib.c | 63 ++++++++++++
> 4 files changed, 214 insertions(+)
>
> diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
> index 3a568c0437e7..90dce69fd472 100644
> --- a/Silicon/NXP/NxpQoriqLs.dec
> +++ b/Silicon/NXP/NxpQoriqLs.dec
> @@ -30,6 +30,7 @@ [PcdsFeatureFlag]
> gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x00000317
> gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA009185|FALSE|BOOLEAN|0x00000318
> gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerBigEndian|FALSE|BOOLEAN|0x00000319
> + gNxpQoriqLsTokenSpaceGuid.PcdScfgBigEndian|FALSE|BOOLEAN|0x00000320
>
> [PcdsFixedAtBuild.common]
> # Pcds for PCI Express
> diff --git a/Silicon/NXP/Chassis2/Include/Chassis.h b/Silicon/NXP/Chassis2/Include/Chassis.h
> index 7e8bf224884b..6dfce425a0b0 100644
> --- a/Silicon/NXP/Chassis2/Include/Chassis.h
> +++ b/Silicon/NXP/Chassis2/Include/Chassis.h
> @@ -11,6 +11,7 @@
> #include <Uefi.h>
>
> #define NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS 0x1EE0000
> +#define NXP_LAYERSCAPE_CHASSIS2_SCFG_ADDRESS 0x1570000
>
> #define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFE)
> #define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
> @@ -45,4 +46,111 @@ typedef struct {
> } NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG;
> #pragma pack()
>
> +/* Supplemental Configuration Unit (SCFG) */
> +typedef struct {
> + UINT8 Res000[0x070-0x000];
> + UINT32 Usb1Prm1Cr;
> + UINT32 Usb1Prm2Cr;
> + UINT32 Usb1Prm3Cr;
> + UINT32 Usb2Prm1Cr;
> + UINT32 Usb2Prm2Cr;
> + UINT32 Usb2Prm3Cr;
> + UINT32 Usb3Prm1Cr;
> + UINT32 Usb3Prm2Cr;
> + UINT32 Usb3Prm3Cr;
> + UINT8 Res094[0x100-0x094];
> + UINT32 Usb2Icid;
> + UINT32 Usb3Icid;
> + UINT8 Res108[0x114-0x108];
> + UINT32 DmaIcid;
> + UINT32 SataIcid;
> + UINT32 Usb1Icid;
> + UINT32 QeIcid;
> + UINT32 SdhcIcid;
> + UINT32 EdmaIcid;
> + UINT32 EtrIcid;
> + UINT32 Core0SftRst;
> + UINT32 Core1SftRst;
> + UINT32 Core2SftRst;
> + UINT32 Core3SftRst;
> + UINT8 Res140[0x158-0x140];
> + UINT32 AltCBar;
> + UINT32 QspiCfg;
> + UINT8 Res160[0x180-0x160];
> + UINT32 DmaMcr;
> + UINT8 Res184[0x188-0x184];
> + UINT32 GicAlign;
> + UINT32 DebugIcid;
> + UINT8 Res190[0x1a4-0x190];
> + UINT32 SnpCnfgCr;
> +#define SCFG_SNPCNFGCR_SECRDSNP BIT31
> +#define SCFG_SNPCNFGCR_SECWRSNP BIT30
> +#define SCFG_SNPCNFGCR_SATARDSNP BIT23
> +#define SCFG_SNPCNFGCR_SATAWRSNP BIT22
> +#define SCFG_SNPCNFGCR_USB1RDSNP BIT21
> +#define SCFG_SNPCNFGCR_USB1WRSNP BIT20
> +#define SCFG_SNPCNFGCR_USB2RDSNP BIT15
> +#define SCFG_SNPCNFGCR_USB2WRSNP BIT16
> +#define SCFG_SNPCNFGCR_USB3RDSNP BIT13
> +#define SCFG_SNPCNFGCR_USB3WRSNP BIT14
> + UINT8 Res1a8[0x1ac-0x1a8];
> + UINT32 IntpCr;
> + UINT8 Res1b0[0x204-0x1b0];
> + UINT32 CoreSrEnCr;
> + UINT8 Res208[0x220-0x208];
> + UINT32 RvBar00;
> + UINT32 RvBar01;
> + UINT32 RvBar10;
> + UINT32 RvBar11;
> + UINT32 RvBar20;
> + UINT32 RvBar21;
> + UINT32 RvBar30;
> + UINT32 RvBar31;
> + UINT32 LpmCsr;
> + UINT8 Res244[0x400-0x244];
> + UINT32 QspIdQScr;
> + UINT32 EcgTxcMcr;
> + UINT32 SdhcIoVSelCr;
> + UINT32 RcwPMuxCr0;
> + /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
> + Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
> + Setting RCW PinMux Register bits 25-27 to select USB3_DRVVBUS
> + Setting RCW PinMux Register bits 29-31 to select USB3_DRVVBUS
> + **/
> +#define SCFG_RCWPMUXCRO_SELCR_USB 0x3333
> + /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
> + Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
> + Setting RCW PinMux Register bits 25-27 to select IIC4_SCL
> + Setting RCW PinMux Register bits 29-31 to select IIC4_SDA
> + **/
> +#define SCFG_RCWPMUXCRO_NOT_SELCR_USB 0x3300
> + UINT32 UsbDrvVBusSelCr;
> +#define SCFG_USBDRVVBUS_SELCR_USB1 0x00000000
> +#define SCFG_USBDRVVBUS_SELCR_USB2 0x00000001
> +#define SCFG_USBDRVVBUS_SELCR_USB3 0x00000003
> + UINT32 UsbPwrFaultSelCr;
> +#define SCFG_USBPWRFAULT_INACTIVE 0x00000000
> +#define SCFG_USBPWRFAULT_SHARED 0x00000001
> +#define SCFG_USBPWRFAULT_DEDICATED 0x00000002
> +#define SCFG_USBPWRFAULT_USB3_SHIFT 4
> +#define SCFG_USBPWRFAULT_USB2_SHIFT 2
> +#define SCFG_USBPWRFAULT_USB1_SHIFT 0
> + UINT32 UsbRefclkSelcr1;
> + UINT32 UsbRefclkSelcr2;
> + UINT32 UsbRefclkSelcr3;
> + UINT8 Res424[0x600-0x424];
> + UINT32 ScratchRw[4];
> + UINT8 Res610[0x680-0x610];
> + UINT32 CoreBCr;
> + UINT8 Res684[0x1000-0x684];
> + UINT32 Pex1MsiIr;
> + UINT32 Pex1MsiR;
> + UINT8 Res1008[0x2000-0x1008];
> + UINT32 Pex2;
> + UINT32 Pex2MsiR;
> + UINT8 Res2008[0x3000-0x2008];
> + UINT32 Pex3MsiIr;
> + UINT32 Pex3MsiR;
> +} NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG;
> +
> #endif // CHASSIS_H__
> diff --git a/Silicon/NXP/Include/Library/ChassisLib.h b/Silicon/NXP/Include/Library/ChassisLib.h
> index 89992a4b6fd5..a038d8e5ce31 100644
> --- a/Silicon/NXP/Include/Library/ChassisLib.h
> +++ b/Silicon/NXP/Include/Library/ChassisLib.h
> @@ -13,6 +13,48 @@
> #include <Chassis.h>
>
> /**
> + Or Scfg register
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +**/
> +UINT32
> +EFIAPI
> +ScfgOr32 (
> + IN UINTN Address,
> + IN UINT32 Value
> + );
> +
> +/**
> + Read Scfg register
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +**/
> +UINT32
> +EFIAPI
> +ScfgRead32 (
> + IN UINTN Address
> + );
> +
> +/**
> + Write Scfg register
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> + @return Value.
> +**/
> +UINT32
> +EFIAPI
> +ScfgWrite32 (
> + IN UINTN Address,
> + IN UINT32 Value
> + );
> +
> +/**
> Read Dcfg register
>
> @param Address The MMIO register to read.
> diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> index 91b19f832f00..e6410a53f480 100644
> --- a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> +++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> @@ -15,6 +15,69 @@
> #include <Library/SerialPortLib.h>
>
> /**
> + Or Scfg register
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +**/
> +UINT32
> +EFIAPI
> +ScfgOr32 (
> + IN UINTN Address,
> + IN UINT32 Value
> + )
> +{
> + MMIO_OPERATIONS *ScfgOps;
> +
> + ScfgOps = GetMmioOperations (FeaturePcdGet (PcdScfgBigEndian));
> +
> + return ScfgOps->Or32 (Address, Value);
> +}
> +
> +/**
> + Read Scfg register
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +**/
> +UINT32
> +EFIAPI
> +ScfgRead32 (
> + IN UINTN Address
> + )
> +{
> + MMIO_OPERATIONS *ScfgOps;
> +
> + ScfgOps = GetMmioOperations (FeaturePcdGet (PcdScfgBigEndian));
> +
> + return ScfgOps->Read32 (Address);
> +}
> +
> +/**
> + Write Scfg register
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> + @return Value.
> +**/
> +UINT32
> +EFIAPI
> +ScfgWrite32 (
> + IN UINTN Address,
> + IN UINT32 Value
> + )
> +{
> + MMIO_OPERATIONS *ScfgOps;
> +
> + ScfgOps = GetMmioOperations (FeaturePcdGet (PcdScfgBigEndian));
> +
> + return ScfgOps->Write32 (Address, Value);
> +}
> +
> +/**
> Read Dcfg register
>
> @param Address The MMIO register to read.
> --
> 1.9.1
>
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Implement workarounds for USB errata A009008,
A009798, A008997, A009007 for chassis2
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
.../NXP/Chassis2/Library/ChassisLib/ChassisLib.inf | 2 +
Silicon/NXP/Chassis2/Include/Chassis.h | 4 +
Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h | 23 +++
Silicon/NXP/Include/Library/ChassisLib.h | 20 +++
Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c | 165 +++++++++++++++++++++
5 files changed, 214 insertions(+)
create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h
create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c
diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
index f5dbd1349dc5..d64286b199c6 100644
--- a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
+++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
@@ -28,6 +28,8 @@ [LibraryClasses]
[Sources.common]
ChassisLib.c
+ Erratum.c
[FeaturePcd]
gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian
+ gNxpQoriqLsTokenSpaceGuid.PcdScfgBigEndian
diff --git a/Silicon/NXP/Chassis2/Include/Chassis.h b/Silicon/NXP/Chassis2/Include/Chassis.h
index 6dfce425a0b0..f8fa7ed67596 100644
--- a/Silicon/NXP/Chassis2/Include/Chassis.h
+++ b/Silicon/NXP/Chassis2/Include/Chassis.h
@@ -27,6 +27,10 @@
#define SCR0_CLIENTPD_MASK 0x00000001
#define SACR_PAGESIZE_MASK 0x00010000
+#define USB_PHY1_BASE_ADDRESS 0x084F0000
+#define USB_PHY2_BASE_ADDRESS 0x08500000
+#define USB_PHY3_BASE_ADDRESS 0x08510000
+
/**
The Device Configuration Unit provides general purpose configuration and
status for the device. These registers only support 32-bit accesses.
diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h b/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h
new file mode 100644
index 000000000000..0231ef0a283d
--- /dev/null
+++ b/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h
@@ -0,0 +1,23 @@
+/** @file
+* Header defining the Base addresses, sizes, flags etc for Erratas
+*
+* Copyright 2020 NXP
+*
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef ERRATUM_H__
+#define ERRATUM_H__
+
+#define USB_TXVREFTUNE 0x9
+#define USB_SQRXTUNE 0xFC7FFFFF
+#define USB_PCSTXSWINGFULL 0x47
+#define USB_PHY_RX_EQ_VAL_1 0x0000
+#define USB_PHY_RX_EQ_VAL_2 0x8000
+#define USB_PHY_RX_EQ_VAL_3 0x8003
+#define USB_PHY_RX_EQ_VAL_4 0x800b
+
+#define USB_PHY_RX_OVRD_IN_HI 0x200c
+
+#endif
diff --git a/Silicon/NXP/Include/Library/ChassisLib.h b/Silicon/NXP/Include/Library/ChassisLib.h
index a038d8e5ce31..c99368b4733d 100644
--- a/Silicon/NXP/Include/Library/ChassisLib.h
+++ b/Silicon/NXP/Include/Library/ChassisLib.h
@@ -90,4 +90,24 @@ ChassisInit (
VOID
);
+VOID
+ErratumA009008 (
+ VOID
+ );
+
+VOID
+ErratumA009798 (
+ VOID
+ );
+
+VOID
+ErratumA008997 (
+ VOID
+ );
+
+VOID
+ErratumA009007 (
+ VOID
+ );
+
#endif // CHASSIS_LIB_H__
diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c b/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c
new file mode 100644
index 000000000000..96afb1850853
--- /dev/null
+++ b/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c
@@ -0,0 +1,165 @@
+/** @file
+ This file containa all erratas need to be applied on different SoCs.
+
+ Copyright 2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Library/ArmLib.h>
+#include <Library/BaseLib.h>
+#include <Library/ChassisLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+
+#include "Erratum.h"
+
+/*
+* A-009008 : USB High Speed (HS) eye height adjustment
+* Affects : USB
+* Description: USB HS eye diagram fails with the default
+* value at many corners, particularly at a
+* high temperature (105°C).
+* Impact : USB HS eye diagram may fail using the default value.
+*/
+VOID
+ErratumA009008 (
+ VOID
+ )
+{
+ NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *Scfg;
+ UINT32 Value;
+
+ Scfg = (NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *)NXP_LAYERSCAPE_CHASSIS2_SCFG_ADDRESS;
+
+ Value = ScfgRead32 ((UINTN)&Scfg->Usb1Prm1Cr);
+ Value &= ~(0xF << 6);
+ ScfgWrite32 ((UINTN)&Scfg->Usb1Prm1Cr, Value|(USB_TXVREFTUNE << 6));
+ Value = ScfgRead32 ((UINTN)&Scfg->Usb2Prm1Cr);
+ Value &= ~(0xF << 6);
+ ScfgWrite32 ((UINTN)&Scfg->Usb2Prm1Cr, Value|(USB_TXVREFTUNE << 6));
+ Value = ScfgRead32 ((UINTN)&Scfg->Usb3Prm1Cr);
+ Value &= ~(0xF << 6);
+ ScfgWrite32 ((UINTN)&Scfg->Usb3Prm1Cr, Value|(USB_TXVREFTUNE << 6));
+
+ return;
+}
+
+/*
+* A-009798 : USB high speed squelch threshold adjustment
+* Affects : USB
+* Description: The default setting for USB high speed
+* squelch threshold results in a threshold close
+* to or lower than 100mV. This leads to a receiver
+* compliance test failure for a 100mV threshold.
+* Impact : If the errata is not applied, only the USB high
+* speed receiver sensitivity compliance test fails,
+* however USB data continues to transfer.
+*/
+VOID
+ErratumA009798 (
+ VOID
+ )
+{
+ NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *Scfg;
+ UINT32 Value;
+
+ Scfg = (NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *)NXP_LAYERSCAPE_CHASSIS2_SCFG_ADDRESS;
+
+ Value = ScfgRead32 ((UINTN)&Scfg->Usb1Prm1Cr);
+ ScfgWrite32 ((UINTN)&Scfg->Usb1Prm1Cr, Value & USB_SQRXTUNE);
+ Value = ScfgRead32 ((UINTN)&Scfg->Usb2Prm1Cr);
+ ScfgWrite32 ((UINTN)&Scfg->Usb2Prm1Cr, Value & USB_SQRXTUNE);
+ Value = ScfgRead32 ((UINTN)&Scfg->Usb3Prm1Cr);
+ ScfgWrite32 ((UINTN)&Scfg->Usb3Prm1Cr, Value & USB_SQRXTUNE);
+
+ return;
+}
+
+/*
+* A-008997 : USB3 LFPS peak-to-peak differential output
+* voltage adjustment settings
+* Affects : USB
+* Description: Low Frequency Periodic Signaling (LFPS)
+* peak-to-peak differential output voltage test
+* compliance fails using default transmitter settings.
+* Software is required to change the transmitter
+* signal swings to pass compliance tests.
+* Impact : LFPS peak-to-peak differential output voltage
+* compliance test fails.
+*/
+VOID
+ErratumA008997 (
+ VOID
+ )
+{
+ NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *Scfg;
+ UINT32 Value;
+
+ Scfg = (NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *)NXP_LAYERSCAPE_CHASSIS2_SCFG_ADDRESS;
+
+ Value = ScfgRead32 ((UINTN)&Scfg->Usb1Prm2Cr);
+ Value &= ~(0x7F << 9);
+ ScfgWrite32 ((UINTN)&Scfg->Usb1Prm2Cr, Value | (USB_PCSTXSWINGFULL << 9));
+ Value = ScfgRead32 ((UINTN)&Scfg->Usb2Prm2Cr);
+ Value &= ~(0x7F << 9);
+ ScfgWrite32 ((UINTN)&Scfg->Usb2Prm2Cr, Value | (USB_PCSTXSWINGFULL << 9));
+ Value = ScfgRead32 ((UINTN)&Scfg->Usb3Prm2Cr);
+ Value &= ~(0x7F << 9);
+ ScfgWrite32 ((UINTN)&Scfg->Usb3Prm2Cr, Value | (USB_PCSTXSWINGFULL << 9));
+
+ return;
+}
+
+/*
+* A-009007 : USB3PHY observing intermittent failure in
+* receive compliance tests at higher jitter frequency
+* using default register values
+* Affects : USB
+* Description: Receive compliance tests may fail intermittently at
+* high jitter frequencies using default register values.
+* Impact : Receive compliance test fails at default register setting.
+*/
+
+VOID
+ConfigUsbLane0 (
+ IN UINTN UsbPhy
+ )
+{
+ UINTN RegAddress;
+
+ RegAddress = UsbPhy + USB_PHY_RX_OVRD_IN_HI;
+
+ ArmDataMemoryBarrier ();
+ MmioWrite16 (RegAddress, USB_PHY_RX_EQ_VAL_1);
+ ArmDataMemoryBarrier ();
+ MmioWrite16 (RegAddress, USB_PHY_RX_EQ_VAL_2);
+ ArmDataMemoryBarrier ();
+ MmioWrite16 (RegAddress, USB_PHY_RX_EQ_VAL_3);
+ ArmDataMemoryBarrier ();
+ MmioWrite16 (RegAddress, USB_PHY_RX_EQ_VAL_4);
+
+ return;
+}
+
+VOID
+ErratumA009007 (
+ VOID
+ )
+{
+ UINTN UsbPhy;
+
+ UsbPhy = USB_PHY1_BASE_ADDRESS;
+ ConfigUsbLane0 (UsbPhy);
+
+ UsbPhy = USB_PHY2_BASE_ADDRESS;
+ ConfigUsbLane0 (UsbPhy);
+
+ UsbPhy = USB_PHY3_BASE_ADDRESS;
+ ConfigUsbLane0 (UsbPhy);
+
+ return;
+}
--
1.9.1
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On Wed, Oct 07, 2020 at 21:40:39 +0530, Meenakshi Aggarwal wrote:
> Implement workarounds for USB errata A009008,
> A009798, A008997, A009007 for chassis2
>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> .../NXP/Chassis2/Library/ChassisLib/ChassisLib.inf | 2 +
> Silicon/NXP/Chassis2/Include/Chassis.h | 4 +
> Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h | 23 +++
> Silicon/NXP/Include/Library/ChassisLib.h | 20 +++
> Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c | 165 +++++++++++++++++++++
> 5 files changed, 214 insertions(+)
> create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h
> create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c
>
> diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
> index f5dbd1349dc5..d64286b199c6 100644
> --- a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
> +++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
> @@ -28,6 +28,8 @@ [LibraryClasses]
>
> [Sources.common]
> ChassisLib.c
> + Erratum.c
>
> [FeaturePcd]
> gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian
> + gNxpQoriqLsTokenSpaceGuid.PcdScfgBigEndian
> diff --git a/Silicon/NXP/Chassis2/Include/Chassis.h b/Silicon/NXP/Chassis2/Include/Chassis.h
> index 6dfce425a0b0..f8fa7ed67596 100644
> --- a/Silicon/NXP/Chassis2/Include/Chassis.h
> +++ b/Silicon/NXP/Chassis2/Include/Chassis.h
> @@ -27,6 +27,10 @@
> #define SCR0_CLIENTPD_MASK 0x00000001
> #define SACR_PAGESIZE_MASK 0x00010000
>
> +#define USB_PHY1_BASE_ADDRESS 0x084F0000
> +#define USB_PHY2_BASE_ADDRESS 0x08500000
> +#define USB_PHY3_BASE_ADDRESS 0x08510000
> +
> /**
> The Device Configuration Unit provides general purpose configuration and
> status for the device. These registers only support 32-bit accesses.
> diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h b/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h
> new file mode 100644
> index 000000000000..0231ef0a283d
> --- /dev/null
> +++ b/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h
> @@ -0,0 +1,23 @@
> +/** @file
> +* Header defining the Base addresses, sizes, flags etc for Erratas
> +*
> +* Copyright 2020 NXP
> +*
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +**/
> +
> +#ifndef ERRATUM_H__
> +#define ERRATUM_H__
> +
> +#define USB_TXVREFTUNE 0x9
> +#define USB_SQRXTUNE 0xFC7FFFFF
> +#define USB_PCSTXSWINGFULL 0x47
> +#define USB_PHY_RX_EQ_VAL_1 0x0000
> +#define USB_PHY_RX_EQ_VAL_2 0x8000
> +#define USB_PHY_RX_EQ_VAL_3 0x8003
> +#define USB_PHY_RX_EQ_VAL_4 0x800b
> +
> +#define USB_PHY_RX_OVRD_IN_HI 0x200c
> +
> +#endif
> diff --git a/Silicon/NXP/Include/Library/ChassisLib.h b/Silicon/NXP/Include/Library/ChassisLib.h
> index a038d8e5ce31..c99368b4733d 100644
> --- a/Silicon/NXP/Include/Library/ChassisLib.h
> +++ b/Silicon/NXP/Include/Library/ChassisLib.h
> @@ -90,4 +90,24 @@ ChassisInit (
> VOID
> );
>
> +VOID
> +ErratumA009008 (
> + VOID
> + );
> +
> +VOID
> +ErratumA009798 (
> + VOID
> + );
> +
> +VOID
> +ErratumA008997 (
> + VOID
> + );
> +
> +VOID
> +ErratumA009007 (
> + VOID
> + );
> +
OK, the ordering here *certainly* doesn't matter - so please sort numerically.
> #endif // CHASSIS_LIB_H__
> diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c b/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c
> new file mode 100644
> index 000000000000..96afb1850853
> --- /dev/null
> +++ b/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c
> @@ -0,0 +1,165 @@
> +/** @file
> + This file containa all erratas need to be applied on different SoCs.
> +
> + Copyright 2020 NXP
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <Base.h>
> +#include <Library/ArmLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/ChassisLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/PcdLib.h>
> +
> +#include "Erratum.h"
> +
> +/*
> +* A-009008 : USB High Speed (HS) eye height adjustment
> +* Affects : USB
> +* Description: USB HS eye diagram fails with the default
> +* value at many corners, particularly at a
> +* high temperature (105°C).
> +* Impact : USB HS eye diagram may fail using the default value.
> +*/
> +VOID
> +ErratumA009008 (
> + VOID
> + )
> +{
> + NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *Scfg;
> + UINT32 Value;
> +
> + Scfg = (NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *)NXP_LAYERSCAPE_CHASSIS2_SCFG_ADDRESS;
> +
> + Value = ScfgRead32 ((UINTN)&Scfg->Usb1Prm1Cr);
> + Value &= ~(0xF << 6);
> + ScfgWrite32 ((UINTN)&Scfg->Usb1Prm1Cr, Value|(USB_TXVREFTUNE << 6));
> + Value = ScfgRead32 ((UINTN)&Scfg->Usb2Prm1Cr);
> + Value &= ~(0xF << 6);
> + ScfgWrite32 ((UINTN)&Scfg->Usb2Prm1Cr, Value|(USB_TXVREFTUNE << 6));
> + Value = ScfgRead32 ((UINTN)&Scfg->Usb3Prm1Cr);
> + Value &= ~(0xF << 6);
> + ScfgWrite32 ((UINTN)&Scfg->Usb3Prm1Cr, Value|(USB_TXVREFTUNE << 6));
> +
> + return;
> +}
> +
> +/*
> +* A-009798 : USB high speed squelch threshold adjustment
> +* Affects : USB
> +* Description: The default setting for USB high speed
> +* squelch threshold results in a threshold close
> +* to or lower than 100mV. This leads to a receiver
> +* compliance test failure for a 100mV threshold.
> +* Impact : If the errata is not applied, only the USB high
> +* speed receiver sensitivity compliance test fails,
> +* however USB data continues to transfer.
> +*/
> +VOID
> +ErratumA009798 (
> + VOID
> + )
> +{
> + NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *Scfg;
> + UINT32 Value;
> +
> + Scfg = (NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *)NXP_LAYERSCAPE_CHASSIS2_SCFG_ADDRESS;
> +
> + Value = ScfgRead32 ((UINTN)&Scfg->Usb1Prm1Cr);
> + ScfgWrite32 ((UINTN)&Scfg->Usb1Prm1Cr, Value & USB_SQRXTUNE);
> + Value = ScfgRead32 ((UINTN)&Scfg->Usb2Prm1Cr);
> + ScfgWrite32 ((UINTN)&Scfg->Usb2Prm1Cr, Value & USB_SQRXTUNE);
> + Value = ScfgRead32 ((UINTN)&Scfg->Usb3Prm1Cr);
> + ScfgWrite32 ((UINTN)&Scfg->Usb3Prm1Cr, Value & USB_SQRXTUNE);
> +
> + return;
> +}
> +
> +/*
> +* A-008997 : USB3 LFPS peak-to-peak differential output
> +* voltage adjustment settings
> +* Affects : USB
> +* Description: Low Frequency Periodic Signaling (LFPS)
> +* peak-to-peak differential output voltage test
> +* compliance fails using default transmitter settings.
> +* Software is required to change the transmitter
> +* signal swings to pass compliance tests.
> +* Impact : LFPS peak-to-peak differential output voltage
> +* compliance test fails.
> +*/
> +VOID
> +ErratumA008997 (
> + VOID
> + )
> +{
> + NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *Scfg;
> + UINT32 Value;
> +
> + Scfg = (NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *)NXP_LAYERSCAPE_CHASSIS2_SCFG_ADDRESS;
> +
> + Value = ScfgRead32 ((UINTN)&Scfg->Usb1Prm2Cr);
> + Value &= ~(0x7F << 9);
> + ScfgWrite32 ((UINTN)&Scfg->Usb1Prm2Cr, Value | (USB_PCSTXSWINGFULL << 9));
> + Value = ScfgRead32 ((UINTN)&Scfg->Usb2Prm2Cr);
> + Value &= ~(0x7F << 9);
> + ScfgWrite32 ((UINTN)&Scfg->Usb2Prm2Cr, Value | (USB_PCSTXSWINGFULL << 9));
> + Value = ScfgRead32 ((UINTN)&Scfg->Usb3Prm2Cr);
> + Value &= ~(0x7F << 9);
> + ScfgWrite32 ((UINTN)&Scfg->Usb3Prm2Cr, Value | (USB_PCSTXSWINGFULL << 9));
> +
> + return;
> +}
> +
> +/*
> +* A-009007 : USB3PHY observing intermittent failure in
> +* receive compliance tests at higher jitter frequency
> +* using default register values
> +* Affects : USB
> +* Description: Receive compliance tests may fail intermittently at
> +* high jitter frequencies using default register values.
> +* Impact : Receive compliance test fails at default register setting.
> +*/
> +
> +VOID
> +ConfigUsbLane0 (
> + IN UINTN UsbPhy
> + )
> +{
> + UINTN RegAddress;
> +
> + RegAddress = UsbPhy + USB_PHY_RX_OVRD_IN_HI;
> +
> + ArmDataMemoryBarrier ();
> + MmioWrite16 (RegAddress, USB_PHY_RX_EQ_VAL_1);
> + ArmDataMemoryBarrier ();
> + MmioWrite16 (RegAddress, USB_PHY_RX_EQ_VAL_2);
> + ArmDataMemoryBarrier ();
> + MmioWrite16 (RegAddress, USB_PHY_RX_EQ_VAL_3);
> + ArmDataMemoryBarrier ();
> + MmioWrite16 (RegAddress, USB_PHY_RX_EQ_VAL_4);
> +
> + return;
> +}
> +
> +VOID
> +ErratumA009007 (
> + VOID
> + )
> +{
> + UINTN UsbPhy;
> +
> + UsbPhy = USB_PHY1_BASE_ADDRESS;
> + ConfigUsbLane0 (UsbPhy);
> +
> + UsbPhy = USB_PHY2_BASE_ADDRESS;
> + ConfigUsbLane0 (UsbPhy);
> +
> + UsbPhy = USB_PHY3_BASE_ADDRESS;
> + ConfigUsbLane0 (UsbPhy);
> +
> + return;
> +}
Please sort the Erratum functions alphabetically here too.
/
Leif
> --
> 1.9.1
>
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-=-=-=-=-=-=-=-=-=-=-=-
Apply USB errata workarounds for LS1046A SoC and
make SATA, USB and SEC snoopable.
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Silicon/NXP/LS1046A/LS1046A.dsc.inc | 1 +
Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf | 2 +
Silicon/NXP/LS1046A/Include/Soc.h | 2 +
Silicon/NXP/LS1046A/Library/SocLib/SocLib.c | 66 +++++++++++++++++++++++++++
4 files changed, 71 insertions(+)
diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
index db110553605f..4e1d6a7ae7a2 100644
--- a/Silicon/NXP/LS1046A/LS1046A.dsc.inc
+++ b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
@@ -34,6 +34,7 @@ [PcdsFixedAtBuild.common]
[PcdsFeatureFlag]
gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
+ gNxpQoriqLsTokenSpaceGuid.PcdScfgBigEndian|TRUE
gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerBigEndian|TRUE
################################################################################
diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
index 01ed0f6592d2..e2336bb18f29 100644
--- a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
+++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
@@ -14,6 +14,7 @@ [Defines]
LIBRARY_CLASS = SocLib
[Packages]
+ ArmPkg/ArmPkg.dec
MdePkg/MdePkg.dec
Silicon/NXP/Chassis2/Chassis2.dec
Silicon/NXP/LS1046A/LS1046A.dec
@@ -25,3 +26,4 @@ [LibraryClasses]
[Sources.common]
SocLib.c
+
diff --git a/Silicon/NXP/LS1046A/Include/Soc.h b/Silicon/NXP/LS1046A/Include/Soc.h
index 84f433d5cb94..e1d97e531263 100644
--- a/Silicon/NXP/LS1046A/Include/Soc.h
+++ b/Silicon/NXP/LS1046A/Include/Soc.h
@@ -25,6 +25,7 @@
#define LS1046A_QSPI0_SIZE (SIZE_512MB)
#define LS1046A_DCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS
+#define LS1046A_SCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS2_SCFG_ADDRESS
/**
Reset Control Word (RCW) Bits
@@ -59,5 +60,6 @@ Bit(s) | Field Name | Description | Notes/comments
#define SYS_PLL_RAT(x) (((x) >> 25) & 0x1f) // Bits 2-6
typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG LS1046A_DEVICE_CONFIG;
+typedef NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG LS1046A_SUPPLEMENTAL_CONFIG;
#endif // SOC_H__
diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
index 3b15aee6ecae..80342d7230e4 100644
--- a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
+++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
@@ -11,6 +11,8 @@
#include <Library/ChassisLib.h>
#include <Library/DebugLib.h>
#include <Library/SocLib.h>
+
+#include <Library/SocLib.h>
#include <Soc.h>
/**
@@ -65,6 +67,47 @@ SocGetClock (
}
/**
+ Function to select pins depending upon pcd using supplemental
+ configuration unit(SCFG) extended RCW controlled pinmux control
+ register which contains the bits to provide pin multiplexing control.
+ This register is reset on HRESET.
+ **/
+STATIC
+VOID
+ConfigScfgMux (VOID)
+{
+ LS1046A_SUPPLEMENTAL_CONFIG *Scfg;
+ UINT32 UsbPwrFault;
+
+ Scfg = (LS1046A_SUPPLEMENTAL_CONFIG *)LS1046A_SCFG_ADDRESS;
+ // Configures functionality of the IIC3_SCL to USB2_DRVVBUS
+ // Configures functionality of the IIC3_SDA to USB2_PWRFAULT
+ // USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA
+ ScfgWrite32 ((UINTN)&Scfg->RcwPMuxCr0, SCFG_RCWPMUXCRO_NOT_SELCR_USB);
+
+ ScfgWrite32 ((UINTN)&Scfg->UsbDrvVBusSelCr, SCFG_USBDRVVBUS_SELCR_USB1);
+ UsbPwrFault = (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
+ (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
+ (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
+ ScfgWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault);
+ ScfgWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault);
+}
+
+STATIC
+VOID
+ApplyErrata (
+ VOID
+ )
+{
+ ErratumA009008 ();
+ ErratumA009798 ();
+ ErratumA008997 ();
+ ErratumA009007 ();
+}
+
+
+
+/**
Function to initialize SoC specific constructs
**/
VOID
@@ -72,7 +115,30 @@ SocInit (
VOID
)
{
+ LS1046A_SUPPLEMENTAL_CONFIG *Scfg;
+
+ Scfg = (LS1046A_SUPPLEMENTAL_CONFIG *)LS1046A_SCFG_ADDRESS;
+
+ /* Make SEC, SATA and USB reads and writes snoopable */
+ ScfgOr32((UINTN)&Scfg->SnpCnfgCr, SCFG_SNPCNFGCR_SECRDSNP |
+ SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
+ SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
+ SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
+ SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
+ SCFG_SNPCNFGCR_SATAWRSNP);
+
+ ApplyErrata ();
ChassisInit ();
+ //
+ // Due to the extensive functionality present on the chip and the limited number of external
+ // signals available, several functional blocks share signal resources through multiplexing.
+ // In this case when there is alternate functionality between multiple functional blocks,
+ // the signal's function is determined at the chip level (rather than at the block level)
+ // typically by a reset configuration word (RCW) option. Some of the signals' function are
+ // determined externel to RCW at Power-on Reset Sequence.
+ //
+ ConfigScfgMux ();
+
return;
}
--
1.9.1
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On Wed, Oct 07, 2020 at 21:40:40 +0530, Meenakshi Aggarwal wrote:
> Apply USB errata workarounds for LS1046A SoC and
> make SATA, USB and SEC snoopable.
>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Silicon/NXP/LS1046A/LS1046A.dsc.inc | 1 +
> Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf | 2 +
> Silicon/NXP/LS1046A/Include/Soc.h | 2 +
> Silicon/NXP/LS1046A/Library/SocLib/SocLib.c | 66 +++++++++++++++++++++++++++
> 4 files changed, 71 insertions(+)
>
> diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
> index db110553605f..4e1d6a7ae7a2 100644
> --- a/Silicon/NXP/LS1046A/LS1046A.dsc.inc
> +++ b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
> @@ -34,6 +34,7 @@ [PcdsFixedAtBuild.common]
>
> [PcdsFeatureFlag]
> gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
> + gNxpQoriqLsTokenSpaceGuid.PcdScfgBigEndian|TRUE
> gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerBigEndian|TRUE
>
> ################################################################################
> diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
> index 01ed0f6592d2..e2336bb18f29 100644
> --- a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
> +++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
> @@ -14,6 +14,7 @@ [Defines]
> LIBRARY_CLASS = SocLib
>
> [Packages]
> + ArmPkg/ArmPkg.dec
> MdePkg/MdePkg.dec
> Silicon/NXP/Chassis2/Chassis2.dec
> Silicon/NXP/LS1046A/LS1046A.dec
> @@ -25,3 +26,4 @@ [LibraryClasses]
>
> [Sources.common]
> SocLib.c
> +
This spuriously added blank line at the end of the file makes git
complain on import. Please drop it.
> diff --git a/Silicon/NXP/LS1046A/Include/Soc.h b/Silicon/NXP/LS1046A/Include/Soc.h
> index 84f433d5cb94..e1d97e531263 100644
> --- a/Silicon/NXP/LS1046A/Include/Soc.h
> +++ b/Silicon/NXP/LS1046A/Include/Soc.h
> @@ -25,6 +25,7 @@
> #define LS1046A_QSPI0_SIZE (SIZE_512MB)
>
> #define LS1046A_DCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS
> +#define LS1046A_SCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS2_SCFG_ADDRESS
>
> /**
> Reset Control Word (RCW) Bits
> @@ -59,5 +60,6 @@ Bit(s) | Field Name | Description | Notes/comments
> #define SYS_PLL_RAT(x) (((x) >> 25) & 0x1f) // Bits 2-6
>
> typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG LS1046A_DEVICE_CONFIG;
> +typedef NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG LS1046A_SUPPLEMENTAL_CONFIG;
>
> #endif // SOC_H__
> diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
> index 3b15aee6ecae..80342d7230e4 100644
> --- a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
> +++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
> @@ -11,6 +11,8 @@
> #include <Library/ChassisLib.h>
> #include <Library/DebugLib.h>
> #include <Library/SocLib.h>
> +
> +#include <Library/SocLib.h>
Why include SocLib.h twice?
> #include <Soc.h>
>
> /**
> @@ -65,6 +67,47 @@ SocGetClock (
> }
>
> /**
> + Function to select pins depending upon pcd using supplemental
> + configuration unit(SCFG) extended RCW controlled pinmux control
> + register which contains the bits to provide pin multiplexing control.
> + This register is reset on HRESET.
> + **/
> +STATIC
> +VOID
> +ConfigScfgMux (VOID)
> +{
> + LS1046A_SUPPLEMENTAL_CONFIG *Scfg;
> + UINT32 UsbPwrFault;
> +
> + Scfg = (LS1046A_SUPPLEMENTAL_CONFIG *)LS1046A_SCFG_ADDRESS;
> + // Configures functionality of the IIC3_SCL to USB2_DRVVBUS
> + // Configures functionality of the IIC3_SDA to USB2_PWRFAULT
> + // USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA
> + ScfgWrite32 ((UINTN)&Scfg->RcwPMuxCr0, SCFG_RCWPMUXCRO_NOT_SELCR_USB);
> +
> + ScfgWrite32 ((UINTN)&Scfg->UsbDrvVBusSelCr, SCFG_USBDRVVBUS_SELCR_USB1);
> + UsbPwrFault = (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
> + (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
> + (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
> + ScfgWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault);
> + ScfgWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault);
> +}
> +
> +STATIC
> +VOID
> +ApplyErrata (
> + VOID
> + )
> +{
> + ErratumA009008 ();
> + ErratumA009798 ();
> + ErratumA008997 ();
> + ErratumA009007 ();
Is there a required order to these workarounds? If not, can they be
done in numerical order?
/
Leif
> +}
> +
> +
> +
> +/**
> Function to initialize SoC specific constructs
> **/
> VOID
> @@ -72,7 +115,30 @@ SocInit (
> VOID
> )
> {
> + LS1046A_SUPPLEMENTAL_CONFIG *Scfg;
> +
> + Scfg = (LS1046A_SUPPLEMENTAL_CONFIG *)LS1046A_SCFG_ADDRESS;
> +
> + /* Make SEC, SATA and USB reads and writes snoopable */
> + ScfgOr32((UINTN)&Scfg->SnpCnfgCr, SCFG_SNPCNFGCR_SECRDSNP |
> + SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
> + SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
> + SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
> + SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
> + SCFG_SNPCNFGCR_SATAWRSNP);
> +
> + ApplyErrata ();
> ChassisInit ();
>
> + //
> + // Due to the extensive functionality present on the chip and the limited number of external
> + // signals available, several functional blocks share signal resources through multiplexing.
> + // In this case when there is alternate functionality between multiple functional blocks,
> + // the signal's function is determined at the chip level (rather than at the block level)
> + // typically by a reset configuration word (RCW) option. Some of the signals' function are
> + // determined externel to RCW at Power-on Reset Sequence.
> + //
> + ConfigScfgMux ();
> +
> return;
> }
> --
> 1.9.1
>
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Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
---
Silicon/NXP/LS1046A/LS1046A.dsc.inc | 3 +++
Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc | 2 ++
Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf | 13 +++++++++++++
3 files changed, 18 insertions(+)
mode change 100644 => 100755 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
mode change 100644 => 100755 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
index 4e1d6a7ae7a2..7004533ed5f1 100644
--- a/Silicon/NXP/LS1046A/LS1046A.dsc.inc
+++ b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
@@ -31,6 +31,9 @@ [PcdsFixedAtBuild.common]
gNxpQoriqLsTokenSpaceGuid.PcdGpioModuleBaseAddress|0x02300000
gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerOffset|0x10000
+ gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr|0x2F00000
+ gNxpQoriqLsTokenSpaceGuid.PcdUsbSize|0x100000
+ gNxpQoriqLsTokenSpaceGuid.PcdNumUsbController|3
[PcdsFeatureFlag]
gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
old mode 100644
new mode 100755
index 3f29dadd5d1d..266fdbd2b4d3
--- a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
@@ -43,4 +43,6 @@ [Components.common]
gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE
}
+ Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf
+
##
diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
old mode 100644
new mode 100755
index 24af547729c7..34c4e5a02516
--- a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
@@ -120,6 +120,19 @@ [FV.FvMain]
INF FatPkg/EnhancedFatDxe/Fat.inf
INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+ INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+
+ #
+ # USB Support
+ #
+ INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+ INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+ INF Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf
+
#
# UEFI application (Shell Embedded Boot Loader)
#
--
1.9.1
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This patch set adds GPIO Library. Gpio Library is required to set muxing to enable USB controller. Changes in v3: - Incorporated review comments Changes in v2: - Modified GpioLib as per review comments - Prepared separate patch for SCFG enablement - Prepared sepaarte patch for USB errata implementation Meenakshi Aggarwal (6): Silicon/NXP: Add GPIO Library support. Platform/NXP/LS1046aFrwyPkg: MUX changes for USB Silicon/NXP: Add SCFG support for Chassis2 Silicon/NXP: Implement USB Errata Workarounds Silicon/NXP/LS1046A: Apply USB errata workarounds LS1046aFrwy: Enable USB support for LS1046AFRWY board. Silicon/NXP/NxpQoriqLs.dec | 9 + Silicon/NXP/LS1046A/LS1046A.dsc.inc | 9 + Silicon/NXP/NxpQoriqLs.dsc.inc | 2 + Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc | 2 + Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf | 13 ++ .../Library/ArmPlatformLib/ArmPlatformLib.inf | 1 + .../NXP/Chassis2/Library/ChassisLib/ChassisLib.inf | 2 + Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf | 1 + Silicon/NXP/Library/GpioLib/GpioLib.inf | 39 ++++ Silicon/NXP/Chassis2/Include/Chassis.h | 112 +++++++++++ Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h | 23 +++ Silicon/NXP/Include/Library/ChassisLib.h | 62 ++++++ Silicon/NXP/Include/Library/GpioLib.h | 110 +++++++++++ Silicon/NXP/LS1046A/Include/Soc.h | 2 + .../Library/ArmPlatformLib/ArmPlatformLib.c | 21 ++ .../NXP/Chassis2/Library/ChassisLib/ChassisLib.c | 63 ++++++ Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c | 165 ++++++++++++++++ Silicon/NXP/LS1046A/Library/SocLib/SocLib.c | 65 ++++++ Silicon/NXP/Library/GpioLib/GpioLib.c | 219 +++++++++++++++++++++ 19 files changed, 920 insertions(+) mode change 100644 => 100755 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc mode change 100644 => 100755 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf create mode 100644 Silicon/NXP/Library/GpioLib/GpioLib.inf create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h create mode 100644 Silicon/NXP/Include/Library/GpioLib.h create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c create mode 100644 Silicon/NXP/Library/GpioLib/GpioLib.c -- 1.9.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#66067): https://edk2.groups.io/g/devel/message/66067 Mute This Topic: https://groups.io/mt/77402666/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
On Fri, Oct 09, 2020 at 20:49:01 +0530, Meenakshi Aggarwal wrote: > This patch set adds GPIO Library. > Gpio Library is required to set muxing to enable USB controller. > > > Changes in v3: > - Incorporated review comments > > Changes in v2: > - Modified GpioLib as per review comments > - Prepared separate patch for SCFG enablement > - Prepared sepaarte patch for USB errata implementation > > Meenakshi Aggarwal (6): > Silicon/NXP: Add GPIO Library support. > Platform/NXP/LS1046aFrwyPkg: MUX changes for USB > Silicon/NXP: Add SCFG support for Chassis2 > Silicon/NXP: Implement USB Errata Workarounds > Silicon/NXP/LS1046A: Apply USB errata workarounds > LS1046aFrwy: Enable USB support for LS1046AFRWY board. For the series: Reviewed-by: Leif Lindholm <leif@nuviainc.com> Pushed as e3461bfe3d3f..325619f738d7. > Silicon/NXP/NxpQoriqLs.dec | 9 + > Silicon/NXP/LS1046A/LS1046A.dsc.inc | 9 + > Silicon/NXP/NxpQoriqLs.dsc.inc | 2 + > Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc | 2 + > Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf | 13 ++ > .../Library/ArmPlatformLib/ArmPlatformLib.inf | 1 + > .../NXP/Chassis2/Library/ChassisLib/ChassisLib.inf | 2 + > Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf | 1 + > Silicon/NXP/Library/GpioLib/GpioLib.inf | 39 ++++ > Silicon/NXP/Chassis2/Include/Chassis.h | 112 +++++++++++ > Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h | 23 +++ > Silicon/NXP/Include/Library/ChassisLib.h | 62 ++++++ > Silicon/NXP/Include/Library/GpioLib.h | 110 +++++++++++ > Silicon/NXP/LS1046A/Include/Soc.h | 2 + > .../Library/ArmPlatformLib/ArmPlatformLib.c | 21 ++ > .../NXP/Chassis2/Library/ChassisLib/ChassisLib.c | 63 ++++++ > Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c | 165 ++++++++++++++++ > Silicon/NXP/LS1046A/Library/SocLib/SocLib.c | 65 ++++++ > Silicon/NXP/Library/GpioLib/GpioLib.c | 219 +++++++++++++++++++++ > 19 files changed, 920 insertions(+) > mode change 100644 => 100755 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc > mode change 100644 => 100755 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf > create mode 100644 Silicon/NXP/Library/GpioLib/GpioLib.inf > create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h > create mode 100644 Silicon/NXP/Include/Library/GpioLib.h > create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c > create mode 100644 Silicon/NXP/Library/GpioLib/GpioLib.c > > -- > 1.9.1 > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#66078): https://edk2.groups.io/g/devel/message/66078 Mute This Topic: https://groups.io/mt/77402666/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
Implement workarounds for USB errata A008997, A009007,
A009008, A009798 for chassis2
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
.../NXP/Chassis2/Library/ChassisLib/ChassisLib.inf | 2 +
Silicon/NXP/Chassis2/Include/Chassis.h | 4 +
Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h | 23 +++
Silicon/NXP/Include/Library/ChassisLib.h | 20 +++
Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c | 165 +++++++++++++++++++++
5 files changed, 214 insertions(+)
create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h
create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c
diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
index f5dbd1349dc5..d64286b199c6 100644
--- a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
+++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
@@ -28,6 +28,8 @@ [LibraryClasses]
[Sources.common]
ChassisLib.c
+ Erratum.c
[FeaturePcd]
gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian
+ gNxpQoriqLsTokenSpaceGuid.PcdScfgBigEndian
diff --git a/Silicon/NXP/Chassis2/Include/Chassis.h b/Silicon/NXP/Chassis2/Include/Chassis.h
index 6dfce425a0b0..f8fa7ed67596 100644
--- a/Silicon/NXP/Chassis2/Include/Chassis.h
+++ b/Silicon/NXP/Chassis2/Include/Chassis.h
@@ -27,6 +27,10 @@
#define SCR0_CLIENTPD_MASK 0x00000001
#define SACR_PAGESIZE_MASK 0x00010000
+#define USB_PHY1_BASE_ADDRESS 0x084F0000
+#define USB_PHY2_BASE_ADDRESS 0x08500000
+#define USB_PHY3_BASE_ADDRESS 0x08510000
+
/**
The Device Configuration Unit provides general purpose configuration and
status for the device. These registers only support 32-bit accesses.
diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h b/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h
new file mode 100644
index 000000000000..0231ef0a283d
--- /dev/null
+++ b/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h
@@ -0,0 +1,23 @@
+/** @file
+* Header defining the Base addresses, sizes, flags etc for Erratas
+*
+* Copyright 2020 NXP
+*
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef ERRATUM_H__
+#define ERRATUM_H__
+
+#define USB_TXVREFTUNE 0x9
+#define USB_SQRXTUNE 0xFC7FFFFF
+#define USB_PCSTXSWINGFULL 0x47
+#define USB_PHY_RX_EQ_VAL_1 0x0000
+#define USB_PHY_RX_EQ_VAL_2 0x8000
+#define USB_PHY_RX_EQ_VAL_3 0x8003
+#define USB_PHY_RX_EQ_VAL_4 0x800b
+
+#define USB_PHY_RX_OVRD_IN_HI 0x200c
+
+#endif
diff --git a/Silicon/NXP/Include/Library/ChassisLib.h b/Silicon/NXP/Include/Library/ChassisLib.h
index a038d8e5ce31..ffe57a6f019d 100644
--- a/Silicon/NXP/Include/Library/ChassisLib.h
+++ b/Silicon/NXP/Include/Library/ChassisLib.h
@@ -90,4 +90,24 @@ ChassisInit (
VOID
);
+VOID
+ErratumA008997 (
+ VOID
+ );
+
+VOID
+ErratumA009007 (
+ VOID
+ );
+
+VOID
+ErratumA009008 (
+ VOID
+ );
+
+VOID
+ErratumA009798 (
+ VOID
+ );
+
#endif // CHASSIS_LIB_H__
diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c b/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c
new file mode 100644
index 000000000000..4f0deb24b658
--- /dev/null
+++ b/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c
@@ -0,0 +1,165 @@
+/** @file
+ This file containa all erratas need to be applied on different SoCs.
+
+ Copyright 2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Library/ArmLib.h>
+#include <Library/BaseLib.h>
+#include <Library/ChassisLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+
+#include "Erratum.h"
+
+/*
+* A-008997 : USB3 LFPS peak-to-peak differential output
+* voltage adjustment settings
+* Affects : USB
+* Description: Low Frequency Periodic Signaling (LFPS)
+* peak-to-peak differential output voltage test
+* compliance fails using default transmitter settings.
+* Software is required to change the transmitter
+* signal swings to pass compliance tests.
+* Impact : LFPS peak-to-peak differential output voltage
+* compliance test fails.
+*/
+VOID
+ErratumA008997 (
+ VOID
+ )
+{
+ NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *Scfg;
+ UINT32 Value;
+
+ Scfg = (NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *)NXP_LAYERSCAPE_CHASSIS2_SCFG_ADDRESS;
+
+ Value = ScfgRead32 ((UINTN)&Scfg->Usb1Prm2Cr);
+ Value &= ~(0x7F << 9);
+ ScfgWrite32 ((UINTN)&Scfg->Usb1Prm2Cr, Value | (USB_PCSTXSWINGFULL << 9));
+ Value = ScfgRead32 ((UINTN)&Scfg->Usb2Prm2Cr);
+ Value &= ~(0x7F << 9);
+ ScfgWrite32 ((UINTN)&Scfg->Usb2Prm2Cr, Value | (USB_PCSTXSWINGFULL << 9));
+ Value = ScfgRead32 ((UINTN)&Scfg->Usb3Prm2Cr);
+ Value &= ~(0x7F << 9);
+ ScfgWrite32 ((UINTN)&Scfg->Usb3Prm2Cr, Value | (USB_PCSTXSWINGFULL << 9));
+
+ return;
+}
+
+/*
+* A-009007 : USB3PHY observing intermittent failure in
+* receive compliance tests at higher jitter frequency
+* using default register values
+* Affects : USB
+* Description: Receive compliance tests may fail intermittently at
+* high jitter frequencies using default register values.
+* Impact : Receive compliance test fails at default register setting.
+*/
+
+VOID
+ConfigUsbLane0 (
+ IN UINTN UsbPhy
+ )
+{
+ UINTN RegAddress;
+
+ RegAddress = UsbPhy + USB_PHY_RX_OVRD_IN_HI;
+
+ ArmDataMemoryBarrier ();
+ MmioWrite16 (RegAddress, USB_PHY_RX_EQ_VAL_1);
+ ArmDataMemoryBarrier ();
+ MmioWrite16 (RegAddress, USB_PHY_RX_EQ_VAL_2);
+ ArmDataMemoryBarrier ();
+ MmioWrite16 (RegAddress, USB_PHY_RX_EQ_VAL_3);
+ ArmDataMemoryBarrier ();
+ MmioWrite16 (RegAddress, USB_PHY_RX_EQ_VAL_4);
+
+ return;
+}
+
+VOID
+ErratumA009007 (
+ VOID
+ )
+{
+ UINTN UsbPhy;
+
+ UsbPhy = USB_PHY1_BASE_ADDRESS;
+ ConfigUsbLane0 (UsbPhy);
+
+ UsbPhy = USB_PHY2_BASE_ADDRESS;
+ ConfigUsbLane0 (UsbPhy);
+
+ UsbPhy = USB_PHY3_BASE_ADDRESS;
+ ConfigUsbLane0 (UsbPhy);
+
+ return;
+}
+
+/*
+* A-009008 : USB High Speed (HS) eye height adjustment
+* Affects : USB
+* Description: USB HS eye diagram fails with the default
+* value at many corners, particularly at a
+* high temperature (105°C).
+* Impact : USB HS eye diagram may fail using the default value.
+*/
+VOID
+ErratumA009008 (
+ VOID
+ )
+{
+ NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *Scfg;
+ UINT32 Value;
+
+ Scfg = (NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *)NXP_LAYERSCAPE_CHASSIS2_SCFG_ADDRESS;
+
+ Value = ScfgRead32 ((UINTN)&Scfg->Usb1Prm1Cr);
+ Value &= ~(0xF << 6);
+ ScfgWrite32 ((UINTN)&Scfg->Usb1Prm1Cr, Value|(USB_TXVREFTUNE << 6));
+ Value = ScfgRead32 ((UINTN)&Scfg->Usb2Prm1Cr);
+ Value &= ~(0xF << 6);
+ ScfgWrite32 ((UINTN)&Scfg->Usb2Prm1Cr, Value|(USB_TXVREFTUNE << 6));
+ Value = ScfgRead32 ((UINTN)&Scfg->Usb3Prm1Cr);
+ Value &= ~(0xF << 6);
+ ScfgWrite32 ((UINTN)&Scfg->Usb3Prm1Cr, Value|(USB_TXVREFTUNE << 6));
+
+ return;
+}
+
+/*
+* A-009798 : USB high speed squelch threshold adjustment
+* Affects : USB
+* Description: The default setting for USB high speed
+* squelch threshold results in a threshold close
+* to or lower than 100mV. This leads to a receiver
+* compliance test failure for a 100mV threshold.
+* Impact : If the errata is not applied, only the USB high
+* speed receiver sensitivity compliance test fails,
+* however USB data continues to transfer.
+*/
+VOID
+ErratumA009798 (
+ VOID
+ )
+{
+ NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *Scfg;
+ UINT32 Value;
+
+ Scfg = (NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *)NXP_LAYERSCAPE_CHASSIS2_SCFG_ADDRESS;
+
+ Value = ScfgRead32 ((UINTN)&Scfg->Usb1Prm1Cr);
+ ScfgWrite32 ((UINTN)&Scfg->Usb1Prm1Cr, Value & USB_SQRXTUNE);
+ Value = ScfgRead32 ((UINTN)&Scfg->Usb2Prm1Cr);
+ ScfgWrite32 ((UINTN)&Scfg->Usb2Prm1Cr, Value & USB_SQRXTUNE);
+ Value = ScfgRead32 ((UINTN)&Scfg->Usb3Prm1Cr);
+ ScfgWrite32 ((UINTN)&Scfg->Usb3Prm1Cr, Value & USB_SQRXTUNE);
+
+ return;
+}
--
1.9.1
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Apply USB errata workarounds for LS1046A SoC and
make SATA, USB and SEC snoopable.
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Silicon/NXP/LS1046A/LS1046A.dsc.inc | 1 +
Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf | 1 +
Silicon/NXP/LS1046A/Include/Soc.h | 2 +
Silicon/NXP/LS1046A/Library/SocLib/SocLib.c | 65 +++++++++++++++++++++++++++
4 files changed, 69 insertions(+)
diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
index db110553605f..4e1d6a7ae7a2 100644
--- a/Silicon/NXP/LS1046A/LS1046A.dsc.inc
+++ b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
@@ -34,6 +34,7 @@ [PcdsFixedAtBuild.common]
[PcdsFeatureFlag]
gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
+ gNxpQoriqLsTokenSpaceGuid.PcdScfgBigEndian|TRUE
gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerBigEndian|TRUE
################################################################################
diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
index 01ed0f6592d2..36c09778b134 100644
--- a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
+++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
@@ -14,6 +14,7 @@ [Defines]
LIBRARY_CLASS = SocLib
[Packages]
+ ArmPkg/ArmPkg.dec
MdePkg/MdePkg.dec
Silicon/NXP/Chassis2/Chassis2.dec
Silicon/NXP/LS1046A/LS1046A.dec
diff --git a/Silicon/NXP/LS1046A/Include/Soc.h b/Silicon/NXP/LS1046A/Include/Soc.h
index 84f433d5cb94..e1d97e531263 100644
--- a/Silicon/NXP/LS1046A/Include/Soc.h
+++ b/Silicon/NXP/LS1046A/Include/Soc.h
@@ -25,6 +25,7 @@
#define LS1046A_QSPI0_SIZE (SIZE_512MB)
#define LS1046A_DCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS
+#define LS1046A_SCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS2_SCFG_ADDRESS
/**
Reset Control Word (RCW) Bits
@@ -59,5 +60,6 @@ Bit(s) | Field Name | Description | Notes/comments
#define SYS_PLL_RAT(x) (((x) >> 25) & 0x1f) // Bits 2-6
typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG LS1046A_DEVICE_CONFIG;
+typedef NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG LS1046A_SUPPLEMENTAL_CONFIG;
#endif // SOC_H__
diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
index 3b15aee6ecae..7726faf748cb 100644
--- a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
+++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
@@ -11,6 +11,7 @@
#include <Library/ChassisLib.h>
#include <Library/DebugLib.h>
#include <Library/SocLib.h>
+
#include <Soc.h>
/**
@@ -65,6 +66,47 @@ SocGetClock (
}
/**
+ Function to select pins depending upon pcd using supplemental
+ configuration unit(SCFG) extended RCW controlled pinmux control
+ register which contains the bits to provide pin multiplexing control.
+ This register is reset on HRESET.
+ **/
+STATIC
+VOID
+ConfigScfgMux (VOID)
+{
+ LS1046A_SUPPLEMENTAL_CONFIG *Scfg;
+ UINT32 UsbPwrFault;
+
+ Scfg = (LS1046A_SUPPLEMENTAL_CONFIG *)LS1046A_SCFG_ADDRESS;
+ // Configures functionality of the IIC3_SCL to USB2_DRVVBUS
+ // Configures functionality of the IIC3_SDA to USB2_PWRFAULT
+ // USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA
+ ScfgWrite32 ((UINTN)&Scfg->RcwPMuxCr0, SCFG_RCWPMUXCRO_NOT_SELCR_USB);
+
+ ScfgWrite32 ((UINTN)&Scfg->UsbDrvVBusSelCr, SCFG_USBDRVVBUS_SELCR_USB1);
+ UsbPwrFault = (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
+ (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
+ (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
+ ScfgWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault);
+ ScfgWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault);
+}
+
+STATIC
+VOID
+ApplyErrata (
+ VOID
+ )
+{
+ ErratumA008997 ();
+ ErratumA009007 ();
+ ErratumA009008 ();
+ ErratumA009798 ();
+}
+
+
+
+/**
Function to initialize SoC specific constructs
**/
VOID
@@ -72,7 +114,30 @@ SocInit (
VOID
)
{
+ LS1046A_SUPPLEMENTAL_CONFIG *Scfg;
+
+ Scfg = (LS1046A_SUPPLEMENTAL_CONFIG *)LS1046A_SCFG_ADDRESS;
+
+ /* Make SEC, SATA and USB reads and writes snoopable */
+ ScfgOr32((UINTN)&Scfg->SnpCnfgCr, SCFG_SNPCNFGCR_SECRDSNP |
+ SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
+ SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
+ SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
+ SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
+ SCFG_SNPCNFGCR_SATAWRSNP);
+
+ ApplyErrata ();
ChassisInit ();
+ //
+ // Due to the extensive functionality present on the chip and the limited number of external
+ // signals available, several functional blocks share signal resources through multiplexing.
+ // In this case when there is alternate functionality between multiple functional blocks,
+ // the signal's function is determined at the chip level (rather than at the block level)
+ // typically by a reset configuration word (RCW) option. Some of the signals' function are
+ // determined externel to RCW at Power-on Reset Sequence.
+ //
+ ConfigScfgMux ();
+
return;
}
--
1.9.1
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On Fri, Oct 09, 2020 at 20:49:03 +0530, Meenakshi Aggarwal wrote:
> Apply USB errata workarounds for LS1046A SoC and
> make SATA, USB and SEC snoopable.
>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Silicon/NXP/LS1046A/LS1046A.dsc.inc | 1 +
> Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf | 1 +
> Silicon/NXP/LS1046A/Include/Soc.h | 2 +
> Silicon/NXP/LS1046A/Library/SocLib/SocLib.c | 65 +++++++++++++++++++++++++++
> 4 files changed, 69 insertions(+)
>
> diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
> index db110553605f..4e1d6a7ae7a2 100644
> --- a/Silicon/NXP/LS1046A/LS1046A.dsc.inc
> +++ b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
> @@ -34,6 +34,7 @@ [PcdsFixedAtBuild.common]
>
> [PcdsFeatureFlag]
> gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
> + gNxpQoriqLsTokenSpaceGuid.PcdScfgBigEndian|TRUE
> gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerBigEndian|TRUE
>
> ################################################################################
> diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
> index 01ed0f6592d2..36c09778b134 100644
> --- a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
> +++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
> @@ -14,6 +14,7 @@ [Defines]
> LIBRARY_CLASS = SocLib
>
> [Packages]
> + ArmPkg/ArmPkg.dec
> MdePkg/MdePkg.dec
> Silicon/NXP/Chassis2/Chassis2.dec
> Silicon/NXP/LS1046A/LS1046A.dec
> diff --git a/Silicon/NXP/LS1046A/Include/Soc.h b/Silicon/NXP/LS1046A/Include/Soc.h
> index 84f433d5cb94..e1d97e531263 100644
> --- a/Silicon/NXP/LS1046A/Include/Soc.h
> +++ b/Silicon/NXP/LS1046A/Include/Soc.h
> @@ -25,6 +25,7 @@
> #define LS1046A_QSPI0_SIZE (SIZE_512MB)
>
> #define LS1046A_DCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS
> +#define LS1046A_SCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS2_SCFG_ADDRESS
>
> /**
> Reset Control Word (RCW) Bits
> @@ -59,5 +60,6 @@ Bit(s) | Field Name | Description | Notes/comments
> #define SYS_PLL_RAT(x) (((x) >> 25) & 0x1f) // Bits 2-6
>
> typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG LS1046A_DEVICE_CONFIG;
> +typedef NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG LS1046A_SUPPLEMENTAL_CONFIG;
>
> #endif // SOC_H__
> diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
> index 3b15aee6ecae..7726faf748cb 100644
> --- a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
> +++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
> @@ -11,6 +11,7 @@
> #include <Library/ChassisLib.h>
> #include <Library/DebugLib.h>
> #include <Library/SocLib.h>
> +
Please take the time to look through the generated patches before
sending. I will delete this spurious blank line addition when pushing,
but it shouldn't have been there in the first place.
/
Leif
> #include <Soc.h>
>
> /**
> @@ -65,6 +66,47 @@ SocGetClock (
> }
>
> /**
> + Function to select pins depending upon pcd using supplemental
> + configuration unit(SCFG) extended RCW controlled pinmux control
> + register which contains the bits to provide pin multiplexing control.
> + This register is reset on HRESET.
> + **/
> +STATIC
> +VOID
> +ConfigScfgMux (VOID)
> +{
> + LS1046A_SUPPLEMENTAL_CONFIG *Scfg;
> + UINT32 UsbPwrFault;
> +
> + Scfg = (LS1046A_SUPPLEMENTAL_CONFIG *)LS1046A_SCFG_ADDRESS;
> + // Configures functionality of the IIC3_SCL to USB2_DRVVBUS
> + // Configures functionality of the IIC3_SDA to USB2_PWRFAULT
> + // USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA
> + ScfgWrite32 ((UINTN)&Scfg->RcwPMuxCr0, SCFG_RCWPMUXCRO_NOT_SELCR_USB);
> +
> + ScfgWrite32 ((UINTN)&Scfg->UsbDrvVBusSelCr, SCFG_USBDRVVBUS_SELCR_USB1);
> + UsbPwrFault = (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
> + (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
> + (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
> + ScfgWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault);
> + ScfgWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault);
> +}
> +
> +STATIC
> +VOID
> +ApplyErrata (
> + VOID
> + )
> +{
> + ErratumA008997 ();
> + ErratumA009007 ();
> + ErratumA009008 ();
> + ErratumA009798 ();
> +}
> +
> +
> +
> +/**
> Function to initialize SoC specific constructs
> **/
> VOID
> @@ -72,7 +114,30 @@ SocInit (
> VOID
> )
> {
> + LS1046A_SUPPLEMENTAL_CONFIG *Scfg;
> +
> + Scfg = (LS1046A_SUPPLEMENTAL_CONFIG *)LS1046A_SCFG_ADDRESS;
> +
> + /* Make SEC, SATA and USB reads and writes snoopable */
> + ScfgOr32((UINTN)&Scfg->SnpCnfgCr, SCFG_SNPCNFGCR_SECRDSNP |
> + SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
> + SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
> + SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
> + SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
> + SCFG_SNPCNFGCR_SATAWRSNP);
> +
> + ApplyErrata ();
> ChassisInit ();
>
> + //
> + // Due to the extensive functionality present on the chip and the limited number of external
> + // signals available, several functional blocks share signal resources through multiplexing.
> + // In this case when there is alternate functionality between multiple functional blocks,
> + // the signal's function is determined at the chip level (rather than at the block level)
> + // typically by a reset configuration word (RCW) option. Some of the signals' function are
> + // determined externel to RCW at Power-on Reset Sequence.
> + //
> + ConfigScfgMux ();
> +
> return;
> }
> --
> 1.9.1
>
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Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
---
Silicon/NXP/LS1046A/LS1046A.dsc.inc | 3 +++
Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc | 2 ++
Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf | 13 +++++++++++++
3 files changed, 18 insertions(+)
mode change 100644 => 100755 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
mode change 100644 => 100755 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
index 4e1d6a7ae7a2..7004533ed5f1 100644
--- a/Silicon/NXP/LS1046A/LS1046A.dsc.inc
+++ b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
@@ -31,6 +31,9 @@ [PcdsFixedAtBuild.common]
gNxpQoriqLsTokenSpaceGuid.PcdGpioModuleBaseAddress|0x02300000
gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerOffset|0x10000
+ gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr|0x2F00000
+ gNxpQoriqLsTokenSpaceGuid.PcdUsbSize|0x100000
+ gNxpQoriqLsTokenSpaceGuid.PcdNumUsbController|3
[PcdsFeatureFlag]
gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
old mode 100644
new mode 100755
index 3f29dadd5d1d..266fdbd2b4d3
--- a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
@@ -43,4 +43,6 @@ [Components.common]
gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE
}
+ Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf
+
##
diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
old mode 100644
new mode 100755
index 24af547729c7..34c4e5a02516
--- a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
@@ -120,6 +120,19 @@ [FV.FvMain]
INF FatPkg/EnhancedFatDxe/Fat.inf
INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+ INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+
+ #
+ # USB Support
+ #
+ INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+ INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+ INF Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf
+
#
# UEFI application (Shell Embedded Boot Loader)
#
--
1.9.1
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