From nobody Fri Apr 19 10:25:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+65266+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+65266+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=oss.nxp.com ARC-Seal: i=1; a=rsa-sha256; t=1600167043; cv=none; d=zohomail.com; s=zohoarc; b=EAmurI6HY2ZgOC4I/0nQiRj5O9kSvV2N012ECxmnjJ0bUS8/5uy4mrW6tD7tchIE0/QwW36G5SYNhtlDyieWvJzvmSjUy5UA8lzpltH9UOQBH1stW+sv3TCMap0Q1uJaxn/s7jPHp4nnYDTr7Z9fTW/b7zRRLJ5Y4GdW7P3p7DA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1600167043; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=DCYyyRnYIBaQMfYJvrC+a4IawxgY1e2vbRQSsu00myc=; b=F37bEx2fMA2FzYhVxqCcqTiOXRrn/ibAaAOxsMJa6Czj6RDbrtSsHTYHKfwOncqkqQbuovLimJs+x17+1udF9x1iQmds5L4tDWR5ZaUZydLVQg9vC1Lc2cqL56ZKhIRCt69lFvOzdbBLk3PJQr2n97/yHgeiaE1xaH5nk4ZXfL8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+65266+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1600167043468485.41356109730737; Tue, 15 Sep 2020 03:50:43 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id zClrYY1788612xZhBawGAD3w; Tue, 15 Sep 2020 03:50:43 -0700 X-Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by mx.groups.io with SMTP id smtpd.web12.10730.1600166866226521850 for ; Tue, 15 Sep 2020 03:47:46 -0700 X-Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id C48CD1A08A1; Tue, 15 Sep 2020 12:47:44 +0200 (CEST) X-Received: from inv0113.in-blr01.nxp.com (inv0113.in-blr01.nxp.com [165.114.116.118]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 6A9E41A0886; Tue, 15 Sep 2020 12:47:44 +0200 (CEST) X-Received: from uefi-OptiPlex-790.ap.freescale.net (unknown [10.232.132.78]) by inv0113.in-blr01.nxp.com (Postfix) with ESMTP id 2BE1E344; Tue, 15 Sep 2020 16:17:43 +0530 (IST) From: Meenakshi Aggarwal To: ard.biesheuvel@arm.com, leif@nuviainc.com, michael.d.kinney@intel.com, devel@edk2.groups.io Cc: v.sethi@nxp.com, Meenakshi Aggarwal , Pramod Kumar , Meenakshi Aggarwal Subject: [edk2-devel] [edk2-platforms 1/4] Silicon/NXP: Add GPIO driver support. Date: Tue, 15 Sep 2020 21:59:00 +0530 Message-Id: <1600187343-18732-2-git-send-email-meenakshi.aggarwal@oss.nxp.com> In-Reply-To: <1600187343-18732-1-git-send-email-meenakshi.aggarwal@oss.nxp.com> References: <1600187343-18732-1-git-send-email-meenakshi.aggarwal@oss.nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,meenakshi.aggarwal@oss.nxp.com X-Gm-Message-State: wTT4FnltqLzEa52D7ubu6aiIx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1600167043; bh=9RpipVenTTC1bvzy/EVTyPRy3Ht269XXPibEWsLjEjI=; h=Cc:Date:From:Reply-To:Subject:To; b=s1JIliOx82EnMbX/xOmOJfnWnQ/IL1CLUhk1jfnAGiF9zC9/Vz+j/zSwboNYUhA79BC 0jyVvApZGakAifuthS+2SeEzcOM9/NXnaJFHG5r0Wus2YVgEGCREP+KEpyQT5Sr04V0kC 4h8ENf8oIQyMLsoZc0xZ2yVkqMeghAUzFDE= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Pramod Kumar Signed-off-by: Meenakshi Aggarwal --- Silicon/NXP/Library/GpioLib/GpioLib.inf | 39 +++++ Silicon/NXP/Include/Library/GpioLib.h | 110 +++++++++++++++ Silicon/NXP/Library/GpioLib/GpioLib.c | 242 ++++++++++++++++++++++++++++= ++++ 3 files changed, 391 insertions(+) create mode 100644 Silicon/NXP/Library/GpioLib/GpioLib.inf create mode 100644 Silicon/NXP/Include/Library/GpioLib.h create mode 100644 Silicon/NXP/Library/GpioLib/GpioLib.c diff --git a/Silicon/NXP/Library/GpioLib/GpioLib.inf b/Silicon/NXP/Library/= GpioLib/GpioLib.inf new file mode 100644 index 000000000000..7878d1d03db2 --- /dev/null +++ b/Silicon/NXP/Library/GpioLib/GpioLib.inf @@ -0,0 +1,39 @@ +/** @file + + Copyright 2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D GpioLib + FILE_GUID =3D addec2b8-d2e0-43c0-a277-41a8d42f3f4f + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D GpioLib + +[Sources.common] + GpioLib.c + +[LibraryClasses] + ArmLib + BaseMemoryLib + BaseLib + IoAccessLib + IoLib + +[Packages] + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/NXP/NxpQoriqLs.dec + +[Pcd] + gNxpQoriqLsTokenSpaceGuid.PcdNumGpioController + gNxpQoriqLsTokenSpaceGuid.PcdGpioModuleBaseAddress + gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerOffset + +[FeaturePcd] + gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerBigEndian diff --git a/Silicon/NXP/Include/Library/GpioLib.h b/Silicon/NXP/Include/Li= brary/GpioLib.h new file mode 100644 index 000000000000..5821806226ee --- /dev/null +++ b/Silicon/NXP/Include/Library/GpioLib.h @@ -0,0 +1,110 @@ +/** @file + + Copyright 2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef GPIO_H__ +#define GPIO_H__ + +#include + +/* enum for GPIO number */ +typedef enum _GPIO_BLOCK { + GPIO1, + GPIO2, + GPIO3, + GPIO4, + GPIO_MAX +} GPIO_BLOCK; + +/* enum for GPIO direction */ +typedef enum _GPIO_DIRECTION { + INPUT, + OUTPUT +} GPIO_DIRECTION; + +/* enum for GPIO state */ +typedef enum _GPIO_STATE { + LOW, + HIGH +} GPIO_VAL; + +/** + SetDir Set GPIO direction as INPUT or OUTPUT + + @param[in] Id GPIO controller number + @param[in] Bit GPIO number + @param[in] Dir GPIO Direction as INPUT or OUTPUT + + @retval EFI_SUCCESS + **/ +EFI_STATUS +SetDir ( + IN UINT8 Id, + IN UINT32 Bit, + IN BOOLEAN Dir + ); + +/** + GetDir Retrieve GPIO direction + + @param[in] Id GPIO controller number + @param[in] Bit GPIO number + + @retval GPIO Direction as INPUT or OUTPUT + **/ +UINT32 +GetDir ( + IN UINT8 Id, + IN UINT32 Bit + ); + + /** + GetData Retrieve GPIO Value + + @param[in] Id GPIO controller number + @param[in] Bit GPIO number + + @retval GPIO value as HIGH or LOW + **/ +UINT32 +GetData ( + IN UINT8 Id, + IN UINT32 Bit + ); + +/** + SetData Set GPIO data Value + + @param[in] Id GPIO controller number + @param[in] Bit GPIO number + @param[in] Data GPIO data value to set + + @retval GPIO value as HIGH or LOW + **/ +EFI_STATUS +SetData ( + IN UINT8 Id, + IN UINT32 Bit, + IN BOOLEAN Data + ); + +/** + SetOpenDrain Set GPIO as Open drain + + @param[in] Id GPIO controller number + @param[in] Bit GPIO number + @param[in] OpenDrain Set as open drain + + @retval EFI_SUCCESS + **/ +EFI_STATUS +SetOpenDrain ( + IN UINT8 Id, + IN UINT32 Bit, + IN BOOLEAN OpenDrain + ); + +#endif diff --git a/Silicon/NXP/Library/GpioLib/GpioLib.c b/Silicon/NXP/Library/Gp= ioLib/GpioLib.c new file mode 100644 index 000000000000..33cc45c2152b --- /dev/null +++ b/Silicon/NXP/Library/GpioLib/GpioLib.c @@ -0,0 +1,242 @@ +/** @file + + Copyright 2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include + +STATIC MMIO_OPERATIONS *mGpioOps; + +/* Structure for GPIO Regsters */ +typedef struct GpioRegs { + UINT32 GpDir; + UINT32 GpOdr; + UINT32 GpData; + UINT32 GpIer; + UINT32 GpImr; + UINT32 GpIcr; +} GPIO_REGS; + +/** + GetBaseAddr GPIO controller Base Address + + @param[in] Id GPIO controller number + + @retval GPIO controller Base Address, if found + @retval NULL, if not a valid controller number + + **/ +STATIC +VOID * +GetBaseAddr ( + IN UINT8 Id + ) +{ + + UINTN GpioBaseAddr; + UINTN MaxGpioController; + + mGpioOps =3D GetMmioOperations (FeaturePcdGet (PcdGpioControllerBigEndia= n)); + + MaxGpioController =3D PcdGet32 (PcdNumGpioController); + + if (Id < MaxGpioController) { + GpioBaseAddr =3D PcdGet64 (PcdGpioModuleBaseAddress) + + (Id * PcdGet64 (PcdGpioControllerOffset)); + return (VOID *) GpioBaseAddr; + } + else { + DEBUG((DEBUG_ERROR, "Invalid Gpio Controller Id %d, Allowed Ids are %d= -%d", + Id, GPIO1, MaxGpioController)); + return NULL; + } +} + +/** + GetBitMask: Return Bit Mask + + @param[in] Bit Bit to create bitmask + @retval Bitmask + + **/ + +STATIC +UINT32 +GetBitMask ( + IN UINT32 Bit + ) +{ + + if (!FeaturePcdGet (PcdGpioControllerBigEndian)) { + return (1 << Bit); + } else { + return (1 << (31 - Bit)); + } +} + + +/** + SetDir Set GPIO direction as INPUT or OUTPUT + + @param[in] Id GPIO controller number + @param[in] Bit GPIO number + @param[in] Dir GPIO Direction as INPUT or OUTPUT + + @retval EFI_SUCCESS + **/ +EFI_STATUS +SetDir ( + IN UINT8 Id, + IN UINT32 Bit, + IN BOOLEAN Dir + ) +{ + GPIO_REGS *Regs; + UINT32 BitMask; + UINT32 Value; + + Regs =3D GetBaseAddr(Id); + BitMask =3D GetBitMask(Bit); + + Value =3D mGpioOps->Read32 ((UINTN)&Regs->GpDir); + + if (Dir) { + mGpioOps->Write32 ((UINTN)&Regs->GpDir, (Value | BitMask)); + } + else { + mGpioOps->Write32 ((UINTN)&Regs->GpDir, (Value & (~BitMask))); + } + + return EFI_SUCCESS; +} + +/** + GetDir Retrieve GPIO direction + + @param[in] Id GPIO controller number + @param[in] Bit GPIO number + + @retval GPIO Direction as INPUT or OUTPUT + **/ +UINT32 +GetDir ( + IN UINT8 Id, + IN UINT32 Bit + ) +{ + GPIO_REGS *Regs; + UINT32 Value; + UINT32 BitMask; + + Regs =3D GetBaseAddr (Id); + BitMask =3D GetBitMask(Bit); + + Value =3D mGpioOps->Read32 ((UINTN)&Regs->GpDir); + + return (Value & BitMask); +} + +/** + GetData Retrieve GPIO Value + + @param[in] Id GPIO controller number + @param[in] Bit GPIO number + + @retval GPIO value as HIGH or LOW + **/ +UINT32 +GetData ( + IN UINT8 Id, + IN UINT32 Bit + ) +{ + GPIO_REGS *Regs; + UINT32 Value; + UINT32 BitMask; + + Regs =3D (VOID *)GetBaseAddr (Id); + BitMask =3D GetBitMask(Bit); + + + Value =3D mGpioOps->Read32 ((UINTN)&Regs->GpData); + + if (Value & BitMask) { + return 1; + } else { + return 0; + } +} + +/** + SetData Set GPIO data Value + + @param[in] Id GPIO controller number + @param[in] Bit GPIO number + @param[in] Data GPIO data value to set + + @retval GPIO value as HIGH or LOW + **/ +EFI_STATUS +SetData ( + IN UINT8 Id, + IN UINT32 Bit, + IN BOOLEAN Data + ) +{ + GPIO_REGS *Regs; + UINT32 BitMask; + UINT32 Value; + + Regs =3D GetBaseAddr (Id); + BitMask =3D GetBitMask(Bit); + + Value =3D mGpioOps->Read32 ((UINTN)&Regs->GpData); + + if (Data) { + mGpioOps->Write32 ((UINTN)&Regs->GpData, (Value | BitMask)); + } else { + mGpioOps->Write32 ((UINTN)&Regs->GpData, (Value & (~BitMask))); + } + + return EFI_SUCCESS; +} + +/** + SetOpenDrain Set GPIO as Open drain + + @param[in] Id GPIO controller number + @param[in] Bit GPIO number + @param[in] OpenDrain Set as open drain + + @retval EFI_SUCCESS + **/ +EFI_STATUS +SetOpenDrain ( + IN UINT8 Id, + IN UINT32 Bit, + IN BOOLEAN OpenDrain + ) +{ + GPIO_REGS *Regs; + UINT32 BitMask; + UINT32 Value; + + Regs =3D GetBaseAddr (Id); + BitMask =3D GetBitMask(Bit); + + Value =3D mGpioOps->Read32 ((UINTN)&Regs->GpOdr); + if (OpenDrain) { + mGpioOps->Write32 ((UINTN)&Regs->GpOdr, (Value | BitMask)); + } + else { + mGpioOps->Write32 ((UINTN)&Regs->GpOdr, (Value & (~BitMask))); + } + + return EFI_SUCCESS; +} --=20 1.9.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,meenakshi.aggarwal@oss.nxp.com X-Gm-Message-State: 9MrOJqlNlRcV0HOiRQEf3D8Ax1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1600167044; bh=B4mZqGtF0Z30DASaSLBeH68M2TE20WUBxJ+qMyt6kyo=; h=Cc:Date:From:Reply-To:Subject:To; b=hRfT4ooUjoXxtjrGIAs6iIfJ7lO4Y+Ddh9R7wNN6j10Nso96ATkENnhOUBfp4pItie2 eo9kZewIOonpaIfsUgikeCJCiwA7L54cqee/KTiGdulQqViOX9XT0DaM8iHCgyXOI/Fil UctjOUkRaZxupHqLfd0SvQqvzG5LW+lmqTE= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Pramod Kumar Signed-off-by: Meenakshi Aggarwal --- Silicon/NXP/NxpQoriqLs.dec | 8 ++++++++ Silicon/NXP/LS1046A/LS1046A.dsc.inc | 5 +++++ Silicon/NXP/NxpQoriqLs.dsc.inc | 2 ++ .../Library/ArmPlatformLib/ArmPlatformLib.inf | 1 + .../Library/ArmPlatformLib/ArmPlatformLib.c | 17 +++++++++++++= ++++ 5 files changed, 33 insertions(+) diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec index 0c3608696569..3a568c0437e7 100644 --- a/Silicon/NXP/NxpQoriqLs.dec +++ b/Silicon/NXP/NxpQoriqLs.dec @@ -29,6 +29,7 @@ [PcdsFeatureFlag] gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|FALSE|BOOLEAN|0x00000316 gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x00000317 gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA009185|FALSE|BOOLEAN|0x00000318 + gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerBigEndian|FALSE|BOOLEAN|0x000= 00319 =20 [PcdsFixedAtBuild.common] # Pcds for PCI Express @@ -48,6 +49,13 @@ [PcdsFixedAtBuild.common] gNxpQoriqLsTokenSpaceGuid.PcdSataSize|0x0|UINT32|0x00000351 gNxpQoriqLsTokenSpaceGuid.PcdNumSataController|0x0|UINT32|0x00000352 =20 + # + # Pcds for Gpio + # + gNxpQoriqLsTokenSpaceGuid.PcdNumGpioController|0|UINT32|0x00000355 + gNxpQoriqLsTokenSpaceGuid.PcdGpioModuleBaseAddress|0|UINT64|0x00000356 + gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerOffset|0|UINT64|0x00000357 + [PcdsDynamic.common] gNxpQoriqLsTokenSpaceGuid.PcdPciCfgShiftEnable|FALSE|BOOLEAN|0x00000600 gNxpQoriqLsTokenSpaceGuid.PcdPciLsGen4Ctrl|FALSE|BOOLEAN|0x00000601 diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc b/Silicon/NXP/LS1046A/LS10= 46A.dsc.inc index dbe7f408fce9..db110553605f 100644 --- a/Silicon/NXP/LS1046A/LS1046A.dsc.inc +++ b/Silicon/NXP/LS1046A/LS1046A.dsc.inc @@ -27,9 +27,14 @@ [PcdsDynamicDefault.common] =20 [PcdsFixedAtBuild.common] gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500 + gNxpQoriqLsTokenSpaceGuid.PcdNumGpioController|0x04 + gNxpQoriqLsTokenSpaceGuid.PcdGpioModuleBaseAddress|0x02300000 + gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerOffset|0x10000 + =20 [PcdsFeatureFlag] gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE + gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerBigEndian|TRUE =20 ##########################################################################= ###### # diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc index fc600de01d74..21c87df73220 100644 --- a/Silicon/NXP/NxpQoriqLs.dsc.inc +++ b/Silicon/NXP/NxpQoriqLs.dsc.inc @@ -103,6 +103,8 @@ [LibraryClasses.common] MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.i= nf UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf =20 + GpioLib|Silicon/NXP/Library/GpioLib/GpioLib.inf + [LibraryClasses.common.SEC] PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf DebugAgentLib|ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsB= aseLib.inf diff --git a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatform= Lib.inf b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib= .inf index 7802696bf39b..2e755842a714 100644 --- a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf +++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf @@ -25,6 +25,7 @@ [Packages] [LibraryClasses] ArmLib DebugLib + GpioLib SocLib =20 [Sources.common] diff --git a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatform= Lib.c b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c index e1f20da09337..d467992a3e47 100644 --- a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c +++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c @@ -8,11 +8,14 @@ =20 #include #include +#include #include =20 #include #include =20 +#define USB2_MUX_SEL_GPIO 23 + ARM_CORE_INFO mLS1046aMpCoreInfoTable[] =3D { { // Cluster 0, Core 0 @@ -89,6 +92,19 @@ NxpPlatformGetClock( } =20 /** + FRWY-LS1046A GPIO 23 use for USB2 + mux seclection +**/ +STATIC VOID MuxSelectUsb2 (VOID) +{ + + SetDir (GPIO3, USB2_MUX_SEL_GPIO, OUTPUT); + SetData (GPIO3, USB2_MUX_SEL_GPIO, HIGH); + + return; +} + +/** Initialize controllers that must setup in the normal world =20 This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/Pl= atformPei @@ -101,6 +117,7 @@ ArmPlatformInitialize ( ) { SocInit (); + MuxSelectUsb2 (); =20 return EFI_SUCCESS; } --=20 1.9.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Tue, 15 Sep 2020 03:47:48 -0700 X-Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 2E68A1A0899; Tue, 15 Sep 2020 12:47:46 +0200 (CEST) X-Received: from inv0113.in-blr01.nxp.com (inv0113.in-blr01.nxp.com [165.114.116.118]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 59F971A0886; Tue, 15 Sep 2020 12:47:45 +0200 (CEST) X-Received: from uefi-OptiPlex-790.ap.freescale.net (unknown [10.232.132.78]) by inv0113.in-blr01.nxp.com (Postfix) with ESMTP id 311A2342; Tue, 15 Sep 2020 16:17:44 +0530 (IST) From: Meenakshi Aggarwal To: ard.biesheuvel@arm.com, leif@nuviainc.com, michael.d.kinney@intel.com, devel@edk2.groups.io Cc: v.sethi@nxp.com, Meenakshi Aggarwal , Meenakshi Aggarwal Subject: [edk2-devel] [edk2-platforms 3/4] Silicon/NXP: Implement USB Errata Date: Tue, 15 Sep 2020 21:59:02 +0530 Message-Id: <1600187343-18732-4-git-send-email-meenakshi.aggarwal@oss.nxp.com> In-Reply-To: <1600187343-18732-1-git-send-email-meenakshi.aggarwal@oss.nxp.com> References: <1600187343-18732-1-git-send-email-meenakshi.aggarwal@oss.nxp.com> MIME-Version: 1.0 X-Virus-Scanned: ClamAV using ClamSMTP Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,meenakshi.aggarwal@oss.nxp.com X-Gm-Message-State: qSdn1rR0DjixnNMLTokfafeJx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1600167046; bh=oGyRTWcFHqqiarJWETkxQ1sZkaY4qiXhOBWE1lfQq5s=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=dVXEN5W2djEXhGzzOF+gaqxXja2++r9FJeGd+HGtrqFANTrZ0qCxPXFDXCZHE2/YziJ A7MGK2kYXBOgGwMaQn/seBNxEPCouXdXFWEM5G9s+ufz2oH8ceLtHUEcMCiM2dXSB1t97 PACcyNhH8bKhnwIh61+hxrkqG9C6+w5+c6c= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Implement USB errata A009008, A009798, A008997, A009007 Make USB,SEC and SATA snoopable Signed-off-by: Meenakshi Aggarwal --- Silicon/NXP/NxpQoriqLs.dec | 1 + Silicon/NXP/LS1046A/LS1046A.dsc.inc | 1 + .../NXP/Chassis2/Library/ChassisLib/ChassisLib.inf | 2 + Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf | 2 + Silicon/NXP/Chassis2/Include/Chassis.h | 112 +++++++++++++++ Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h | 23 +++ Silicon/NXP/Include/Library/ChassisLib.h | 62 ++++++++ Silicon/NXP/LS1046A/Include/Soc.h | 2 + .../NXP/Chassis2/Library/ChassisLib/ChassisLib.c | 63 ++++++++ Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c | 159 +++++++++++++++++= ++++ Silicon/NXP/LS1046A/Library/SocLib/SocLib.c | 66 +++++++++ 11 files changed, 493 insertions(+) create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec index 3a568c0437e7..90dce69fd472 100644 --- a/Silicon/NXP/NxpQoriqLs.dec +++ b/Silicon/NXP/NxpQoriqLs.dec @@ -30,6 +30,7 @@ [PcdsFeatureFlag] gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x00000317 gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA009185|FALSE|BOOLEAN|0x00000318 gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerBigEndian|FALSE|BOOLEAN|0x000= 00319 + gNxpQoriqLsTokenSpaceGuid.PcdScfgBigEndian|FALSE|BOOLEAN|0x00000320 =20 [PcdsFixedAtBuild.common] # Pcds for PCI Express diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc b/Silicon/NXP/LS1046A/LS10= 46A.dsc.inc index db110553605f..4e1d6a7ae7a2 100644 --- a/Silicon/NXP/LS1046A/LS1046A.dsc.inc +++ b/Silicon/NXP/LS1046A/LS1046A.dsc.inc @@ -34,6 +34,7 @@ [PcdsFixedAtBuild.common] =20 [PcdsFeatureFlag] gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE + gNxpQoriqLsTokenSpaceGuid.PcdScfgBigEndian|TRUE gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerBigEndian|TRUE =20 ##########################################################################= ###### diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf b/Silic= on/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf index f5dbd1349dc5..d64286b199c6 100644 --- a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf +++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf @@ -28,6 +28,8 @@ [LibraryClasses] =20 [Sources.common] ChassisLib.c + Erratum.c =20 [FeaturePcd] gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian + gNxpQoriqLsTokenSpaceGuid.PcdScfgBigEndian diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf b/Silicon/NXP/LS= 1046A/Library/SocLib/SocLib.inf index 01ed0f6592d2..e2336bb18f29 100644 --- a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf +++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf @@ -14,6 +14,7 @@ [Defines] LIBRARY_CLASS =3D SocLib =20 [Packages] + ArmPkg/ArmPkg.dec MdePkg/MdePkg.dec Silicon/NXP/Chassis2/Chassis2.dec Silicon/NXP/LS1046A/LS1046A.dec @@ -25,3 +26,4 @@ [LibraryClasses] =20 [Sources.common] SocLib.c + diff --git a/Silicon/NXP/Chassis2/Include/Chassis.h b/Silicon/NXP/Chassis2/= Include/Chassis.h index 7e8bf224884b..f8fa7ed67596 100644 --- a/Silicon/NXP/Chassis2/Include/Chassis.h +++ b/Silicon/NXP/Chassis2/Include/Chassis.h @@ -11,6 +11,7 @@ #include =20 #define NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS 0x1EE0000 +#define NXP_LAYERSCAPE_CHASSIS2_SCFG_ADDRESS 0x1570000 =20 #define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFE) #define SVR_MAJOR(svr) (((svr) >> 4) & 0xf) @@ -26,6 +27,10 @@ #define SCR0_CLIENTPD_MASK 0x00000001 #define SACR_PAGESIZE_MASK 0x00010000 =20 +#define USB_PHY1_BASE_ADDRESS 0x084F0000 +#define USB_PHY2_BASE_ADDRESS 0x08500000 +#define USB_PHY3_BASE_ADDRESS 0x08510000 + /** The Device Configuration Unit provides general purpose configuration and status for the device. These registers only support 32-bit accesses. @@ -45,4 +50,111 @@ typedef struct { } NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG; #pragma pack() =20 +/* Supplemental Configuration Unit (SCFG) */ +typedef struct { + UINT8 Res000[0x070-0x000]; + UINT32 Usb1Prm1Cr; + UINT32 Usb1Prm2Cr; + UINT32 Usb1Prm3Cr; + UINT32 Usb2Prm1Cr; + UINT32 Usb2Prm2Cr; + UINT32 Usb2Prm3Cr; + UINT32 Usb3Prm1Cr; + UINT32 Usb3Prm2Cr; + UINT32 Usb3Prm3Cr; + UINT8 Res094[0x100-0x094]; + UINT32 Usb2Icid; + UINT32 Usb3Icid; + UINT8 Res108[0x114-0x108]; + UINT32 DmaIcid; + UINT32 SataIcid; + UINT32 Usb1Icid; + UINT32 QeIcid; + UINT32 SdhcIcid; + UINT32 EdmaIcid; + UINT32 EtrIcid; + UINT32 Core0SftRst; + UINT32 Core1SftRst; + UINT32 Core2SftRst; + UINT32 Core3SftRst; + UINT8 Res140[0x158-0x140]; + UINT32 AltCBar; + UINT32 QspiCfg; + UINT8 Res160[0x180-0x160]; + UINT32 DmaMcr; + UINT8 Res184[0x188-0x184]; + UINT32 GicAlign; + UINT32 DebugIcid; + UINT8 Res190[0x1a4-0x190]; + UINT32 SnpCnfgCr; +#define SCFG_SNPCNFGCR_SECRDSNP BIT31 +#define SCFG_SNPCNFGCR_SECWRSNP BIT30 +#define SCFG_SNPCNFGCR_SATARDSNP BIT23 +#define SCFG_SNPCNFGCR_SATAWRSNP BIT22 +#define SCFG_SNPCNFGCR_USB1RDSNP BIT21 +#define SCFG_SNPCNFGCR_USB1WRSNP BIT20 +#define SCFG_SNPCNFGCR_USB2RDSNP BIT15 +#define SCFG_SNPCNFGCR_USB2WRSNP BIT16 +#define SCFG_SNPCNFGCR_USB3RDSNP BIT13 +#define SCFG_SNPCNFGCR_USB3WRSNP BIT14 + UINT8 Res1a8[0x1ac-0x1a8]; + UINT32 IntpCr; + UINT8 Res1b0[0x204-0x1b0]; + UINT32 CoreSrEnCr; + UINT8 Res208[0x220-0x208]; + UINT32 RvBar00; + UINT32 RvBar01; + UINT32 RvBar10; + UINT32 RvBar11; + UINT32 RvBar20; + UINT32 RvBar21; + UINT32 RvBar30; + UINT32 RvBar31; + UINT32 LpmCsr; + UINT8 Res244[0x400-0x244]; + UINT32 QspIdQScr; + UINT32 EcgTxcMcr; + UINT32 SdhcIoVSelCr; + UINT32 RcwPMuxCr0; + /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS + Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT + Setting RCW PinMux Register bits 25-27 to select USB3_DRVVBUS + Setting RCW PinMux Register bits 29-31 to select USB3_DRVVBUS + **/ +#define SCFG_RCWPMUXCRO_SELCR_USB 0x3333 + /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS + Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT + Setting RCW PinMux Register bits 25-27 to select IIC4_SCL + Setting RCW PinMux Register bits 29-31 to select IIC4_SDA + **/ +#define SCFG_RCWPMUXCRO_NOT_SELCR_USB 0x3300 + UINT32 UsbDrvVBusSelCr; +#define SCFG_USBDRVVBUS_SELCR_USB1 0x00000000 +#define SCFG_USBDRVVBUS_SELCR_USB2 0x00000001 +#define SCFG_USBDRVVBUS_SELCR_USB3 0x00000003 + UINT32 UsbPwrFaultSelCr; +#define SCFG_USBPWRFAULT_INACTIVE 0x00000000 +#define SCFG_USBPWRFAULT_SHARED 0x00000001 +#define SCFG_USBPWRFAULT_DEDICATED 0x00000002 +#define SCFG_USBPWRFAULT_USB3_SHIFT 4 +#define SCFG_USBPWRFAULT_USB2_SHIFT 2 +#define SCFG_USBPWRFAULT_USB1_SHIFT 0 + UINT32 UsbRefclkSelcr1; + UINT32 UsbRefclkSelcr2; + UINT32 UsbRefclkSelcr3; + UINT8 Res424[0x600-0x424]; + UINT32 ScratchRw[4]; + UINT8 Res610[0x680-0x610]; + UINT32 CoreBCr; + UINT8 Res684[0x1000-0x684]; + UINT32 Pex1MsiIr; + UINT32 Pex1MsiR; + UINT8 Res1008[0x2000-0x1008]; + UINT32 Pex2; + UINT32 Pex2MsiR; + UINT8 Res2008[0x3000-0x2008]; + UINT32 Pex3MsiIr; + UINT32 Pex3MsiR; +} NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG; + #endif // CHASSIS_H__ diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h b/Silicon/NX= P/Chassis2/Library/ChassisLib/Erratum.h new file mode 100644 index 000000000000..0231ef0a283d --- /dev/null +++ b/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h @@ -0,0 +1,23 @@ +/** @file +* Header defining the Base addresses, sizes, flags etc for Erratas +* +* Copyright 2020 NXP +* + SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#ifndef ERRATUM_H__ +#define ERRATUM_H__ + +#define USB_TXVREFTUNE 0x9 +#define USB_SQRXTUNE 0xFC7FFFFF +#define USB_PCSTXSWINGFULL 0x47 +#define USB_PHY_RX_EQ_VAL_1 0x0000 +#define USB_PHY_RX_EQ_VAL_2 0x8000 +#define USB_PHY_RX_EQ_VAL_3 0x8003 +#define USB_PHY_RX_EQ_VAL_4 0x800b + +#define USB_PHY_RX_OVRD_IN_HI 0x200c + +#endif diff --git a/Silicon/NXP/Include/Library/ChassisLib.h b/Silicon/NXP/Include= /Library/ChassisLib.h index 89992a4b6fd5..c99368b4733d 100644 --- a/Silicon/NXP/Include/Library/ChassisLib.h +++ b/Silicon/NXP/Include/Library/ChassisLib.h @@ -13,6 +13,48 @@ #include =20 /** + Or Scfg register + + @param Address The MMIO register to read. + + @return The value read. +**/ +UINT32 +EFIAPI +ScfgOr32 ( + IN UINTN Address, + IN UINT32 Value + ); + +/** + Read Scfg register + + @param Address The MMIO register to read. + + @return The value read. +**/ +UINT32 +EFIAPI +ScfgRead32 ( + IN UINTN Address + ); + +/** + Write Scfg register + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + + @return Value. +**/ +UINT32 +EFIAPI +ScfgWrite32 ( + IN UINTN Address, + IN UINT32 Value + ); + +/** Read Dcfg register =20 @param Address The MMIO register to read. @@ -48,4 +90,24 @@ ChassisInit ( VOID ); =20 +VOID +ErratumA009008 ( + VOID + ); + +VOID +ErratumA009798 ( + VOID + ); + +VOID +ErratumA008997 ( + VOID + ); + +VOID +ErratumA009007 ( + VOID + ); + #endif // CHASSIS_LIB_H__ diff --git a/Silicon/NXP/LS1046A/Include/Soc.h b/Silicon/NXP/LS1046A/Includ= e/Soc.h index 84f433d5cb94..e1d97e531263 100644 --- a/Silicon/NXP/LS1046A/Include/Soc.h +++ b/Silicon/NXP/LS1046A/Include/Soc.h @@ -25,6 +25,7 @@ #define LS1046A_QSPI0_SIZE (SIZE_512MB) =20 #define LS1046A_DCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS +#define LS1046A_SCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS2_SCFG_ADDRESS =20 /** Reset Control Word (RCW) Bits @@ -59,5 +60,6 @@ Bit(s) | Field Name | Description | Not= es/comments #define SYS_PLL_RAT(x) (((x) >> 25) & 0x1f) // Bits 2-6 =20 typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG LS1046A_DEVICE_CONFIG; +typedef NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG LS1046A_SUPPLEMENTAL_C= ONFIG; =20 #endif // SOC_H__ diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c b/Silicon= /NXP/Chassis2/Library/ChassisLib/ChassisLib.c index 91b19f832f00..e6410a53f480 100644 --- a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c +++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c @@ -15,6 +15,69 @@ #include =20 /** + Or Scfg register + + @param Address The MMIO register to read. + + @return The value read. +**/ +UINT32 +EFIAPI +ScfgOr32 ( + IN UINTN Address, + IN UINT32 Value + ) +{ + MMIO_OPERATIONS *ScfgOps; + + ScfgOps =3D GetMmioOperations (FeaturePcdGet (PcdScfgBigEndian)); + + return ScfgOps->Or32 (Address, Value); +} + +/** + Read Scfg register + + @param Address The MMIO register to read. + + @return The value read. +**/ +UINT32 +EFIAPI +ScfgRead32 ( + IN UINTN Address + ) +{ + MMIO_OPERATIONS *ScfgOps; + + ScfgOps =3D GetMmioOperations (FeaturePcdGet (PcdScfgBigEndian)); + + return ScfgOps->Read32 (Address); +} + +/** + Write Scfg register + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + + @return Value. +**/ +UINT32 +EFIAPI +ScfgWrite32 ( + IN UINTN Address, + IN UINT32 Value + ) +{ + MMIO_OPERATIONS *ScfgOps; + + ScfgOps =3D GetMmioOperations (FeaturePcdGet (PcdScfgBigEndian)); + + return ScfgOps->Write32 (Address, Value); +} + +/** Read Dcfg register =20 @param Address The MMIO register to read. diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c b/Silicon/NX= P/Chassis2/Library/ChassisLib/Erratum.c new file mode 100644 index 000000000000..1806975ec8f5 --- /dev/null +++ b/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c @@ -0,0 +1,159 @@ +/** @file + This file containa all erratas need to be applied on different SoCs. + + Copyright 2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include + +#include "Erratum.h" + +/* +* A-009008: USB High Speed (HS) eye height adjustment +* Affects: USB +* Description: USB HS eye diagram fails with the default value at many cor= ners, particularly at a high +* temperature (105=C2=B0C). +* Impact: USB HS eye diagram may fail using the default value. +*/ +VOID +ErratumA009008 ( + VOID + ) +{ + NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *Scfg; + UINT32 Value; + + Scfg =3D (NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *)NXP_LAYERSCAPE_C= HASSIS2_SCFG_ADDRESS; + + Value =3D ScfgRead32 ((UINTN)&Scfg->Usb1Prm1Cr); + Value &=3D ~(0xF << 6); + ScfgWrite32 ((UINTN)&Scfg->Usb1Prm1Cr, Value|(USB_TXVREFTUNE << 6)); + Value =3D ScfgRead32 ((UINTN)&Scfg->Usb2Prm1Cr); + Value &=3D ~(0xF << 6); + ScfgWrite32 ((UINTN)&Scfg->Usb2Prm1Cr, Value|(USB_TXVREFTUNE << 6)); + Value =3D ScfgRead32 ((UINTN)&Scfg->Usb3Prm1Cr); + Value &=3D ~(0xF << 6); + ScfgWrite32 ((UINTN)&Scfg->Usb3Prm1Cr, Value|(USB_TXVREFTUNE << 6)); + + return; +} + +/* +* A-009798: USB high speed squelch threshold adjustment +* Affects: USB +* Description: The default setting for USB high speed squelch threshold re= sults in a threshold close to or +* lower than 100mV. This leads to a receiver compliance test failure for a= 100mV threshold. +* Impact: If the errata is not applied, only the USB high speed receiver s= ensitivity compliance test fails, +* however USB data continues to transfer. +*/ +VOID +ErratumA009798 ( + VOID + ) +{ + NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *Scfg; + UINT32 Value; + + Scfg =3D (NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *)NXP_LAYERSCAPE_C= HASSIS2_SCFG_ADDRESS; + + Value =3D ScfgRead32 ((UINTN)&Scfg->Usb1Prm1Cr); + ScfgWrite32 ((UINTN)&Scfg->Usb1Prm1Cr, Value & USB_SQRXTUNE); + Value =3D ScfgRead32 ((UINTN)&Scfg->Usb2Prm1Cr); + ScfgWrite32 ((UINTN)&Scfg->Usb2Prm1Cr, Value & USB_SQRXTUNE); + Value =3D ScfgRead32 ((UINTN)&Scfg->Usb3Prm1Cr); + ScfgWrite32 ((UINTN)&Scfg->Usb3Prm1Cr, Value & USB_SQRXTUNE); + + return; +} + +/* +* A-008997: USB3 LFPS peak-to-peak differential output voltage adjustment = settings +* Affects: USB +* Description: Low Frequency Periodic Signaling (LFPS) peak-to-peak differ= ential output voltage test +* compliance fails using default transmitter settings. Software is require= d to change the +* transmitter signal swings to pass compliance tests. +* Impact: LFPS peak-to-peak differential output voltage compliance test fa= ils. +*/ +VOID +ErratumA008997 ( + VOID + ) +{ + NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *Scfg; + UINT32 Value; + + Scfg =3D (NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *)NXP_LAYERSCAPE_C= HASSIS2_SCFG_ADDRESS; + + Value =3D ScfgRead32 ((UINTN)&Scfg->Usb1Prm2Cr); + Value &=3D ~(0x7F << 9); + ScfgWrite32 ((UINTN)&Scfg->Usb1Prm2Cr, Value | (USB_PCSTXSWINGFULL << 9)= ); + Value =3D ScfgRead32 ((UINTN)&Scfg->Usb2Prm2Cr); + Value &=3D ~(0x7F << 9); + ScfgWrite32 ((UINTN)&Scfg->Usb2Prm2Cr, Value | (USB_PCSTXSWINGFULL << 9)= ); + Value =3D ScfgRead32 ((UINTN)&Scfg->Usb3Prm2Cr); + Value &=3D ~(0x7F << 9); + ScfgWrite32 ((UINTN)&Scfg->Usb3Prm2Cr, Value | (USB_PCSTXSWINGFULL << 9)= ); + + return; +} + +/* +* A-009007: USB3PHY observing intermittent failure in receive compliance t= ests +* at higher jitter frequency using default register values +* +* Affects: USB +* +* Description: Receive compliance tests may fail intermittently at high ji= tter +* frequencies using default register values. +* +* Impact: Receive compliance test fails at default register setting. +*/ + +VOID +ConfigUsbLane0 ( + IN UINTN UsbPhy + ) +{ + UINTN RegAddress; + + RegAddress =3D UsbPhy + USB_PHY_RX_OVRD_IN_HI; + + ArmDataMemoryBarrier (); + MmioWrite16 (RegAddress, USB_PHY_RX_EQ_VAL_1); + ArmDataMemoryBarrier (); + MmioWrite16 (RegAddress, USB_PHY_RX_EQ_VAL_2); + ArmDataMemoryBarrier (); + MmioWrite16 (RegAddress, USB_PHY_RX_EQ_VAL_3); + ArmDataMemoryBarrier (); + MmioWrite16 (RegAddress, USB_PHY_RX_EQ_VAL_4); + + return; +} + +VOID +ErratumA009007 ( + VOID + ) +{ + UINTN UsbPhy; + + UsbPhy =3D USB_PHY1_BASE_ADDRESS; + ConfigUsbLane0 (UsbPhy); + + UsbPhy =3D USB_PHY2_BASE_ADDRESS; + ConfigUsbLane0 (UsbPhy); + + UsbPhy =3D USB_PHY3_BASE_ADDRESS; + ConfigUsbLane0 (UsbPhy); + + return; +} diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c b/Silicon/NXP/LS10= 46A/Library/SocLib/SocLib.c index 3b15aee6ecae..80342d7230e4 100644 --- a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c +++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c @@ -11,6 +11,8 @@ #include #include #include + +#include #include =20 /** @@ -65,6 +67,47 @@ SocGetClock ( } =20 /** + Function to select pins depending upon pcd using supplemental + configuration unit(SCFG) extended RCW controlled pinmux control + register which contains the bits to provide pin multiplexing control. + This register is reset on HRESET. + **/ +STATIC +VOID +ConfigScfgMux (VOID) +{ + LS1046A_SUPPLEMENTAL_CONFIG *Scfg; + UINT32 UsbPwrFault; + + Scfg =3D (LS1046A_SUPPLEMENTAL_CONFIG *)LS1046A_SCFG_ADDRESS; + // Configures functionality of the IIC3_SCL to USB2_DRVVBUS + // Configures functionality of the IIC3_SDA to USB2_PWRFAULT + // USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA + ScfgWrite32 ((UINTN)&Scfg->RcwPMuxCr0, SCFG_RCWPMUXCRO_NOT_SELCR_USB); + + ScfgWrite32 ((UINTN)&Scfg->UsbDrvVBusSelCr, SCFG_USBDRVVBUS_SELCR_USB1); + UsbPwrFault =3D (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHI= FT) | + (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT= ) | + (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT); + ScfgWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault); + ScfgWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault); +} + +STATIC +VOID +ApplyErrata ( + VOID + ) +{ + ErratumA009008 (); + ErratumA009798 (); + ErratumA008997 (); + ErratumA009007 (); +} + + + +/** Function to initialize SoC specific constructs **/ VOID @@ -72,7 +115,30 @@ SocInit ( VOID ) { + LS1046A_SUPPLEMENTAL_CONFIG *Scfg; + + Scfg =3D (LS1046A_SUPPLEMENTAL_CONFIG *)LS1046A_SCFG_ADDRESS; + + /* Make SEC, SATA and USB reads and writes snoopable */ + ScfgOr32((UINTN)&Scfg->SnpCnfgCr, SCFG_SNPCNFGCR_SECRDSNP | + SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP | + SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP | + SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP | + SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP | + SCFG_SNPCNFGCR_SATAWRSNP); + + ApplyErrata (); ChassisInit (); =20 + // + // Due to the extensive functionality present on the chip and the limite= d number of external + // signals available, several functional blocks share signal resources t= hrough multiplexing. + // In this case when there is alternate functionality between multiple f= unctional blocks, + // the signal's function is determined at the chip level (rather than at= the block level) + // typically by a reset configuration word (RCW) option. Some of the sig= nals' function are + // determined externel to RCW at Power-on Reset Sequence. + // + ConfigScfgMux (); + return; } --=20 1.9.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#65269): https://edk2.groups.io/g/devel/message/65269 Mute This Topic: https://groups.io/mt/76861999/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Apr 19 10:25:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+65268+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+65268+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=oss.nxp.com ARC-Seal: i=1; a=rsa-sha256; t=1600167046; cv=none; d=zohomail.com; s=zohoarc; b=hUHtKti+qZvJ6r2yev2wsE5VwzaNhPA0un6aT+rJGrPGA4AYRTC85BFwfh6Q7eLESmmF1N4er35EFkjuaQei6qTTIjGmqF5agkxBJD3fb/A4lVfwIWvzW6Pjeo/cVLIH6xyCtyGwQg4BRqq/EK3lxueTTx9LLamUMWLY3B9N/XE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1600167046; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=hH9YhVRhpyWo6R9PRr3jdu20NMkdHkd3ej94xlc4JSM=; b=eRHkdY6bcCWtEHeexN6Je0OH3yGTeBKK08qVwGMlmwlp+nLgSEY6m6pGqd+Etg25a0KuNicWNaSzY6zENm+IkU0GqmU4rhDDeIJblQDyfCPHaaKQmwRK8ocCvjd0bHGWleA6bdHWbuF4Nvi+Yv6Czr60razNvKF6NbbFd14G+yI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+65268+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1600167046101405.3882640168547; Tue, 15 Sep 2020 03:50:46 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 7mv4YY1788612xXBhn0dYuAp; Tue, 15 Sep 2020 03:50:45 -0700 X-Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by mx.groups.io with SMTP id smtpd.web12.10732.1600166867626010707 for ; Tue, 15 Sep 2020 03:47:47 -0700 X-Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 123EB1A08AB; Tue, 15 Sep 2020 12:47:46 +0200 (CEST) X-Received: from inv0113.in-blr01.nxp.com (inv0113.in-blr01.nxp.com [165.114.116.118]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id CAFB81A0899; Tue, 15 Sep 2020 12:47:45 +0200 (CEST) X-Received: from uefi-OptiPlex-790.ap.freescale.net (unknown [10.232.132.78]) by inv0113.in-blr01.nxp.com (Postfix) with ESMTP id 9EEE135D; Tue, 15 Sep 2020 16:17:44 +0530 (IST) From: Meenakshi Aggarwal To: ard.biesheuvel@arm.com, leif@nuviainc.com, michael.d.kinney@intel.com, devel@edk2.groups.io Cc: v.sethi@nxp.com, Meenakshi Aggarwal , Meenakshi Aggarwal Subject: [edk2-devel] [edk2-platforms 4/4] LS1046aFrwy: Enable USB support for LS1046AFRWY board. Date: Tue, 15 Sep 2020 21:59:03 +0530 Message-Id: <1600187343-18732-5-git-send-email-meenakshi.aggarwal@oss.nxp.com> In-Reply-To: <1600187343-18732-1-git-send-email-meenakshi.aggarwal@oss.nxp.com> References: <1600187343-18732-1-git-send-email-meenakshi.aggarwal@oss.nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,meenakshi.aggarwal@oss.nxp.com X-Gm-Message-State: CbbsDpiwVuhkUHifbNOMTbShx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1600167045; bh=PLVMNTRtb2f/C7sJj97hprI9tu5YkHu6zdoTpdi7iII=; h=Cc:Date:From:Reply-To:Subject:To; b=SKpVkuiNZkbAr0SpQbi0bKtltLLNw7I/nRi86Kt6hoWnEsW5ey8Lxb0W41MCPweTHM/ mTkvFR23ytrqZbe7dm2B3thTHyaEKRHPWSbtORiJf7+wQBN7CvmUwcfCEKar5jR5NNWyp JWzHysNvrzLlOJc9/CSkGnvWLoXIwV0aa6w= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Meenakshi Aggarwal Reviewed-by: Leif Lindholm --- Silicon/NXP/LS1046A/LS1046A.dsc.inc | 3 +++ Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc | 2 ++ Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf | 13 +++++++++++++ 3 files changed, 18 insertions(+) mode change 100644 =3D> 100755 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.= dsc mode change 100644 =3D> 100755 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.= fdf diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc b/Silicon/NXP/LS1046A/LS10= 46A.dsc.inc index 4e1d6a7ae7a2..7004533ed5f1 100644 --- a/Silicon/NXP/LS1046A/LS1046A.dsc.inc +++ b/Silicon/NXP/LS1046A/LS1046A.dsc.inc @@ -31,6 +31,9 @@ [PcdsFixedAtBuild.common] gNxpQoriqLsTokenSpaceGuid.PcdGpioModuleBaseAddress|0x02300000 gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerOffset|0x10000 =20 + gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr|0x2F00000 + gNxpQoriqLsTokenSpaceGuid.PcdUsbSize|0x100000 + gNxpQoriqLsTokenSpaceGuid.PcdNumUsbController|3 =20 [PcdsFeatureFlag] gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc b/Platform/NXP/= LS1046aFrwyPkg/LS1046aFrwyPkg.dsc old mode 100644 new mode 100755 index 3f29dadd5d1d..266fdbd2b4d3 --- a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc +++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc @@ -43,4 +43,6 @@ [Components.common] gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE } =20 + Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf + ## diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf b/Platform/NXP/= LS1046aFrwyPkg/LS1046aFrwyPkg.fdf old mode 100644 new mode 100755 index 24af547729c7..34c4e5a02516 --- a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf +++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf @@ -120,6 +120,19 @@ [FV.FvMain] INF FatPkg/EnhancedFatDxe/Fat.inf INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.i= nf =20 + INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciD= eviceDxe.inf + + # + # USB Support + # + INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf + INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + INF Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf + # # UEFI application (Shell Embedded Boot Loader) # --=20 1.9.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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